August, 2016

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Application Note

Clock Jitter Basics

Introduction
The aim of this paper is to provide a short introduction to some of the terminology surrounding clock jitter and to provide an
overview of the approaches used to specify and measure jitter in timing devices.

What is Jitter?
Jitter as defined by NIST is the “short term phase variation of the significant instants of a digital signal from their ideal positions in
time”. Essentially, timing jitter is the deviation of an oscillator’s edge from its ideal location. As an oscillator’s signal gets multiplied
and filtered, the jitter gets multiplied and filtered as well, and a system’s timing budget can quickly disappear. Here we see just
how problematic jitter can be, and as a consequence it has become a necessity for designers to possess a good understanding of
timing jitter and how it will affect their system design.

Jitter can be caused by noise within the oscillator circuit or other disturbances in the system, such as power supply noise, thermal
noise, vibration, and many other factors. In most discussions, the Total Jitter (TJ) of a system is split into two main categories:
Deterministic and Random Jitter (DJ and RJ). The figure below shows a quick analysis of jitter including a brief introduction to the
different components of DJ and RJ.

Figure 1: Total Jitter and its Components

Random Jitter

Random jitter is an ever present phenomenon that cannot always be predicted. The random jitter experienced by a device
is a combination of multiple factors, including thermal noise, trace width variations, shot noise, flicker, etc. Random jitter is a
broadband stochastic Gaussian process that is sometimes referred to as intrinsic noise because it is always present. Random jitter
has a normal probability distribution function (PDF) that is unbounded, and cannot maintain a well-defined peak-to-peak value.
Instead it is commonly described by its standard deviation. Random jitter is also independent from other sources of jitter, in that
its presence does not magnify the effects of other sources of jitter.

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 Application Note
Deterministic Jitter

Deterministic jitter is sometimes referred to as bounded jitter. If all components of a system are known, then you can accurately
predict how much jitter will be observed at each transitional edge. Since deterministic jitter is composed of all other non-random
forms of jitter, it does not follow a general distribution function. There is a finite amount of non-random jitter sources, and
therefore we can deduce that it has a PDF that is bounded. This allows us to characterize deterministic jitter by its peak-to-peak
value (a quantifiable value).

Deterministic jitter can be further broken down into two subcategories: Periodic Jitter and Data-Dependent Jitter. Periodic jitter
includes any jitter at a fixed frequency or period. It is easy to measure accurately and appears in the frequency spectrum as
distinct peaks. Some good examples of periodic jitter are power supply noise and crosstalk from neighboring data lines. Data-
dependent jitter encompasses all jitter whose magnitude is affected by changes in a signal’s duty cycle or clock edges. For
example, in a data stream the transition between a 0 and 1 of alternating bits (01010101) is going to be different compared to a
transition that follows a long string of identical bits (00011001). As this type of behavior is not present in clocks and oscillators,
this form of deterministic jitter is considered a non-factor.

There are many ways to categorize jitter, and while it is important to understand what type of jitter you are observing, it is equally
as important to be able to measure the different types of jitter. By being able to accurately measure jitter, efforts can be made to
filter/remove it and reduce the overall Bit Error Rate (BER) of a system.

How Low is Low Jitter?

Quick Answer: It depends.

The simple concept of the word ‘Jitter’ can take on multiple meanings depending on how it is measured and characterized.
Oftentimes, it can be helpful to look at a traditional Figure Of Merit in the clock industry, such as integrated phase jitter using
no additional filtering in the band of 12kHz to 20MHz, to get a sense of the performance range that is covered by modern clock
oscillators. On the Vectron website we have summarized data on a selection of devices at standard frequencies.

Devices that can be classified as ‘low jitter’ can cover a wide range that goes from 1ps all the way down to 23fs. These numbers
are strongly dependent on the details of the measurement, even within the narrow definition of phase jitter we have established.
Further variation in phase jitter would be seen if we superimposed additional filtering on the data beyond that already assumed
by the ‘brick wall’ filter used during measurement.

The message here is that benchmarks like phase jitter are useful, but even then details about the measurement can lead to a range
of results. When comparing clocks that claim ‘low jitter’ performance always keep in mind the differences between what ‘Jitter’
actually means and the particulars of how the numbers on datasheets and in electrical specifications were calculated.

Jitter Specifications
Timing noise/jitter is a very complicated phenomenon, and in order to understand how jitter can impact a system it needs to be
measured and quantified. Historically, clock specifications have defined jitter from two different perspectives: measurements in
the time domain, and measurements in the frequency domain.

Time Domain Jitter Measurements

There are three types of jitter that are measured in the time domain: period jitter, cycle-to-cycle jitter, and time interval error (TIE)
jitter.

The period jitter represents the maximum deviation of an oscillator’s period in a waveform over a specified number of clock
cycles. Given a number of clock cycles (typically in the 10,000+ range) each period is measured in order to calculate the mean
value, standard deviation and peak-peak value. As this measures the clock period deviations over time, there is no reference to an
ideal value. Any difference between the mean and expected value can be looked at as an offset, and easily designed around.

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 Application Note

The cycle-to-cycle jitter represents how much the oscillator’s period changes between any two adjacent cycles. Much like period
jitter, cycle-to-cycle jitter is not measured in reference to an ideal value. Cycle-to-cycle jitter for an oscillator is reported as a peak
value which defines the maximum deviation between the rising edges of any two consecutive clocks. For example, if one period is
-20pS from the average, and another period is +15pS from the average, the maximum cycle-to-cycle jitter is 20pS. There are some
measuring devices that calculate the cycle-to-cycle jitter by applying a first order difference operation to the period jitter.

TIE jitter measures how far each edge of the clock varies from its ideal position. Unlike period and cycle-to-cycle jitter, TIE jitter
measurements require the tester to know where the ideal edges should be, and for this reason it is difficult to observe TIE in real
time with an oscilloscope. In most cases TIE jitter measurements require the tester to capture and post-process the data. The TIE
may also be obtained by integrating the period jitter, after first subtracting the nominal (ideal) clock period from each measured
period. TIE is important because it shows the cumulative effect that even a small amount of period jitter can have over time.

Frequency Domain: Phase Noise Jitter Measurements

Phase noise is often considered an important measurement of spectral purity, which is the inherent stability of a timing signal.
Let’s take s sinusoidal oscillator that outputs a sine wave with a frequency Fc. An ideal oscillator will have perfect spectral purity,
with all of its power concentrated at Fc. As jitter causes variations in frequency, this results in power being spread out to adjacent
frequencies, creating sidebands. By measuring the amount of power in the sidebands relative to the carrier, we can derive a jitter
value.

Phase jitter can be calculated by measuring the phase spectral density of the clock’s signal and integrating over a specific
frequency band of interest. The area under the spectrum plot represents the power level of the phase modulating (jitter
producing) noise, and the power of the noise is proportional to the RMS phase jitter squared. In most cases the upper frequency
can be specified up to the Nyquist frequency of the system. An application may only be interested in a range of the phase noise
plot and typically will specify that range or apply a mask to identify the area of interest and maximum dBc values permitted. This
mask is often called a Jitter Mask.

In order to specify a Jitter Mask, a system’s transfer function must be analyzed. The jitter mask will specify the clock performance in
how it will actually affect the system, with the goal of avoiding over-specification. In today’s engineering world, many jitter masks
have been predetermined by industry protocols, the most common being the requirement for SONET (12kHz to 20MHz) and
related telecom standards for optical carrier network OC48. This jitter mask has become an unofficial industry standard, regardless
of whether the clock will be used in a SONET application or not.

This can be problematic, as it is not always the case that the 12 kHz to 20 MHz jitter bandwidth can be measured, or even make
sense, if the carrier or clock frequency is too low. Practical systems have digital sampling, or equivalent mixing and filtering
limitations, which require the minimum carrier frequency to be roughly 2X or more than the maximum offset frequency. Even if
this was not the case, one cannot measure a clock with a carrier frequency < 20 MHz directly, with offsets out to 20 MHz. It is for
this reason that a designer (both for the oscillator and the system) must have a firm understanding of what exactly they are asking
for when it comes to a phase jitter spec.

How to Measure Jitter

Continuous advances in high-speed communication and measurement systems require higher levels of performance from system
clocks and references. Performance acceptable in the past may not be sufficient to support high-speed synchronous equipment.
Perhaps the most important and least understood measure of clock performance is jitter. One of the main challenges with jitter
measurements is that there are currently no industry standard methods established. There are multiple variables to consider,
from what test equipment is used to what the actual test conditions are. While JEDEC standards do provide definitions and
suggested test conditions, there is a lack of consistency between measurements from different testers.

There are three components that remain consistent for all forms of jitter testing: the device under test (DUT), a reference oscillator,
and a power supply. A reference oscillator is a vital component for the test setup, as the equipment measuring the DUT needs to
have a better noise floor than the DUT. Otherwise the performance of the DUT will be degraded by the noise of the equipment.

Standard measurement equipment (oscilloscopes, counters, signal source analyzers) contain an internal TCXO/OCXO, and for most
timing devices these are sufficient. Vectron’s test equipment uses a low phase noise OCXO, locked to an external 10MHz Rubidium
clock which is in turn locked to a GPS receiver.

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 Application Note
Time Domain Jitter Measurements

Oscilloscopes are the main device used for time domain jitter measurements. Oscilloscopes allow for the easy viewing of
waveforms and pulses, and are considered indispensable for any time and frequency lab. While there are many vendors who can
offer jitter measurement test packets, they are often provided at an additional cost. An oscilloscope that is high-speed (1GHz+)
and has a high sampling bandwidth (10GS/s+) should be sufficient to gather the desired data. We also need to recall that time
domain jitter measurements (specifically period and cycle-to-cycle) are random and expressed in terms of mean value and
standard deviation over a number of samples. JEDEC standard 65 requires a minimum of 1000 samples, but a 10,000 sample
minimum is preferred by most applications.

Period Jitter

Although the official definition of period jitter is the difference between a measured clock period and the ideal period, in real
world applications it is often difficult to quantify what the ideal period is. If we observe the output from an oscillator set to 125
MHz using an oscilloscope, the average measured clock period may be 7.996 ns instead of 8 ns. Therefore, it is more practical to
treat the average observed period as the ideal period, and is a common practice by timing device manufacturers. The standard
procedure for measuring period jitter involves randomly measuring the duration of one clock period 10,000 times, and using the
recorded data to calculate the mean, standard deviation and peak-to-peak values. Due to the random nature of period jitter, the
peak-to-peak values can vary greatly, and often times period jitter needs to be re-calculated several times to come up with an
average value.

Below is an example of period jitter measured on a Wavecrest SIA-3300C signal integrity analyzer for a 200MHz XO. This analyzer
platform is setup to measure 30,000 samples at a time, and is executed three times in order to obtain an average peak-to-peak
value.

Figure 2: Period Jitter Measurement for a 200MHz XO

Cycle-to-Cycle Jitter

Measuring cycle-to-cycle jitter is very similar to measuring period jitter, but with one additional step. The standard procedure
for measuring cycle-to-cycle jitter involves randomly measuring the duration of two clock periods 10,000 times, and taking the
absolute difference between the two. The recorded data is used to calculate the mean and standard deviation values, and the
peak value is simply the largest difference in periods observed. As with period jitter, the peak-to-peak values can vary greatly,
and often times cycle-to-cycle jitter needs to be re-calculated several times to come up with an average value. Some digital
oscilloscopes have a histogram feature, which simplifies a lot of the math.

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 Application Note
Below is an example of cycle-to-cycle jitter measured on a LeCroy Waverunner 610ZI Digital Oscilloscope for a 50MHz XO. In
this case, a jitter measurement tool, assigned to P8 and labeled ‘dper’, is used to calculate the cycle-to-cycle jitter. This analyzer
platform is setup to measure 30,000 samples at a time, and is executed three times in order to obtain an average peak-to-peak
value.

Figure 3: Cycle-to-Cycle Jitter Measurement for a 50MHz XO

Tie Jitter

Measuring TIE jitter is very difficult with only an oscilloscope. Typically, a histogram is necessary to plot the measurement values
against the frequency of occurrence of the measurements. An example of a jitter histogram for a TIE measurement is shown
below. In this case, the continuous variable is mapped into 500 bins, and the total population of the data set is 3,200,000.
The mean value of TIE is theoretically zero, and as can be seen in this measurement, the mean value is 0 ns. For this plot, the
distribution is approximately Gaussian with a standard deviation of 1.3 ps.

Figure 4: TIE Jitter Histogram

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 Application Note
Frequency Domain Jitter Measurements

Whereas time domain measurements are handled primarily by an oscilloscope, frequency domain measurements are handled
primarily by a signal source analyzer (SSA). Most SSA’s have a very low noise floor (-180dBc/Hz), and have integrated cross-
correlation techniques that further reduces the test system noise. Cross-correlation essentially cancels noise by taking the vector
sum of the measurement results of two independent measurement channels.

For measuring phase noise, Vectron prefers using the Agilent E5052B. The 5052B includes two independent PLL paths with
two built-in reference sources that are uncorrelated with each other (there is also an option for an external reference source). If
two signals are uncorrelated, their vector sum, meaning the total noise power from the reference sources taken through vector
averaging, lowers the system noise floor by canceling the noise from its internal reference sources and other related circuits, while
the noise signal from the DUT is emphasized. This allows for fast and user-friendly testing, with the main downside being that only
one device can be tested at a time. The E5052B can also calculate the integrated noise over a desired range (see example below,
measuring from 12kHz to 5MHz), and calculate the integrated phase jitter.

Figure 5: Phase Noise and RMS Jitter Measurement for 156.25MHz XO

If one does not have a signal source/spectrum analyzer that can calculate the jitter by itself, any analyzer with a decent noise floor
can be used to calculate the frequency domain phase jitter and integrated period jitter using the formulas below.

RMS Noise (Radians) RMS Noise (Degrees) Integrated Period Jitter (Seconds)

As an example, these formulas were used for the same part displayed above, and only using markers 4-7, we were able to calculate
RMS phase jitter of 10.0468 degrees and an integrated period jitter of 178.611fs, as compared to the E5052B’s results of 10.1156
degrees and 179.834fs. There are also several free web tools that can calculate these values based off of inputting the data.
Vectron has used the Jitter Labs application to confirm the measurements of our test setup.

Common Sources of Jitter in Oscillators

There are a number of external factors which can induce jitter on an oscillator, and each be compensated via different means.
Here we will discuss several major sources of jitter: thermal noise, crosstalk, vibration and power supply noise.

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 Application Note
Thermal Noise

Thermal noise goes under a number of names including Johnson-Nyquist noise, Johnson noise, or Nyquist noise. This electrical or
RF noise is generated as a result of thermal agitation of the charge carriers (electrons within an electrical conductor). This thermal
noise actually occurs regardless of the applied voltage because the charge carriers vibrate as a result of the temperature. This
vibration is dependent upon the temperature - the higher the temperature, the higher the agitation and hence the thermal noise
level. Thermal noise is random in nature and not possible to predict its waveform. Therefore, it is not possible to reduce the effects
by cancellation or other similar techniques. The only ways to reduce the thermal noise content are to reduce the temperature of
operation, or selecting components with more favorable temperature coefficients (such as thin film versus thick film resistors).

An example of this problem is demonstrated in the figure below. Here the shaded band between the red and black curves
represents the range of different phase noise measurement results of the same oscillator at 100 MHz. This measurement
was made with the same test setup, but changing some resistors on the PCB. The results shown below might also have been
affected by uncontrolled AM noise leakage or electromagnetic interference (EMI) that is now reduced having selected different
components. This illustrates why in most conversations, thermal noise, EMI and AM noise leakage are grouped together.

Figure 6: Effects of Thermal Noise on an Oscillator’s Phase Noise

Crosstalk

As the feature sizes have been shrinking with process-technology scaling, the spacing between adjacent interconnect wires/traces
keeps decreasing in every process technology. When a signal on one of these wires generates a rising/falling edge, this can have
an effect on a neighboring wire, and is generally referred to as crosstalk. Crosstalk can be due to electric or magnetic field lines
interacting between two adjacent lines, and is due to the capacitance and inductance between them.

In capacitive crosstalk, the two wires are denoted as the aggressor (the wire with a signal) and the victim (the wire receiving the
noise). As the edge generated by the aggressor propagates down the line, it will inject current into the victim line through their
capacitance. As the current is injected, the current will see an equal impedance in both the forward and reverse directions, and as
a result, the current will split equally, with half travelling forward and half travelling backwards.

Figure 7: Demonstration of Capacitive Crosstalk

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 Application Note
In inductive crosstalk, magnetic fields exist as the current travels down the aggressor line. These B-field lines induce B-field lines
around the victim line, which in turn creates current travelling in the opposite direction. The direction of the induced current
creates a negative voltage at the far-end and a positive voltage at the near-end as it flows through the termination impedances.

Figure 8: Demonstration of Inductive Crosstalk

The effects of crosstalk on an oscillator are largely contributed from the PCB the oscillator is mounted to. By following proper
design guidelines, crosstalk can be minimized/eliminated. Other methods include inserting buffers, cell resizing, track
reassignment of the victim traces and additional spacing allocated to victim traces.

Vibration

One of the characteristics of quartz is that any movement or change in forces on the crystal can change the frequency. This is
typically represented in datasheets in units of ppm or ppb/g. For example, a common spec might indicate that a 10 MHz crystal
will change approximately 1 ppm/g. The sensitivity means that when the crystal is exposed to mechanical vibration, it will have
a higher phase noise due to these random slight movements. This occurs in helicopters, jets, or even in locations that are in close
proximity to other mechanical vibrating elements like a cooling fan.

The change in respect to the frequency of vibration can be calculated by the following equation. In this equation, ‘Γ’ represents
the acceleration sensitivity of the crystal, ‘a’ represents the acceleration seen by the crystal, ‘fo’ is the frequency of oscillation and ‘fv’
is the frequency of the vibration.

For a sinusoidal vibration, ‘a’ is the peak applied vibration level in units of g, and L(fv) is expressed in units of dBc. In most real-
world applications, vibration is completely random. With random vibration the power is randomly distributed over a range of
frequencies, phases, and amplitudes, and it is more practical to have acceleration represented by its power spectral density (PSD).
For random vibration, ‘a’ is the square-root of twice the PSD, and represented in units of g2/Hz, and therefore L(fv) is expressed in
units of dBc/Hz.

Below are examples of vibration on an oscillator. On the left, we see sinusoidal vibration producing spectral lines at ± fv from the
carrier. As these vibrations increase in magnitude, the sidebands will eventually overpower the carrier, causing a collapse. On the
right we see the effects of random vibration being applied along the x-axis of an oscillator, and how it can severely impact phase
noise performance.

Figure 9: Sinusoidal Vibration Figure 10: Random Vibration

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 Application Note

Methods most commonly used in order to reduce vibration-induced phase noise can be as simple as isolating the vibration
(using rubber, foam, or springs) and using more rigid materials (ceramic versus aluminum) to as complicated as active vibration
cancellation. One such method would be that while an oscillator is under vibration, an estimate of a complex-conjugate (same
amplitude, opposite phase) signal can be generated from accelerometer signals and used to modulate the oscillator’s output
phase in such a way as to suppress or cancel the induced sidebands.

Power Supply Noise

Hardware designers are typically faced with the challenge of increasing the amount of functionality on a PCB while reducing the
overall footprint. This often leads to switching to cleaner power supplies at the cost of removing previously necessary filtering
circuitry. The often overlooked side-effect is that having multiple components sharing an unfiltered common power supply will
propagate any noise, and interference generated by one device will now directly impact the jitter performance of all other devices.

For clocking circuits, power supply noise translates into additional jitter. Traditional XOs are very simple circuits composed of an
inverting amplifier driving a crystal. Due to their simple design, vendors often overlook evaluating these devices for power supply
noise rejection. In many cases, the amplifier is designed, tested and evaluated only in low-noise environments, using a clean
power supply and minimal discrete components. Being primarily an analog circuit, sensitive nodes can easily couple noise. That
noise will translate to output jitter in the form of spurs that modulate at the fundamental oscillation frequency. The more sensitive
the amplifier, the higher the spur magnitude will be for a given amount of noise.

A device’s power supply rejection can typically be managed by applying a filter across the power supply. This can be as simple the
addition of a ferrite bead and a discrete SMD capacitor (a low pass filter). A linear regulator can also be used to filter supply noise.
Depending on what is observed on the power supply, some cases might require having to use both circuits in order to filter across
the entire frequency band that a device might experience supply ripple.

Conclusion
This paper breaks down a number of commonly used terms associated with oscillators and their jitter performance. The primary
goal of clock-jitter analysis should be to determine what type of jitter the specific application is sensitive to, and analyze how their
effects can be minimized. While clock vendors are responsible for guaranteeing a high level of performance, only so much design
can be done at the component level. A design engineer that knows how jitter can be generated and mitigated will be able to save
themselves a great deal of trouble down the line.

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Disclaimer
Vectron International reserves the right to make changes to the product(s) and or information contained herein without notice. No liability is assumed as a result of their use or application.
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