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lec25

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priyambanerjee2017
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PE-EC-505A –L25: Additional Concepts of FinFET

SOI(Silicon-On-Insulator) vs FINFET:
As SOI technology is very close to planner bulk technology, it does not require much
investment in Fabrication. So, existing bulk technology libraries can easily be converted to
SOI libraries. Another advantage of SOI over FinFET is, that it has good back gate bias
option. By creating back gate region below BOX, we can also control Vt. This make it
suitable for low power applications.

The primary limitation of SOI technology is the cost of an SOI wafer which is higher than a
bulk Silicon wafer because it is very difficult to control the tin silicon film throughout the
wafers. Another stumbling block for SOI adoption is a limited number of SOI wafer
suppliers. According to Intel, SOI wafer adds approximately 10% to the total process cost.

In comparison to SOI, FinFET has higher drive current. Moreover in FinFET, the strain
technology can be used to increase carrier mobility.

One of the downsides of FinFET is its complex manufacturing process. According to Intel,
the cost of FinFET manufacturing can increase by 2-3% over bulk.

Structure:
The FinFET structure consists of a thin fin of silicon on a substrate with the gate wrapped
over the fin. The two sides of the fin which are not wrapped under the gate forms the source
and the drain. The gate orientation is at right angles to the vertical fin. The channel is formed
in the fin area wrapped under the gate.
Structure of FinFET
The gate surrounds the channel from three sides providing better electrostatic control of the
channel. Such a gate structure is known as a tri-gate structure and can fully deplete the
channel of carriers, providing better electrical characteristics with reduced leakage current
and reduced short-channel effects. This design is called the FinFET because its Si body
resembles the back fin of a fish.
In planner CMOS devices, the channel is horizontal while in FinFETs, the channel is vertical.
The width of the FinFET is dependent on the height of the Fin.
In above Fig., w1 = w3 = Height of the Fin, w2 = Thickness of the fin.
The width of the channel is given in the equation given below :
Effective Channel Width = (2 * Height of Fin) + Thickness of the fin
W= (2*w1) + w2
Effective Channel Length = Length of the gate = L
This type of gate structure provides improved electrical control over the channel conduction
and helps reduce leakage current levels and overcome some of the short-channel effects.

Operation of an n-Type FinFET:

Figure : Current flow through the channel

ON Condition: Vgate > Vth, Vdrain = ‘+’ ve, Vsource = 0V.


When the gate electrode is given a voltage higher than the threshold voltage, the region
beneath the gate is inverted and forms a channel, providing a conducting path between the
source and the drain. The current flows from Drain to Source in the channel as represented in
Fig. 2. Both sides of the channel conduct, delivering more current than the planar CMOS
transistor, as FinFETs have wider active current area and higher electron mobility.

Off Condition: Vgate < 0V, Vsource = 0V, Vdrain = ‘+’ve.


Transistor is in OFF condition and since the gate controls the channel from both sides, the
leakage is reduced better than a planar CMOS transistor.

MOSFET Scaling Challenges


For many generations, the switching speed – and hence the performance of the transistor –
could be increased by shrinking the gate length (L) and by applying stress to improve the
channel mobility. However, these strategies ran into difficulties when the gate reached a
length of around 20 nm. At dimensions that small, transistor performance was affected by
short-channel effects. For example, current could leak between the source and drain even
when flow should have been turned off. This and other technical challenges drove engineers
to look at alternative transistor designs.

Short-channel effects, such as leakage current, occur when the gate length becomes too short

A 3D Scaling Solution using FinFET


One way to regain control over channel current flow is to raise the channel above the plane of
the silicon, creating the “fin” that is characteristic of the FinFET design. The gate wraps
around the channel on three sides of the raised fin, instead of only across its top. The greater
surface area between gate and channel provides better control of the electric field and thereby
reduces leakage in the “off” state. Another advantage is that a lower gate voltage is needed to
operate the transistor. The result is a transistor with better performance and reduced power
consumption. The three-dimensional FinFET geometry is a key technology inflection that
also provides a possible roadmap to further scaling. By building the transistor vertically,
chipmakers are able to continue shrinking dimensions and packing more components onto a
chip. Designers can also choose to increase the height of the fin, which allows higher current
flow through the channel without taking up more room on the die.
Comparison of planar transistor and FinFET architectures

General layout and mode of operation


The basic electrical layout and the mode of operation of a FinFET does not differ from a
traditional field effect transistor. There is one source and one drain contact as well as a gate to
control the current flow.
In contrast to planar MOSFETs the channel between source and drain is build as a three
dimensional bar on top of the silicon substrate, called fin. The gate electrode is then wrapped
around the channel, so that there can be formed several gate electrodes on each side which
leads to reduced leakage effects and an enhanced drive current.
The manufacture of a bulk silicon-based multi gate transistor with three gates (tri gate) is
described below.
Construction of a bulk silicon-based FinFET
1. Substrate
Basis for a FinFET is a lightly p-doped substrate with a hard mask on top (e.g. silicon nitride) as well
as a patterned resist layer.

2. Fin etch
The fins are formed in a highly anisotropic etch process. Since there is no stop layer on a bulk wafer
as it is in SOI, the etch process has to be time based. In a 22 nm process the width of the fins might be
10 to 15 nm, the height would ideally be twice that or more.
3. Oxide deposition
To isolate the fins from each other a oxide deposition with a high aspect ratio filling behavior is
needed.

4. Planarization
The oxide is planarized by chemical mechanical polishing. The hard mask acts as a stop layer.

5. Recess etch
Another etch process is needed to recess the oxide film to form a lateral isolation of the fins.

6. Gate oxide
On top of the fins the gate oxide is deposited via thermal oxidation to isolate the channel from the gate
elctrode. Since the fins are still connected underneath the oxide, a high-dose angled implant at the
base of the fin creates a dopant junction and completes the isolation (not illstrated).

7. Deposition of the gate


Finally a highly n+-doped poly silicon layer is deposited on top of the fins, thus up to three gates are
wrapped around the channel: one on each side of the fin, and - depending on the thickness of the gate
oxide on top - a third gate above.
The influence of the top gate can also be inhibited by the deposition of a nitride layer on top of the
channel.

Since there is an oxide layer on an SOI wafer, the channels are isolated from each other anyway. In
addition the etch process of the fins is simplified as the process can be stopped on the oxide easily.

FinFET Application

 FinFET is used in low power design in digital circuit, such as RAM, because of its low off-
state current.

 FinFET is used in Power amplifier or other application in analog area which requires good
linearity.

 Exynos has been leading the FinFET innovation. In 2018, Samsung proudly announced the
Exynos 9 Series (9810), a mobile processor built on the 2nd generation 10nm FinFET
process. However, it’s not the first processor that Samsung utilized FinFET technology. In
January of 2015, Samsung began mass production of Exynos 7 Octa (7420), the industry's
first mobile processor using the 14nm FinFET process technology. The Samsung Exynos
processor will continue to be built on the industry’s most advanced process technology to
create infinite possibilities on mobile life.

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