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Lab 7 DLD Ai231032

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Sheikh Moosa Aijaz
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16 views4 pages

Lab 7 DLD Ai231032

Uploaded by

Sheikh Moosa Aijaz
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as DOCX, PDF, TXT or read online on Scribd
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Moosa Aijaz Ai231032

DHA SUFFA UNIVERSITY Dept. of Computer Science


Digital Logic Design

LAB # 7
Half Adder & Full Adder
Objective:
Be able to verify working of half adder and full adder.
Requirement:
 7408 IC (AND gate)
 7432 IC (OR gate)
 7486 IC (XOR gate)
 LED
 Breadboard
 5 Volt DC Power Supply
Theoretical Background:
HALF ADDER:
A combinational circuit that performs the addition of two bits is called a half-adder. This
circuit consists of two binary inputs and two binary outputs. Let the inputs be A & B. The
low order output will be called “S” and it represents the sum, and the high order output
will be called “C”, and it represents the carry out.
Equation for half adder is

FULL ADDER:
A full adder is a combinational circuit that forms the arithmetic sum of three input bits. It
consists of three inputs and two outputs. Two of the input variables represent the two
significant bits to be added. The third input represents the input carry from the previous
lower significant position. The two outputs are sum and carry out. The binary variable S
gives the value of the least significant bit of the sum. The binary variable C gives the
output carry. A full adder can be combined with other full adders or work on its own.
Equation for full adder is

Lab 07| Half Adder & Full Adder Page 1 of 4


Moosa Aijaz Ai231032

DHA SUFFA UNIVERSITY Dept. of Computer Science


Digital Logic Design

Procedure:
Design the combinational circuit using below circuit diagrams on Breadboard. After
designing both circuits, observe the output and complete the truth table.
Half adder

Figure 7.1: Half Adder

Full adder

Figure 7.2: Full Adder

Lab 07| Half Adder & Full Adder Page 2 of 4


Moosa Aijaz Ai231032

DHA SUFFA UNIVERSITY Dept. of Computer Science


Digital Logic Design

Truth Table
Table 7.1: Half Adder

A B C S
0 0 0 0
0 1 1 0
1 0 1 0
A B C in C out S
1 1 0 1
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Table 7.2: Full Adder

Post Lab:
Fill in the blanks
1. Full adder performs the arithmetic addition of **three** input bits.

Lab 07| Half Adder & Full Adder Page 3 of 4


Moosa Aijaz Ai231032

DHA SUFFA UNIVERSITY Dept. of Computer Science


Digital Logic Design

2. The half adder produces a **Sum** and a **Carry** value which are both binary
digits.
3. The **half** adder is one that does not take a carry-in from another adder.

Question
Draw logic diagram of half adder using NOT gate, AND gate & OR gate.

Learning Outcomes:
Upon successful completion of the lab, students will be able to:
LO1: Understand Half Adder & Full Adder

Lab 07| Half Adder & Full Adder Page 4 of 4

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