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TUSB422
ZHCSFQ2C – NOVEMBER 2016 – REVISED JUNE 2018

TUSB422 具有供电功能的 USB Type-C™ 端口控制

1 特性 3 说明
•
1 支持 USB Type-C™1.2 和电源供电 (PD) 规范 TUSB422 是一款 USB PD PHY，可在 USB
• 支持 I2C 接口 (TCPCi) 的 USB PD 物理层 Type-C 端口中实现 USB Type-C 生态系统所需的配置
– 5V 至 24V 拉灌电压 通道 (CC) 逻辑。该器件集成 USB 双相标记编码
– 2.5W VCONN 开关 (BMC) 供电 (PD) 协议的物理层，允许使用功率高达
– 交替模式协商 100W 的电源并支持备用模式接口。具备 USB Type-C
• 针对支持 自主双角色端口 (DRP) 的 应用进行了优 端口管理器 (TCPM) 的外部处理器通过 I2C 接口与
化 TUSB422 进行通信。
• 软件可配置为专用主机、专用器件或兼具两种角色
在 TCPM 的控制下，TUSB322 使用 CC 引脚确定端
– 下行数据端口 (DFP)、上行数据端口 (UFP) 和
口连接状态、电缆方向并进行角色检测和 USB Type-C
双角色端口 (DRP)
电流模式控制。TUSB422 可根据应用配置为 DFP、
– 连接/断开 USB 端口
UFP 或 DRP。TUSB422 应用 VBUS 检测和放电功
– 电缆方向检测
能，从而实现兼容性 USB Type-C 端口。
– 电流模式通告与检测
– 调试和音频附件支持 TUSB422 集成 2.5W 开关，可为有源电缆提供
– 有源电缆检测 VCONN 电源。该器件还提供 VCONN 放电功能。
– 为有源电缆提供 VCONN TUSB422 还支持 USB Type-C 可选 功能， 例如音频
• 支持电量耗尽的电池 和调试附件。
• 集成过热检测二极管 (OTSD) 该器件能够在宽电源范围内工作，功耗较低。
• VBUS 检测与放电控制 TUSB422 可在工业级温度范围内运行。
• 电源电压：2.7V 至 5.5V
• 低电流消耗 器件信息(1)
器件型号 封装 封装尺寸（标称值）
• -40°C 至 85°C 的工业温度范围
1.335mm x 1.380mm，
TUSB422 WCSP (9)
间距为 0.4mm
2 应用
(1) 要了解所有可用封装，请见数据表末尾的可订购产品附录。
• 智能手机
• 平板电脑、笔记本电脑、台式机
• 墙式充电器、移动电源
空白
简化电路原理图
USB Type-C 智能手机
VDD VCONN

VBUS
VCONN
Detection &
VBUS_DET Switch
Discharge

I2C CC1
Type-C
Slave
Channel
INT TCPC
Configuration
CC2
SCL
Config
APU
SDA Control
USB PD Phy USB Type-C
Port Manager

GND TUSB422
USB Typ-C
Port Controller

USB Type-C

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
English Data Sheet: SLLSEW6
TUSB422
ZHCSFQ2C – NOVEMBER 2016 – REVISED JUNE 2018 www.ti.com.cn

目录
1 特性 .......................................................................... 1 7.4 Device Functional Modes........................................ 17
2 应用 .......................................................................... 1 7.5 Programming........................................................... 19
3 说明 .......................................................................... 1 7.6 Register Maps ......................................................... 22
4 修订历史记录 ........................................................... 2 8 Application and Implementation ........................ 63
8.1 Application Information............................................ 63
5 Pin Configuration and Functions ......................... 3
8.2 Typical Application ................................................. 63
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4 9 Power Supply Recommendations...................... 65
6.2 ESD Ratings.............................................................. 4 10 Layout................................................................... 66
6.3 Recommended Operating Conditions....................... 4 10.1 Layout Guidelines ................................................. 66
6.4 Thermal Information .................................................. 5 10.2 Layout Example .................................................... 66
6.5 Electrical Characteristics........................................... 5 11 器件和文档支持 ..................................................... 67
6.6 Timing Requirements ................................................ 8 11.1 接收文档更新通知 ................................................. 67
6.7 Typical Characteristics ............................................ 10 11.2 社区资源................................................................ 67
7 Detailed Description ............................................ 11 11.3 商标 ....................................................................... 67
7.1 Overview ................................................................. 11 11.4 静电放电警告......................................................... 67
7.2 Functional Block Diagram ....................................... 11 11.5 术语表 ................................................................... 67
7.3 Feature Description................................................. 12 12 机械、封装和可订购信息 ....................................... 68

4 修订历史记录
Changes from Revision B (August 2017) to Revision C Page

• Changed the VCONN pin description in the Pin Functions table ........................................................................................... 3
• Deleted VRX(FRS_PD) from electrical characteristics .................................................................................................................. 6
• Deleted tFRSWAPRX from timing requirements section............................................................................................................... 8
• Added NOTE: "The TUSB422 supports all PD2.0 and PD 3.0..." to the USB PD BMC PHY section ................................. 12
• Deleted text from the first paragraph of the Fast Role Swap secton. ................................................................................. 16
• From: Once VBUS is at VSafe0V, change .. To: Once VBUS is at VSafe0V, disable
AUTO_DISCHARGE_DISCONNECT in Power Control Register and change .. ................................................................ 17
• From: Once VBUS is at vSafe5V, the TCPM should then send PS_RDY to its port partner. To: Once VBUS is at
vSafe5V, the TCPM should update message header information and then send PS_RDY to its port partner. ................. 17
• Added NOTE: "During Power-role swap, the TUSB422..." to the Power Role Swap section. ............................................. 18
• Added NOTE: "When exiting dead battery mode..." to the Dead Battery Mode section...................................................... 18
• Changed bit 0 From: VCONN_OC_FAULT To Reserved in 图 31 and 表 28...................................................................... 37
• Added text: "VBUS present status may be invalid..." to the Bit 2 VBUS_PRESENT description in 表 31........................... 40
• Added text: "Before attempting to transmit..." to the Transmit Register (address = 0x50) [reset = 0x00] register .............. 51
• Changed bit 0 From: FAST_ROLE_SWAP_STAT To Reserved in 图 65 and 表 62........................................................... 56
• Changed bit 0 From: FAST_ROLE_SWAP_MASK To Reserved in 图 66 and 表 63.......................................................... 57
• Changed bit 3 From: FASTROLE_RX_EN To Reserved in 图 69 and 表 66....................................................................... 59

Changes from Revision A (April 2017) to Revision B Page

• Changed Bit TX_BUFF_OBJx_BYTE_x From: Read Only To Read/Wright in 图 54 and 表 51 ......................................... 52

Changes from Original (November 2016) to Revision A Page

• Deleted text: "Following sentence optional..." from the ESD Ratings table notes.................................................................. 4

2 Copyright © 2016–2018, Texas Instruments Incorporated

 TUSB422
www.ti.com.cn ZHCSFQ2C – NOVEMBER 2016 – REVISED JUNE 2018

5 Pin Configuration and Functions

YFF Package
9 Pin (DSBGA)
Top View
1 2 3

A CC2 VBUSIN VDD

B VCONN INT_N SCL

C CC1 GND SDA

Not to scale

Pin Functions
PIN
I/O DESCRIPTION
NO. NAME
Type-C Configuration channel signal 2. Used for connector orientation, connection detection
A1 CC2 I/O (FS) and removal, current capabilities, and PD communication. This pin requires an external
CRX(SHUNT) capacitor.
A2 VBUSIN I 5-24 V VBUS input voltage. Tie directly to VBUS at Type-C connector.
A3 VDD P 2.7 V to 5.5 V Positive supply voltage
2.7 V to 5.5 V VCONN. VCONN voltage should be at a valid stable value before software
B1 VCONN P closes the VCONN switch. If VCONN support is not required in the system, then this pin can
be left floating.
Open drain output. Asserted low to indicate status change occurred. Requires an external
B2 INT_N O (FS)
pull-up resistor.
I/O Open-
B3 SCL SCL - I2C communication clock signal. Requires an external pull-up resistor.
drain (FS)
Type-C Configuration channel signal 1. Used for connector orientation, connection detection
C1 CC1 I/O (FS) and removal, current capabilities, and PD communication. This pin requires an external
CRX(SHUNT) capacitor.
C2 GND G Ground
I/O Open-
C3 SDA SDA - I2C communication data signal. Requires an external pull-up resistor.
drain (FS)

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6 Specifications

6.1 Absolute Maximum Ratings

over operating free-air temperature range (unless otherwise noted) (1)
MIN MAX UNIT
Supply Voltage VDD -0.3 6 V
VCONN Switch
VCONN -0.3 6 V
voltage
INT_N, SDA, SCL -0.3 6 V
Control pins CC1, CC2 -0.3 6 V
VBUSIN -0.3 26 V
Storage temperature, Tstg -65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

6.2 ESD Ratings

VALUE UNIT
Human body model (HBM), per
±1500
ANSI/ESDA/JEDEC JS-001, all pins (1)
V(ESD) Electrostatic discharge Charged device model (CDM), per V
JEDEC specification JESD22-C101, all ±1500
pins (2)

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
VDD Supply voltage range 2.7 3.7 5.5 V
VCONN VCONN voltage range 2.7 5 5.5 V
VBUSIN System VBUS voltage 0 5 24 V
VI2C_SYS System I2C voltage range that SDA and 1.65 1.8 3.6 V
SCL are pulled up to
Operating Free air temperature with
-40 25 105 °C
VCONN not supported in the system
TA
Operating Free air temperature with
-40 25 85 °C
VCONN supported in the system
TJ Junction temperature -40 125 °C

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 TUSB422
www.ti.com.cn ZHCSFQ2C – NOVEMBER 2016 – REVISED JUNE 2018

6.4 Thermal Information

TUSB422
THERMAL METRIC (1) YFF (DSBGA) UNIT
9 PINS
RΘJA Junction-to-ambient thermal resistance 114.3 °C/W
RΘJC(top) Junction-to-case (top) thermal resistance 0.7 °C/W
RΘJB Junction-to-board thermal resistance 24.9 °C/W
ΨJT Junction-to-top characterization parameter 0.3 °C/W
ΨJB Junction-to-board characterization parameter 24.9 °C/W
RΘJC(bot) Junction-to-case (bottom) thermal resistance NA °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

6.5 Electrical Characteristics

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Power Consumption
UFP Current consumption in
I(UNATTACHED_ Unattached.SNK when port is
VDD = 3.7V 10 µA
UFP) unconnected and waiting for
connection
DRP Current consumption while
toggling between Unattached.SNK and
I(UNATTACHED_
Unattached.SRC when port is VDD = 3.7V 12 µA
DRP) unconnected and waiting for
connection.
I(UNATTACHED_ DFP Current consumption in VDD = 3.7V 11 µA
DFP) Unattached.SRC when port is
unconnected and waiting for
connection
UFP Current consumption in
I(ACTIVE_UFP) attached.SNK Active Mode. PD VDD = 3.7V 330 µA
Disabled.
UFP current consumption in
I(ACTIVE_UFP_P attached.SNK with PD enabled and VDD = 3.7V;
5.2 mA
D) transmitting continuous BIST Carrier TX_CARRIER_MODE2_SEL = 1;
Mode 2.
CC pins (CC1 and CC2)
Voltage on both CC pins when in dead
battery and the attached DFP is
VCC(USB_DB) VDD = 0V 0.25 1.5 V
presenting default current
advertisement
Voltage on both CC pins when in dead
battery and the attached DFP is
VCC(MED_DB) VDD = 0V 0.45 1.5 V
presenting medium current (1.5A)
advertisement
Voltage on both CC pins when in dead
battery and the attached DFP is
VCC(HIGH_DB) VDD = 0V 0.88 2.18 V
presenting high current (3.0A)
advertisement
Pull-down resistor when in UFP or
R(CC_RD) VDD = 2.7V to 5.5V 4.6 5.1 5.6 kΩ
DRP mode
R(CC_RA) Pull-down resistor for active cable VDD = 2.7V to 5.5V 0.8 1 1.2 kΩ
VDD = 0V; VCONN = 0V; CC pin =
ICC(LKG) Leakage current through CC pins 1.36 mA
5.5V
Voltage level range for detecting a
V(UFP_CC_USB DFP attach when configured as a UFP
0.25 0.61 V
) and DFP is advertising default current
source capability

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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Voltage level range for detecting a
V(UFP_CC_MED DFP attach when configured as a UFP
0.7 1.16 V
) and DFP is advertising medium (1.5A)
current source capability
Voltage level range for detecting a
V(UFP_CC_HIG DFP attach when configured as a UFP
1.31 2.04 V
H) and DFP is advertising high (3.0A)
current source capability
Voltage threshold for detecting a UFP
VTH(DFP_CC_U
attach when TUSB422 is advertising 1.51 1.6 1.64 V
SB) default current source capability.
Voltage threshold for detecting a UFP
VTH(DFP_CC_M attach when TUSB422 is advertising
1.51 1.6 1.64 V
ED) medium current (1.5A) source
capability.
Voltage threshold for detecting a UFP
VTH(DFP_CC_HI
attach when TUSB422 is advertising 2.46 2.6 2.74 V
GH) high current (3.0A) source capability.
Voltage threshold for detecting a
VTH(AC_CC_US
active cable attach when advertising 0.15 0.2 0.25 V
B) default current
Voltage threshold for detecting a
VTH(AC_CC_ME
active cable attach when advertising 0.35 0.4 0.45 V
D) medium current
Voltage threshold for detecting a
VTH(AC_CC_HI
active cable attach when advertising 0.76 0.8 0.84 V
GH) high current.
ICC(DEFAULT_P Default mode pull-up current source
64 80 96 µA
) when advertising default current.
Medium (1.5A) mode pull-up current
ICC(MED_P) source when advertising medium 166 180 194 µA
current.
High (3.0A) mode pull-up current
ICC(HIGH_P) VDD > 3.0V 304 330 356 µA
source when advertising high current.
Output impedance of CC1/CC2 during
RTX(PD) TX when operating in PD mode and At 750KHz 33 48 75 Ω
driving the CC line.
Fast Role Swap request transmit
RTX(FRS_PD) driver resistance (excluding cable 5 Ω
resistance)
Transmit high voltage when operating
VOH(PD) 1.05 1.125 1.2 V
in PD mode
Transmit low voltage when operating
VOL(PD) 0.07 V
in PD mode.
Receiver input impedance. Does Not
RRX(PD) include pull-up or pulldown resistance TX is Hi-Z 1 MΩ
from cable detect.
Input high voltage when sourcing
VIH(PD_SRC) power. Selected when POWER_ROLE 0.8925 1.5325 V
= 1.
Input high voltage when sinking
VIH(PD_SNK) power. Selected when POWER_ROLE 0.6425 1.5325 V
= 0.
Input low voltage when sourcing
VIL(PD_SRC) power. Selected when POWER_ROLE -0.3325 0.4825 V
= 1.
Input low voltage when sinking power.
VIL(PD_SNK) -0.3325 0.2325 V
Selected when POWER_ROLE = 0.

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 TUSB422
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Electrical Characteristics (continued)

over operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
External shunt capacitance on both
CRX(SHUNT) 200 450 pF
CC1 and CC2.
Control pins: INT_N
I(INTN_LEAK) INT_N leakage VDD = 0V; 0 < INT_N < 3.3V -1 1 µA
VOL Low-level signal output voltage IOL = -2mA 0.4 V
I2C (SDA and SCL). VDD must be above 3V to operate at 3.3V I2C levels
VIH(I2C) High-level input signal voltage 1.2 V
VIL(I2C) Low-level input signal voltage 0.4 V
Low-level signal output voltage (open-
VOL(I2C) 0.4 V
drain)
IOL(I2C) Low level output current 6 mA
I(I2C_LKG) Leakage through SDA and SCL pins VDD = 0V; pin pulled up to 3.6V -1 1 µA
C(I2C) Capacitance for SDA and SCL pins 10 pF
C(I2C_FM+_BUS
I2C bus capacitance for FM+ (1MHz) 150 pF
)
C(I2C_FM_BUS) I2C bus capacitance for FM (400KHz) 150 pF
R(EXT_I2C_FM+ External resistors on both SDA and
C(I2C_FM+_BUS) = 150pF 620 820 910 Ω
) SCL when operating at FM+ (1MHz)
External resistors on both SDA and
R(EXT_I2C_FM) C(I2C_FM_BUS) = 150pF 620 1500 2200 Ω
SCL when operating at FM (400KHz)
VCONN
ON resistance of the VCONN power
RDS(ON) 0.4 0.75 Ω
FET.
Voltage to pass through VCONN
V(PASS) 5 V
power FET
VCONN current limit; VCONN is
I(VCONN) 500 650 850 mA
disconnected above this voltage.
V(VCONN_PRES
Threshold for detecting Vconn present. 2 2.4 V
)
Bulk capacitance on VCONN; Placed
C(VCONN) 10 200 µF
on VCONN pin supply
Resistance to GND when Vconn
R(VCONN_DIS) 4.6 5.1 5.6 KΩ
discharge is enabled
VBUSIN
Source External bulk capacitance
C(BULK_SRC) 10 150 µF
when operating as VBUS Source.
Sink External bulk capacitance on
C(SNK) 1 10 µF
VBUS at connector
Sink External bulk capacitance on
C(SNKPD) 1 100 µF
VBUS after success PD negotiation
Resistance to gnd when bleed
R(BLEED) 8 10 12.5 KΩ
discharge is enabled
V(SRCSLEWNE
VBUS discharge maximum slew rate -30 mV/µs
G)
V(VBUS_MEASU VBUS_VOLTAGE register
-2 2 %
RE_ACC) measurement accuracy
OTSD
TJ over temperature trip threshold
T(OTSD1) resulting in VCONN turn off and flag 150 °C
set.

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6.6 Timing Requirements

MIN NOM MAX UNIT
CC pins in PD mode
Fbr_PD Bit Rate 270 300 330 Kbps
tUI_PD Unit Interval 3.03 3.3 3.7 µs
tRISE_PD Rise time 10% to 90%; CRX(SHUNT) = 200pF 300 ns
tFALL_PD Fall time 90% to 10%; CRX(SHUNT) = 200pF 300 ns
tRxFilter Rx Bandwidth limiting filter 100 ns
Time from the end of last bit of a
tInterFrameCap frame until the state of the first bit of 25 50 µs
the next pre-amble
Time before the start of the first bit of
tStartDrive the preamble when the transmitter -1 1 µs
shall start driving the line.
Time to cease driving the line after the
tEndDriveBMC 23 µs
end of the last bit of a frame
Time to cease driving the line after the
tHoldLowBMC 1 23 µs
final high-to-low transition
nTransitionC Number of transitions to be detected
Transitions for signal detect 3
ount to declare bus non-idle
Fast Role Swap request transmit
tFRSWAPTX 60 120 µs
duration
I2C (SDA and SCL)
fSCL SCL clock frequency 0.001 1 MHz
tHD;STA Hold time (repeated) start condition 0.26 µs
tLOW Low period of SCL 0.5 µs
tHIGH High period of SCL 0.26 µs
Setup time for a repeated start
tSU;STA 0.26 µs
condition
tHD;DAT Data Hold Time 0 µs
tSU;DAT Data setup time 50 µs
tSU;STOP Setup time for STOP condition 0.26 µs
Bus free time between STOP and
tBUF 0.5 µs
START condition
tVD;DAT Data valid time 0.45 µs
tVD;ACK Data valid acknowledge time 0.45 µs
tR_I2C Rise time of both SDA and SCL 30% to 70% 120 ns
tF_I2C Fall time of both SDA and SCL 70% to 30% 14 120 ns
VCONN Fault
tVCONN_FAULT Delay from Vconn fault detected to
20 µs
_DLY Vconn fault status flag set
Delay from Vconn fault detected to
tVCONN_OPEN 50 ns
Vconn switch opened
Power-Up Requirements
Time from VDD (min) to TUSB422 Measured from VDD(min) to INT_N
tINT_N_LOW 4 ms
asserts INT_N low. pin at VOL(min).
tVDD_RISE VDD rise time Measured from 0V to VDD(min) 40 ms
Sampling timings
tCC_SAMPLE_R Delay from Vconn fault detected to
CC_SAMPLE_RATE = 2'b01 2 ms
ATE Vconn fault status flag set
The sampling interval of VBUS
tVBUSINRATE CC_SAMPLE_RATE = 2'b01 2.2 ms
Voltage

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VCONN(max)

VCONN pin

0V

VDD(max)

VDD pin VDD(min)

0V
Vinternal
Internal
POR

0V

VDD_I2C

INT_N pin
VOL(min)
0V

TINT_N_LOW

图 1. Power-Up Timing

图 2. VCONN Fault Timing

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6.7 Typical Characteristics

700 530

510
600
490
500
470

RDS(ON) (m:)
I_Limit (mA)

400 450

300 430

410
200
390
RDS(ON) (m:) at VDD = 3.7 V
100 RDS(ON) (m:) at VDD = 2.7 V
370
RDS(ON) (m:) at VDD = 5.5 V
0 350
2.7 3 3.3 3.6 3.9 4.2 4.5 4.8 5.1 5.4 -40 -15 10 35 60 85 110
VCONN (V) D001
Junction Temperature (qC) D002

图 3. VCONN Voltage vs Current Limit 图 4. VCONN RDS(ON) vs Junction Temperature

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 TUSB422
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7 Detailed Description

7.1 Overview
The USB Type-C ecosystem operates around a small form factor connector and cable that is flippable and
reversible. Due to the nature of the connector, a scheme is needed to determine the connector orientation.
Additional schemes are needed to determine when a USB port is attached, determine the acting role of the USB
port (Source, Sink, active cable, audio accessory, debug accessory), and communicate Type-C current
capabilities. These schemes are implemented over the CC pins according to the USB Type-C Specification 1.2.
The TUSB422 provides Configuration Channel (CC) logic for determining USB port attach and detach, role
detection, cable orientation, and Type-C Current detection/advertisement. The TUSB422 also contains several
features such as VCONN sourcing, VBUS enable, VBUS discharge enable, detection of vSafe0V, and low
standby current.
The TUSB422 provides a USB Type-C Port Controller Interface (TCPCi) allowing the USB Type-C Port Manager
(TCPM) residing in an external microprocessor the ability to determine when a port partner is attached or
removed, cable orientation, enable or remove power to the Type-C port. The TUSB422 implements a USB PD
BMC physical layer and protocol layer for communication over the Type-C port for purposes like power
negotiations, alternate mode enablement (ie DisplayPort over Type-C), and data role negotiations just to mention
a few. The TUSB422 takes a message provided by external processor, calculate and append a 32-bit CRC,
encode, and transmit the encoded message over the CC wire in the cable. The TUSB422 also receives data
from the CC wire and determined if packet is valid or not, respond with GoodCRC, and notify external processor
of its arrival by asserting the interrupt (INT_N).

7.2 Functional Block Diagram

VDD VCONN GND

VBUS D0 Internal_VDD
VBUSIN Detection
ADC
D9
LDO
VBUSDIS_EN

Rvbusdis

VCONN_EN

Cable Detection Ip
And
Orientation CC1_PD_CTL
CC1
BMC_CLK
CC1_RD_RP
CC1_RD_RA
RX 32-bit 4b5b BMC
FIFO CRC decode decode + Hi_Cur1
-
SDA Ra Rd + Med_Cur1
I2C Configuration -

Slave And + Def_Cur1

Status -
(FM+) Registers VCNDIS_EN
SCL

TX 32-bit 4b5b BMC

FIFO CRC encode encode Rvcn_dis

INT_N

Ip

CC2
OSC
CC2_PD_CTL CC2_RD_RP

CC2_RD_RA

+ Hi_Cur2
-

Ra Rd + Med_Cur2
-

+ Def_Cur2
-

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接下页)
Functional Block Diagram (接
7.2.1 Cables, Adapters, and Direct Connect Devices
Type-C Specification 1.2 defines several cables, plugs and receptacles to be used to attach ports. TUSB422
supports all cables, receptacles, and plugs.

7.2.1.1 USB Type-C receptacles and Plugs

• USB Type-C receptacle for USB2.0 and USB3.1 and full-featured platforms and devices
• USB Full-Featured Type-C plug
• USB2.0 Type-C Plug

7.2.1.2 USB Type-C Cables

• USB Full-featured Type-C cable with USB3.1 full featured plug
• USB2.0 Type-C cable with USB2.0 plug
• Captive cable with either a USB Full featured plug or USB2.0 plug

7.2.1.3 Direct Connect Devices

TUSB422 supports the attaching and detaching of a direct connect device such as a cradle dock or captive
cable.

7.3 Feature Description

7.3.1 USB PD I2C Type-C Port Controller Interface (TCPC)

The TUSB422 provides up to 1Mbps I2C USB Type-C Port Controller Interface (TCPC) interface and register set
allowing for control by external processor. The TUSB422 implements the following optional TCPC features.
• Up to 24 V VBUS Measurement and Alarms
• Default, 1.5 A, and 3 A Source Resistor (Rp) advertisement
• Source VCONN
• VCONN overcurrent fault detection

7.3.2 USB PD BMC PHY

The TUSB422 contains a USB Power Delivery BMC (Bi-phase Mark coded) Baseband phy. The TCPM can
enable the TUSB422’s USB PD BMC phy for any of the following conditions when the TUSB422 is in
Attached.SNK, Attach.SRC, DebugAccessory, or PoweredAccessory state:
• Receiver Detect Register is non-zero
The USB PD phy will always be disabled when the TUSB422 is in the unattached mode.
The TUSB422 PD BMC phy receiver threshold will be set based on the value of the POWER_ROLE field in the
Message Header Info register. The default receiver threshold can be changed by setting the VIX_PD and
VIX_PD_OVERRIDE fields in the PHY BMC RX Control register.

注
The TUSB422 supports all PD2.0 and PD 3.0 messages except for the PD 3.0 Get Source
Capabilities Extended Message. Upon receipt of this message, GoodCRC is not returned,
and no Rx alert flag is set. The side effect is that the port partner will retry the message.
After the retries are exhausted, the port partner will send a soft reset message.

表 1. Power Role
POWER-ROLE VIH VIL
0 VIH(PD_SRC) VIL(PD_SRC)
1 VIH(PD_SNK) VIL(PD_SNK)

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7.3.3 DFP (Downstream Facing Port)

The TUSB422 can be used in applications in which USB devices are connected too. For example, in a desktop
application the Type-C port(s) must be able to determine when a device is attached and enable both power (in
the form of VBUS) and datapath (either USB data and/or Alternate Mode data like DisplayPort) to attached
device. The TUSB422 can be used in a DFP application by programming the Role Control register to 0x05. This
presents Rp on both of TUSB422 CC pins. When configured as a DFP, the TUSB422 can be used to control the
sourcing of VCONN. Control of VBUS source path must be handled outside of the TUSB422.
Upon enabling TUSB422 for DFP, the TUSB422 will continuously monitor both CC1 and CC2 for a connection.
After a connection has been determined, the TUSB422 will notify system of event by asserting the INT_N pin
low. Upon detecting assertion of INT_N, the external microprocessor should read and clear the appropriate Alert
registers.
The following steps are for initialization of the TUSB422 for DFP operation.
1. Upon TUSB422 power-up, the Power Status flag in Alert Register should get set indicating TUSB422 is
initialized. When set, this flag will cause the INT_N pin to be assert low.
2. SW read the Alert Registers to determine reason for INT_N assertion. The expectation is Power Status bit
(Reg10h bit 1) is set.
3. SW read Power Status register and notice that TCPC_INIT_STATUS flag is cleared. This indicates TUSB422
is ready.
4. SW clear Power Status bit in Alert register by writing a 1’b1 to the bit.
5. Program the TUSB422 to present Rp on both CC pins. This is done by writing 0x05 to the Role Control
register. If advertising greater than default Type-C current is desired, then write 0x15 for 1.5 A current or
0x25 for 3 A current advertisement
6. Write Look4Connection command to the Command register.
7. The TUSB422 now presents Rp on both CC pins and look for a connection.

注
Because TUSB422 supports Dead Battery Mode, a dedicated DFP application (like a Car
Charger) which uses the TUSB422 should incorporate a diode in the source power path
circuitry to block VBUS from being received by another attached DFP/DRP that is
providing VBUS.

7.3.4 UFP (Upstream Facing Port)

A UFP is a port that will present Rd on its CC pins and sink VBUS. The TUSB422 functions as a UFP by
programming the Role Control register to 0x0A. This will cause TUSB422 to present a Rd on both CC pins.
The following steps are for initialization of the TUSB422 for DFP operation.
1. Upon TUSB422 power-up, the Power Status flag in Alert Register should get set indicating TUSB422 is
initialized. When set, this flag will cause the INT_N pin to be assert low.
2. SW read the Alert Registers to determine reason for INT_N assertion. The expectation is Power Status bit
(Reg10h bit 1) is set.
3. SW read Power Status register and notice that TCPC_INIT_STATUS flag is cleared. This indicates TUSB422
is ready.
4. SW clear Power Status bit in Alert register by writing a 1’b1 to the bit.
5. Program the TUSB422 to present Rd on both CC pins. This is done by writing 0x0A to the Role Control
register
6. Write Look4Connection command to the Command register.
7. The TUSB422 now presents Rd on both CC pins and look for a connection.

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7.3.5 DRP (Dual-Role Port)

A Dual-Role port functions as both a DFP and a UFP. The TUSB422 supports DRP either autonomously or
manually. In autonomous DRP mode, the TUSB422 state machine toggles between UFP (Rd) and DFP (Rp) on
both its CC pins. Autonomous DRP is enabled by programming Role Control register to 0x4A and writing
Looking4Connection command to the Command register. Manual mode is under complete control of external
processor. External processor must toggle between writing 0x0A and 0x05 to Role Control register at interval
defined by Type-C specification summarized in 表 2.

表 2. USB Type-C DRP Toggle Requirements

PARAMETER MIN MAX DESCRIPTION
The period a DRP shall complete a Source (Rp) to Sink (Rd) and back
tDRP 50 ms 100 ms
advertisement
dcSRC.DRP 30% 70% The percent of time that DRP shall advertise Source (Rp) during tDRP .

The following steps are for initialization of the TUSB422 for DRP operation.
1. Upon TUSB422 power-up, the Power Status flag in Alert Register should get set indicating TUSB422 is
initialized. When set, this flag will cause the INT_N pin to be assert low.
2. SW read the Alert Registers to determine reason for INT_N assertion. The expectation is Power Status bit
(Reg10h bit 1) is set.
3. SW read Power Status register and notice that TCPC_INIT_STATUS flag is cleared. This indicates TUSB422
is ready.
4. SW clear Power Status bit in Alert register by writing a 1’b1 to the bit.
5. Program the TUSB422 to present Rd on both CC pins. This is done by writing 0x4A to the Role Control
register
6. Write Look4Connection command to the Command register.
7. The TUSB422 now presents Rd on both Rp pins and look for a connection.
The TUSB422 autonomously toggles between Rd and Rp according to the setting of the CC General Control
register. If a value other than default value is desired, then CC General control should be programmed to desired
value before performing Step 6.

7.3.6 Type-C Current Mode Advertising

Once a valid cable detection and attach have been completed, the TUSB422 has the option to advertise thru
CC1/CC2 pins the level of Type-C current a UFP can sink. The TUSB422 supports all three possible Type-C
current options: Default (500 mA / 900 mA), Medium(1.5 A), and High (3 A). The current advertisement used by
TUSB422 is determined by the value programmed in the Role Control register.

注
VDD must be greater than 3.0 V to advertise 3 A current.

7.3.7 VBUS Source Enable/Disable Control

The TUSB422 is unable to directly control VBUS enable due to no GPIO support. For this reason, external
microprocessor must directly control the Vbus enable. If it wishes, the external microprocessor may notify the
TUSB422 when Vbus has been enable/disabled, or raised above vSafe5V value. Notification to TUSB422 comes
in the form of writing to the Command register any of the following commands: SourceVbusDefaultVoltage (that
is, vSafe5V enable), SourceVbusHighVoltage (that is, greater than vSafe5V), or DisableSourceVbus. If these
commands are issued to the TUSB422, the TUSB422 ignores these commands.

7.3.8 VBUS Sink Enable/Disable Control

The TUSB422 cannot directly control VBUS Sink path, and therefore; VBUS sink path control is handled
externally. Software may write the SinkVbus command to TUSB422 Command register, but the TUSB422
ignores this command.

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7.3.9 VBUS Monitoring

One of the features of USB PD is the ability to raise VBUS above the default vSafe5V level. The ability to monitor
the VBUS voltage level is critical to determining when VBUS is at desired level as well as when VBUS is no
longer present. The TUSB422 implements measuring of VBUS and the results are stored in the VBUS Voltage
register. The VBUS voltage measurement is enabled by setting the VBUS_VOLTAGE_MONITOR bit in the
Power Control register.

7.3.10 VBUS Discharge

The TUSB422 implements internal VBUS discharge. The TUSB422 can be setup to discharge VBUS
automatically based on Type-C conditions or software can force a VBUS discharge by setting the
FORCE_DISCHARGE bit in the Power Control register.
The TUSB422 cannot directly control the enable of external VBUS switch. Therefore, software must disable
VBUS switch before or immediately after discharge of VBUS is required.
The TUSB422 meets the USB PD standard with a bulk capacitance defined by C(BULK_SRC). If bulk capacitance
greater than C(BULK_SRC) is required, then external VBUS discharge must be used. If an external VBUS discharge
is desired, the TUSB422 internal VBUS discharge circuit can be disabled by setting the INT_VBUSDIS_DISABLE
bit in the VBUS and VCONN Control register.

7.3.11 VBUS to CC Short Detection from Legacy Charger

A legacy Type-A charger will always have VBUS active. When customer plugs a Type-A to Type-C cable into
both charger and TUSB422, the TUSB422 immediately detects Rp and then detects VBUS. If for some reason,
there is a short between VBUS and CC, the TUSB422 the CC pin is exposed to VBUS voltage. The TUSB422
implements a detection of VBUS to CC short by monitoring voltage level on each the CC pin. If the initial voltage
is above 3.5 V and TUSB422 is presenting Rd, then the TUSB422 will set the CC_FAULT status flag. The
TUSB422 keeps the CC1_STATE and CC2_STATE flags in the open state. This indicates a invalid connection
exist and user should be notified. The TUSB422 continues to look for a valid connection. Once user removes the
fault condition (for example, selects a new cable), the TUSB422 indicates a valid connection by updating
CC1_STATE and CC2_STATE to appropriate value.

7.3.12 VBUS Power Source Requirements

The TUSB422 is a Source if MESSAGE_HEADER_INFO POWER_ROLE = 1. As outlined in the USB TCPCi
specification, the TUSB422 when operating as a source discharges VBUS under any of the following conditions
when Auto Discharge (AUTO_DISCHARGE_DISCONNECT = 1) is enabled.
• Disconnect (Removal of Rd by port partner) is detected. The TUSB422 discharges VBUS to vSafe0V.
• Upon setting Force Discharge bit, the TUSB422 discharges VBUS to either vSafe0V or to the voltage
specified by VBUS Stop Discharge register.
The TUSB422 does not automatically discharge VBUS upon reception of a Hard Reset.

7.3.13 VBUS Power Sink Requirements.

The TUSB422 is a Sink if MESSAGE_HEADER_INFO POWER_ROLE = 0. As outlined in the TCPC
specification, the TUSB422 when operating as a sink must discharge VBUS to vSafe0V under any of the
following conditions when Auto Discharge (AUTO_DISCHARGE_DISCONNECT = 1) is enabled.
• If VBUS present detection is enabled and VBUS Sink Disconnect Threshold register is zero and VBUS
present bit in the Power Status register transitions from a 1 to 0.
• VBUS crosses the threshold programmed in the VBUS Sink Disconnect Threshold register.

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7.3.14 VCONN
VCONN is required by active cables, emarker, and VCONN powered accessories like Alt Mode adapters. These
types of devices or cables present Ra on one CC pin and Rd on the other CC pin. VCONN must be enabled
when any of device or cable requiring VCONN is connected to a Type-C port and the TUSB422 is operating as a
DFP or DFP in DRP mode. Software can also enable the VCONN switch when the TUSB422 is a UFP during a
VCONN_SWAP sequence. The TUSB422 implements a VCONN switch which is controlled by software. The
default state of this switch is open. By setting the ENABLE_VCONN bit in Power Control register, the TUSB422
removes closes the switch resulting in VCONN power to be connected to the CC pin indicated by value of
PLUG_ORIENTATION bit in TCPC Control register.
Once the VCONN switch is closed, the switch can be opened by any of the following conditions.
• Software clear ENABLE_VCONN bit in Power Control register.
• VCONN overcurrent fault condition occurs resulting in TUSB422 opening VCONN switch and setting the
VCONN_OCP_FAULT_STATUS bit in Fault Status register.
• Over temperature condition detected by TUSB422. Must be enabled in OTSD Control register.
• Hard Reset ordered set is received.
• Cable is removed (Rd no longer present) results in TUSB422 opening VCONN switch and discharging
VCONN to vSafe0V
The TUSB422 discharges VCONN to vSafe0V by enabling Rd at designated CC pin anytime the VCONN switch
transitions from closed to open state. Once at vSafe0V, the TUSB422 disables the discharge circuit by removing
Rd and then re-enable Rp (assuming it is still enabled in Role Control register).
If an external VCONN discharge is desired, the TUSB422 internal VCONN discharge circuit can be disabled by
setting the INT_VCONNDIS_DISABLE bit in the VBUS and VCONN Control register.
Before closing the VCONN switch, the TCPM must make sure the voltage on VCONN pin is at a valid level.
When opening the VCONN switch by clearing the ENABLE_VCONN bit, the TCPM software must make sure
voltage on VCONN pin is at valid level until after VCONN switch is opened and then, if desired, can remove the
voltage from the VCONN pin. Removing the voltage on VCONN pin before Vconn switch is opened will result in a
false VCONN fault condition.

7.3.15 Interrupts
The TUSB422 asserts the INT_N pin low anytime an unmasked event occurs. Upon assertion of the interrupt, the
TCPM should read the Alert Registers to determine the reason for interrupt. Upon reading the Alert register, the
TCPM should clear the interrupt by writing a 1’b1 to the appropriate field in the Alert register.
If the FAULT flag is set in the Alert register, the TCPM must first read the Fault Status register to determine
reason for fault. Then clear the appropriate field in the Fault Status register by writing a 1’b1. Once all fields in
Fault Status register are cleared, the TCPM can then clear the flag in the Alert Register by writing a 1’b1.
The TUSB422 also has Vendor Defined Interrupt registers which is not part of the USB TCPC specification.
These vendor defined interrupts are masked by default. Software can enable vendor interrupts by setting the
appropriate bit in the Vendor Interrupts Mask Register and setting the VENDOR_IRQ_MASK field in the Alert
Mask register.

7.3.16 Fast Role Swap

The TUSB422 supports Fast Role Swap TX as defined in the USB Power Delivery 3.0 specification. The
TUSB422 does not support Fast Role Swap RX function.
The TUSB422 can also transmit a FastRole swap pulse. This is done by writing a 1’b1 to the
TX_FAST_ROLE_SWAP bit in the PHY BMC TX Control register. Upon setting this bit, the TUSB422 generates
a FastRole swap pulse as defined by TFRSWAPTX parameter. The TUSB422 clears the TX_FAST_ROLE_SWAP
bit after it has completed the transmission.

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7.4 Device Functional Modes

7.4.1 Unattached Mode
Unattached mode is the primary mode of operation for the TUSB422 since a USB port can be unattached for a
lengthy period of time. In this mode, the TUSB422 may be configured as UFP (present Rd on both CC pins),
DFP (present Rp on both CC pins), or DRP (alternate between Rp and Rd on both CC pins) operation and
waiting for a connection. The TUSB422 remains in this mode until a connection is detected. Upon detection of a
connection, the INT_N pin will be asserted low.
In Unattached mode, VDD is available, and all IOs are operational. VCONN is disabled. USB PD BMC phy is
disabled.

7.4.2 Active Mode

The TUSB422 is in the Active mode when either CC1_STATE field or CC2_STATE field in the CC Status register
are non-zero, the TCPM has completed the required Type-C debounce of CC pins, and the TCPM has set the
AUTO_DISCHARGE_DISCONNECT in the Power Control register. In active mode, all IOs are operational, and
VCONN is available for an active cable. The USB PD phy can be enabled in this mode by setting the Receiver
Detect Register to a non-zero value. The USB PD BMC PHY functionality can only be used if the TUSB422 is in
any of the following active states: Attached.SRC, Attached.SNK, DebugAccessory, or PoweredAccessory. Use of
TUSB422 USB PD BMC PHY in any other active state is not permitted.

7.4.3 Power Role Swap

Upon entering the active mode, the power provider and consumer is determined by whether or not TUSB422 is
presenting a Rp or a Rd on CC pins. If TUSB422 is presenting a Rp, then TUSB422 is a power provider. If
TUSB422 is presenting a Rd, then TUSB422 is a power consumer. Once in the active mode, it may become
necessary change power role through performing a power role swap. Key requirements for performing a power
role swap by the software are listed below. For additional details on power role swap, consult the USB PD
specification.
Transition from power provider to power consumer:
1. TCPM state machine needs to transition from Attached.SRC to Attached.SNK.
2. Disable VBUS source. TCPM should send DisableSourceVbus command to TUSB422 Command register.
3. Once VBUS is at vSafe0V, disable AUTO_DISCHARGE_DISCONNECT in Power Control register and
change Role Control register to present a Rd.
4. Upon reception of PS_RDY message from port partner, update message header information and send
PS_RDY back to port partner.
5. Enable Sink VBUS and VBUS presence detection. TCPM should send SinkVbus and EnableVbusDetect
commands to TUSB422 Command register.
Transition from power consumer to power provider:
1. Disable AUTO_DISCHARGE_DISCONNECT in the Power Control register
2. Disable VBUS presence detection. TCPM should send DisableVbusDetect command to TUSB422 Command
register.
3. Disable system sink VBUS. TCPM should also send DisableSinkVbus command to TUSB422 Command
register.
4. TCPM state machine needs to transition from Attached.SNK to Attached.SRC.
5. Upon reception of PS_RDY message from port partner, change Role Control register to present a Rp.
6. Enable system source VBUS. TCPM should send SourceVbusDefaultVoltage command to TUSB422
Command register.
7. Once VBUS is at vSafe5V, the TCPM should update message header information and then send PS_RDY to
its port partner.
8. Upon successful completion of power-role swap, enable AUTO_DISCHARGE_DISCONNECT in the Power
Control register

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接下页)
Device Functional Modes (接

注
During Power-role swap, the TUSB422 will disable its VCONN. Software workaround is to
re-enable VCONN and issue error recovery for VCONN powered accessories. This may
result in momentary loss of video/data.

7.4.4 Debug Accessory

A Debug accessory is a device which presents Rd on both of TUSB422 CC pins or Rp on both of TUSB422 CC
pins. The TUSB422 upon detecting either of these two conditions on its CC pins performs the required Type-C
debounce. If either condition is still present at end of the debounce, the TUSB422 sets the
DEBUG_ACC_CONNECTED bit in the Power Status Register.
The TCPM is required to determine cable orientation by reading the CC1_STATE and CC2_STATE in the CC
Status register and writing the orientation to the PLUG_ORIENTATION bit in the TCPC Control register.

表 3. DebugAccessory Attached as a Sink

CC1_STATE CC2_STATE TCPM Writes to PLUG_ORIENTATION bit
2’b10 (Rd) 2’b01 (Ra) 1’b0. PD communication over CC1
2’b01 (Ra) 2’b10 (Rd) 1’b1. PD communication over CC2

表 4. DebugAccessory Attached as a Source

CC1_STATE CC2_STATE TCPM Writes to PLUG_ORIENTATION bit
Voltage is greater than CC2_STATE. Voltage is less than CC1_STATE. 1’b0. PD communication over CC1
Voltage is less than CC2_STATE Voltage is greater than CC1_STATE. 1’b1. PD communication over CC2

7.4.5 Dead Battery Mode

Low battery power could cause conditions in which communication over USB Type-C can no longer be
maintained. When this situation occurs, it is critical to transition to attached.SNK state so that power from VBUS
can be used to charge the battery back to an operational level. This condition is known as Dead Battery Mode.
The TUSB422 supports dead-battery mode by presenting Rd to both CC pins when VDD is no longer active.
In the dead-battery mode access to TUSB422 registers is not available. Upon exiting dead-battery mode, the
TUSB422 enters mode dictated by the value of Role Control register.

注
When exiting dead battery mode, the TUSB422's Rd is momentarily removed for about
100 µs during power up. This should not cause an issue in system since USB-C standard
requires 100 ms debounce on CC pins.

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7.5 Programming
The TUSB422 is controlled using I2C. The TUSB422 local I2C interface is available for reading/writing after
TINT_N_LOW after the device is powered up. The SCL and SDA terminals are used for I2C clock and I2C data
respectively.
图 5. TUSB422 I2C Addresses
7 (MSB) 6 5 4 3 2 1 0 (W/R)
0 1 0 0 0 0 0 0/1

TUSB422's Slave Address TUSB422's Register Offset Data written

S A6 A5 A4 A3 A2 A1 A0 0 A C7 C6 C5 C4 C3 C2 C1 C0 A D7 D6 D5 D4 D3 D2 D1 D0 A P

Start Write Ack Stop

图 6. I2C Write With Data

The following procedure should be followed to write data to TUSB422 I2C registers (refer to 图 6):
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB422 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB422 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB422) to be written, consisting of one byte of
data, MSB-first.
4. The TUSB422 acknowledges the sub-address cycle.
5. The master presents the first byte of data to be written to the I2C register.
6. The TUSB422 acknowledges the byte transfer
7. The master may continue presenting additional bytes of data to be written, with each byte transfer completing
with an acknowledge from the TUSB422.
8. The master terminates the write operation by generating a stop condition (P).
Data from offset 0x00
TUSB422's Slave Address or
last read address + 1

S A6 A5 A4 A3 A2 A1 A0 1 A D7 D6 D5 D4 D3 D2 D1 D0 A P

Start Read Ack Stop

图 7. I2C Read Without Repeated Start

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The following procedure should be followed to read the TUSB422 I2C registers without a repeated Start (refer 图
7).
1. The master initiates a read operation by generating a start condition (S), followed by the TUSB422 7-bit
address and a zero-value “W/R” bit to indicate a read cycle.
2. The TUSB422 acknowledges the 7-bit address cycle.
3. Following the acknowledge the master continues sending clock.
4. The TUSB422 transmit the contents of the memory registers MSB-first starting at register 00h or last read
sub-address+1. If a write to the I2C register occurred prior to the read, then the TUSB422 shall start at the
sub-address specified in the write.
5. The TUSB422 waits for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master after
each byte transfer; the I2C master acknowledges reception of each data byte transfer.
6. If an ACK is received, the TUSB422 transmits the next byte of data as long as master provides the clock. If a
NAK is received, the TUSB422 stops providing data and waits for a stop condition (P).
7. The master terminates the write operation by generating a stop condition (P).

TUSB422's Slave
TUSB422's Register Offset Xh
Address

C C C C C C C C
S A6 A5 A4 A3 A2 A1 A0 0 A A Sr
7 6 5 4 3 2 1 0

Start Write Ack Repeated Start

TUSB422's Slave Data from Register Xh

Address Data from Register Xh + 1

D D D D D D D D D D D D D D D D
S A6 A5 A4 A3 A2 A1 A0 1 A A A P
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0

Start Read Ack Stop

图 8. I2C Read With Repeated Start

The following procedure should be followed to read the TUSB422 I2C registers with a repeated Start (refer 图 8).
1. The master initiates a read operation by generating a start condition (S), followed by the TUSB422 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB422 acknowledges the 7-bit address cycle.
3. The master presents the sub-address (I2C register within TUSB422) to be written, consisting of one byte of
data, MSB-first.
4. The TUSB422 acknowledges the sub-address cycle.
5. The master presents a repeated start condition (Sr).
6. The master initiates a read operation by generating a start condition (S), followed by the TUSB422 7-bit
address and a one-value “W/R” bit to indicate a read cycle.
7. The TUSB422 acknowledges the 7-bit address cycle.
8. The TUSB422 transmit the contents of the memory registers MSB-first starting at the sub-address.
9. The TUSB422 shall wait for either an acknowledge (ACK) or a not-acknowledge (NACK) from the master
after each byte transfer; the I2C master acknowledges reception of each data byte transfer.
10. If an ACK is received, the TUSB422 transmits the next byte of data as long as master provides the clock. If
a NAK is received, the TUSB422 stops providing data and waits for a stop condition (P).
11. The master terminates the read operation by generating a stop condition (P).

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TUSB422's Slave Address TUSB422's Register Offset

S A6 A5 A4 A3 A2 A1 A0 0 A C7 C6 C5 C4 C3 C2 C1 C0 A P

Start Write Ack Stop

图 9. I2C Write Without Data

The following procedure should be followed for setting a starting sub-address for I2C reads (refer to 图 8).
1. The master initiates a write operation by generating a start condition (S), followed by the TUSB422 7-bit
address and a zero-value “W/R” bit to indicate a write cycle.
2. The TUSB422 acknowledges the address cycle.
3. The master presents the sub-address (I2C register within TUSB422) to be written, consisting of one byte of
data, MSB-first.
4. The TUSB422 acknowledges the sub-address cycle.
5. The master terminates the write operation by generating a stop condition (P).
After initial power-up, if no sub-addressing is included for the read procedure (refer to 图 8), then reads start at
register offset 00h and continue byte by byte through the registers until the I2C master terminates the read
operation. During a read operation, the TUSB422 auto-increments the I2C internal register address of the last
byte transferred independent of whether or not an ACK was received from the I2C master.

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7.6 Register Maps

表 5. Register Maps
ADDRESS REGISTER NAME RESET DEFINITION
0x00 VENDOR_ID_BYTE_0 0x51
0x01 VENDOR_ID_BYTE_1 0x04
0x02 PRODUCT_ID_BYTE_0 0x22
0x03 PRODUCT_ID_BYTE_1 0x04
0x04 DEVICE_ID_BYTE_0 0x00
0x05 DEVICE_ID_BYTE_1 0x01
0x06 USBTYPEC_REV_BYTE_0 0x11
0x07 USBTYPEC_REV_BYTE_1 0x00
0x08 USBPD_REV_VER_BYTE_0 0x11
0x09 USBPD_REV_VER_BYTE_1 0x20
0x0A PD_INTERFACE_REV_BYTE_0 0x10
0x0B PD_INTERFACE_REV_BYTE_1 0x10
0x0C .. 0x0F Reserved 0x00 Reserved
0x10 ALERT_BYTE_0 0x00
0x11 ALERT_BYTE_1 0x00
0x12 ALERT_MASK_BYTE_0 0xFFh
0x13 ALERT_MASK_BYTE_1 0x0F
0x14 POWER_STATUS_MASK 0xFF
0x15 FAULT_STATUS_MASK 0x7F
0x16 .. 0x17 Reserved 0x00 Reserved
0x18 CONFIG_STARDARD_OUTPUT 0x60
0x19 TCPC_CONTROL 0x00
0x1A ROLE_CONTROL 0x0A
0x1B FAULT_CONTROL 0x06
0x1C POWER_CONTROL 0x60
0x1D CC_STATUS 0x00
0x1E POWER_STATUS 0x00
0x1F FAULT_STATUS 0x00
0x20 .. 0x22 Reserved 0x00 Reserved
0x23 COMMAND 0x00
0x24 DEVICE_CAPABILITIES_1_BYTE_0 0x98
0x25 DEVICE_CAPABILITIES_1_BYTE_1 0x1E
0x26 DEVICE_CAPABILITIES_2_BYTE_0 0xC5
0x27 DEVICE_CAPABILITIES_2_BYTE_1 0x00
0x28 STANDARD_INPUT_CAPABILITIES 0x00
0x29 STANDARD_OUTPUT_CAPABILITIES 0x00
0x2A .. 0x2D Reserved 0x00 Reserved
0x2E MESSAGE_HEADER_INFO 0x02
0x2F RECEIVE_DETECT 0x00
Number of Bytes in the RECEIVE_BUFFER that are not
0x30 RECEIVE_BYTE_COUNT 0x00
stale.
Type of received frame (with a reference to a description
0x31 RX_BUF_FRAME_TYPE 0x00
of the register)
0x32 RX_BUF_HEADER_BYTE_0 0x00 Byte 0 (bits 7..0) of RX message header
0x33 RX_BUF_HEADER_BYTE_1 0x00 Byte 1 (bits 15..8) of RX message header
0x34 RX_BUF_OBJ1_BYTE_0 0x00 RX Byte 0 (bits 7..0) of 1st data object

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接下页)
Register Maps (接
表 5. Register Maps (接
接下页)
ADDRESS REGISTER NAME RESET DEFINITION
0x35 RX_BUF_OBJ1_BYTE_1 0x00 RX Byte 1 (bits 15..8) of 1st data object
0x36 RX_BUF_OBJ1_BYTE_2 0x00 RX Byte 2 (bits 23..16) of 1st data object
0x37 RX_BUF_OBJ1_BYTE_3 0x00 RX Byte 3 (bits 31..24) of 1st data object
0x38 RX_BUF_OBJ2_BYTE_0 0x00 RX Byte 0 (bits 7..0) of 2nd data object
0x39 RX_BUF_OBJ2_BYTE_1 0x00 RX Byte 1 (bits 15..8) of 2nd data object
0x3A RX_BUF_OBJ2_BYTE_2 0x00 RX Byte 2 (bits 23..16) of 2nd data object
0x3B RX_BUF_OBJ2_BYTE_3 0x00 RX Byte 3 (bits 31..24) of 2nd data object
0x3C RX_BUF_OBJ3_BYTE_0 0x00 RX Byte 0 (bits 7..0) of 3rd data object
0x3D RX_BUF_OBJ3_BYTE_1 0x00 RX Byte 1 (bits 15..8) of 3rd data object
0x3E RX_BUF_OBJ3_BYTE_2 0x00 RX Byte 2 (bits 23..16) of 3rd data object
0x3F RX_BUF_OBJ3_BYTE_3 0x00 RX Byte 3 (bits 31..24) of 3rd data object
0x40 RX_BUF_OBJ4_BYTE_0 0x00 RX Byte 0 (bits 7..0) of 4th data object
0x41 RX_BUF_OBJ4_BYTE_1 0x00 RX Byte 1 (bits 15..8) of 4th data object
0x42 RX_BUF_OBJ4_BYTE_2 0x00 RX Byte 2 (bits 23..16) of 4th data object
0x43 RX_BUF_OBJ4_BYTE_3 0x00 RX Byte 3 (bits 31..24) of 4th data object
0x44 RX_BUF_OBJ5_BYTE_0 0x00 RX Byte 0 (bits 7..0) of 5th data object
0x45 RX_BUF_OBJ5_BYTE_1 0x00 RX Byte 1 (bits 15..8) of 5th data object
0x46 RX_BUF_OBJ5_BYTE_2 0x00 RX Byte 2 (bits 23..16) of 5th data object
0x47 RX_BUF_OBJ5_BYTE_3 0x00 RX Byte 3 (bits 31..24) of 5th data object
0x49 RX_BUF_OBJ6_BYTE_1 0x00 RX Byte 1 (bits 15..8) of 6th data object
0x4A RX_BUF_OBJ6_BYTE_2 0x00 RX Byte 2 (bits 23..16) of 6th data object
0x4B RX_BUF_OBJ6_BYTE_3 0x00 RX Byte 3 (bits 31..24) of 6th data object
0x4C RX_BUF_OBJ7_BYTE_0 0x00 RX Byte 0 (bits 7..0) of 7th data object
0x4D RX_BUF_OBJ7_BYTE_1 0x00 RX Byte 1 (bits 15..8) of 7th data object
0x4E RX_BUF_OBJ7_BYTE_2 0x00 RX Byte 2 (bits 23..16) of 7th data object
0x4F RX_BUF_OBJ7_BYTE_3 0x00 RX byte 3 (bits 31..24) of 7th data object
0x50 TRANSMIT 0x00 Retry count and SOP* TX type
0x51 TRANSMIT_BYTE_COUNT 0x00 The number of bytes the TCPM will write
0x52 TX_BUF_HEADER_BYTE_0 0x00 Byte 0 (bits 7..0) of TX message header
0x53 TX_BUF_HEADER_BYTE_1 0x00 Byte 1 (bits 15..8) of TX message header
0x54 TX_BUF_OBJ1_BYTE_0 0x00 TX Byte 0 (bits 7..0) of 1st data object
0x55 TX_BUF_OBJ1_BYTE_1 0x00 TX Byte 1 (bits 15..8) of 1st data object
0x56 TX_BUF_OBJ1_BYTE_2 0x00 TX Byte 2 (bits 23..16) of 1st data object
0x57 TX_BUF_OBJ1_BYTE_3 0x00 TX Byte 3 (bits 31..24) of 1st data object
0x58 TX_BUF_OBJ2_BYTE_0 0x00 TX Byte 0 (bits 7..0) of 2nd data object
0x59 TX_BUF_OBJ2_BYTE_1 0x00 TX Byte 1 (bits 15..8) of 2nd data object
0x5A TX_BUF_OBJ2_BYTE_2 0x00 TX Byte 2 (bits 23..16) of 2nd data object
0x5B TX_BUF_OBJ2_BYTE_3 0x00 TX Byte 3 (bits 31..24) of 2nd data object
0x5C TX_BUF_OBJ3_BYTE_0 0x00 TX Byte 0 (bits 7..0) of 3rd data object
0x5D TX_BUF_OBJ3_BYTE_1 0x00 TX Byte 1 (bits 15..8) of 3rd data object
0x5E TX_BUF_OBJ3_BYTE_2 0x00 TX Byte 2 (bits 23..16) of 3rd data object
0x5F TX_BUF_OBJ3_BYTE_3 0x00 TX Byte 3 (bits 31..24) of 3rd data object
0x60 TX_BUF_OBJ4_BYTE_0 0x00 TX Byte 0 (bits 7..0) of 4th data object
0x61 TX_BUF_OBJ4_BYTE_1 0x00 TX Byte 1 (bits 15..8) of 4th data object
0x62 TX_BUF_OBJ4_BYTE_2 0x00 TX Byte 2 (bits 23..16) of 4th data object
0x63 TX_BUF_OBJ4_BYTE_3 0x00 TX Byte 3 (bits 31..24) of 4th data object

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接下页)
Register Maps (接
表 5. Register Maps (接
接下页)
ADDRESS REGISTER NAME RESET DEFINITION
0x64 TX_BUF_OBJ5_BYTE_0 0x00 TX Byte 0 (bits 7..0) of 5th data object
0x65 TX_BUF_OBJ5_BYTE_1 0x00 TX Byte 1 (bits 15..8) of 5th data object
0x66 TX_BUF_OBJ5_BYTE_2 0x00 TX Byte 2 (bits 23..16) of 5th data object
0x67 TX_BUF_OBJ5_BYTE_3 0x00 TX Byte 3 (bits 31..24) of 5th data object
0x68 TX_BUF_OBJ6_BYTE_0 0x00 TX Byte 0 (bits 7..0) of 6th data object
0x69 TX_BUF_OBJ6_BYTE_1 0x00 TX Byte 1 (bits 15..8) of 6th data object
0x6A TX_BUF_OBJ6_BYTE_2 0x00 TX Byte 2 (bits 23..16) of 6th data object
0x6B TX_BUF_OBJ6_BYTE_3 0x00 TX Byte 3 (bits 31..24) of 6th data object
0x6C TX_BUF_OBJ7_BYTE_0 0x00 TX Byte 0 (bits 7..0) of 7th data object
0x6D TX_BUF_OBJ7_BYTE_1 0x00 TX Byte 1 (bits 15..8) of 7th data object
0x6E TX_BUF_OBJ7_BYTE_2 0x00 TX Byte 2 (bits 23..16) of 7th data object
0x6F TX_BUF_OBJ7_BYTE_3 0x00 TX Byte 3 (bits 31..24) of 7th data object
0x70 VBUS_VOLTAGE_BYTE_0 0x00 LSB of VBUSIN measured voltage in 25mV steps.
0x71 VBUS_VOLTAGE_BYTE_1 0x00 MSB of VBUSIN measured voltage in 25mV steps.
VBUS_SINK_DISCONNECT_THRESH
0x72 0x00
OLD_BYTE_0
VBUS_SINK_DISCONNECT_THRESH
0x73 0x00
OLD_BYTE_1
VBUS_STOP_DISCHARGE_THRESH
0x74 0x00
OLD_BYTE_0
VBUS_STOP_DISCHARGE_THRESH
0x75 0x00
OLD_BYTE_1
VBUS_VOLTAGE_ALARM_HI_CFG_B
0x76 0x00
YTE_0
VBUS_VOLTAGE_ALARM_HI_CFG_B
0x77 0x00
YTE_1
VBUS_VOLTAGE_ALARM_LO_CFG_
0x78 0x00
BYTE_0
VBUS_VOLTAGE_ALARM_LO_CFG_
0x79 0x00
BYTE_1
0x7A .. 0x7F Reserved 0x00 Reserved
Vendor Defined Space (0x80 thru 0xFF)
0x80 .. 0x8F Reserved 0x00 Reserved.
0x90 Vendor Interrupt Status 0x00
0x92 Vendor Interrupt Mask 0x00
0x94 CC General Control 0x04
0x95 PHY BMC TX Control 0x00
0x96 PHY BMC RX Control 0x00
0x97 PHY BMC RX Status 0x00
0x98 VBUS and VCONN Control 0x00
0x99 OTSD Control 0x00
0x9A .. 0x9F Reserved 0x00
0xA0 LFO Timer Low 0x00
0xA1 LFO Timer High 0x00
0xA2 .. 0xFE Reserved 0x00 Reserved.
0xFF Page Select 0x00 Page Select

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7.6.1 CSR Registers

表 6. Register Definitions
ACCESS TAG NAME DESCRIPTION
R Read The field may be read by software
W Write The field may be written by software
S Set The field may be set by a write of one. Writes of zeros to the field have no effect.
C Clear The field may be cleared by a write of one. Write of zero to the field have no effect.
A Clear after Read The field will be cleared by hardware upon software reading from the field
U Update Hardware may autonomously update this field.
NA No Access Not accessible or not applicable

Unless otherwise noted, all undefined or reserved registers are read-only and return zeros when read. Also
unless otherwise noted, writes to undefined or reserved registers will be acknowledged but data will be
discarded.

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7.6.2 Vendor ID Byte 0 Register (address = 0x00) [reset = 0x51]

图 10. Vendor ID Byte 0 Register
7 6 5 4 3 2 1 0
VENDOR_ID_BYTE_0
R
LEGEND: R/W = Read/Write; R = Read only

表 7. Vendor ID Byte 0 Register Field Descriptions

Bit Field Type Reset Description
7:0 VENDOR_ID_BYTE_0 R 0x51 Byte 0 of a 16-bit USB-IF defined Texas Instruments vendor ID
of 0x0451.

7.6.3 Vendor ID Byte 1 Register (address = 0x01) [reset = 0x04]

图 11. Vendor ID Byte 1 Register
7 6 5 4 3 2 1 0
VENDOR_ID_BYTE_0
R
LEGEND: R/W = Read/Write; R = Read only

表 8. Vendor ID Byte 1 Register Field Descriptions

Bit Field Type Reset Description
7:0 VENDOR_ID_BYTE_1 R 0x04 Byte 1 of a 16-bit USB-IF defined Texas Instruments vendor ID
of 0x0451.

7.6.4 Product ID Byte 0 Register (address = 0x02) [reset = 0x22]

图 12. Product ID Byte 0 Register
7 6 5 4 3 2 1 0
PRODUCT_ID_BYTE_0
R
LEGEND: R/W = Read/Write; R = Read only

表 9. Product ID Byte 0 Register Field Descriptions

Bit Field Type Reset Description
7:0 PRODUCT_ID_BYTE_0 R 0x22 Byte 0 of a TUSB422 16-bit Product ID of 0x0422.

7.6.5 Product ID Byte 1 Register (address = 0x03) [reset = 0x04]

图 13. Product ID Byte 1 Register
7 6 5 4 3 2 1 0
PRODUCT_ID_BYTE_1
R
LEGEND: R/W = Read/Write; R = Read only

表 10. Product ID Byte 1 Register Field Descriptions

Bit Field Type Reset Description
7:0 PRODUCT_ID_BYTE_1 R 0x04 Byte 1 of a TUSB422 16-bit Product ID of 0x0422.

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7.6.6 Device ID Byte 0 Register (address = 0x04) [reset = 0x00]

图 14. Device ID Byte 0 Register
7 6 5 4 3 2 1 0
Device_ID_BYTE_0
R
LEGEND: R/W = Read/Write; R = Read only

表 11. Device ID Byte 0 Register Field Descriptions

Bit Field Type Reset Description
7:0 Device_ID_BYTE_0 R 0x00 Byte 0 of a 16-bit Device ID.

7.6.7 Device ID Byte 1 Register (address = 0x05) [reset = 0x01]

图 15. Device ID Byte 1 Register
7 6 5 4 3 2 1 0
Device_ID_BYTE_0
R
LEGEND: R/W = Read/Write; R = Read only

表 12. Device ID Byte 1 Register Field Descriptions

Bit Field Type Reset Description
7:0 Device_ID_BYTE_1 R 0x01 Byte 1 of a 16-bit Device ID.

7.6.8 USB Type-C Revision Byte 0 Register (address = 0x06) [reset = 0x11]
图 16. USB Type-C Revision Byte 0 Register
7 6 5 4 3 2 1 0
USBTYPEC_REV_BYTE_0
R
LEGEND: R/W = Read/Write; R = Read only

表 13. USB Type-C Revision Byte 0 Register Field Descriptions

Bit Field Type Reset Description
7:0 USBTYPEC_REV_BYTE_0 R 0x11 Byte 0 of a 16-bit USB Type-C Revision. Revision 1.1. The
TUSB422 also supports USB Type-C Revision 1.2.

7.6.9 USB Type-C Revision Byte 1 Register (address = 0x07) [reset = 0x00]
图 17. USB Type-C Revision Byte 1
7 6 5 4 3 2 1 0
USBTYPEC_REV_BYTE_1
R
LEGEND: R/W = Read/Write; R = Read only

表 14. USB Type-C Revision Byte 1 Descriptions

Bit Field Type Reset Description
7:0 USBTYPEC_REV_BYTE_1 R 0x00 Byte 1 of a 16-bit USB Type-C Revision.

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7.6.10 USB PD Revision Version Byte 0 Register (address = 0x08) [reset = 0x11]
图 18. USB PD Revision Version Byte 0
7 6 5 4 3 2 1 0
USBPD_REV_VER_BYTE_0
R
LEGEND: R/W = Read/Write; R = Read only

表 15. USB PD Revision Version Byte 0 Descriptions

Bit Field Type Reset Description
7:0 USBPD_REV_VER_BYTE_0 R 0x11 Byte 0 of a 16-bit USB PD version. Version 1.1.

7.6.11 USB PD Revision Version Byte 1 Register (address = 0x09) [reset = 0x20]
图 19. USB PD Revision Version Byte 1
7 6 5 4 3 2 1 0
USBPD_REV_VER_BYTE_1
R
LEGEND: R/W = Read/Write; R = Read only

表 16. USB PD Revision Version Byte 1 Descriptions

Bit Field Type Reset Description
7:0 USBPD_REV_VER_BYTE_1 R 0x20 Byte 1 of a 16-bit USB PD Revision. Revision 2.0.

7.6.12 PD Interface Revision Byte 0 Register (address = 0x0A) [reset = 0x10]

图 20. PD Interface Revision Byte 0
7 6 5 4 3 2 1 0
PD_INTERFACE_REV_BYTE_0
R
LEGEND: R/W = Read/Write; R = Read only

表 17. PD Interface Revision Byte 0 Descriptions

Bit Field Type Reset Description
7:0 PD_INTERFACE_REV_BYTE_0 R 0x10 Byte 0 of a 16-bit PD Interface (TCPC) Version. Version 1.0

7.6.13 PD Interface Revision Byte 1 Register (address = 0x0B) [reset = 0x10]

图 21. PD Interface Revision Byte 1
7 6 5 4 3 2 1 0
PD_INTERFACE_REV_BYTE_1
R
LEGEND: R/W = Read/Write; R = Read only

表 18. PD Interface Revision Byte 1 Descriptions

Bit Field Type Reset Description
7:0 PD_INTERFACE_REV_BYTE_1 R 0x10 Byte 1 of a 16-bit PD Interface (TCPC) Revision. Revision 1.0

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7.6.14 Alert Byte 0 Register (address = 0x10) [reset = 0x00]

This register is used to indicate a status change event. When a status change event occurs and its
corresponding Alert mask is unmasked, the TUSB422 will assert the INT_N low. The INT_N remains asserted
until all events are cleared by write of 1’b1. Once all events are cleared or corresponding Alert mask is masked,
the INT_N will be de-asserted high.
图 22. Alert Byte 0 Register
7 6 5 4 3 2 1 0
VBUS_ALARM TX_SOP_SUC TX_SOP_DISC TX_SOP_FAIL RX_HARD_RE RX_SOP_STA CC_STATUS CC_STATUS
_HI CESS ARD SET TUS
RCU RCU RCU RCU RCU RCU RCU RCU
LEGEND: R/W = Read/Write; R = Read only

表 19. Alert Byte 0 Register Descriptions

Bit Field Type Reset Description
VBUS Voltage Alarm Hi.
7 VBUS_ALARM_HI RCU 0 0b: Cleared
1b: A high-voltage alarm has occurred
Transmit SOP* Message Successful
0b: Cleared
6 TX_SOP_SUCCESS RCU 0 1b: Reset or SOP* message transmission successful. GoodCRC
response received on SOP* message transmission. Transmit
SOP* message buffer registers are empty.
Transmit SOP* Message Discarded
0b: Cleared
5 TX_SOP_DISCARD RCU 0 1b: Reset or SOP* message transmission not sent due to
incoming receive message. Transmit SOP* message buffer
registers are empty.
Transmit SOP* Message Failed
0b: Cleared
4 TX_SOP_FAIL RCU 0 1b: SOP* message transmission not successful, no GoodCRC
response received on SOP* message transmission. Transmit
SOP* message buffer registers are empty.
Received Hard Reset.
3 RX_HARD_RESET RCU 0 0b: Cleared.
1b: Received Hard Reset message
Receive SOP* Message Status.
Note RECEIVE_BYTE_COUNT being zero does not set this bit.
2 RX_SOP_STATUS RCU 0
0b: Cleared.
1b: Receive buffer register changed.
Power Status
1 PWR_STATUS RCU 0 0b: Cleared.
1b: Power Status Changed
CC Status.
0 CC_STATUS RCU 0 0b: Cleared
1b: CC status changed

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7.6.15 Alert Byte 1 Register (address = 0x11) [reset = 0x00]

This register is used to indicate a status change event. When a status change event occurs and its
corresponding Alert mask is unmasked, the TUSB422 will assert the INT_N low. The INT_N remains asserted
until all events are cleared by write of 1’b1. Once all events are cleared or corresponding Alert mask is masked,
the INT_N will be de-asserted high.
图 23. Alert Byte 1 Register
7 6 5 4 3 2 1 0
VENDOR_IRQ Reserved VBUS_SINK_D RX_BUF_OVR FAULT VBUS_ALARM
_STAT IS _LO
RCU R RCU RCU RCU RCU
LEGEND: R/W = Read/Write; R = Read only

表 20. Alert Byte 1 Register Descriptions

Bit Field Type Reset Description
This field is set if a Vendor defined interrupt that is unmasked is
set. TCPM SW should first clear the appropriate bit in Vendor
7 VENDOR_IRQ_STAT RCU 0 Interrupt Status register before clearing this field.
0b: Vendor IRQ not asserted.
1b: Vendor IRQ asserted.
6:4 Reserved R 0x0 Reserved
VBUS Sink Disconnect Detected.
0b: Cleared
3 VBUS_SINK_DIS RCU 0
1b: A VBUS Sink Disconnect Threshold crossing has been
detected
Rx Buffer Overflow 0b: TUSB422 Rx buffer is functioning
properly
2 RRX_BUF_OVR RCU 0 1b: TUSB422 Rx buffer has overflowed Writing 1 to this register
acknowledges the overflow. The overflow is cleared by writing to
ALERT.ReceiveSOP*MessageStatus
Fault
1 FAULT RCU 0 0b: No Fault
1b: A Fault has occurred. Read the FAULT_STATUS register
VBUS Voltage Alarm Lo
0 VBUS_ALARM_LO RCU 0 0b: Cleared
1b: A low-voltage alarm has occurred

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7.6.16 Alert Mask Byte 0 Register (address = 0x12) [reset = 0xFFh]

This register controls whether or not a status change event in Alert register will cause the INT_N to be asserted
low. When a specific event is masked, its corresponding status change event will not cause INT_N to be
asserted low.
图 24. Alert Mask Byte 0 Register
7 6 5 4 3 2 1 0
VBUS_ALARM TX_SOP_SUC TX_SOP_DISC TX_SOP_FAIL RX_HARD_RE RX_SOP_STA PWR_STATUS CC_STATUS_
_HI_MASK CESS_MASK ARD_MASK _MASK SET_MASK TUS_MASK _MASK MASK
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 21. Alert Mask Byte 0 Register Descriptions

Bit Field Type Reset Description
VBUS Voltage Alarm Hi
7 VBUS_ALARM_HI_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Transmit SOP* Message successful Interrupt Mask
6 TX_SOP_SUCCESS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Transmit SOP* Message discarded Interrupt Mask
5 TX_SOP_DISCARD_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Transmit SOP* Message failed Interrupt Mask
4 TX_SOP_FAIL_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Received Hard Reset Message Status Interrupt Mask
3 RX_HARD_RESET_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Receive SOP* Message Status Interrupt Mask
2 RX_SOP_STATUS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Power Status Interrupt Mask
1 PWR_STATUS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
CC Status Interrupt Mask
0 CC_STATUS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked

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7.6.17 Alert Mask Byte 1 Register (address = 0x13) [reset = 0x0F]

This register controls whether or not a status change event in Alert register will cause the INT_N to be asserted
low. When a specific event is masked, its corresponding status change event will not cause INT_N to be
asserted low.
图 25. Alert Mask Byte 1 Register
7 6 5 4 3 2 1 0
VBUS_AIRQ_M Reserved VBUS_SINK_D RX_BUF_OVR FAULT_MASK VBUS_ALARM
ASK IS_MASK _MASK _LO_MASK
R/W R R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 22. Alert Mask Byte 1 Register Descriptions

Bit Field Type Reset Description
Vendor Defined interrupt mask. . When this field is set to a 1’b1,
the unmasked vendor interrupts can cause INT_N to be
7 VBUS_IRO_MASK R/W 1 asserted.
0b: Interrupt masked
1b: Interrupt unmasked
6:4 Reserved R 0x0 Reserved
VBUS Sink Disconnect Detected Mask
3 VBUS_SINK_DIS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Rx Buffer Overflow Mask
2 RX_BUF_OVR_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Fault Mask
1 FAULT_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
VBUS Voltage Alarm Lo Mask
0 VBUS_ALARM_LO_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked

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7.6.18 Power Status Mask Register (address = 0x14) [reset = 0xFF]

图 26. Power Status Mask Register
7 6 5 4 3 2 1 0
DEBUG_ACCE TCPC_INIT_ST SRC_HIGH_VB SRC_VBUS_S VBUS_PRES_ VBUS_PRES_I VCONN_PRES SINK_VBUS_S
SSORY_MASK ATUS_MASK US_STATUS_ TATUS_MASK DET_STATUS_ NT_MASK _INT_MASK TATUS_INT_M
MASK MASK ASK
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 23. Power Status Mask Register Descriptions

Bit Field Type Reset Description
Debug Accessory Connected Mask
7 DEBUG_ACCESSORY_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
TCPC Initialization Status Mask
6 TCPC_INIT_STATUS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Sourcing High Voltage Status Interrupt Mask
SRC_HIGH_VBUS_STATUS_MAS
5 R/W 1 0b: Interrupt masked
K
1b: Interrupt unmasked
Sourcing VBUS Status Interrupt Mask
4 SRC_VBUS_STATUS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
VBUS Present Detection Status Interrupt Mask
VBUS_PRES_DET_STATUS_MAS
3 R/W 1 0b: Interrupt masked
K
1b: Interrupt unmasked
VBUS Present Status Interrupt Mask
2 VBUS_PRES_INT_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
VCONN Present Status Interrupt Mask
1 VCONN_PRES_INT_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Sinking VBUS Status Interrupt Mask
0 SINK_VBUS_STATUS_INT_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked

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7.6.19 FAULT Status Mask Register (address = 0x15) [reset = 0x7F]

图 27. FAULT Status Mask Register
7 6 5 4 3 2 1 0
Reserved FORCE_VBUS AUTO_DISC_F FORCE_DISC_ VBUS_OCP_F VBUS_OVP_F VCONN_OCP_ I2C_INT_ERR_
_MASK AIL_MASK FAIL_MASK AIL_STATUS_ AIL_STATUS_ FAULT_STATU STATUS_MAS
MASK MASK S_MASK K
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 24. FAULT Status Mask Register Descriptions

Bit Field Type Reset Description
7 Reserved R/W 0 Reserved
Force Off VBUS Interrupt Status Mask
6 FORCE_VBUS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Auto Discharge Failed Mask
5 AUTO_DISC_FAIL_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Force Discharge Failed Mask
4 FORCE_DISC_FAIL_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
Internal or External OCP VBUS Over Current Protection Fault
Interrupt Status Mask
3 VBUS_OCP_FAIL_STATUS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
For TUSB422 this field has no meaning.
Internal or External OVP VBUS Over Voltage Protection Fault
Interrupt Status Mask
2 VBUS_OVP_FAIL_STATUS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked
For TUSB422 this field has no meaning.
V(VCONN) Over Current Fault Interrupt Status Mask
VCONN_OCP_FAULT_STATUS_M
1 R/W 1 0b: Interrupt masked
ASK
1b: Interrupt unmasked
I2C Interface Error Interrupt Status Mask
0 I2C_INT_ERR_STATUS_MASK R/W 1 0b: Interrupt masked
1b: Interrupt unmasked

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7.6.20 Config Standard Output Register (address = 0x18) [reset = 0x60]

图 28. Config Standard Output
7 6 5 4 3 2 1 0
HIGH_Z_OUTP DEBUG_ACC_ AUDIO_ACC_C ACTIVE_CABL MUX_CTRL CONNECTION CONN_ORIEN
UTS CONNECTED# ONNECTED# E_CONNECTE _PRES T
D
R/W R/W R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 25. Config Standard Output Descriptions

Bit Field Type Reset Description
High Impedance outputs
0b: Standard output control (default)
7 HIGH_Z_OUTPUTS R/W 0 1b: Force all outputs to high impedance May be used to save
power in Sleep.
For TUSB422 this field has no meaning.
Debug Accessory Connected#
0b: Debug Accessory Connected# output is driven low
6 DEBUG_ACC_CONNECTED# R/W 1 1b: Debug Accessory Connected# output is driven high
Controlled by either the TCPM or TUSB422.
For TUSB422 this field has no meaning.
Audio Accessory Connected#
0b: Audio Accessory connected
5 AUDIO_ACC_CONNECTED# R/W 1
1b: No Audio Accessory connected (default)
For TUSB422 this field has no meaning.
Active Cable Connected
0b: No Active Cable connected (default)
4 ACTIVE_CABLE_CONNECTED R/W 0
1b: Active Cable connected
For TUSB422 this field has no meaning.
MUX Control 00b: No connection (default)
01b: USB3.1 Connected 10b: DP Alternate Mode – 4 lanes
3:2 MUX_CTRL R/W 0
11b: USB3.1 + Display Port Lanes 0 & 1
For TUSB422 this field has no meaning.
Connection Present
0b: No Connection (default)
1 CONNECTION_PRES R/W 0
1b: Connection Controlled by the TCPM.
For TUSB422 this field has no meaning.
Connector Orientation
0b: Normal (CC1=A5, CC2=B5, TX1=A2/A3, RX1=B10/B11)
0 CONN_ORIENT R/W 0 default
1b: Flipped (CC2=A5, CC1=B5, TX1=B2/B3, RX1=A10/A11) .
For TUSB422 this field has no meaning.

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7.6.21 TCPC Control Register (address = 0x19) [reset = 0x00]

图 29. TCPC Control Register
7 6 5 4 3 2 1 0
Reserved DEBUG_ACC_ I2C_CLOCK_STRETCHING_CT BIST_TEST_M PLUG_ORIENT
CTL L ODE ATION
R R/W R R R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 26. TCPC Control Register Descriptions

Bit Field Type Reset Description
7:5 Reserved R 000 Reserved
0b: Controlled by TUSB422 (power on default)
1b: Controlled by TCPM. The TCPM writes 1b to this register to
4 DEBUG_ACC_CTL R/W 0
take over control of asserting the DebugAccessoryConnected#.
This field has no meaning for TUSB422.
Clock Stretching Control
00b: Disable clock stretching. TUSB422 will not perform any
clock stretching during I2C transfers.
01b: Reserved
10b: Enable clock stretching. TUSB422 is allowed limited clock
3:2 I2C_CLOCK_STRETCHING_CTL R 00
stretching during each I2C Transfer.
11b: Enable clock stretching only if the Alert pin is not asserted.
As soon as Alert is asserted, clock stretching is disabled by the
TUSB422.
TUSB422 does not support clock stretching
Setting this bit to 1 is intended to be used only when a USB
compliance tester is using USB BIST Test Data to test the PHY
layer of the TUSB422. The TCPM should clear this bit when a
detach is detected.
1 BIST_TEST_MODE R/W 0 0: Normal Operation. Incoming messages enabled by
RECEIVE_DETECT passed to TCPM via Alert.
1: BIST Test Mode. Incoming messages enabled by
RECEIVE_DETECT result in GoodCRC response but will not be
passed to the TCPM via Alert.
0b: When VCONN is enabled, apply it to the CC2 pin. Monitor
the CC1 pin for BMC communications if PD messaging is
enabled.
0 PLUG_ORIENTATION R/W 0
1b: When VCONN is enabled, apply it to the CC1 pin. Monitor
the CC2 pin for BMC communications if PD messaging is
enabled.

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7.6.22 ROLE Control Register (address = 0x1A) [reset = 0x0A]

图 30. ROLE Control Register
7 6 5 4 3 2 1 0
Reserved. DRP RP_VALUE CC2 CC1
R R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 27. ROLE Control Register Descriptions

Bit Field Type Reset Description
7 Reserved R 0 Reserved.
0b: No DRP. Bits B3..0 determine Rp/Rd/Ra or open settings 1b:
6 DRP R/W 0
DRP
00b: Rp default current
01b: Rp 1.5 A
5:4 RP_VALUE R/W 00
10b: Rp 3 A
11b: Reserved
00b: Ra
01b: Rp (Use Rp definition in B5..4)
3:2 CC2 R/W 2’b10
10b: Rd
11b: Open (Disconnect or don’t care)
00b: Ra
01b: Rp (Use Rp definition in B5..4)
1:0 CC1 R/W 2’b10
10b: Rd
11b: Open (Disconnect or don’t care)

7.6.23 FAULT Control Register (address = 0x1B) [reset = 0x06]

图 31. FAULT Control Register
7 6 5 4 3 2 1 0
Reserved FORCE_OFF_ VBUS_DIS_FA VBUS_OCP_F VBUS_OVP_F Reserved
VBUS ULT_DETECT_ AULT AULT
TIMER
R R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 28. FAULT Control Register Descriptions

Bit Field Type Reset Description
7:5 Reserved R 0 Reserved
0b: Allow STANDARD INPUT SIGNAL Force Off VBUS control
(default)
4 FORCE_OFF_VBUS R/W 0
1b: Block STANDARD INPUT SIGNAL Force Off VBUS control.
This field has no meaning for TUSB422.
VBUS_DIS_FAULT_DETECT_TIME 0b: VBUS Discharge Fault Detection Timer enabled
3 R/W 0
R 1b: VBUS Discharge Fault Detection Timer disabled
0b: Internal and External OCP circuit enabled
2 VBUS_OCP_FAULT R/W 1 1b: Internal and External OCP circuit disabled
This field has no meaning for TUSB422.
0b: Internal and External OVP circuit enabled
1 VBUS_OVP_FAULT R/W 1 1b: Internal and External OVP circuit disabled
This field has no meaning for TUSB422.
0 Reserved R/W 0 Reserved

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7.6.24 Power Control Register (address = 0x1C) [reset = 0x60]

图 32. Power Control Register
7 6 5 4 3 2 1 0
Reserved VBUS_VOLTA DISABLE_VOL AUTO_DISCHA EN_BLEED_DI FORCE_DISC VCONN_PWR_ ENABLE_VCO
GE_MONITOR TAGE_ALARM RGE_DISCON SCHARGE HARGE SUPPORTED NN
S NECT
R R/W R/W R/W R/W RWU RWU R/W
LEGEND: R/W = Read/Write; R = Read only

表 29. Power Control Register Descriptions

Bit Field Type Reset Description
7 Reserved R 0 Reserved
0b: VBUS_VOLTAGE Monitoring is enabled.
1b: VBUS_VOLTAGE Monitoring is disabled.
6 VBUS_VOLTAGE_MONITOR R/W 1
Controls only VBUS VOLTAGE Monitoring. VBUS_VOLTAGE
will report all zeroes if disabled.
0b: Voltage Alarms Power status reporting is enabled
1b: Voltage Alarms Power status reporting is disabled
5 DISABLE_VOLTAGE_ALARMS R/W 1
Controls VBUS_VOLTAGE_ALARM_HI_CFG and
VBUS_VOLTAGE_ALARM_LO_CFG.
0b: The TUSB422 shall not automatically discharge VBUS
AUTO_DISCHARGE_DISCONNEC
4 R/W 0 based on VBUS voltage. (Default)
T
1b: The TUSB422 shall automatically discharge
0b: Disable bleed discharge
3 EN_BLEED_DISCHARGE R/W 0
1b: Enable bleed discharge of VBUS
When this field is set, the TUSB422 will discharge VBUS to
Vsafe0V or threshold programmed in the
VBUS_STOP_DISCHARGE_THRESHOLD register. Once VBUS
2 FORCE_DISCHARGE RWU 0 is discharged to desired level, the TUSB422 will disable the
Force Discharge.
0b: Disable forced discharge
1b: Enable forced discharge of VBUS.
0b: TUSB422 delivers at least 1W on VCONN
1 VCONN_PWR_SUPPORTED R/W 0 1b: TUSB422 delivers at least the power indicated in
DEVICE_CAPABILITIES.VCONNPowerSupported
0b: Disable VCONN Source
0 ENABLE_VCONN RWU 0 1b: Enable VCONN Source to CC indicated by
PLUG_ORIENTATION in TCPC Control register.

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7.6.25 CC Status Register (address = 0x1D) [reset = 0x00]

The CC pins are sampled based on the value CC_SAMPLE_RATE field but the TUSB422 will also immediately
sample the CC pins when software reads from this register unless PD is not idle.
图 33. CC Status Register
7 6 5 4 3 2 1 0
Reserved LOOKING4CO CONNECT_RE CC2_STATE CC1_STATE
NNECTION SULT
R RU RU RU RU
LEGEND: R/W = Read/Write; R = Read only

表 30. CC Status Register Descriptions

Bit Field Type Reset Description
7:6 Reserved R 0 Reserved
0b: TUSB422 is not actively looking for a connection. A
transition from '1' to '0' indicates a potential connection has been
5 LOOKING4CONNECTION RU 0 found.
1b: TUSB422 is looking for a connection (toggling as a DRP or
looking for a connection as Sink/Source only condition)
0b: the TUSB422 is presenting Rp
4 CONNECT_RESULT RU 0
1b: the TUSB422 is presenting Rd
If (ROLE_CONTROL.CC2=Rp) or (CONNECT_RESULT=0)
00b: SRC.Open (Open, Rp)
01b: SRC.Ra (below maximum vRa)
10b: SRC.Rd (within the vRd range)
11b: reserved
If (ROLE_CONTROL.CC2=Rd) or (CONNECT_RESULT=1)
00b: SNK.Open (Below maximum vRa)
01b: SNK.Default (Above minimum vRd-Connect)
10b: SNK.Power1.5 (Above minimum vRd-Connect) Detects Rp
3:2 CC2_STATE RU 00
1.5A
11b: SNK.Power3.0 (Above minimum vRd-Connect) Detects Rp
3.0A
If ROLE_CONTROL.CC2=Ra, this field is set to 00b
If ROLE_CONTROL.CC2=Open, this field is set to 00b
This field always returns 00b if (Looking4Connection=1) or
(POWER_CONTROL.ENABLE_VCONN=1 and
TCPC_CONTROL.PLUG_ORIENTATION =0). Otherwise, the
returned value depends upon ROLE_CONTROL.CC2.
If (ROLE_CONTROL.CC1 = Rp) or (CONNECT_RESULT=0)
00b: SRC.Open (Open, Rp)
01b: SRC.Ra (below maximum vRa)
10b: SRC.Rd (within the vRd range)
11b: reserved
If (ROLE_CONTROL.CC1 = Rd) or (CONNECT_RESULT=1)
00b: SNK.Open (Below maximum vRa)
01b: SNK.Default (Above minimum vRd-Connect)
10b: SNK.Power1.5 (Above minimum vRd-Connect) Detects Rp-
1:0 CC1_STATE RU 00
1.5A
11b: SNK.Power3.0 (Above minimum vRd-Connect) Detects Rp-
3.0A
If ROLE_CONTROL.CC1=Ra, this field is set to 00b
If ROLE_CONTROL.CC1=Open, this field is set to 00b
This field always returns 00b if (Looking4Connection=1) or
(POWER_CONTROL.ENABLE_VCONN=1 and
TCPC_CONTROL.PLUG_ORIENTATION =1). Otherwise, the
returned value depends upon ROLE_CONTROL.CC1.

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7.6.26 Power Status Register (address = 0x1E) [reset = 0x00]

图 34. Power Status Register
7 6 5 4 3 2 1 0
DEBUG_ACC_ TCPC_INIT_ST SOURCING_HI SOURCING_V VBUS_PRES_ VBUS_PRESE VCONN_PRES SINKING_VBU
CONNECTED ATUS GH_VOLTAGE BUS DETECT_ENA NT ENT S
BLED
RU RU RU RU RU RU RU RU
LEGEND: R/W = Read/Write; R = Read only

表 31. Power Status Register Descriptions

Bit Field Type Reset Description
0b: No Debug Accessory connected (default)
1b: Debug Accessory connected
Reflects the state of the DebugAccessoryConnected# output if
7 DEBUG_ACC_CONNECTED RU 0
supported. Even though the TUSB422 doesn’t have a debug
accessory pin, TUSB422will set this flag to 1 if a debug
accessory is detected.
0b: The TUSB422 has completed initialization and all registers
are valid.
1b: The TUSB422 is still performing internal initialization and the
6 TCPC_INIT_STATUS RU 0 only registers that will return the correct values are 00h..0Fh.
The TUSB422 will never set this flag so software needs to be
aware at power-up one reason for INT_N assertion is TUSB422
has completed its initialization.
0b: vSafe5V
1b: High Voltage
5 SOURCING_HIGH_VOLTAGE RU 0 This does not control the path, just provides a monitor of the
status. Assert as long as supplying voltage greater than
vSafe5V.
0b: Sourcing VBUS is disabled
1b: Sourcing VBUS is enabled
4 SOURCING_VBUS RU 0
This does not control the path, just provides a monitor of the
status.
0b: VBUS Present Detection Disabled (Default)
1b: VBUS Present Detection Enabled
3 VBUS_PRES_DETECT_ENABLED RU 0
Indicates if the TUSB422 is monitoring for VBUS Present or if
the circuit has been powered off
0b: VBUS Disconnected
1b: VBUS Connected
The TUSB422 shall report VBUS present when TUSB422
detects VBUS rises above 4 V. The TUSB422 shall report VBUS
is not present when TUSB422 detects VBUS falls below 3.5 V.
The TUSB422 may report VBUS is not present if VBUS is
2 VBUS_PRESENT RU 0
between 3.5 V and 4 V. When this field transitions from 1 to 0,
VBUS Sink Disconnect Threshold field is all zeros, and Auto
Discharge is enabled, the TUSB422 will discharge to vSafe0V.
VBUS present status may be invalid immediately after enabling
detection. Software needs to delay 1 polling period (~1ms) after
enabling detection before reading VBUS_PRESENT status.
0b: VCONN is not present
1 VCONN_PRESENT RU 0 1b: This bit is asserted when VCONN present CC1 or CC2.
Threshold is fixed at 2.4 V
0b: Sink is Disconnected
0 SINKING_VBUS RU 0
1b: TUSB422 is sinking VBUS to the system load

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7.6.27 Fault Status Register (address = 0x1F) [reset = 0x00]

图 35. Fault Status Register
7 6 5 4 3 2 1 0
Reserved FORCEOFF_V AUTO_DIS_FAI FORCE_DIS_F VBUS_OCP_F VBUS_OVP_F VCONN_OCP_ I2C_INT_ERR
BUS_STATUS L_STATUS AIL_STATUS AULT_STATUS AULT_STATUS FAULT_STATU OR_STATUS
S
R RCU RCU RCU RCU RCU RCU RCU
LEGEND: R/W = Read/Write; R = Read only

表 32. Fault Status Register Descriptions

Bit Field Type Reset Description
7 Reserved R 0 Shall be set to zero by sender and ignored by receiver
0b: No Fault Detected, no action (default and not supported)
1b: VBUS Source/Sink has been forced off due to external fault
6 FORCEOFF_VBUS_STATUS RCU 0 The TUSB422 has disconnected VBUS due to
STANDARD_INPUT.ForceOffVbus.
This field has no meaning for TUSB422
0b: No discharge failure
1b: Discharge commanded by the TCPM failed
5 AUTO_DIS_FAIL_STATUS RCU 0 If POWER_CONTROL.AutoDischargeDisconnect is set, the
TUSB422 will report discharge fails if VBUS is not below
vSafe0V within tSafe0V.
0b: No discharge failure
1b: Discharge commanded by the TCPM failed
4 FORCE_DIS_FAIL_STATUS RCU 0 If POWER_CONTROL.ForceDischarge is set, the TUSB422 will
report a discharge fails if VBUS is not below vSafe0V within
tSafe0V.
0b: Not in an over-current protection state
3 VBUS_OCP_FAULT_STATUS RCU 0 1b: Over-current fault latched
This field has no meaning for TUSB422
0b: Not in an over-voltage protection state
2 VBUS_OVP_FAULT_STATUS RCU 0 1b: Over-voltage fault latched.
This field has no meaning for TUSB422
The TUSB422 will set this flag if an VCONN over current fault is
detected. This flag will also get set if voltage on VCONN pin
drops between VCONN present threshold while the Vconn
1 VCONN_OCP_FAULT_STATUS RCU 0
switch is still closed.
0b: No Fault detected
1b: Over current VCONN fault latched
0b: No Error
0 I2C_INT_ERROR_STATUS RCU 0 1b: I2C error has occurred. A TRANSMIT has been sent with an
empty TRANSMIT_BUFFER.

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7.6.28 Command Register (address = 0x23) [reset = 0x00]

图 36. Command Register
7 6 5 4 3 2 1 0
COMMAND
RWU
LEGEND: R/W = Read/Write; R = Read only

表 33. Command Register Descriptions

Bit Field Type Reset Description
0001 0001b
WakeI2C. The TUSB422 will accept this command but will do
nothing with it.
0010 0010b
DisableVbusDetect. Disable Vbus present detection. v
0011 0011b
EnableVbusDetect. Enable Vbus present detection.
0100 0100b
DisableSinkVbus. The TUSB422 clears SINKING_VBUS bit in
Power Status register
0101 0101b
SinkVbus. If SNK_VBUS_SUPPORT bit is set, then TUSB422
will set SINKING_VBUS bit in Power Status register and enable
VBUS present detection.
0110 0110b
DisableSourceVbus. The TUSB422 will clear SOURCING_VBUS
and SOURCING_HIGH_VOLTAGE bits in Power Status register.
0111 0111b
SourceVbusDefaultVoltage. If SRC_VBUS_SUPPORT is set, the
TUSB422 will set SOURCING_VBUS in Power Status register
and will also enable VBUS present detection.
1000 1000b
SourceVbusHighVoltage. If SRC_VBUS_HIGH_SUPPORT is
set, then TUSB422 will set SOURCING_HIGH_VOLTAGE in
Power Status register.
7 COMMAND RWU 0x00 1001 1001b
Look4Connection. Start DRP Toggling if
ROLE_CONTROL.DRP=1b. If ROLE_CONTROL.CC1/CC2 =
01b start with Rp, if ROLE_CONTROL.CC1/CC2 =10b start with
Rd.
If ROLE_CONTROL.CC1/CC2 are not both 01b or 10b, then do
not start toggling. The TCPM shall issue
COMMAND.Look4Connection to enable the TUSB422 to restart
Connection Detection in cases where the ROLE_CONTROL
contents will not change. An example of this is when a potential
connection as a Source occurred but was further debounced by
the TCPM to find the Sink disconnected. In this case a Source
Only or DRP should go back to its Unattached.Src state. This
would result in ROLE_CONTROL staying the same.
TUSB422 to MAINTAIN_STATE
1010 1010b
RxOneMore. Configure the receiver to automatically clear the
RECEIVE_DETECT register after sending the next GoodCRC.
This is used to shutdown reception of packets at a known point
regardless of packet separation or the depth of the receive FIFO
in the TUSB422.
1100 1100b: Reserved. No Action
1101 1101b: Reserved. No Action
1110 1110b: Reserved. No Action
1111 1111b
I2C Idle. The TUSB422 will accept this command but will do
nothing with it.

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7.6.29 Device Capabilities 1 Byte 0 Register (address = 0x24) [reset = 0x98]

图 37. Device Capabilities 1 Byte 0
7 6 5 4 3 2 1 0
ROLES_SUPPORTED SOP_DBG_SU SRC_VCONN_ SNK_VBUS_S SRC_VBUS_HI SRC_VBUS_S
PPORT SUPPORT UPPORT GH_SUPPORT UPPORT
R R R R R R
LEGEND: R/W = Read/Write; R = Read only

表 34. Device Capabilities 1 Byte 0 Descriptions

Bit Field Type Reset Description
Roles Supported.
000b: Type-C Port Manager can configure the Port as Source
only or Sink only (not DRP)
001b: Source only.
010b: Sink only
7:5 ROLES_SUPPORTED R 100
011b: Sink with accessory support
100b: DRP only (Default for TUSB422)
101b: Source, Sink, DRP, Adapter/Cable all supported
110b: Source, Sink, DRP
111b: Not valid
SOP’_DBG/SOP”_DBG Support
0b: All SOP* except SOP’_DBG/SOP”_DBG
4 SOP_DBG_SUPPORT R 1
1b: All SOP* messages are supported
Configured in RECEIVE_DETECT and TRANSMIT
Source VCONN.
3 SRC_VCONN_SUPPORT R 1 0b: TUSB422 is not capable of switching VCONN
1b: TUSB422 is capable of switching VCONN
Sink VBUS.
0b: TUSB422 is not capable controlling the sink path to the
2 SNK_VBUS_SUPPORT R 0 system load
1b: TUSB422 is capable of controlling the sink path to the
system load
Source High Voltage VBUS.
0b: TUSB422 is not capable of controlling the source high
1 SRC_VBUS_HIGH_SUPPORT R 0 voltage path to VBUS
1b: TUSB422 is capable of controlling the source high voltage
path to VBUS
Source VBUS.
0b: TUSB422 is not capable of controlling the source path to
0 SRC_VBUS_SUPPORT R 0
VBUS
1b: TUSB422 is capable of controlling the source path to VBUS

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7.6.30 Device Capabilities 1 Byte 1 Register (address = 0x25) [reset = 0x1E]

图 38. Device Capabilities 1 Byte 1
7 6 5 4 3 2 1 0
Reserved VBUS_OCP_S VBUS_OVP_S BLEED_DISCH FORCE_DISC VBUS_MEASU SRC_RP_SUPPORT
UPPORT UPPORT ARGE_SUPPO HARGE_SUPP RE_ALARM_S
RT ORT UPPORT
R R R R R R R
LEGEND: R/W = Read/Write; R = Read only

表 35. Device Capabilities 1 Byte 1 Descriptions

Bit Field Type Reset Description
7 Reserved R 0 Reserved
VBUS OCP Reporting
6 VBUS_OCP_SUPPORT R 0 0b: VBUS OCP is not reported by the TUSB422
1b: VBUS OCP is reported by the TUSB422
VBUS OVP Reporting
5 VBUS_OVP_SUPPORT R 0 0b: VBUS OVP is not reported by the TUSB422
1b: VBUS OVP is reported by the TUSB422
Bleed Discharge
0b: No Bleed Discharge implemented in TUSB422
4 BLEED_DISCHARGE_SUPPORT R 1 1b: Bleed Discharge is implemented in the TUSB422
Support for POWER_CONTROL.EnableBleedDischarge
implemented
Force Discharge.
0b: No Force Discharge implemented in TUSB422
1b: Force Discharge is implemented in the TUSB422
3 FORCE_DISCHARGE_SUPPORT R 1 Support for POWER_CONTROL.ForceDischarge,
FAULT_STATUS.VbusDischargeFail,
FAULT_STATUS.VBUSDischargeFaultDetectionTimer, and
VBUS_STOP_DISCHARGE_THRESHOLD implemented
VBUS Measurement and Alarm Capable
0b: No VBUS voltage measurement nor VBUS Alarms
VBUS_MEASURE_ALARM_SUPP 1b; VBUS voltage measurement and VBUS Alarms
2 R 1
ORT Support for VBUS_VOLTAGE,
VBUS_VOLTAGE_ALARM_HI_CFG,
VBUS_VOLTAGE_ALARM_LO_CFG implemented
Source Resistor Supported
00b: Rp default only
01b: Rp 1.5 A and default
1:0 SRC_RP_SUPPORT R 10b 10b: Rp 3 A, 1.5 A, and default
11b: Reserved
Rp values which may be configured by the TCPM via the
ROLE_CONTROL register

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7.6.31 Device Capabilities 2 Byte 0 Register (address = 0x26) [reset = 0xC5]

图 39. Device Capabilities 2 Byte 0 Register
7 6 5 4 3 2 1 0
SINK_DISCON STOP_DISCHA VBUS_VOLTAGE_ALARM_LSB VCONN_PWR_SUPPORT VCONN_OC_F
NECT_DETEC RGE_THRESH AULT_SUPPO
T_SUPPORT OLD_SUPPOR RT
T
R R R R R
LEGEND: R/W = Read/Write; R = Read only

表 36. Device Capabilities 2 Byte 0 Register Descriptions

Bit Field Type Reset Description
Sink Disconnect Detection
SINK_DISCONNECT_DETECT_SU 0b: VBUS_SINK_DISCONNECT_THRESHOLD not
7 R 1
PPORT implemented
1b: VBUS_SINK_DISCONNECT_THRESHOLD implemented
Stop Discharge Threshold
STOP_DISCHARGE_THRESHOLD
6 R 1 0b: VBUS_STOP_DISCHARGE_THRESHOLD not implemented
_SUPPORT
1b: VBUS_STOP_DISCHARGE_THRESHOLD implemented
VBUS Voltage Alarm LSB.
00: TUSB422 has 25mV LSB for its voltage alarm and uses all
10 bits in VBUS_VOLTAGE_ALARM_HI_CFG and
VBUS_VOLTAGE_ALARM_LO_CFG.
01: TUSB422 has 50mV LSB for its voltage alarm and uses only
9 bits. VBUS_VOLTAGE_ALARM_HI_CFG[0] and
VBUS_VOLTAGE_ALARM_LO_CFG[0] are ignored by
5:4 VBUS_VOLTAGE_ALARM_LSB R 00
TUSB422.
10: TUSB422 has 100mV LSB for its voltage alarm and uses
only 8 bits. VBUS_VOLTAGE_ALARM_HI_CFG[1:0] and
VBUS_VOLTAGE_ALARM_LO_CFG[1:0] are ignored by
TUSB422.
11: reserved Support for VBUS_VOLTAGE_ALARM_LO_CFG
and VBUS_VOLTAGE_ALARM_HI implemented
VCONN Power Supported
000b: 1 W
001b: 1.5 W
010b: 2 W
3:1 VCONN_PWR_SUPPORT R 010 011b: 3 W
100b: 4 W
101b: 5 W
110b: 6 W
111b: External
VCONN Overcurrent Fault Capable.
0b: TUSB422 is not capable of detecting a VCONN fault
0 VCONN_OC_FAULT_SUPPORT R 1 1b: TUSB422 is capable of detecting a VCONN fault
Support for FAULT_STATUS.VCONNOverCurrentFault and
FAULT_CONTROL.VCONNOverCurrentFault implemented

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7.6.32 Device Capabilities 2 Byte 1 Register (address = 0x27) [reset = 0x00]

图 40. Device Capabilities 2 Byte 1 Register
7 6 5 4 3 2 1 0
Reserved
R
LEGEND: R/W = Read/Write; R = Read only

表 37. Device Capabilities 2 Byte 1 Register Descriptions

Bit Field Type Reset Description
7:0 Reserved R 0x00 Reserved

7.6.33 Standard Input Capabilities Register (address = 0x28) [reset = 0x00]

图 41. Standard Input Capabilities Register
7 6 5 4 3 2 1 0
Reserved EXT_VBUS_O EXT_VBUS_O EXT_FORCE_
VF_SUPPORT CF_SUPPORT OFF_VBUS_S
UPPORT
R R R R
LEGEND: R/W = Read/Write; R = Read only

表 38. Standard Input Capabilities Register Descriptions

Bit Field Type Reset Description
7:3 Reserved R 0 Reserved
VBUS External Over Voltage Fault
0b: Not present in TUSB422
2 EXT_VBUS_OVF_SUPPORT R 0
1b: Present in TUSB422
This field has no meaning for TUSB422
VBUS External Over Current Fault
0b: Not present in TUSB422
1 EXT_VBUS_OCF_SUPPORT R 0
1b: Present in TUSB422
This field has no meaning for TUSB422
Force Off VBUS (Source or Sink)
EXT_FORCE_OFF_VBUS_SUPPO 0b: Not present in TUSB422
0 R 0
RT 1b: Present in TUSB422
This field has no meaning for TUSB422

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7.6.34 Standard Output Capabilities Register (address = 0x29) [reset = 0x00]

图 42. Standard Output Capabilities Register
7 6 5 4 3 2 1 0
Reserved DEBUG_ACCE VBUS_PRESE AUDIO_ACCE ACTIVE_CABL MUX_OUT CONNECTION CONNECTOR_
SSORY_OUT NT_OUT SSORY_OUT E_OUT _OUT ORIENT_OUT
R R R R R R R R
LEGEND: R/W = Read/Write; R = Read only

表 39. Standard Output Capabilities Register Descriptions

Bit Field Type Reset Description
7 Reserved R 0 Reserved
Debug Accessory Indicator
6 DEBUG_ACCESSORY_OUT R 0 0b: Not present in TUSB422
1b: Present in TUSB422
VBUS Present Monitor
5 VBUS_PRESENT_OUT R 0 0b: Not present in TUSB422
1b: Present in TUSB422
Audio Adapter Accessory Indicator
4 AUDIO_ACCESSORY_OUT R 0 0b: Not present in TUSB422
1b: Present in TUSB422
Active Cable Indicator
3 ACTIVE_CABLE_OUT R 0 0b: Not present in TUSB422
1b: Present in TUSB422
MUX Configuration Control
2 MUX_OUT R 0 0b: Not present in TUSB422
1b: Present in TUSB422
Connection Present
1 CONNECTION_OUT R 0 0b: Not present in TUSB422
1b: Present in TUSB422
Connector Orientation
0 CONNECTOR_ORIENT_OUT R 0 0b: Not present in TUSB422
1b: Present in TUSB422

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7.6.35 Message Header Info Register (address = 0x2E) [reset = 0x02]

The TCPM may change the default values. After a detach, the TCPM must clear this field back to default setting.
图 43. Message Header Info Register
7 6 5 4 3 2 1 0
Reserved CABLE_PLUG DATA_ROLE USBPD_SPECREV POWER_ROLE
R/W R/W R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 40. Message Header Info Register Descriptions

Bit Field Type Reset Description
7:5 Reserved R/W 000 Shall be set to zero by sender and ignored by receiver
0b: Message originated from Source, Sink, or DRP
4 CABLE_PLUG R/W 0
1b: Message originated from a Cable Plug
0b: UFP
3 DATA_ROLE R/W 0
1b: DFP
00b: Revision 1.0
01b: Revision 2.0
10b: Revision 3.0
2:1 USBPD_SPECREV R/W 01 11b: Reserved
Even though this field defaults to Revision 2.0, the TUSB422
does support some PD 3.0 features like Fast Role swap and
chunked extended messages.
0b: Sink
0 POWER_ROLE R/W 0
1b: Source

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7.6.36 Receiver Detect Register (address = 0x2F) [reset = 0x00]

The TUSB422 will clear this register upon detect of a Hard Reset. The TUSB422 will not clear this register when
a disconnect is detected. The TCPM must clear this register after detecting a disconnect.
图 44. Receiver Detect Register
7 6 5 4 3 2 1 0
Reserved EN_CABLE_R EN_HARD_RE EN_SOP_DBG EN_SOP_DBG EN_SOPPP_M EN_SOPP_ME EN_SOP_MES
ESET SET PP P ESSAGE SSAGE SAGE
R RWU RWU RWU RWU RWU RWU RWU
LEGEND: R/W = Read/Write; R = Read only

表 41. Receiver Detect Register Descriptions

Bit Field Type Reset Description
7 Reserved R 0 Shall be set to zero by sender and ignored by receiver
0b: TUSB422 does not detect Cable Reset signaling
6 EN_CABLE_RESET RWU 0
1b: TUSB422 detects Cable Reset signaling
0b: TUSB422 does not detect Hard Reset signaling
5 EN_HARD_RESET RWU 0
1b: TUSB422 detects Hard Reset signaling
0b: TUSB422 does not detect SOP_DBG’’ message
4 EN_SOP_DBGPP RWU 0
1b: TUSB422 detects SOP_DBG’’ message
0b: TUSB422 does not detect SOP_DBG’ message
3 EN_SOP_DBGP RWU 0
1b: TUSB422 detects SOP_DBG’ message
0b: TUSB422 does not detect SOP’’ message
2 EN_SOPPP_MESSAGE RWU 0
1b: TUSB422 detects SOP’’ message
0b: TUSB422 does not detect SOP’ message
1 EN_SOPP_MESSAGE RWU 0
1b: TUSB422 detects SOP’ message
0b: TUSB422 does not detect SOP message
0 EN_SOP_MESSAGE RWU 0
1b: TUSB422 detects SOP message

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7.6.37 Receive Byte Count Register (address = 0x30) [reset = 0x00]

The TUSB422 clears this field to 0x00 upon reception or transmission of a Hard Reset ordered set or after a
disconnection is detected. The TUSB422 will also clear this field to 0x00 after the RX_SOP_STATUS bit in Alert
register is cleared. Software will use this register to determine the numbers of bytes in the Receiver Buffer Data
object.
图 45. Receive Byte Count Register
7 6 5 4 3 2 1 0
RECEIVE_BYTE_COUNT
RU
LEGEND: R/W = Read/Write; R = Read only

表 42. Receive Byte Count Register Descriptions

Bit Field Type Reset Description
Indicates number of bytes in this register that are not stale. The
TCPM should read the first RECEIVE_BYTE_COUNT bytes in
7:0 RECEIVE_BYTE_COUNT RU 0x00 this register. This is the number of bytes in the
RX_BUFFER_DATA_OBJECTS plus three (for the
RX_BUF_FRAME_TYPE and RX_BUF_HEADER).

7.6.38 Receive Buffer Frame Type Register (address = 0x31) [reset = 0x00]
图 46. Receive Buffer Frame Type Register
7 6 5 4 3 2 1 0
Reserved RX_SOP_MESSAGE
R RU
LEGEND: R/W = Read/Write; R = Read only

表 43. Receive Buffer Frame Type Register Descriptions

Bit Field Type Reset Description
7:3 Reserved R 0x00 Shall be set to zero by sender and ignored by receiver
000b: Received SOP
001b: Received SOP'
010b: Received SOP''
2:0 RX_SOP_MESSAGE RU 0x0 011b: Received SOP_DBG’
100b: Received SOP_DBG’’
110b: Received Cable Reset
All others are reserved.

7.6.39 Receive Buffer Header Byte 0 Register (address = 0x32) [reset = 0x00]
图 47. Receive Buffer Header Byte 0 Register
7 6 5 4 3 2 1 0
RX_BUF_HDR_BYTE_0
RU
LEGEND: R/W = Read/Write; R = Read only

表 44. Receive Buffer Header Byte 0 Descriptions

Bit Field Type Reset Description
7:0 RX_BUF_HDR_BYTE_0 RU 0x00 Byte 0 (bits 7:0) of USB PD message header.

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7.6.40 Receive Buffer Header Byte 1 Register (address = 0x33) [reset = 0x00]
图 48. Receive Buffer Header Byte 1 Register
7 6 5 4 3 2 1 0
RX_BUF_HDR_BYTE_1
RU
LEGEND: R/W = Read/Write; R = Read only

表 45. Receive Buffer Header Byte 1 Descriptions

Bit Field Type Reset Description
7:0 RX_BUF_HDR_BYTE_1 RU 0x00 Byte 1 (bits 15:8) of USB PD message header.

7.6.41 Receive Buffer Data Object 1 Through 7 Register (address = 0x34 through 0x4F) [reset = 0x00]
图 49. Receive Buffer Data Object 1 Through 7 Register
7 6 5 4 3 2 1 0
RX_BUFF_OBJx_BYTE_x
RU
LEGEND: R/W = Read/Write; R = Read only

表 46. Receive Buffer Data Object 1 Through 7 Descriptions

Bit Field Type Reset Description
7 RX_BUFF_OBJy_BYTE_x R 0x00 RX Byte x.

7.6.42 Transmit Register (address = 0x50) [reset = 0x00]

The TUSB422 clears this register after packet is transmitted regardless of outcome.
Before attempting to transmit a packet, the RX_SOP_STATUS alert flag must be cleared; otherwise, the packet
is discarded.
图 50. Transmit Register
7 6 5 4 3 2 1 0
Reserved RETRY_COUNTER Reserved TX_SOP_MESSAGE
R/W RWU R/W RWU
LEGEND: R/W = Read/Write; R = Read only

表 47. Transmit Register Descriptions

Bit Field Type Reset Description
7:6 Reserved R/W 00 Shall be set to zero by sender and ignored by receiver
00b: No message retry is required
01b: Automatically retry message transmission once
5:4 RETRY_COUNTER RWU 00
10b: Automatically retry message transmission twice
11b: Automatically retry message transmission three times
3 Reserved R/W 0 Shall be set to zero by sender, shall be ignored by receiver
000b: Transmit SOP
001b: Transmit SOP'
010b: Transmit SOP''
011b: Transmit SOP_DBG’
2:0 TX_SOP_MESSAGE RWU 000
100b: Transmit SOP_DBG’’
101b: Transmit Hard Reset
110b: Transmit Cable Reset
111b: Transmit BIST Carrier Mode 2

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7.6.43 Transmit Byte Count Register (address = 0x51) [reset = 0x00]

The TUSB422 clears this register after packet is transmitted regardless of outcome.
图 51. Transmit Byte Count Register
7 6 5 4 3 2 1 0
TX_BYTE_COUNT
RWU
LEGEND: R/W = Read/Write; R = Read only

表 48. Transmit Byte Count Register Descriptions

Bit Field Type Reset Description
The number of bytes the TCPM will write. This is the number of
7:0 TX_BYTE_COUNT RWU 0x00 bytes in the TX_BUFFER_DATA_OBJECTS plus two (for the
TX_BUF_HEADER)

7.6.44 Transmit Buffer Header Byte 0 Register (address = 0x52) [reset = 0x00]
图 52. Transmit Buffer Header Byte 0 Register
7 6 5 4 3 2 1 0
TX_BUF_HDR_BYTE_0
R/W
LEGEND: R/W = Read/Write; R = Read only

表 49. Transmit Buffer Header Byte 0 Register Descriptions

Bit Field Type Reset Description
7:0 TX_BUF_HDR_BYTE_0 R/W 0x00 Byte 0 (bits 7:0) of USB PD message header.

7.6.45 Transmit Buffer Header Byte 1 Register (address = 0x53) [reset = 0x00]
图 53. Transmit Buffer Header Byte 1 Register
7 6 5 4 3 2 1 0
TX_BUF_HDR_BYTE_1
R/W
LEGEND: R/W = Read/Write; R = Read only

表 50. Transmit Buffer Header Byte 1 Register Descriptions

Bit Field Type Reset Description
7:0 TX_BUF_HDR_BYTE_1 R/W 0x00 Byte 1 (bits 15:8) of USB PD message header.

7.6.46 Transmit Buffer Data Object 1 Through 7 Register (address = 0x54 through 0x6F) [reset = 0x00]

图 54. Transmit Buffer Data Object 1 Through 7 Register

7 6 5 4 3 2 1 0
TX_BUFF_OBJx_BYTE_x
R/W
LEGEND: R/W = Read/Write; R = Read only

表 51. Transmit Buffer Data Object 1 Through 7 Register Descriptions

Bit Field Type Reset Description
7:0 TX_BUFF_OBJx_BYTE_x R/W 0 TX Byte Data object 1 through 7.

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7.6.47 VBUS Voltage Byte 0 Register (address = 0x70) [reset = 0x00]

图 55. VBUS Voltage Byte 0 Register
7 6 5 4 3 2 1 0
VBUS_MEASUREMENT
RU
LEGEND: R/W = Read/Write; R = Read only

表 52. VBUS Voltage Byte 0 Descriptions

Bit Field Type Reset Description
10-bit measurement of (VBUS / Scale Factor) TCPM multiplies
this value by the scale factor to obtain the voltage measurement.
7:0 VBUS_MEASUREMENT RU 0x00
All Voltages shall meet ±2% absolute value or ±50 mV,
whichever is greater. The lsb is 25 mV.

7.6.48 VBUS Voltage Byte 1 Register (address = 0x71) [reset = 0x00]

图 56. VBUS Voltage Byte 1 Register
7 6 5 4 3 2 1 0
Reserved SCALE_FACTOR VBUS_MEASUREMENT[9:8]
R R RU
LEGEND: R/W = Read/Write; R = Read only

表 53. VBUS Voltage Byte 1 Register Descriptions

Bit Field Type Reset Description
7:4 Reserved R 0 Reserved.
00: VBUS measurement not scaled.
01: VBUS measurement divided by 2
3:2 SCALE_FACTOR R 0
10: VBUS measurement divided by 4
11: reserved
10-bit measurement of (VBUS / Scale Factor) TCPM multiplies
this value by the scale factor to obtain the voltage measurement.
1:0 VBUS_MEASUREMENT[9:8] RU 0
All Voltages shall meet ±2% absolute value or ±50 mV,
whichever is greater.

7.6.49 VBUS Sink Disconnect Threshold Byte 0 Register (address = 0x72) [reset = 0x00]
When this register is programmed to a non-zero value and AUTO_DISCHARGE_DISCONNECT is enabled, the
TUSB422 will use this field instead of VBUS_PRESENT to know when a detach has occurred and then
discharge to vSafe0V. This threshold register is disabled if programmed to zero.
图 57. VBUS Sink Disconnect Threshold Byte 0 Register
7 6 5 4 3 2 1 0
VBUS_SNK_DISC_THRESHOLD[7:0]
R/W
LEGEND: R/W = Read/Write; R = Read only

表 54. VBUS Sink Disconnect Threshold Byte 0 Register Descriptions

Bit Field Type Reset Description
VBUS_SNK_DISC_THRESHOLD[7: 10-bit for voltage threshold with 25 mV LSB. ±5% accuracy. A
7:0 R/W 0x00
0] value of B9:0=000h disables this threshold

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7.6.50 VBUS Sink Disconnect Threshold Byte 1 Register (address = 0x73) [reset = 0x00]
图 58. VBUS Sink Disconnect Threshold Byte 1 Register
7 6 5 4 3 2 1 0
Reserved VBUS_SNK_DISC_THRESHOL
D[9:8]
R R/W
LEGEND: R/W = Read/Write; R = Read only

表 55. VBUS Sink Disconnect Threshold Byte 1 Register Descriptions

Bit Field Type Reset Description
7:2 Reserved R 0x00 Reserved
VBUS_SNK_DISC_THRESHOLD[9: 10-bit for voltage threshold with 25 mV LSB. (Default vSafe5V)
1:0 R/W 00
8] ±5% accuracy. A value of B9:0=000h disables this threshold

7.6.51 VBUS Stop Discharge Threshold Byte 0 Register (address = 0x74) [reset = 0x00]
When VBUS Stop Discharge Threshold register is programmed to a non-zero value and TUSB422 is a VBUS
Source, the TUSB422 will discharge to value programmed into this register. If this register is programmed to all
zeros, then TUSB422 will discharge to vSafe0V. If Software requires discharge to voltage other than vSafe0V,
then software must program this register to desired voltage. When TUSB422 is a VBUS Sink and a detach
occurs, discharge will always stop at vSafe0V.
图 59. VBUS Stop Discharge Threshold Byte 0 Register
7 6 5 4 3 2 1 0
VBUS_STOP_DISCHARGE_THRESHOLD[7:0]
R/W
LEGEND: R/W = Read/Write; R = Read only

表 56. VBUS Stop Discharge Threshold Byte 0 Register Descriptions

Bit Field Type Reset Description
VBUS_STOP_DISCHARGE_THRE 10-bit for voltage threshold with 25 mV LSB.
7:0 R/W 0x00
SHOLD[7:0]

7.6.52 VBUS Stop Discharge Threshold Byte 1 Register (address = 0x75) [reset = 0x00]
图 60. Stop Discharge Threshold Byte 1 Register
7 6 5 4 3 2 1 0
Reserved VBUS_STOP_DISCHARGE_TH
RESHOLD[9:8]
R R/W
LEGEND: R/W = Read/Write; R = Read only

表 57. VBUS Stop Discharge Threshold Byte 1 Register Descriptions

Bit Field Type Reset Description
7:2 Reserved R 0x00 Reserved
VBUS_STOP_DISCHARGE_THRE 10-bit for voltage threshold with 25 mV LSB.
1:0 R/W 00
SHOLD[9:8]

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7.6.53 VBUS Voltage Alarm High Config Byte 0 Register (address = 0x76) [reset = 0x00]
This register contains the lower 8 bits of the 10-bit VBUS Voltage Alarm High Configuration register. When
DISABLE_VOLTAGE_ALARMS = 1’b0, a VBUS voltage higher than value programmed into this register will
cause VBUS_ALARM_HI alert flag to get set. This threshold is always enabled. SW needs to program to a value
greater than VBUS to prevent VBUS_ALARM_HI alert from continuously being set.
图 61. VBUS Voltage Alarm High Config Byte 0 Register
7 6 5 4 3 2 1 0
VBUS_ALARM_HIGH_THRESHOLD[7:0]
R/W
LEGEND: R/W = Read/Write; R = Read only

表 58. VBUS Voltage Alarm High Config Byte 0 Register Descriptions

Bit Field Type Reset Description
ReservedVBUS_ALARM_HIGH_TH 10-bit for voltage threshold with 25 mV LSB. ±5% accuracy.
7:0 R/W 0x00
RESHOLD[7:0]

7.6.54 VBUS Voltage Alarm High Config Byte 1 Register (address = 0x77) [reset = 0x00]
This register contains the upper two bits of the 10-bit VBUS Voltage Alarm High Configuration register. When
DISABLE_VOLTAGE_ALARMS = 1’b0, a VBUS voltage higher than value programmed into this register will
cause VBUS_ALARM_HI alert flag to get set. This threshold is always enabled. SW needs to program to a value
greater than VBUS to prevent VBUS_ALARM_HI alert from continuously being set.
图 62. VBUS Voltage Alarm High Config Byte 1 Register
7 6 5 4 3 2 1 0
Reserved VBUS_ALARM_HIGH_THRESH
OLD[9:8]
R R/W
LEGEND: R/W = Read/Write; R = Read only

表 59. VBUS Voltage Alarm High Config Byte 1 Register Descriptions

Bit Field Type Reset Description
7:2 Reserved R 0x00 Reserved
VBUS_ALARM_HIGH_THRESHOL 10-bit for voltage threshold with 25 mV LSB. ±5% accuracy.
1:0 R/W 0x00
D[9:8]

7.6.55 VBUS Voltage Alarm Low Config Byte 0 Register (address = 0x78) [reset = 0x00]
This register contains the lower 8 bits of the 10-bit VBUS Voltage Alarm Low Configuration register. When
DISABLE_VOLTAGE_ALARMS = 1’b0, a VBUS voltage lower than value programmed into this register will
cause VBUS_ALARM_LO alert flag to get set.
图 63. VBUS Voltage Alarm Low Config Byte 0 Register
7 6 5 4 3 2 1 0
VBUS_ALARM_LOW_THRESHOLD[7:0]
R/W
LEGEND: R/W = Read/Write; R = Read only

表 60. VBUS Voltage Alarm Low Config Byte 0 Register Descriptions

Bit Field Type Reset Description
VBUS_ALARM_LOW_THRESHOL 10-bit for voltage threshold with 25 mV LSB. ±5% accuracy.
7:0 R/W 0x00
D[7:0]

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7.6.56 VBUS Voltage Alarm Low Config Byte 1 Register (address = 0x79) [reset = 0x00]
This register contains the upper two bits of the 10-bit VBUS Voltage Alarm Low Configuration register. When
DISABLE_VOLTAGE_ALARMS = 1’b0, a VBUS voltage lower than value programmed into this register will
cause VBUS_ALARM_LO alert flag to get set.
图 64. VBUS Voltage Alarm Low Config Byte 1 Register
7 6 5 4 3 2 1 0
Reserved VBUS_ALARM_LOW_THRESH
OLD[9:8]
R R/W
LEGEND: R/W = Read/Write; R = Read only

表 61. VBUS Voltage Alarm Low Config Byte 1 Register Descriptions

Bit Field Type Reset Description
7:2 Reserved R 0x00 Reserved
VBUS_ALARM_LOW_THRESHOL 10-bit for voltage threshold with 25 mV LSB. ±5% accuracy.
1:0 R/W 0x00
D[9:8]

7.6.57 Vendor Interrupts Status Register (address = 0x90) [reset = 0x00]

图 65. Vendor Interrupts Status Register
7 6 5 4 3 2 1 0
Reserved LFO_TIMER_S CC_FAULT OTSD_STAT Reserved
TAT
R RCU RCU R R
LEGEND: R/W = Read/Write; R = Read only

表 62. Vendor Interrupts Status Register Descriptions

Bit Field Type Reset Description
7:5 Reserved R 0000 Reserved
0b: LFO Timer not expired or disabled.
4 LFO_TIMER_STAT RCU 0
1b: LFO Timer expired.
Set when TUSB422 detects CC pin greater than 3.5 V in
unattached state. This typically will indicate a CC to VBUS short.
3 CC_FAULT RCU 0
0b: CC Fault not detected.
1b: CC Fault detected
0b: OTSD not detected.
2 OTSD_STAT RCU 0
1b: OTSD detected.
1:0 Reserved R 0 Reserved

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7.6.58 Vendor Interrupts Mask Register (address = 0x92) [reset = 0x00]

图 66. Vendor Interrupts Mask Register
7 6 5 4 3 2 1 0
Reserved LFO_TIMER_M CC_FAULT_M OTSD_MASK Reserved
ASK ASK
R R/W R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 63. Vendor Interrupts Mask Register Descriptions

Bit Field Type Reset Description
7:5 Reserved R 000 Reserved
0b: Interrupt masked.
4 LFO_TIMER_MASK R/W 0
1b: Interrupt unmasked
0b: Interrupt masked.
3 CC_FAULT_MASK R/W 0
1b: Interrupt unmasked
0b: Interrupt masked.
2 OTSD_MASK R/W 0
1b: Interrupt unmasked
1:0 Reserved R/W 0 Reserved

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7.6.59 CC General Control Register (address = 0x94) [reset = 0x04]

图 67. CC General Control Register
7 6 5 4 3 2 1 0
ALERT_CLEAR PD_TXRX_RE GLOBAL_SW_ AUTO_DRP_S CC_SAMPLE_RATE DRP_DUTY_CYCLE
_READ SET RESET AMPLE_CTL
R R/W
LEGEND: R/W = Read/Write; R = Read only

表 64. CC General Control Register Descriptions

Bit Field Type Reset Description
This field controls whether Status registers are cleared by write
of 1’b0 (RCU) or are cleared after reading them (RAU). The
registers affected by this field as the following: Alert Byte 0, Alert
Byte 1, Fault Status, and Vendor Interrupts Status registers. The
7 ALERT_CLEAR_READ R 0 RX_SOP_STATUS in Alert register is not affected by this
register.
0 – Alert Status flags are cleared by write of 1’b1 (RCU).
1 – Alert Status flags are cleared after reading corresponding
status register (RAU).
When SW writes this field with a 1’b1, TUSB422 PD TX and RX
state machines is reset . The TUSB422 clears this field upon
reset completion. The TUSB422 behavior is similar to receiving
6 PD_TXRX_RESET R/W 0
a hard reset message.
0b: Normal.
1b: PD_TXRX reset.
When SW writes this field with a 1’b1, the TUSB422’s will be
reset, CSRs included, to power-on defaults. The TUSB422 will
clear this field upon reset completion. SW must reinitialize the
5 GLOBAL_SW_RESET R/W 0
TUSB422 upon completion of Global reset
0b: Normal.
1b: Global Reset.
When TUSB422 is enabled for autonomous DRP toggle, this
field controls when CC pins are sampled while unattached.
4 AUTO_DRP_SAMPLE_CTL R/W 0 0b: Continuously checks CC pins based on CC_SAMPLE_RATE
field.
1b: Only checks CC pins just before Role toggle.
This field controls the TUSB422 CC pins sample rate.
00b: 1 ms (typ)
3:2 CC_SAMPLE_RATE R/W 01 01b: 2 ms (typ)
10b: 8 ms (typ)
11b: 16 ms (typ)
Percent of time that DRP advertises DFP during t DRP.
00b: 30% (typ)
1:0 DRP_DUTY_CYCLE R/W 00 01b: 10% (typ)
10b: 50% (typ)
11b: 60% (typ)

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7.6.60 PHY BMC TX Control Register (address = 0x95) [reset = 0x00]

图 68. PHY BMC TX Control Register
7 6 5 4 3 2 1 0
Reserved TX_CARRIER_ TX_FAST_ROL Reserved
MODE2_SEL E_SWAP
R R/W RSU R
LEGEND: R/W = Read/Write; R = Read only

表 65. PHY BMC TX Control Register Descriptions

3 Field Type Reset Description
7:3 Reserved R 0 Reserved
0b: TX BIST Carrier Mode 2 only for tBISTContMode
2 TX_CARRIER_MODE2_SEL R/W 0
1b: TX BIST Carrier Mode 2 continuously.
0b: Normal operation.
1 TX_FAST_ROLE_SWAP RSU 0
1b: TX a Fast Role Swap.
0 Reserved R 0 Reserved

7.6.61 PHY BMC RX Control Register (address = 0x96) [reset = 0x00]

图 69. PHY BMC RX Control Register
7 6 5 4 3 2 1 0
Reserved Reserved VIX_PD_OVER VIX_PD
RIDE
R R/W R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 66. PHY BMC RX Control Register Descriptions

Bit Field Type Reset Description
7:4 Reserved R 0 Reserved
3 Reserved R/W 0 Reserved
0b: BMC RX threshold is controlled by POWER_ROLE field.
2 VIX_PD_OVERRIDE R/W 0
1b: BMC RX threshold is control by value of VIX_PD field.
00b: BMC RX set to VIH(PD_SNK) and VIL(PD_SNK).
01b: BMC RX set to VIH(PD_SRC) and VIL(PD_SRC).
1:0 VIX_PD R/W 00
10b: BMC RX set to VIH(PD_NEU) and VIL(PD_NEU).
11b: BMC RX set to VIH(PD_SNK) and VIL(PD_SRC).

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7.6.62 PHY BMC RX Status Register (address = 0x97) [reset = 0x00]

图 70. PHY BMC RX Status Register
7 6 5 4 3 2 1 0
Reserved RX_PREAMBL RX_CRC_OK_ RX_EOP_STA RX_SOP_STA
E_STAT STAT T T
R RU RU RU RU
LEGEND: R/W = Read/Write; R = Read only

表 67. PHY BMC RX Status Register Descriptions

Bit Field Type Reset Description
7:4 Reserved R 0 Reserved
0b: Preamble not received.
3 RX_PREAMBLE_STAT RU 0
1b: Preamble received.
0b: CRC not ok.
2 RX_CRC_OK_STAT RU 0
1b: CRC ok.
0b: EOP not received
1 RX_EOP_STAT RU 0
. 1b: EOP received.
0b: SOP not received
0 RX_SOP_STAT RU 0
1b: SOP received.

7.6.63 VBUS and VCONN Control Register (address = 0x98) [reset = 0x00]
图 71. VBUS and VCONN Control Register
7 6 5 4 3 2 1 0
Reserved INT_VCONNDI INT_VBUSDIS_
S_DISABLE DISABLE
R R/W R/W
LEGEND: R/W = Read/Write; R = Read only

表 68. VBUS and VCONN Control Descriptions

Bit Field Type Reset Description
7:2 Reserved R 0 Reserved
When a VCONN discharge condition occurs, this register
controls whether TUSB422 internal VCONN discharge circuit is
used or not. When not used, it is assumed that VCONN
1 INT_VCONNDIS_DISABLE R/W 0
discharge is handled external to TUSB422.
0b: Internal VCONN discharge enable
1b: Internal VCONN discharge disabled.
When a VBUS discharge condition occurs, this register controls
whether TUSB422 internal VBUS discharge circuit is used or
not. When not used, it is assumed that VBUS discharge is
0 INT_VBUSDIS_DISABLE R/W 0
handled external to TUSB422.
0b: Internal VBUS discharge enable
1b: Internal VBUS discharge disabled.

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7.6.64 OTSD Control Register (address = 0x99) [reset = 0x00]

图 72. OTSD Control Register
7 6 5 4 3 2 1 0
Reserved OTSD_RAW_S Reserved OTSD_EN
TATUS
R RU R R/W
LEGEND: R/W = Read/Write; R = Read only

表 69. OTSD Control Register Descriptions

Bit Field Type Reset Description
7:5 Reserved R 0 Reserved
4 OTSD_RAW_STATUS RU 0 This field represents the raw status of the OTSD.
3:1 Reserved R 0 Reserved
0b: Disabled
0 OTSD_EN R/W 0
1b: Enabled

7.6.65 LFO Timer Low Register (address = 0xA0) [reset = 0x00]

The value programmed into 16-bit LFP timer will not get applied until LFO Timer High register is written. The
value of this register will always return the value written to it; and therefore, after the timer is enabled this register
will not reflect the actual LFP timer value.
图 73. LFO Timer Low Register
7 6 5 4 3 2 1 0
LFO_TIMER_LO
R/W
LEGEND: R/W = Read/Write; R = Read only

表 70. LFO Timer Low Register Descriptions

Bit Field Type Reset Description
Lower 8-bits of the 16-bit LFO Timer. When LFO timer is set to a
non-zero value, the timer is enabled and start counting to zero.
7:0 LFO_TIMER_LO R/W 0x00 Upon reaching zero, the LFO_TIMER_STAT flag is set. Timer
can be disabled by programming LFP_TIMER to zero. LSB is
1000 µs.

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7.6.66 LFO Timer High Register (address = 0xA1) [reset = 0x00]

The value programmed into 16-bit LFP timer will not get applied until LFO Timer High register is written. The
value of this register will always return the value written to it and therefore after the timer is enabled this register
will not reflect the actual LFP timer value.
图 74. LFO Timer High Register
7 6 5 4 3 2 1 0
LFO_TIMER_HI
R/W
LEGEND: R/W = Read/Write; R = Read only

表 71. LFO Timer High Register Descriptions

Bit Field TypeW Reset Description
Upper 8-bits of the 16-bit LFO Timer. When LFO timer is set to a
non-zero value, the timer is enabled and start counting to zero.
7:0 LFO_TIMER_HI R/W 0x00
Upon reaching zero, the LFO_TIMER_STATUS flag is set. Timer
can be disabled by programming LFP_TIMER to zero.

7.6.67 Page Select Register (address = 0xFF) [reset = 0x00]

图 75. Page Select Register
7 6 5 4 3 2 1 0
Reserved PAGE_SELEC
T
R R/W
LEGEND: R/W = Read/Write; R = Read only

表 72. Page Select Register Descriptions

Bit Field Type Reset Description
7:1 Reserved R 0 Reserved
0b: Page 0
0 PAGE_SELECT R/W 0
1b: Page 1 (TI Test Registers)

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8 Application and Implementation

注
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

8.1 Application Information

图 76 is for the TUSB422 in WLCSP package configured in DRP mode.

8.2 Typical Application

Battery
Charger Csnkpd
VBAT

VCHARGE_EN#

VBUS
DC/DC
Boost
Csnk

VCHARGE_EN# VSAFE5V_EN
VDDIO_1.8V CVCONN
VSAFE5V_EN
VCONN

VBUS_DET
SCL

Receptacle
Type-C
SDA TUSB422 CC1
SoC
(9-pin WCSP)
INT_N CC2

VDD CRX_SHUNT CRX_SHUNT

VBAT GND

0.1uF

图 76. TUSB422 in DRP Application

8.2.1 Design Requirements

For this design example, use the parameters shown in 表 73.

表 73. Design Parameters

PARAMETER VALUE
VDD supply (2.7 V to 5.5 V) VBAT
V(CC1/CC2), Minimum Voltage on CC1/CC2 when VCONN switch is
3V
closed.
Minimum V(VCONN) power 1 Watt
2
I C Level (1.8 V or 3.3 V) 1.8 V
Max I2C bus capacitance 150 pF
I2C Speed (400 KHz or 1 MHz). 400 KHz
External pull-up resistor on SDA and SCL. 1.5 KΩ
External pull-up resistor on INT_N 200 KΩ
CRX_SHUNT (200 pF to 450 pF) 220 pF
C(VCONN) 10 µF

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8.2.2 Detailed Design Procedure

The TUSB422 supports a large VDD supply range allowing it to be powered from an external battery (VBAT).
The TUSB422 I2C slave interface supports up to 1 MHz (Fast Mode+) at either 1.8 V or 3.3 V signal levels.
Depending on the signaling level of the I2C master, the TUSB422 SDA and SCL should be pulled up to either 1.8
V or 3.3 V. For this particular example, the SDA and SCL are pulled up to 1.8 V. The actual pullup resistor value
chosen is based maximum I2C bus capacitance and the maximum I2C frequency. A 1.5 KΩ resistor was chosen
to support a 150 pF maximum I2C bus capacitance and a 400 KHz I2C clock.
The INT_N pin is used by the TUSB422 to communicate events to software running on an external CPU. This pin
requires an external pull-up resistor to 1.8 V, 3.3 V, or TUSB422 VDD supply. Typically, INT_N is pulled up to the
same supply as the SDA and SCL pins. The recommend pull-up value is 200 KΩ.
The USB Type-C specification uses VCONN to power Type-C active cables and cable plugs. The minimum
VCONN power mandated by the specification is 1 W. The TUSB422 incorporates an internal switch to route
power from VCONN pin to one of the CC pins (CC1 or CC2). A recent ECN for VCONN redefines VCONN
voltage range to 3 V — 5.5 V from the originally defined 4.75 V — 5.5 V. Given TUSB422 maximum Rds(on) and
the minimum I(VCONN) current, the allowable VCONN power through the TUSB422 is derived by 公式 1.
(V(VCONN) – V(VCC1/CC2)) / Rds(on)(max) < I(VCONN) (min) (1)
where:
• where V(VCONN) represents voltage on VCONN pin.
• V(VCONN) is voltage on CC pins.
• Rds(on) (max) is VCONN switch maximum ON resistance,
• and I(VCONN) (min) is the minimum VCONN current fault threshold.
For this example, to support the minimum Type-C V(VCONN) requirement (1 Watt at 3 V), the voltage on the
VCONN pin must be greater than 3.25 Volts [(0.333 A x 0.75 Ω) + 3 V]. If system designer desires to support the
old VCONN requirement of 1 W at 4.75 V, then the voltage on the VCONN pin must be greater than 4.9 volts
[(0.21 A x 0.75 Ω) + 4.75 V].

8.2.3 Application Curve

图 77. USB PD Tx Eye

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9 Power Supply Recommendations

The TUSB422 has a wide power supply range from 2.7 V — 5.5 V.
General Power up Sequence for TUSB422:
• System is powered off (device has no VDD).
• VDD ramps
• TUSB422 asserts INT_N low when initial initialization is complete.
• Software can then start configuring the TUSB422.

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10 Layout

10.1 Layout Guidelines

1. Trace width and thickness size for CC1, CC2, and VCONN should be set to meet at least 1 Watt.
2. A 0.1 µF capacitor should be placed as close as possible to TUSB422 VDD pin.
图 78 shows via-in-pad for inner pad B2. This is due to the tight placing between two pads. If PCB manufacturing
restrictions allows for very small width traces like 2 mils, then via-in-pad is not needed.

10.2 Layout Example

INT_N

GND

SDA CC1
C3 C2 C1

SCL VCONN
B3 B1
B2

VDD VBUSIN

CC2
A3 A2 A1

图 78. Example Layout

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11 器件和文档支持

11.1 接收文档更新通知
要接收文档更新通知，请导航至 TI.com.cn 上的器件产品文件夹。单击右上角的通知我 进行注册，即可每周接收产
品信息更改摘要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。

11.2 社区资源
下列链接提供到 TI 社区资源的连接。链接的内容由各个分销商“按照原样”提供。这些内容并不构成 TI 技术规范，
并且不一定反映 TI 的观点；请参阅 TI 的 《使用条款》。
TI E2E™ 在线社区 TI 的工程师对工程师 (E2E) 社区。此社区的创建目的在于促进工程师之间的协作。在
e2e.ti.com 中，您可以咨询问题、分享知识、拓展思路并与同行工程师一道帮助解决问题。
设计支持 TI 参考设计支持 可帮助您快速查找有帮助的 E2E 论坛、设计支持工具以及技术支持的联系信息。

11.3 商标
E2E is a trademark of Texas Instruments.
USB Type-C is a trademark of USB Implementers Forum.
All other trademarks are the property of their respective owners.
11.4 静电放电警告
ESD 可能会损坏该集成电路。德州仪器 (TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理措施和安装程序 , 可
能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级 , 大至整个器件故障。 精密的集成电路可能更容易受到损坏 , 这是因为非常细微的参数更改都可
能会导致器件与其发布的规格不相符。

11.5 术语表
SLYZ022 — TI 术语表。
这份术语表列出并解释术语、缩写和定义。

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12 机械、封装和可订购信息
以下页面包含机械、封装和可订购信息。这些信息是指定器件的最新可用数据。数据如有变更，恕不另行通知，且
不会对此文档进行修订。如需获取此产品说明书的浏览器版本，请参阅左侧的导航栏。

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 TUSB422
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TUSB422IYFP PACKAGE OUTLINE

YFP0009-C01 SCALE 10.000
DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

1.41
B A
1.35

BALL A1
CORNER

1.365
1.305

C
0.5 MAX

SEATING PLANE
0.19
0.13 BALL TYP
0.05 C

0.8 TYP
SYMM

0.8
TYP B SYMM

0.4 TYP

0.25 1 2 3
9X
0.21 0.4
0.015 C A B TYP

4223654/A 04/2017

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.

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TUSB422
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TUSB422IYFP EXAMPLE BOARD LAYOUT

YFP0009-C01 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

9X ( 0.23)
1 2 3

(0.4) TYP

SYMM
B

SYMM

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:50X

( 0.23) 0.05 MAX 0.05 MIN METAL UNDER

METAL SOLDER MASK

SOLDER MASK EXPOSED EXPOSED ( 0.23)

OPENING METAL METAL SOLDER MASK
OPENING
NON-SOLDER MASK SOLDER MASK
DEFINED DEFINED
(PREFERRED)

SOLDER MASK DETAILS

NOT TO SCALE
4223654/A 04/2017

NOTES: (continued)

3. Final dimensions may vary due to manufacturing tolerance considerations and also routing constraints.
For more information, see Texas Instruments literature number SNVA009 (www.ti.com/lit/snva009).

www.ti.com
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 TUSB422
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TUSB422IYFP EXAMPLE STENCIL DESIGN

YFP0009-C01 DSBGA - 0.5 mm max height
DIE SIZE BALL GRID ARRAY

(0.4) TYP

9X ( 0.25) (R0.05) TYP

1 2 3

(0.4) TYP

B SYMM

METAL
TYP

SYMM

SOLDER PASTE EXAMPLE

BASED ON 0.1 mm THICK STENCIL
SCALE:50X

4223654/A 04/2017

NOTES: (continued)

4. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release.

www.ti.com
版权 © 2016–2018, Texas Instruments Incorporated 71
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

TUSB422IYFPR ACTIVE DSBGA YFP 9 3000 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 422

TUSB422IYFPT ACTIVE DSBGA YFP 9 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -40 to 85 422

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Apr-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TUSB422IYFPR DSBGA YFP 9 3000 180.0 8.4 1.5 1.45 0.6 4.0 8.0 Q1
TUSB422IYFPT DSBGA YFP 9 250 180.0 8.4 1.5 1.45 0.6 4.0 8.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 16-Apr-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
TUSB422IYFPR DSBGA YFP 9 3000 182.0 182.0 20.0
TUSB422IYFPT DSBGA YFP 9 250 182.0 182.0 20.0

Pack Materials-Page 2
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