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Test_2_partB_Monsoon2021

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Test_2_partB_Monsoon2021

Uploaded by

salusivasankaran
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
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EC6101D DIGITAL SYSTEM DESIGN USING HDL

TEST-2 (Part B)
Monsoon 2021
Duration: 1 hour Total Marks: 10

1. A 4-bit shift register is shown in Fig.1. With a similar functionality, model a parameterized
N-bit shift register using parameter and generate. D filp-flop and mux modules may
be described using behavioural Verilog statements. Assume reset signal is used in the design,
even though it is not shown explicitly. (4 Marks)

Fig.1 Circuit diagram of 4-bit shift_reg

2. Using the N-bit shift register developed in Q1, write a Verilog code to describe the design
given in Fig.2. To increase clarity in the diagram, ‘clk’ and ‘rst’ signal are not shown.
(3 Marks)

Fig. 2 Block diagram of ctrl_sequence


3. Assume that a parameter defines the width of an input vector named num. Write a task which
reverses the bits in num. For example, if the parameter value is 4, and if num=4’b1110 then
the output of the task is 4’b0111. Write the entire Verilog module. (3 marks)

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