OPA277, OPA2277, OPA4277

SBOS079C – MARCH 1999 – REVISED FEBRUARY 2023

OPAx277 High-Precision Operational Amplifiers

1 Features 3 Description
• Ultra-low offset voltage: 10 μV The OPAx277 series of precision operational
• Ultra-low drift: ±0.1 μV/°C amplifiers replace the industry standard OP-177. The
• High open-loop gain: 134 dB OPAx277 devices offer improved noise, wider output
• High common-mode rejection: 140 dB voltage swing, and are twice as fast with half the
• High power-supply rejection: 130 dB quiescent current. Features include ultra-low offset
• Low bias current: 1-nA maximum voltage and drift, low bias current, high common-
• Wide supply range: ±2 V to ±18 V mode rejection, and high power supply rejection.
• Low quiescent current: 800 μA/amplifier
The OPAx277 operate from ±2-V to ±18-V supplies
• Single, dual, and quad versions
with excellent performance. Unlike most op amps that
• Replaces OP-07, OP-77, and OP-177
are specified at only one supply voltage, the OPAx277
• For similar performance with ±40-V overvoltage
series is specified for real-world applications; a single
protection, see the OPA2206
limit applies over the ±5-V (10-V) to ±15-V (30-V)
2 Applications supply range. High performance is maintained as the
amplifiers swing to the specified limits. Because the
• Analog input module
initial offset voltage (±20 μV, maximum) is so low,
• Weigh scale
user adjustment is usually not required. However, the
• Temperature transmitter
single version (OPA277) provides external trim pins
• Pressure transmitter
for special applications.
• Data acquisition (DAQ)
• Lab and field instrumentation The OPAx277 are easy to use and free from phase
• Battery test inversion and the overload problems found in some
other op amps. These devices are unity-gain stable
and provide excellent dynamic behavior over a wide
range of load conditions. Dual and quad versions
feature completely independent circuitry for lowest
Noise signal is bandwidth limited to
lie between 0.1Hz and 10Hz. crosstalk and freedom from interaction, even when
overdriven or overloaded.
50nV/div

Device Information
PART NUMBER PACKAGE(1) BODY SIZE (NOM)
D (SOIC, 8) 3.91 mm × 4.90 mm
OPA277,
DRM (VSON, 8) 4.00 mm × 4.00 mm
OPA2277
P (PDIP, 8) 6.35 mm × 9.81 mm
D (SOIC, 14) 3.91 mm × 8.65 mm
OPA4277
1s/div P (PDIP, 14) 6.35 mm × 19.30 mm
0.1-Hz to 10-Hz Noise (1) For all available packages, see the orderable addendum at
the end of the data sheet.

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features............................................................................1 7.3 Feature Description...................................................14
2 Applications..................................................................... 1 7.4 Device Functional Modes..........................................17
3 Description.......................................................................1 8 Application and Implementation.................................. 18
4 Revision History.............................................................. 2 8.1 Application Information............................................. 18
5 Pin Configuration and Functions...................................3 8.2 Typical Applications.................................................. 18
6 Specifications.................................................................. 6 8.3 Power Supply Recommendations.............................20
6.1 Absolute Maximum Ratings........................................ 6 8.4 Layout....................................................................... 21
6.2 ESD Ratings............................................................... 6 9 Device and Documentation Support............................23
6.3 Recommended Operating Conditions.........................6 9.1 Device Support......................................................... 23
6.4 Thermal Information: OPA277.................................... 7 9.2 Documentation Support............................................ 24
6.5 Thermal Information: OPA2277.................................. 7 9.3 Receiving Notification of Documentation Updates....24
6.6 Thermal Information: OPA4277.................................. 7 9.4 Support Resources................................................... 24
6.7 Electrical Characteristics.............................................8 9.5 Trademarks............................................................... 24
6.8 Typical Characteristics.............................................. 10 9.6 Electrostatic Discharge Caution................................24
7 Detailed Description......................................................14 9.7 Glossary....................................................................24
7.1 Overview................................................................... 14 10 Mechanical, Packaging, and Orderable
7.2 Functional Block Diagram......................................... 14 Information.................................................................... 24

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision B (April 2015) to Revision C (February 2023) Page
• Updated the numbering format for tables, figures, and cross-references throughout the document..................1
• Changed Applications bullets to include links.....................................................................................................1
• Deleted text regarding identical specification for the single, dual, and quad versions........................................1
• Changed Offset Trim pin type from "Input" to "—".............................................................................................. 3
• Changed "DFN" to "DRM (VSON)" in OPA2277 Pin Functions table................................................................. 3
• Added table note for 10-mA current limit on input pins in Absolute Maxiimum Ratings .................................... 6
• Deleted operating temperature from Absolute Maximum Ratings ..................................................................... 6
• Deleted lead temperature from Absolute Maximum Ratings ............................................................................. 6
• Changed Thermal Information values for OPA2277 and OPA4277 SOIC packages..........................................7
• Added test conditions to Electrical Characteristics header.................................................................................8
• Changed format of Electrical Characteristcs for readability................................................................................8
• Changed input offset voltage vs. time to long-term drift in Electrical Characteristics ........................................ 8
• Changed input bias current test condition to separate over temperature specification...................................... 8
• Deleted redundant row in open-loop gain parameter......................................................................................... 8
• Changed CLOAD to CL for consistency................................................................................................................ 8
• Changed Figure 6-14, Change in Input Bias Current vs Common-Mode Voltage, to correct typo in note....... 10
• Changed "DFN package" to "DRM package (8-pin VSON)".............................................................................21
• Changed "DFN package" to "DRM Package" and added "8-Pin VSON"..........................................................21
• Changed Development Support section to show updated links and resources................................................23

Changes from Revision A (April 2005) to Revision B (April 2015) Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and
Implementation section, Power Supply Recommendations section, Layout section, Device and
Documentation Support section, and Mechanical, Packaging, and Orderable Information section................... 1

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5 Pin Configuration and Functions

Offset Trim 1 8 Offset Trim

Offset Trim 1 8 Offset Trim
–In 2 7 V+
Pin 1
−In 2 Indicator 7 V+
+In 3 6 Output

V– 4 5 NC(1) +In 3 6 Output

Figure 5-1. OPA277 P Package, 8-Pin PDIP and V− 4 5 NC

D Package, 8-Pin SOIC (Top View)

Thermal Pad
on Bottom
(Connect to V−)

Figure 5-2. OPA277 DRM Package, 8-Pin VSON

(Top View)

Table 5-1. Pin Functions: OPA277

PIN
TYPE DESCRIPTION
NAME NO.
–In 2 Input Inverting input
+In 3 Input Noninverting input
NC 5 — No internal connection (can be left floating)
Offset Trim 1 — Input offset voltage trim (leave floating if not used)
Offset Trim 8 — Input offset voltage trim (leave floating if not used)
Output 6 Output Output
V– 4 — Negative (lowest) power supply
V+ 7 — Positive (highest) power supply

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Out A 1 8 V+
Out A 1 8 Out B
–In A 2 A 7 Out B Pin 1
B −In A 2 Indicator 7 V+
+In A 3 6 –In B

V– 4 5 +In B +In A 3 6 −In B

Figure 5-3. OPA2277 P Package, 8-Pin PDIP and V− 4 5 +In B

D Package, 8-Pin SOIC (Top View)

Thermal Pad
on Bottom
(Connect to V−)

Figure 5-4. OPA2277 DRM Package, 8-Pin VSON

(Top View)

Table 5-2. Pin Functions: OPA2277

PIN
D (SOIC), DRM TYPE DESCRIPTION
NAME
P (PDIP) (VSON)
–In A 2 2 Input Inverting input channel A
–In B 6 6 Input Inverting input channel B
+In A 3 3 Input Noninverting input channel A
+In B 5 5 Input Noninverting input channel B
Out A 1 1 Output Output channel A
Out B 7 8 Output Output channel B
V– 4 4 — Negative (lowest) power supply
V+ 8 7 — Positive (highest) power supply

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Out A 1 14 Out D

–In A 2 13 –In D
A D
+In A 3 12 +In D

V+ 4 11 V–

+In B 5 10 +In C
B C
–In B 6 9 –In C

Out B 7 8 Out C

Figure 5-5. OPA4277 P Package, 14-Pin PDIP and D Package, 14-Pin SOIC (Top View)

Table 5-3. Pin Functions: OPA4277

PIN
TYPE DESCRIPTION
NAME NO.
–In A 2 Input Inverting input channel A
–In B 6 Input Inverting input channel B
–In C 9 Input Inverting input channel C
–In D 13 Input Inverting input channel D
+In A 3 Input Noninverting input channel A
+In B 5 Input Noninverting input channel B
+In C 10 Input Noninverting input channel C
+In D 12 Input Noninverting input channel D
Out A 1 Output Output channel A
Out B 7 Output Output channel B
Out C 8 Output Output channel C
Out D 14 Output Output channel D
V+ 4 — Positive (highest) power supply
V– 11 — Negative (lowest) power supply

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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN MAX UNIT
VS Supply voltage, VS = (V+) – (V–) 36 V
Input voltage(2) (V–) – 0.7 (V+) + 0.7 V
ISC Output short circuit(3) Continuous
TJ Junction temperature 150 °C
TSTG Storage temperature –55 125 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress
ratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under
Recommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device
reliability.
(2) Limit input signals that can swing more than 0.7 V beyond the supply rails to 10 mA or less.
(3) Short-circuit to ground, one amplifier per package.

6.2 ESD Ratings

VALUE UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V
V(ESD) Electrostatic discharge
Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±500 V

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Single supply 4 30 36
VS Supply voltage, VS = (V+) – (V–) V
Dual supply ±2 ±15 ±18
TA Ambient temperature –40 85 °C

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6.4 Thermal Information: OPA277

OPA277
THERMAL METRIC(1) D (SOIC) DRM (VSON) P (PDIP) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 110.1 40.7 49.2 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 52.2 41.3 39.4 °C/W
RθJB Junction-to-board thermal resistance 52.3 16.7 26.4 °C/W
ψJT Junction-to-top characterization parameter 10.4 0.6 15.4 °C/W
ψJB Junction-to-board characterization parameter 51.5 16.9 26.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A 3.3 N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report

6.5 Thermal Information: OPA2277

OPA2277
THERMAL METRIC(1) D (SOIC) DRM (VSON) P (PDIP) UNIT
8 PINS 8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 126.9 39.3 47.2 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 67.1 36.9 36.0 °C/W
RθJB Junction-to-board thermal resistance 70.3 15.4 24.4 °C/W
ψJT Junction-to-top characterization parameter 18.8 0.4 13.4 °C/W
ψJB Junction-to-board characterization parameter 69.5 15.6 24.3 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A 2.2 N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report

6.6 Thermal Information: OPA4277

OPA4277
THERMAL METRIC(1) D (SOIC) P (PDIP) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 86.5 66.3 °C/W
RθJC(top) Junction-to-case(top) thermal resistance 38.5 20.5 °C/W
RθJB Junction-to-board thermal resistance 43.5 26.8 °C/W
ψJT Junction-to-top characterization parameter 7.4 2.1 °C/W
ψJB Junction-to-board characterization parameter 42.9 26.2 °C/W
RθJC(bot) Junction-to-case(bottom) thermal resistance N/A N/A °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report

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6.7 Electrical Characteristics

at TA = 25°C, VS = 10 V to 30 V, VCM = VOUT = VS / 2, and RL = 2 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OFFSET VOLTAGE
OPA277P, U ±10 ±20
OPA2277P, U ±10 ±25
OPAx277PA, UA ±20 ±50
OPAx277AIDRM ±35 ±100
VOS Input offset voltage µV
OPA277P, U ±30
OPA2277P, U ±50
TA = –40°C to +85°C
OPAx277PA, UA ±100
OPAx277AIDRM ±165
OPA277P, U ±0.1 ±0.15
dVOS/dT Input offset voltage drift TA = –40°C to +85°C OPA2277P, U ±0.1 ±0.25 µV/°C
OPAx277AIDRM, PA, UA ±0.15 ±1
Long-term drift 0.2 µV/mo
OPAx277P, U ±0.3 ±0.5
VS = ±2 V to ±18 V
Power-supply rejection OPAx277AIDRM, PA, UA ±0.3 ±1
PSRR µV/V
ratio OPAx277P, U ±0.5
VS = ±2 V to ±18 V,
TA = –40°C to +85°C OPAx277AIDRM, PA, UA ±1
Channel separation
dc 0.1 µV/V
(dual, quad)
INPUT BIAS CURRENT
OPAx277P, U ±0.5 ±1
OPAx277AIDRM, PA, UA ±0.5 ±2.8
IB Input bias current nA
OPAx277P, U ±2
TA = –40°C to +85°C
OPAx277AIDRM, PA, UA ±4
OPAx277P, U ±0.5 ±1
OPAx277AIDRM, PA, UA ±0.5 ±2.8
IOS Input offset current nA
OPAx277P, U ±2
TA = –40°C to +85°C
OPAx277AIDRM, PA, UA ±4
NOISE
Input voltage noise f = 0.1 Hz to 10 Hz 0.22 µVPP
f = 10 Hz 12

Input voltage noise f = 100 Hz 8

en nV/√Hz
density f = 1 kHz 8
f = 10 kHz 8
Input current noise
in f = 1 kHz 0.2 pA/√Hz
density
INPUT VOLTAGE
Common-mode voltage
VCM (V–) + 2 (V+) – 2 V
range
OPAx277P, U 130 140
VCM = (V–) + 2 V to (V+) – 2 V
Common-mode rejection OPAx277AIDRM, PA, UA 115 140
CMRR dB
ratio OPAx277P, U 128
VCM = (V–) + 2 V to (V+) – 2 V,
TA = –40°C to +85°C OPAx277AIDRM, PA, UA 115
INPUT IMPEDANCE
ZID Differential 100 || 3 MΩ || pF
ZIC Common-mode VCM = (V–) + 2 V to (V+) – 2 V 250 || 3 GΩ || pF

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6.7 Electrical Characteristics (continued)

at TA = 25°C, VS = 10 V to 30 V, VCM = VOUT = VS / 2, and RL = 2 kΩ connected to VS / 2 (unless otherwise noted)
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPEN-LOOP GAIN
VO = (V–) + 0.5 V to (V+) – 1.2 V,
140
RL = 10 kΩ
AOL Open-loop voltage gain dB
VO = (V–) + 1.5 V to (V+) – 1.5 V, 126 134
RL = 2 kΩ TA = –40°C to +85°C 126
FREQUENCY RESPONSE
GBW Gain-bandwidth product 1 MHz
SR Slew rate 0.8 V/µs
To 0.1% 14
ts Settling time VS = ±15 V, G = 1, 10-V step µs
To 0.01% 16
tOR Overload recovery time VIN × G = VS 3 µs
Total harmonic distortion
THD+N G = 1, f = 1 kHz, VO = 3.5 VRMS 0.002%
+ noise
OUTPUT
(V–) + 0.5 (V+) – 1.2
RL = 10 kΩ
TA = –40°C to +85°C (V–) + 0.5 (V+) – 1.2
VO Voltage output V
(V–) + 1.5 (V+) – 1.5
RL = 2 kΩ
TA = –40°C to +85°C (V–) + 1.5 (V+) – 1.5
ISC Short-circuit current ±35 mA
CL Capacitive load drive See Typical Characteristics
Open-loop output
ZO f = 1 MHz 40 Ω
impedance
POWER SUPPLY

Quiescent current per ±790 ±825

IQ IO = 0 A µA
amplifier TA = –40°C to +85°C ±900

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6.8 Typical Characteristics

At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

140 140
G CL = 0
120 0 120
CL = 1500pF +PSR
100 –30 –PSR
100

PSR, CMR (dB)

80 –60

Phase (°)
AOL (dB)

φ 80
60 –90 CMR
60
40 –120
40
20 –150
20
0 –180

–20 0
0.1 1 10 100 1k 10k 100k 1M 10M 0.1 1 10 100 1k 10k 100k 1M

Frequency (Hz) Frequency (Hz)

Figure 6-1. Open-Loop Gain and Phase vs Frequency Figure 6-2. Power Supply and Common-Mode Rejection vs
Frequency
INPUT NOISE AND CURRENT NOISE
SPECTRAL DENSITY vs FREQUENCY
1000
Noise signal is bandwidth limited to
Current Noise lie between 0.1Hz and 10Hz.
Voltage Noise (nV/√Hz)
Current Noise (fA/√Hz)

100
50nV/div

10 Voltage Noise

1
0.1 1 10 100 1k
Frequency (Hz)
1s/div

Figure 6-3. Input Noise and Current Noise Spectral Density vs Figure 6-4. Input Noise Voltage vs Time
Frequency
140 1
VOUT = 3.5Vrms

120
Channel Separation (dB)

THD+Noise (%)

0.1
100
Dual and quad devices. G = 1,
G = 10, RL = 2kΩ, 10kΩ
all channels. Quad measured
80 channel A to D or B to C —other
combinations yield similar or 0.01
improved rejection.
60 G = 1, RL = 2kΩ, 10kΩ

40 0.001
10 100 1k 10k 100k 1M 10 100 1k 10k 100k
Frequency (Hz) Frequency (Hz)

Figure 6-5. Channel Separation vs Frequency Figure 6-6. Total Harmonic Distortion + Noise vs Frequency

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6.8 Typical Characteristics (continued)

At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

16 35
Typical distribution Typical distribution
14 of packaged units. 30 of packaged units.
Single, dual, and Single, dual, and

Percent of Amplifiers (%)

Percent of Amplifiers (%)

12 quad included. quad included.

25
10
20
8
15
6
10
4

2 5

0 0
– 50– 45– 40– 35– 30– 25– 20– 15– 10– 5 0 5 10 15 20 25 30 35 40 45 50 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Offset Voltage (µV) Offset Voltage (µV/°C)

Figure 6-7. Offset Voltage Production Distribution Figure 6-8. Offset Voltage Drift Production Distribution
3 160

2 150
Offset Voltage Change (µV)

CMR
AOL, CMR, PSR (dB)

1 140 AOL

0 130
PSR
–1 120

–2 110

–3 100
0 15 30 45 60 75 90 105 120 –75 –50 –25 0 25 50 75 100 125
Time from Power Supply Turn-On (s) Temperature ( °C)

Figure 6-9. Warm-Up Offset Voltage Drift Figure 6-10. AOL, CMR, PSR vs Temperature
5 1000 100
4 950 90
3 900 80

Short-Circuit Current (mA)

Input Bias Current (nA)

Quiescent Current (µA)

2 850 70
±I Q
1 800 60
0 750 50
–ISC
–1 700 40
–2 650 +ISC 30
Curves represent typical
–3 600 20
production units.
–4 550 10
–5 500 0
–75 –50 –25 0 25 50 75 100 125 –75 –50 –25 0 25 50 75 100 125
Temperature ( °C) Temperature (°C)

Figure 6-11. Input Bias Current vs Temperature Figure 6-12. Quiescent Current and Short-Circuit Current vs
Temperature

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6.8 Typical Characteristics (continued)

At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

2.0 2.0
Curve shows normalized change in bias current
Curve shows normalized change in
1.5 1.5 with respect to VCM = 0V. Typical I B may range
bias current with respect to VS = ±10V
from –0.5nA to +0.5nA at V CM = 0V.
(+20V). Typical I B may range from 1.0
1.0
–0.5nA to +0.5nA at V S = ±10V. VS = ±5V
0.5 0.5

∆IB (nA)
∆IB (nA)

0.0 0.0
VCM = 0V
–0.5 –0.5
VS = ±15V
–1.0 –1.0

–1.5 –1.5

–2.0 –2.0
0 5 10 15 20 25 30 35 40 –15 –10 –5 0 5 10 15
Supply Voltage (V) Common-Mode Voltage (V)

Figure 6-13. Change in Input Bias Current vs Power-Supply Figure 6-14. Change in Input Bias Current vs Common-Mode
Voltage Voltage

1000 100
10V step
per amplifier
CL = 1500pF
900
Quiescent Current (µA)

50
Settling Time (µs)

0.01%
800
0.1%

700
20
600

500 10
0 ±5 ±10 ±15 ±20 ±1 ±10 ±100
Supply Voltage (V) Gain (V/V)

Figure 6-15. Quiescent Current vs Supply Voltage Figure 6-16. Settling Time vs Closed-Loop Gain
30 (V+)
VS = ±15V (V+) – 1
25 –55°C
(V+) – 2
Output Voltage Swing (V)
Output Voltage (V PP)

(V+) – 3
20 125°C
(V+) – 4
(V+) – 5 25°C
15
(V–) + 5
125°C 25°C
10 (V–) + 4
VS = ±5V (V–) + 3
5 (V–) + 2
–55°C
(V–) + 1
0 (V–)
1k 10k 100k 1M 0 ±5 ±10 ±15 ±20 ±25 ±30
Frequency (Hz) Output Current (mA)

Figure 6-17. Maximum Output Voltage vs Frequency Figure 6-18. Output Voltage Swing vs Output Current

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6.8 Typical Characteristics (continued)

At TA = 25°C, VS = ±15 V, and RL = 2 kΩ, unless otherwise noted.

60
Gain = –1
50

40
Overshoot (%)

Gain = +1

2V/div
30

20
Gain = ±10
10

0
10 100 1k 10k 100k
Load Capacitance (pF) 10µs/div
G = 1, CL = 1500 pF, VS = ±15 V
Figure 6-19. Small-Signal Overshoot vs Load Capacitance Figure 6-20. Large-Signal Step Response
20mV/div

20mV/div

1µs/div 1µs/div
G = 1, CL = 0, VS = ±15 V G = 1, CL = 1500 pF, VS = ±15 V
Figure 6-21. Small-Signal Step Response Figure 6-22. Small-Signal Step Response
100
70
50

30
Impedance (:)

20

10
7
5

3
2

1
1k 10k 100k 1M
Frequency (Hz)
VS = ±15 V
Figure 6-23. Open-Loop Output Impedance

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7 Detailed Description
7.1 Overview
The OPAx277 series precision operational amplifiers replace the industry standard OP-177. These devices offer
improved noise, wider output voltage swing, and are twice as fast with half the quiescent current. Features
include ultra-low offset voltage and drift, low bias current, high common-mode rejection, and high power-supply
rejection.
7.2 Functional Block Diagram
Input Offset
Adjust
(OPA277 only)

+IN +
Output
-IN ±

Input Offset
Adjust Compensation
(OPA277 only)

7.3 Feature Description

The OPAx277 series is unity-gain stable and free from unexpected output phase reversal, making these devices
easy to use in a wide range of applications. Applications with noisy or high-impedance power supplies can
require decoupling capacitors close to the device pins. In most cases 0.1-μF capacitors are adequate.
The OPAx277 series has low offset voltage and drift. To achieve highest performance, optimize the circuit layout
and mechanical conditions. Offset voltage and drift can be degraded by small thermoelectric potentials at the
operational amplifier inputs. Connections of dissimilar metals generate thermal potential, which can degrade the
ultimate performance of the OPAx277 series. To cancel these thermal potentials, make sure that the thermal
potentials are equal in both input pins.
• Keep the thermal mass of the connections to the two input pins similar
• Locate heat sources as far as possible from the critical input circuitry
• Shield operational amplifier and input circuitry from air currents, such as cooling fans
7.3.1 Operating Voltage
The OPAx277 series of operational amplifiers operate from ±2-V to ±18-V supplies with excellent performance.
Unlike most operational amplifiers, which are specified at only one supply voltage, the OPAx277 series is
specified for real-world applications; a single limit applies over the ±5-V to ±15-V supply range. This single limit
allows a customer operating at VS = ±10 V to have the same specified performance as a customer using ±15-V
supplies. In addition, key parameters are specified over the specified temperature range of –40°C to +85°C.
Most behavior remains unchanged through the full operating voltage range of ±2 V to ±18 V. Parameters that
vary significantly with operating voltage or temperature are shown in Section 6.8.
7.3.2 Offset Voltage Adjustment
The OPAx277 series is laser-trimmed for low offset voltage and drift, so most circuits do not require external
adjustment. However, for the OPA277, offset voltage trim connections are provided on pins 1 and 8. Figure 7-1
shows how the offset voltage can be adjusted by connecting a potentiometer. Only use this adjustment to null
the offset of the operational amplifier. Do not use this adjustment to compensate for offsets created elsewhere in
a system, because additional temperature drift can be introduced.

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V+
Trim Range: Exceeds
Offset Voltage Specification
0.1µF
20kΩ
7
2 1
8
OPA277 6
3

4 OPA277 single op amp only.

0.1µF Use offset adjust pins only to null
offset voltage of op amp—see text.

V–

Figure 7-1. OPA277 Offset Voltage Trim Circuit

7.3.3 Input Protection

The inputs of the OPAx277 devices protected with 1-kΩ series input resistors and diode clamps. The inputs can
withstand ±30-V differential inputs without damage. The protection diodes conduct current when the inputs are
overdriven. This conducted current can disturb the slewing behavior of unity-gain follower applications, but does
not damage the operational amplifier.
1k

1k ±

Figure 7-2. OPAx277 Input Protection

7.3.4 Input Bias Current Cancellation

The input stage base current of the OPAx277 series is internally compensated with an equal and opposite
cancellation circuit. The resulting input bias current is the difference between the input stage base current and
the cancellation current. This residual input bias current can be positive or negative.
When the bias current is canceled in this manner, the input bias current and input offset current are
approximately the same magnitude. As a result, a bias current cancellation resistor is not necessary, as is
often done with other operational amplifiers. Figure 7-3 shows a conventional op amp with external bias current
cancellation resistor compared to the OPA277 with no external bias current cancellation resistor. A resistor
added to cancel input bias current errors can actually increase offset voltage and noise.
R2 R2

R1 R1

Op Amp OPA277

RB = R2 || R1
No bias current
cancellation resistor
(see text)

(a) (b)
Conventional op amp with external bias OPA277 with no external bias current
current cancellation resistor. cancellation resistor.

Figure 7-3. Input Bias Current Cancellation

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7.3.5 EMI Rejection Ratio (EMIRR)

The electromagnetic interference (EMI) rejection ratio, or EMIRR, describes the EMI immunity of operational
amplifiers. An adverse effect that is common to many operational amplifiers is a change in the offset voltage as a
result of RF signal rectification. An operational amplifier that is more efficient at rejecting this change in offset as
a result of EMI has a higher EMIRR and is quantified by a decibel value. Measuring EMIRR can be performed in
many ways, but this report provides the EMIRR IN+, which specifically describes the EMIRR performance when
the RF signal is applied to the noninverting input pin of the operational amplifier. In general, only the noninverting
input is tested for EMIRR for the following three reasons:
1. Operational amplifier input pins are known to be the most sensitive to EMI, and typically rectify RF signals
better than the supply or output pins.
2. The noninverting and inverting operational amplifier inputs have symmetrical physical layouts and exhibit
nearly matching EMIRR performance.
3. EMIRR is easier to measure on noninverting pins than on other pins because the noninverting input terminal
can be isolated on a printed circuit board (PCB). This isolation allows the RF signal to be applied directly
to the noninverting input terminal with no complex interactions from other components or connecting PCB
traces.
A more formal discussion of the EMIRR IN+ definition and test method is provided in the EMI Rejection Ratio of
Operational Amplifiers application note, available for download at www.ti.com. Figure 7-4 shows the EMIRR IN+
of the OPA277 plotted versus frequency.
120
PRF = -10 dbm
VS = r2.5 V
100 VCM = 0 V

80
EMIRR IN+ (db)

60

40

20

0
10 100 1k 10k
Frequency (MHz)

Figure 7-4. OPA277 EMIRR IN+ vs Frequency

If available, any dual and quad operational amplifier device versions have nearly similar EMIRR IN+
performance. The OPA277 unity-gain bandwidth is 1 MHz. EMIRR performance below this frequency denotes
interfering signals that fall within the operational amplifier bandwidth.

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Table 7-1 shows the EMIRR IN+ values for the OPA277 at particular frequencies commonly encountered in
real-world applications. Applications listed in Table 7-1 can be centered on or operated near the particular
frequency shown. This information is of special interest to designers working with these types of applications, or
working in other fields likely to encounter RF interference from broad sources, such as the industrial, scientific,
and medical (ISM) radio band.
Table 7-1. OPA277 EMIRR IN+ for Frequencies of Interest
FREQUENCY APPLICATION/ALLOCATION EMIRR IN+
400 MHz Mobile radio, mobile satellite-space operation, weather, radar, UHF 59.1 dB
900 MHz GSM, radio com-nav-GPS (to 1.6 GHz), ISM, aeronautical mobile, UHF 77.9 dB
1.8 GHz GSM, mobile personal comm. broadband, satellite, L-band 91.3 dB
2.4 GHz 802.11b/g/n, Bluetooth®, mobile personal comm, ISM, amateur radio-satellite, S-band 93.3 dB
3.6 GHz Radiolocation, aero comm-nav, satellite, mobile, S-band 105.9 dB
5.0 GHz 802.11a/n, aero comm-nav, mobile comm, space-satellite operation, C-band 107.5 dB

7.3.5.1 EMIRR IN+ Test Configuration

Figure 7-5 shows the circuit configuration for testing the EMIRR IN+. An RF source is connected to the
operational amplifier noninverting input terminal using a transmission line. The operational amplifier is configured
in a unity-gain buffer topology with the output connected to a low-pass filter (LPF) and a digital multimeter
(DMM). A large impedance mismatch at the operational amplifier input causes a voltage reflection; however, this
effect is characterized and accounted for when determining the EMIRR IN+. The resulting dc offset voltage is
sampled and measured by the multimeter. The LPF isolates the multimeter from residual RF signals that can
interfere with multimeter accuracy. See the EMI Rejection Ratio of Operational Amplifiers application note for
more details.
Ambient temperature: 25Û&

+VS

±
50 Low-Pass Filter
+

RF source
-VS
DC Bias: 0 V Sample /
Modulation: None (CW) Averaging Digital Multimeter
Frequency Sweep: 201 pt. Log Not shown: 0.1 µF and 10 µF
supply decoupling

Figure 7-5. EMIRR IN+ Test Configuration Schematic

7.4 Device Functional Modes

The OPAx277 has a single functional mode and is operational when the power-supply voltage is greater than 4 V
(±2 V). The maximum power supply voltage for the OPAx277 is 36 V (±18 V).

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8 Application and Implementation

Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.

8.1 Application Information

The OPAx277 family offers outstanding dc precision and ac performance. These devices operate up to 36-V
supply rails and offer ultralow offset voltage and offset voltage drift, as well as 1-MHz bandwidth and high
capacitive load drive. These features make the OPAx277 a robust, high-performance operational amplifier for
high-voltage industrial applications.
8.2 Typical Applications
8.2.1 Second-Order, Low-Pass Filter
2.25 k

1 nF
2.25 k 1.13 k
Input ±
Output
4 nF +

Figure 8-1. Second-Order, Low-Pass Filter

8.2.1.1 Design Requirements

• Gain = 1 V/V
• Low-pass cutoff frequency = 50 kHz
• –40 db/dec filter response
• Maintain less than 3-dB gain peaking in the gain versus frequency response
8.2.1.2 Detailed Design Procedure
The Filter Design Tool is a simple, powerful, and easy-to-use active filter design program. The Filter Design Tool
lets you create optimized filter designs using a selection of TI operational amplifiers and passive components
from TI's vendor partners.
Available as a web based tool from the Design tools and simulation website, the Filter Design Tool allows you to
design, optimize, and simulate complete multistage active-filter solutions within minutes.

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8.2.1.3 Application Curve

20

Gain (db)
-20

-40

-60
100 1k 10k 100k 1M
Frequency (Hz)

Figure 8-2. OPA277 Second-Order, 50-kHz, Low-Pass Filter

8.2.2 Load Cell Amplifier

V+

1/2 R2
VOUT = (V1 – V2)(1 + )
OPA2277 R1

R2

V–

R–∆R R+∆R V+
V2 R1
V1 Load
Cell
1/2
R+∆R R–∆R
OPA2277

V–
R2 R1

For integrated solution see: INA126, INA2126 (dual)

INA125 (on-board reference)
INA122 (single-supply)

Figure 8-3. Load Cell Amplifier

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8.2.3 Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction Compensation

IREG ∼ 1mA
5V

12
V+ VLIN 1
1/2 13 IR1 14
+
IR2 11
OPA2277 VIN 10
Type J VREG
V+
RF 4
10kΩ RG

RG 9
R XTR105 B
RF 1250Ω
412Ω
10kΩ
3 E
RG
8
IO
–
1/2 2 VIN 7
1kΩ
OPA2277 IRET
IO = 4mA + (V IN – VIN) 40
+ –

50Ω V– 6 RG

25Ω
RCM = 1250Ω

2RF
(G = 1 + = 50)
R
0.01µF

Figure 8-4. Thermocouple Low-Offset, Low-Drift Loop Measurement With Diode Cold Junction
Compensation

8.3 Power Supply Recommendations

The OPAx277 is specified for operation from 4 V to 36 V (±2 V to ±18 V); many specifications apply from –40°C
to 85°C. Parameters that can exhibit significant variance with regard to operating voltage or temperature are
presented in Section 6.8.

CAUTION
Supply voltages larger than 36 V can permanently damage the device; see Section 6.1.

Place 0.1-μF bypass capacitors close to the power-supply pins to reduce errors coupling in from noisy or
high-impedance power supplies. For more detailed information on bypass capacitor placement, see Section
8.4.1.

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8.4 Layout
8.4.1 Layout Guidelines
For best operational performance of the device, use good PCB layout practices, including:
• Noise can propagate into analog circuitry through the power pins of the circuit as a whole and operational
amplifier itself. Bypass capacitors are used to reduce the coupled noise by providing low-impedance power
sources local to the analog circuitry.
– Connect low-ESR, 0.1-µF ceramic bypass capacitors between each supply pin and ground, placed as
close to the device as possible. A single bypass capacitor from V+ to ground is applicable for single-
supply applications.
• Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective
methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes.
A ground plane helps distribute heat and reduces EMI noise pickup. Make sure to physically separate digital
and analog grounds paying attention to the flow of the ground current.
• To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If
these traces cannot be kept separate, crossing the sensitive trace perpendicular is much better as opposed
to in parallel with the noisy trace.
• Place the external components as close to the device as possible. As shown in Section 8.4.2, keeping RF
and RG close to the inverting input minimizes parasitic capacitance.
• Keep the length of input traces as short as possible. Always remember that the input traces are the most
sensitive part of the circuit.
• Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce
leakage currents from nearby traces that are at different potentials.
• Cleaning the PCB following board assembly is recommended for best performance.
• Any precision integrated circuit can experience performance shifts due to moisture ingress into the plastic
package. Following any aqueous PCB cleaning process, baking the PCB assembly is recommended to
remove moisture introduced into the device packaging during the cleaning process. A low temperature, post
cleaning bake at 85°C for 30 minutes is sufficient for most circumstances.
• DRM package (8-pin VSON) only: Solder the leadframe die pad to a thermal pad on the PCB. The
mechanical drawings located at the end of this data sheet list the physical dimensions for the package
and pad.
• DRM package (8-pin VSON) only: Soldering the exposed pad significantly improves board-level reliability
during temperature cycling, key push, package shear, and similar board-level tests. Even with applications
that have low-power dissipation, the exposed pad must be soldered to the PCB to provide structural integrity
and long term reliability.
8.4.1.1 DRM Package (8-Pin VSON)
The OPAx277 series uses the DRM package (also known as an 8-pin VSON), a leadless package with contacts
on only two sides of the package bottom. This near-chip-scale package maximizes board space and enhances
thermal and electrical characteristics through an exposed pad.
DRM packages are physically small, have a smaller routing area, improved thermal performance, and improved
electrical parasitics, with a pinout scheme that is consistent with other commonly-used packages, such as SOIC
and VSSOP. Additionally, the absence of external leads eliminates bent-lead issues.
The DRM package can be easily mounted using standard printed-circuit-board (PCB) assembly techniques. See
the QFN/SON PCB Attachment and Quad Flatpack No-Lead Logic Packages application notes, both available
for download at www.ti.com.
The exposed leadframe die pad on the bottom of the package must be connected to V–.

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8.4.2 Layout Example

VIN +
RG VOUT

RF

(Schematic Representation)

Place components
Run the input traces close to device and to
as far away from each other to reduce
the supply lines parasitic errors VS+
as possible RF

Offset trim Offset trim

RG
GND ±IN V+ GND

VIN +IN OUTPUT

Use low-ESR, ceramic

V± NC
bypass capacitor

Use low-ESR, GND VOUT

VS±
ceramic bypass Ground (GND) plane on another layer
capacitor

Figure 8-5. OPA277 Layout Example for the Noninverting Configuration

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9 Device and Documentation Support

9.1 Device Support
9.1.1 Development Support
9.1.1.1 PSpice® for TI
PSpice® for TI is a design and simulation environment that helps evaluate performance of analog circuits. Create
subsystem designs and prototype solutions before committing to layout and fabrication, reducing development
cost and time to market.
9.1.1.2 TINA-TI™ Simulation Software (Free Download)
TINA-TI™ simulation software is a simple, powerful, and easy-to-use circuit simulation program based on a
SPICE engine. TINA-TI simulation software is a free, fully-functional version of the TINA™ software, preloaded
with a library of macromodels, in addition to a range of both passive and active models. TINA-TI simulation
software provides all the conventional dc, transient, and frequency domain analysis of SPICE, as well as
additional design capabilities.
Available as a free download from the Design tools and simulation web page, TINA-TI simulation software offers
extensive post-processing capability that allows users to format results in a variety of ways. Virtual instruments
offer the ability to select input waveforms and probe circuit nodes, voltages, and waveforms, creating a dynamic
quick-start tool.

Note
These files require that either the TINA software or TINA-TI software be installed. Download the free
TINA-TI simulation software from the TINA-TI™ software folder.

9.1.1.3 DIP-Adapter-EVM
Speed up your op amp prototyping and testing with the DIP-Adapter-EVM, which provides a fast, easy and
inexpensive way to interface with small, surface-mount devices. Connect any supported op amp using the
included Samtec terminal strips or wire them directly to existing circuits. The DIP-Adapter-EVM kit supports
the following industry-standard packages: D or U (SOIC-8), PW (TSSOP-8), DGK (VSSOP-8), DBV (SOT-23-6,
SOT-23-5 and SOT-23-3), DCK (SC70-6 and SC70-5), and DRL (SOT563-6).
9.1.1.4 DIYAMP-EVM
The DIYAMP-EVM is a unique evaluation module (EVM) that provides real-world amplifier circuits, enabling the
user to quickly evaluate design concepts and verify simulations. This EVM is available in three industry-standard
packages (SC70, SOT23, and SOIC) and 12 popular amplifier configurations, including amplifiers, filters, stability
compensation, and comparator configurations for both single and dual supplies.
9.1.1.5 TI Reference Designs
TI reference designs are analog solutions created by TI’s precision analog applications experts. TI reference
designs offer the theory of operation, component selection, simulation, complete PCB schematic and layout, bill
of materials, and measured performance of many useful circuits. TI reference designs are available online at
https://www.ti.com/reference-designs.
9.1.1.6 Filter Design Tool
The filter design tool is a simple, powerful, and easy-to-use active filter design program. The filter design tool
allows the user to create optimized filter designs using a selection of TI operational amplifiers and passive
components from TI's vendor partners.
Available as a web-based tool from the Design tools and simulation web page, the filter design tool allows the
user to design, optimize, and simulate complete multistage active filter solutions within minutes.

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9.2 Documentation Support

9.2.1 Related Documentation
For related documentation, see the following application reports and publications (available for download from
www.ti.com):
• Texas Instruments, QFN/SON PCB Attachment
• Texas Instruments, Quad Flatpack No-Lead Logic Packages
• Texas Instruments, EMI Rejection Ratio of Operational Amplifiers
9.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
9.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
9.5 Trademarks
TINA-TI™ and TI E2E™ are trademarks of Texas Instruments.
TINA™ is a trademark of DesignSoft, Inc.
Bluetooth® is a registered trademark of Bluetooth SIG, Inc.
PSpice® is a registered trademark of Cadence Design Systems, Inc.
All trademarks are the property of their respective owners.
9.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.

9.7 Glossary
TI Glossary This glossary lists and explains terms, acronyms, and definitions.

10 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

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 PACKAGE OPTION ADDENDUM

www.ti.com 27-Jun-2024

PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

OPA2277AIDRMT ACTIVE VSON DRM 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM BHZ Samples

OPA2277P ACTIVE PDIP P 8 50 RoHS & Green Call TI | NIPDAU N / A for Pkg Type OPA2277P Samples

OPA2277PA ACTIVE PDIP P 8 50 RoHS & Green Call TI | NIPDAU N / A for Pkg Type (OPA2277P, OPA2277 Samples
PA)
A
OPA2277U ACTIVE SOIC D 8 75 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR OPA Samples
2277U
OPA2277U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 85 OPA Samples
2277U
OPA2277UA ACTIVE SOIC D 8 75 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 85 OPA Samples
2277U
A
OPA2277UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-3-260C-168 HR -40 to 85 OPA Samples
2277U
A
OPA277AIDRMR ACTIVE VSON DRM 8 3000 RoHS & Green NIPDAU Level-1-260C-UNLIM NSS Samples

OPA277AIDRMT ACTIVE VSON DRM 8 250 RoHS & Green NIPDAU Level-1-260C-UNLIM NSS Samples

OPA277P ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA277P Samples

OPA277PA ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA277P Samples
A
OPA277PAG4 ACTIVE PDIP P 8 50 RoHS & Green Call TI N / A for Pkg Type OPA277P Samples
A
OPA277U ACTIVE SOIC D 8 75 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR OPA Samples
277U
OPA277U/2K5 ACTIVE SOIC D 8 2500 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR OPA Samples
277U
OPA277UA ACTIVE SOIC D 8 75 RoHS & Green Call TI | NIPDAU Level-3-260C-168 HR -40 to 85 OPA Samples
277U
A
OPA277UA/2K5 ACTIVE SOIC D 8 2500 RoHS & Green NIPDAU Level-2-260C-1 YEAR -40 to 85 OPA Samples
277U

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 27-Jun-2024

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)
A
OPA277UAG4 ACTIVE SOIC D 8 75 TBD Call TI Call TI -40 to 85 Samples

OPA4277PA ACTIVE PDIP N 14 25 RoHS & Green NIPDAU N / A for Pkg Type OPA4277PA Samples

OPA4277UA ACTIVE SOIC D 14 50 RoHS & Green NIPDAU | NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA Samples

OPA4277UA/2K5 ACTIVE SOIC D 14 2500 RoHS & Green NIPDAU | NIPDAU-DCC Level-3-260C-168 HR -40 to 85 OPA4277UA Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

Addendum-Page 2
 PACKAGE OPTION ADDENDUM

www.ti.com 27-Jun-2024

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF OPA2277, OPA4277 :

• Enhanced Product : OPA2277-EP, OPA4277-EP

• Space : OPA4277-SP

NOTE: Qualified Version Definitions:

• Enhanced Product - Supports Defense, Aerospace and Medical Applications

• Space - Radiation tolerant, ceramic packaging and qualified for use in Space-based application

Addendum-Page 3
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
OPA2277AIDRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
OPA2277AIDRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
OPA2277U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2277U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2277UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA2277UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA277AIDRMR VSON DRM 8 3000 330.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
OPA277AIDRMT VSON DRM 8 250 180.0 12.4 4.25 4.25 1.15 8.0 12.0 Q2
OPA277U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA277U/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA277UA/2K5 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1
OPA4277UA/2K5 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1
OPA4277UA/2K5 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
OPA2277AIDRMT VSON DRM 8 250 210.0 185.0 35.0
OPA2277AIDRMT VSON DRM 8 250 210.0 185.0 35.0
OPA2277U/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA2277U/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA2277UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA2277UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA277AIDRMR VSON DRM 8 3000 356.0 356.0 35.0
OPA277AIDRMT VSON DRM 8 250 210.0 185.0 35.0
OPA277U/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA277U/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA277UA/2K5 SOIC D 8 2500 356.0 356.0 35.0
OPA4277UA/2K5 SOIC D 14 2500 356.0 356.0 35.0
OPA4277UA/2K5 SOIC D 14 2500 356.0 356.0 35.0

Pack Materials-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 25-Sep-2024

TUBE

T - Tube
height L - Tube length

W - Tube
width

B - Alignment groove width

*All dimensions are nominal

Device Package Name Package Type Pins SPQ L (mm) W (mm) T (µm) B (mm)
OPA2277P P PDIP 8 50 506 13.97 11230 4.32
OPA2277PA P PDIP 8 50 506 13.97 11230 4.32
OPA2277U D SOIC 8 75 506.6 8 3940 4.32
OPA2277UA D SOIC 8 75 506.6 8 3940 4.32
OPA277P P PDIP 8 50 506 13.97 11230 4.32
OPA277PA P PDIP 8 50 506 13.97 11230 4.32
OPA277PAG4 P PDIP 8 50 506 13.97 11230 4.32
OPA277U D SOIC 8 75 506.6 8 3940 4.32
OPA277UA D SOIC 8 75 506.6 8 3940 4.32
OPA4277PA N PDIP 14 25 506 13.97 11230 4.32
OPA4277UA D SOIC 14 50 506.6 8 3940 4.32

Pack Materials-Page 3
 PACKAGE OUTLINE
D0014A SCALE 1.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

C
6.2
TYP SEATING PLANE
5.8

A PIN 1 ID 0.1 C
AREA
12X 1.27
14
1

8.75 2X
8.55 7.62
NOTE 3

7
8
0.51
14X
4.0 0.31
B 1.75 MAX
3.8 0.25 C A B
NOTE 4

0.25
TYP
0.13
SEE DETAIL A
0.25
GAGE PLANE

0.25
0 -8 1.27 0.10
0.40

DETAIL A
TYPICAL

4220718/A 09/2016

NOTES:

1. All linear dimensions are in millimeters. Dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm, per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.43 mm, per side.
5. Reference JEDEC registration MS-012, variation AB.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(R0.05)
TYP
(5.4)

LAND PATTERN EXAMPLE

SCALE:8X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.07 MAX 0.07 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4220718/A 09/2016
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0014A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

14X (1.55) SYMM

1
14

14X (0.6)

12X (1.27)
SYMM

7 8

(5.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:8X

4220718/A 09/2016
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
 PACKAGE OUTLINE
D0008A SCALE 2.800
SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

SEATING PLANE
.228-.244 TYP
[5.80-6.19]
.004 [0.1] C
A PIN 1 ID AREA
6X .050
[1.27]
8
1

.189-.197 2X
[4.81-5.00] .150
NOTE 3 [3.81]

4X (0 -15 )

4
5
8X .012-.020
B .150-.157 [0.31-0.51]
.069 MAX
[3.81-3.98] .010 [0.25] C A B [1.75]
NOTE 4

.005-.010 TYP
[0.13-0.25]

4X (0 -15 )

SEE DETAIL A
.010
[0.25]

.004-.010
0 -8 [0.11-0.25]
.016-.050
[0.41-1.27] DETAIL A
(.041) TYPICAL
[1.04]

4214825/C 02/2019

NOTES:

1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.

www.ti.com
 EXAMPLE BOARD LAYOUT
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55]
SYMM SEE
DETAILS
1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
[0.05]
5
4
6X (.050 )
[1.27]
(.213)
[5.4]

LAND PATTERN EXAMPLE

EXPOSED METAL SHOWN
SCALE:8X

SOLDER MASK SOLDER MASK

METAL METAL UNDER
OPENING OPENING SOLDER MASK

EXPOSED
METAL EXPOSED
METAL
.0028 MAX .0028 MIN
[0.07] [0.07]
ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

4214825/C 02/2019

NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

www.ti.com
 EXAMPLE STENCIL DESIGN
D0008A SOIC - 1.75 mm max height
SMALL OUTLINE INTEGRATED CIRCUIT

8X (.061 )
[1.55] SYMM

1
8

8X (.024)
[0.6] SYMM

(R.002 ) TYP
5 [0.05]
4
6X (.050 )
[1.27]
(.213)
[5.4]

SOLDER PASTE EXAMPLE

BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X

4214825/C 02/2019

NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

www.ti.com
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