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2022-23Nov-2022VRegularAR20B Tech ECE20ECC11Other

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chandukuriti5
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3 views1 page

2022-23Nov-2022VRegularAR20B Tech ECE20ECC11Other

Uploaded by

chandukuriti5
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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SEMESTER END REGULAR/SUPPLEMENTARY EXAMINATIONS (AR20), NOV - 2022

Electronics and
U.G. Degree Bachelor of Technology
Communication Engineering
Academic Year 2022-2023 Sem. 5th
Course Title
Course Code 20ECC11
RTL CODING TECHNIQUES
Duration 3 Hours Maximum Marks 60 (SIXTY)
Remember % 22 Understand % 61 Apply % 17 Analyze % …

SECTION-I 6 x 2 = 12 Marks
1.
Questions (a to f) RBT Level COs
a Show how 1-bit ALU can be designed. Remember 1
b Give an example to differentiate blocking and non-blocking assignments. Remember 2
Write a single assignment statement to implement a 4 to 1 multiplexer using
c Remember 3
conditional statement.
d Draw the state machine for serial multiplier. Remember 4
e Exemplify Mealy machine. Remember 4
f What is DDR? Remember 5
SECTION-II 4 x 12 = 48 Marks
Questions (2 to 9) RBT Level COs Marks
(a) What are the different modeling styles in Verilog HDL? Remember 1 6M
2 Differentiate between blocking and non - blocking
(b) Remember 1 6M
assignments.
OR
(a) Compare the parallel and priority logic with an example. Understand 2 4M
Illustrate with an example how the design is affected if the
3
(b) ordering of multiple blocking assignments is changed in the Understand 2 8M
same always block.
Demonstrate the inference of Unintentional latches with an
(a) Understand 2 6M
example.
4
Explain the operation of Synchronous reset D flip flop with
(b) Understand 2 6M
help of its RTL.
OR
Illustrate the concept of Gated clock with the help of
(a) Understand 3 6M
5 diagram.
(b) Demonstrate the Verilog RTL code for Ring counter. Understand 3 6M
(a) Differentiate between Moore and Mealy machines. Understand 4 6M
6 Demonstrate the Verilog RTL for a Sequence detector
(b) Apply 4 6M
using FSM.
OR
(a) Demonstrate the Verilog RTL for pipelining in a design. Apply 2 6M
7 Explain the implementation of priority checking with
(b) Understand 2 6M
help of an RTL.
(a) What is Bus arbitration, draw a diagram Understand 5 6M
8 (b) Write the Verilog code for Single port RAM Apply 5 6M
OR
Explain the different functional blocks of an SRAM
9 (a) Understand 5 6M
controller.
(b) Outline the control path and data path in digital design Understand 6 6M
******

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