Linear Integrated Circuits

Laboratory Manual

Name :

USN :

Dr. S.B. Bhanu Prashanth

Professor
Department of Medical Electronics
B.M.S. College of Engineering
Bengaluru 560 019

021
Dept of ECE, PPGIT 1 4th Sem LIC Lab Manual
 CONTENTS

Sl. Page
No. Particulars No.
Basic Op-Amp Applications
1. 3
Voltage to Current Converter
2. 9
Instrumentation Amplifier
3. 12
Wein Bridge and RC Phase-shift Oscillators
4. 16
ZCD & Voltage Level detectors
5. 20
Schmitt Trigger Circuit
6. 24
Precision HW and FW Rectifiers.
7. 28
First & Second order Active Low Pass Filters
8. 33
First & Second order Active High Pass Filters
9. 38
Astable and Monostable multivibrators using IC 555
10. 43
DAC using R-2R ladder network
11. 50

Get the facts, or the facts will get you.

And when you get them, get them right.
Or they will get you wrong.
- Thomas Fuller

Dept of ECE, PPGIT 2 4th Sem LIC Lab Manual

 EXPERIMENT NO. 1 Date:-
BASIC OP-AMP APPLICATIONS
Aim: To design and study the basic applications of Op-amp as amplifiers and
Summing Amplifiers.
Apparatus Required:
Sl. Particulars Range Quantity
No.
1 Op-amp A 741 2
2. Resistors 1K, 10K 2 each
3. Base board (IC and Spring) 1 each
4. Adopters 2
5. DMM and Probes 1+2 set
6. Connecting wires
7. Power supply 0-5 V & + /-15V 1

Procedure :-
I. Amplifiers:
1. Connections are made as shown in the circuit diagram of figure (1).
2. Input voltage Vi is increased in steps of 0.1 V and at each step the output
voltage Vo is noted down.
3. Readings are tabulated and a graph of Vo Vs Vi is plotted.
4. The input DC supply is replaced with an ASG and a sinusoidal input of
adequate amplitude (to cause output saturation) @ a frequency of 1 KHz is
applied. The input and output are simultaneously fed to a CRO and the transfer
curve is observed and traced.
5. The above procedure is repeated for circuit of figure (2).
II. Adders/Subtractors :- [In Inverting and Non-inverting modes]
1. Connections are made as shown in the circuit diagram of figure (3).
2. Different input voltages (V1 and V2) are applied and the output voltage is
measured using a multimeter.

Dept of ECE, PPGIT 3 4th Sem LIC Lab Manual

 3. The readings are tabulated and the measured values are compared with the
theoretical values.
4. The above procedure is repeated for circuits of figures (4), (5).
III. Buffer/ Voltage Follower:-
1. Connections are made as shown in the circuit diagram of figure (6).
2. The input voltage is varied in steps and the output voltage is noted to be
approximately equal to input.
Circuit diagrams and designs:-

1) Inverting Amplifier :-

Rf = 10 K 

+15 V
R1 = 1K 

(0-30V) Vi V0 =  Rf 
  Vi


 R1 

-15V Af = 10

Fig (1) :Circuit diagram of an Inverting amplifier:

Vo volts
+VSAT

Vi Volts 
-VSAT

Fig (1a): Transfer Characteristics of Inv.Amp

Dept of ECE, PPGIT 4 4th Sem LIC Lab Manual

 Design Example:

Let |Av | = 10 . Choose R1 = 1 k

Rf
|Av| = Therefore Rf = 10 k
R1
Tabular Column:-
Sl. Vi Volts Vo (Theoretical) Vo (Practical)
No. Volts Volts

2) Non- Inverting Amplifier:- Rf =10 K



 +15 V

 R1 = 1 K
 R f 
V0 = 1   Vi
 R 1 



 -15 V
 Vi
 (0-30 V)


Fig (2): Circuit Diagram of a Non –inverting amplifier

Dept of ECE, PPGIT 5 4th Sem LIC Lab Manual

Design Example :
Rf
Let |Av | = = 11. Let R1 = 1 K  .== > Rf = 10 k
R1

Vo volts
+VSAT

-VSAT Vi Volts 

Fig (2a) :Transfer Characteristics of Non-inv Amp

Tabular Column :-
Sl. Vi Volts Vo (Theoretical) Vo (Practical)
No.
0.0
0.1
0.2
-0.3
-0.65
3.0
-3.0
---------------------------------------------------------------------------------------------------
3) Inverting adder :-
Rf = 10 K

+15V
10K R1

10K R2

Vo
(0-5V) (0-5V)
V1 V2
-15V

Fig (3): Circuit diagram of an Inverting adder

Dept of ECE, PPGIT 6 4th Sem LIC Lab Manual

 R 
Design Example: R f
Vo = -  fV 
 V1 2 
 

 R1 R2 
If Rf = R1 = R2 = 10 K . Then V 0 = - [V1 + V2]
Tabular Column :-

Sl. V1 (volts) V2 (Volts) Vo (volts)

No.

5) Differential Amplifier as Subtractor ;-

Rf = 10 k

 +15 V


 R1 =10 k
V2
Vo = V2 – V1
R2 = R1 =10 k
V1

-15V

R3 = Rf = 10 k

Fig (5): Circuit Diagram of Subtractor ( Differential Amplifier )

Design Example:-
Vo = - R f V2  V1 
R1
R1 = R2 = Rf = 10 k   Vo = [V1 – V2]

Dept of ECE, PPGIT 7 4th Sem LIC Lab Manual

Tabular Column :-

Sl. V1 V2 Vo(practical) Vo (theoritical)

No. Volts Volts Volts Volts

6) Buffer/Voltage Follower ;-

+15V

Vout= Vin

-15V
Vin

Fig (6): Circuit diagram of a Buffer

TABULAR COLUMN:-

Sl. Vin Volts Vout Volts

No.

Dept of ECE, PPGIT 8 4th Sem LIC Lab Manual

 Experiment No. 2 Date:

VOLTAGE TO CURRENT CONVERTER

AIM : To design and test I to V and V to I converters for the given specifications.

APPARATUS REQUIRED:

Sl.
Particulars Range Quantity
No.
1 IC A 741 1
2 Milli ammeters 0-100 mA 1
0-50 mA 1
0-10 mA 1
3 Power supply 0-30 volts 1
4. Power supply +15 / –15 V 1
5. Resistors 470  2
1 k  2
6 IC base board 1
Base board 1
7 Multimeter and probes 1 set
8 Connecting wires

PROCEDURE :-

I. Voltage to Current converter:-

1. The connections are made as shown in the circuit of figure (1).

2. The load resistor RL a constant value ( say RL = 200  )
3. The input voltage Vi is varied in steps and corresponding values of If are
noted. The theoretical values of If are computed and compared.
4. All the readings are tabulated in table (1).
5. The i/p voltage Vi is kept at a constant value ( at 2 Volts ) and the load
resistance is varied from around 50 ohms to 10 kohms and at each step the
corresponding values of IL & VL are noted down and recorded in table (2).
6. The above procedure is repeated for circuit of figure (2). The readings are
tabulated in tables (3) and (4).

Dept of ECE, PPGIT 9 4th Sem LIC Lab Manual

 (0-10)mA R LOAD

+ - DRB
 IR +15 V
R= 1 k
 I1
Vsource VI
-15 V

Fig (1): V TO I CONVERTERS FOR FLOATING LOAD

Vi
Design Example: I1 = IR = because of virtual ground .
R
1
Therefore IL = VI
R
Here IL is independent of RLOAD within specified limits.
Choose R = 1 k 

Therefore IL = ( 10 –3 VI ) Amperes. Where VI is in volts.

Tabular Column (1):- Tabular Column (2):-

For RL = 200  constant Vi = 2 V constant
Vi IL (Practical) IL (Theoretical) RL IL
Volts

Dept of ECE, PPGIT 10 4th Sem LIC Lab Manual

 R2

470 
+15 V
R1 470 

-15 V
R3 =R1 R4 = R2
470  470 
Vin 0-10 mA (MC)

RL VL

Fig (2): V to I Converter for grounded Load

[ Also called Howland Current Generator ]
Design Example :-
1
Io = Vi
R3
Let R3 = 470 
Then Io = 0.0021 x Vi volts
Io = Amps

Tabular Column(3):- Tabular Column(4):-

RL = 500  constant Vi = 5 volts (constant)
Vi in IL IL (Practical) RL IL VL
volts (Theoretical)

Dept of ECE, PPGIT 11 4th Sem LIC Lab Manual

 Experiment No. 3 Date :

INSTRUMENTATION AMPLIFIER

AIM : To design and test an instrumentation amplifier for the given gain and to
determine CMRR.

APPARATUS REQUIRED :
Sl.
Particulars Range Quantity
No.
1. IC A 741 3

2. Resistors 10 k  7

3. Power supply +15 / –15 V 1

0-30 volts 2

4. Multimeter and probes 1 set

5. Connecting wires 1 set

6. IC base board 1

7. Base board 1

PROCEDURE :
1. Circuit connections are made as shown in figure (1) for the differential mode .
2. Inputs V1 and V2 are varied in steps and Vo is measured using a Multimeter
and tabulated.
3. The Differential gain is calculated and verified with the designed gain.
4. For the common mode, connections are made as per circuit diagram (2), and Vin
is varied in steps ( 2 V, 3V etc., ) .Vo is measured using a multimeter and
recorded at each step.
4. The Common mode gain is calculated and recorded.
5. The CMRR in calculated and recorded.

Dept of ECE, PPGIT 12 4th Sem LIC Lab Manual

CIRCUIT DIAGRAMS AND DESIGN:-
+Vcc
+15 V

R1 Rf
Vx .
10 k  10 k

10 k  R4 +Vcc
- Vee +15 v
-15 V
+
_ V2( 0-30V ) Rg Vo
10 k 

+Vcc R4
+ 15v 10 k  R3 = Rf - Vee
=10 k  -15 V

V1( 0-30V )

Vy R2 = R1 = 10 k 

- Vee
-15 V
Fig (1) : INSTRUMENTATION AMPLIFIER IN DIFFERENTIAL MODE

Design Example:-
R  2R 4
Vo =  f 1  (V1  V2 )
R1  R g 
V R  2R 
Avf = 4 
o
=  f 1
V 1  V2 R1  R g 
For Rf = R1 = R4 = Rg = 10 K

Vo = -3 ( V1 – V2) i.e. Vo = - 3 Vd

Dept of ECE, PPGIT 13 4th Sem LIC Lab Manual

Tabular Column (1):-
V1 V2 Vo Vo Vo
in volts in volts (Theoretical) (measured) Ad =
V1  V2
in volts in volts diff. gain
0.0 0.5
1.5 0.8
2.0 2.6
2.2 2.55
5.4 4.4
6.4 7.4
4.6 6.8

Average A d =
---------------------------------------------------------------------------------------------------
+Vcc
+15 V

R1 Rf
Vx .
10 k  10 k

10 k  R4 +Vcc
- Vee +15 V
-15 V

Rg Vo
10 k 

+Vcc R4
+ 15v 10 k  R3 = Rf - Vee
=10 k  -15 V

V2

Vy R2 = R1 = 10 k 

Vin
- Vee -15 V
Fig (2):- INSTRUMENTATION AMPLIFIER IN COMMON MODE

Dept of ECE, PPGIT 14 4th Sem LIC Lab Manual

Tabular Column
Vin Vo in volts Vo
Ac =
in volts Vin
Common mode gain

2.0
3.0
5.6
12.0

Average A c =
---------------------------------------------------------------------------------------------------

Ad
CMRR = 20 log ----------( in dBs )
Ac

Results:-

Exercise : Design and test an Instrumentation Amplifier for different gains like
30 and 100. Calculate the CMRR and comment on the results.

Dept of ECE, PPGIT 15 4th Sem LIC Lab Manual

 Experiment No. 4 Date:

WEIN BRIDGE AND RC PHASE-SHIFT OSCILLATORS.

AIM : To design and test Op-amp based Weinbridge and RC -Phase Shift
Oscillators.

APPARATUS REQUIRED :

Sl.
Particulars Range Quantity
No.
1. OP-Amp LM 741 or OP 07 1
2 Resistors 2
3. Capacitors 2
4. Dual Power Supply + / –15 volts 1
5. IC Base board 1
6. Multimeter and probes 1 set
7. Connecting wires

PROCEDURE :-

1. The Wein bridge oscillator is designed for a given value of frequency

( say 1 kHz ) and the connections are made as shown in figure (1).
2. The dual power supply is verified to be +/- 15 V and then switched ON.
3. The feed-back resistor Rf is adjusted to get sustained oscillations.

4. The output waveform is observed on the CRO. The frequency and amplitude of
oscillations are measured and recorded.
5. The measured frequency is compared with the designed frequency.

6. Steps 1-5 are repeated for different frequencies.

7. The above procedure is repeated for the RC Phase-shift oscillator circuit shown
in figure (2).

Dept of ECE, PPGIT 16 4th Sem LIC Lab Manual

Circuit diagrams and designs:-

I. WEINBRIDGE OSCILLATOR :-
Rf = 2Rin

DRB
Rin +Vcc

V0 to CRO

-VEE

R1

C1

R2 C2

Fig (1): CIRCUIT DIAGRAM OF WEINBRIDGE OSCILLATOR

DESIGN EXAMPLE : The expression for frequency is :

1 1
f= Assuming R1 = R2 & C1 = C2 , we have f =
2 R1 R2C1C2 2RC

Let f = 1 kHz.

Dept of ECE, PPGIT 17 4th Sem LIC Lab Manual

Assume C = 0.1 F
1 1
f= or R
2RC 2fc

1
 R=  1.591 k
2 x 1K x 0.1 

Rcal =1.59 k , Use R = 1.6 k

The condition for sustained oscillations is :
Rf
1+ 3
Rin

Rf
i.e.  2 or Rf = 2 Rin
Rin
Use Rin = 1 K  . Rf = 2 K  [ Use a DRB and trim Rf to get
sustained oscillations ]
TABULAR COLUMN :-
Sl. R C fcal Tmeas fmeas Vo (p-p) Rf
No.  F in Hz Msec Hz Volts 

Dept of ECE, PPGIT 18 4th Sem LIC Lab Manual

II. RC-PHASE SHIFT OSCILLATOR:-
Rf = 29 R1 DRB

+15V + VCC To CRO

R = R1
10K  0.1F 0.1F 0.1F

C C C

R R
-15V - VEE

Fig (2): CIRCUIT DIAGRAM OF RC-PHASE SHIFT OSCILLATOR

DESIGN EXAMPLE :- To design for a frequency of f = 1 KHz

The frequency of oscillations is given by f= 1
2 6RC
Let f = 1 kHz. Assuming C = 0.1 F
1 1
f= == > R=
2 6RC 2 6 f C
1
R= = 649.747  [ Use R = 660  ]
2 6 x 1K Hz x 0.1F
Rf
The Necessary condition to get sustained oscillations is  29
R1
Therefore Rf = 29 R1
Assuming R1 , Rf can be found [ R1  10 R ]
Let R1 = 10 K  == > Rf = 290 K 
TABULAR COLUMN:-
Sl. R C fcal Tmeas f meas Vo (P-P) Rf
No.  F Hz m sec Hz volts 
1 660 0.1 984

Dept of ECE, PPGIT 19 4th Sem LIC Lab Manual

 Experiment No. 5 Date:

ZCD AND VOLTAGE LEVEL DETECTORS.

AIM : To design and test the operation of ZCDs and voltage level detectors.

APPARATUS REQUIRED :

Sl.
Particulars Range Quantity
No.
1. IC A 741 1

2. Power supply +15 v to –15 v 1

3. ASG and probes 1 set

4. Adapters, CRO 3+1

5. Multimeter and Probes 1 set

6. IC base board, base board

7. Connecting wires

PROCEDURE :

1. Circuit connections are made as shown in figure (1)

2. Sinusoidal input signal of is applied from an ASG.
3. Vo is observed on CRO . The Transfer characteristics is observed and the
switching points at the Zero Crossing of the input are noted.
4. The circuit of figure (1) is modified to detect the input-crossing at specific
positive and negative voltage levels == > Voltage Level detectors of figure (2)
& (3) are tested.

Dept of ECE, PPGIT 20 4th Sem LIC Lab Manual

Circuit diagrams, Waveforms and Transfer Characteristics :-

(1) ZCD

+VCC
R =10K

Vo

Vin
-VEE

Fig (1): ZCD CIRCUIT

Zero Crossing

Vm
Vi
Volts time

+ VSAT

Vo
Volts time

- VSAT

Fig (1a): INPUT- OUTPUT WAVEFORMS of a ZCD

Dept of ECE, PPGIT 21 4th Sem LIC Lab Manual

 (2) Positive Voltage Level Detector

+VCC
10K

Vo

Vin
-VEE
VR (2V)

Fig (2): Positive Voltage Level Detector CIRCUIT

Vm
+2V
Vi
Volts time

1: VN > VP
2: VP > VN
+ VSAT

Vo
Volts time

- VSAT

Fig (2a): INPUT- OUTPUT WAVEFORMS of a Positive Voltage Level Detector

Dept of ECE, PPGIT 22 4th Sem LIC Lab Manual

 (3) Negative Voltage Level Detector

+VCC
10K

Vo

Vin
-VEE
VR (-2V)

Fig (3): Negative Voltage Level Detector CIRCUIT

Vm
Vi
Volts time
- 2V

+ VSAT

Vo
Volts time

- VSAT

Fig (3a): INPUT- OUTPUT WAVEFORMS of a Positive Voltage Level Detector

Dept of ECE, PPGIT 23 4th Sem LIC Lab Manual

 Experiment No. 6 Date:-

SCHMITT TRIGGER CIRCUIT

AIM : To design and test an inverting Schmitt trigger circuit for a given value of
Hysterisis or UTP and LTP points.

APPARATUS REQUIRED:

Sl.
Particulars Range Quantity
No.
1. IC A 741 1

2. Resistors

3. Power supply +15 v to –15 v 1

4. ASG and probes 1 set

5. Adapters, CRO 3+1

6. Multimeter and Probes 1 set

7. IC base board, base board

8. Connecting wires

PROCEDURE:

1. Circuit connections are made as shown in figure (2)

2. Sinusoidal input signal of adequate amplitude ( more than the UTP & LTP
values ) is applied from an ASG.
3. Vo is observed on CRO . The Transfer characteristics is observed and the
switching points [ UTP & LTP ] are verified and noted.
4. The circuit is designed for a different value of hysterisis and tested.

Dept of ECE, PPGIT 24 4th Sem LIC Lab Manual

Circuit diagrams, Waveforms and Transfer Characteristics :-

+VCC
R

Vo

Vin R1
-VEE

R2

VR = 0
Fig (1) :SCHMITT TRIGGER CIRCUIT

+VSAT Vm
UTP
Vi
Volts time
-  VSAT LTP

+ VSAT

Vo
Volts time

- VSAT
Fig (1a): INPUT- OUTPUT WAVEFORMS ( with VR = 0 )

Dept of ECE, PPGIT 25 4th Sem LIC Lab Manual

 Y- axis

+VSAT

Vlt Vut Vi = +Vm

Vi =-Vm -Vsat Vsat X-axis

-Vi Volts +Vi Volts

Hysterisis Voltage
(Vu t – Vl t) -VSAT

Vu t = Vcc = Upper trip point / UTP

Fig (1b) : TRANSFER CHARACTERISTICS ( With VR = 0 ) Vl t = - Vcc = Lower trip point / LTP

Design Example : To design a Schmitt trigger circuit using op-amp for an UTP
of +5 volts and LTP of +2 volts . Assume +VSAT = +14 volts and - VSAT = -14 V.

+15 Volts
1 k
R Vo

Vin
-15 Volts R1 ( 27.7 k  )

R2 ( 3.3 k  )

VR = 3.96 volts
Fig (2): Circuit diagram of Schmitt trigger for design example ( 1)

Dept of ECE, PPGIT 26 4th Sem LIC Lab Manual

 Y- axis
Vo volts
Vsat = +14 volts

- X-axis - Vm 2V 5V +Vm
X- axis
-Vi Volts +Vi Volts

-Vsat
= -14 volts

- Vo
volts -Y axis
Fig (1b) : TRANSFER CHARACTERISTICS ( With +ve VR )

WKT : UTP =  VSAT + K VR --- ( 1)

LTP = - VSAT + K VR --- (2)
& VH = UTP – LTP ---( 3 ) Step(2) : To find VR :
UTP =  Vcc + KVR
Given : VH = 5 –2 = 3 i.e.  VSAT = 1.5
Step ( 1)
Eqn(1)-Eqn(2)= Eqn (3) yields We can write
2  VSAT = 3 5 = 1.5 + KVR
3 R1
=  0.1071428 3.5 = VR
28 R1  R 2
R2
 0.1071428 3.5 = 0.8935483 VR
R1  R 2
or R1 = 8.333 R2 or VR = + 3.92 volts
for R2 = 3.3 k 
we get R1 = 27.7 k 

Dept of ECE, PPGIT 27 4th Sem LIC Lab Manual

 Experiment No.7 Date:
PRECISION HW & FW RECTIFIERS
Aim : To rig up and test Half wave and Full wave Precision Rectifiers.
Apparatus Required :
Sl. Apparatus Range Quantity
No.
1. IC A 741 2
2. Diodes BY 127 2
3. Resistors 10 k  5
1 k  2
4. Multi meter 1
5. Adopters 3
6. IC base board, 1 set
Base board
7. ASG, Power 1 set
supply, CRO
8. Connecting wires 1 set

Procedure :
1) Connections are made as shown in the circuit of figure (1).
2) The bias supply is switched ON.
3) Sinusoidal input voltage of amplitude less than 0.7 V at a frequency of 1 kHz is
applied and the output waveform is observed.
4) The input and output waveform are observed together on the CRO. The CRO is
then set to X-Y mode and its transfer characteristic is observed.
5) The Values of Ra and / or Rb are changed and the change in the slope of
the transfer curve is observed.
6) The above procedure is repeated for circuits of figure (2), (3)and (4).

Dept of ECE, PPGIT 28 4th Sem LIC Lab Manual

 Circuit Diagrams and Waveforms:-
Sl.No 1. ( Ra ) 10 K

D2 IN4001

+VCC

(Rb)
D1
10K

ASG IN4001

Vi = 0.2 v
fi = 1 KHz -VEE VO to CRO

Fig (1):- Negative half wave rectifier circuit.

Vi  Vm
Volts t

Vo  D2 on D1 on D2 on D1 on
Volts D1 off D2 off D1 off D2 off t

Vo

 Vi Vi 
Transfer Characteristics
Fig (1a): WAVEFORMS & TRANSFER CURVE

Dept of ECE, PPGIT 29 4th Sem LIC Lab Manual

 Sl.No 2.
(Ra) 10 K


 D2 IN4001

 +VCC


 D1

10K


ASG IN4001

 Vi = 0.2 V
fi = 1 KHz -VEE VO to CRO

Fig (2) : Positive half wave rectifier circuit.

Vi  Vm
Volts t

Vo 
Volts t
D1 on D2 on D1 on D2 on
D2 off D1 off D2 off D1 off

 Vi Vi 

+Vi (max)
Vo

-Vo

max Transfer Characteristics

Fig (2a) : WAVEFORMS & TRANSFER CURVE

Dept of ECE, PPGIT 30 4th Sem LIC Lab Manual

 Sl.No 3. ( Ra ) 10 k  10 k  10 k

+Vcc +Vcc
IN4001
10 k

fI = 1KHz
VI = 0.2v
ASG

IN4001 VO TO CRO
-VEE -VEE

( Rb ) 10 K

Fig (3) : Positive Full Wave Rectifier Circuit

Vi  Vm
Volts t

Vo 
Volts t

Vo

-VI(max) VI (max)  Vi
 Vi

Fig (3a): WAVEFORMS & TRANSFER CURVE

Dept of ECE, PPGIT 31 4th Sem LIC Lab Manual

Sl.No 4. Ra R R

+Vcc +Vcc
IN4001
R

Fin = 1KHz
Vin = 0.2 V
ASG

IN4001 V0
-VEE -VEE

Rb Use R=Ra=Rb= 10 K initially

Fig (4) : Negative Full Wave Rectifier Circuit

Vi  Vm
Volts t

Vo 
Volts t

Vo

-VI(max) VI (max)  Vi
 Vi

Fig (4a): WAVEFORMS & TRANSFER CURVE

Dept of ECE, PPGIT 32 4th Sem LIC Lab Manual

 Experiment No. 8 Date:

FIRST AND SECOND ORDER ACTIVE LOW PASS FILTERS

AIM : To design and test I and II order ACTIVE LOW pass filters, and to obtain
the frequency responses.

APPARATUS REQUIRED:

Sl.
Particulars Range Quantity
No.
1. OP amp A 741
2. Resistors 10 k  3
3. Capacitors 0.01 F 2
4. ASG, CRO
5. Adopters 2
6. Power supply +/-15V 1
7. Multimeter and probes 1 + 2 set
8. IC base board 1
base board 1
9. Connecting wires

PROCEDURE :
1. The first order LPF is designed for a given cut-off frequency fh , say 5 KHz .
2. Connections are made as shown in figure(1) as per the design.
3. The input voltage is kept at a constant value ( say 2 V ) and the frequency is
varied from 10 Hz to 100 KHz in steps, and at each step the output voltage is
measured using a CRO and recorded.
4. The readings are tabulated and the gains in dB are calculated.
5. A graph of frequency Vs. gain in dB is plotted and the actual cut-off frequency
(fh ) and the slope in the stop band (Roll-off rate) are determined from the
graph plotted.
6. The above procedure is repeated for a II order LPF shown in figure (2).

Dept of ECE, PPGIT 33 4th Sem LIC Lab Manual

 Circuit Diagrams , Ideal Graphs and Designs :-

Rf

10 k 
+15 v
R1
10 k
3.3 k
R

ASG Vin C -15 V TO CRO

0.01 F

Fig (1): FIRST ORDER LOW PASS FILTER

Design Example:-

Let the filter’s PB gain Af = 2

Choose Rf = R1 = 10 k 


1
WKT, fh = . Given fh = 5 KHz
2RC
1  3.183 k  .
If C = 0.01 F then ., R = 2 x 0.01  x 5k

[ Use 2.2 K + 1 K ]

AF 3 dB
0.707 Af
-20 dB/ decade
Voltage Gain dB
Pass Band Stop band
fh Frequency ( Log Scale)
Fig (1a) : Frequency response curve

Dept of ECE, PPGIT 34 4th Sem LIC Lab Manual

 Tabular column :-

Constant Vin = 2.0 volts

Sl. Frequency Vo volts Vo 20 logAv

Av =
No. (Hz) (Gain in dBs)
Vi

Rf = 5.86 k 


- 15 V

 R1
 10k
Vo
R2 R3

3.3k 3.3 k

C3 0.01 F
Vin 0.01F C2 -15 V CRO

Fig (2) : Circuit Diagram of Second order low pass filter

Dept of ECE, PPGIT 35 4th Sem LIC Lab Manual

 Design Example:
For Butterworth response (Flat Pass band), Af = 1.586
R
But Af = 1 + f
R1
let R1 = 10 k  , therefore Rf = 5.80 k 

1
Now fh = Assuming R2 = R3 = R and C2 = C3 = C ,
2 R2 R3C2C3
1
We have fh = Given fh= 5 kHz.
2 RC
Assuming C = 0.01 F ,
1
R= = 3.183 K [Use 2.2 K + 1 K]
2 x 0.01 x 5 k

Frequency response curve

Y – axis

Af
0.707 Af -40 dB/ decade
Voltage Gain
Pass Band Stop Band
Frequency ( Log Scale)
fh
Fig(2a) : Frequency response curve

TABULAR COLUMN :-
Constant Vin = 4 volts
Sl. Frequency Vo volts Vo 20 logAv
Av =
No. (Hz) (Gain in dBs)
Vi

Dept of ECE, PPGIT 36 4th Sem LIC Lab Manual

Dept of ECE, PPGIT 37 4th Sem LIC Lab Manual
 Experiment No. 9 Date:

FIRST AND SECOND ORDER ACTIVE HIGH PASS FILTERS

AIM: To design and obtain the frequency responses of I and II order active
high pass filters :

APPARATUS REQUIRED:

Sl. Particulars Range Quantity

No.
1. Op amp A 741 IC 1
2. Resistors
3. Capacitors 0.01 F 1
4. ASG, CRO 1
5. Adopters 2
6. Power supply +/– 15 V 1
7. Multimeter with 1+ 2 set
probes
8. Base board , 1 set
IC Base board
9. Connecting wires 1 set

PROCEDURE :-
7. The I order HPF is designed for a particular cut-off frequency ( fL )
( say 5 KHz ) by choosing proper values of R and C .
8. Connections are made as shown in figure(1) as per the design.
9. The input voltage is kept at a constant value ( say 2 V ) and the frequency is
varied from 10 Hz to 100 KHz in steps, and at each step the output voltage is
measured using a CRO and recorded.
10. All the readings are tabulated and the gain in dB is calculated.
11. A graph of frequency Vs. gain in dB is plotted and the actual cut-off frequency
(fL ) and the slope in the stop band are determined from the graph plotted.
12. The above procedure is repeated for the circuit of a II order HPF shown in
figure (2).

Dept of ECE, PPGIT 38 4th Sem LIC Lab Manual

CIRCUIT DIAGRAMS,DESIGNS AND FREQUENCY RESPONSES:-
Rf

10 k 

+VCC
+15 V
R1

10 k 
Vo to CRO

C 0.01 F
Vin R - VEE
(3-4) V ASG 3.3 k  - 15 V

Fig (1) :CIRCUIT DIAGRAM OF I ORDER HIGH PASS FILTER

FREQUENCY RESPONSE:-
Y – axis Pass Band gain = AF = 2

AF
3 dB
0.707 AF

20 dB / dec

Stop Band Pass Band

X- axis

Fig (1a) fL = 5K [ Log Scale ]

Frequency 

DESIGN EXAMPLE:-

1
The cut-off frequency fL =
2 RC
Let C = 0.01 F
1
5K= R = 3.18 k  { Use 2.2K and 1K in series }
2 0.01  * R
Rf
Use R1 = Rf = 10 k   AF = 1+ A gain of 2.
R1

Dept of ECE, PPGIT 39 4th Sem LIC Lab Manual

TABULAR COLUMN:-
CONSTANT Vin = 4 volts
Vo
f in Hz V o Volts AV = AV in dB
Vi

-------------------------------------------------------------------------------------------------

Rf

5.86 k 

+VCC
+15 V
R1
10 k 

C C Vo to CRO

0.01 F
Vin R 3.3 k  R 3.3 k  - Vee
(3-4) V ASG - 15 V

Fig (2) :CIRCUIT DIAGRAM OF II ORDER HIGH PASS FILTER

Dept of ECE, PPGIT 40 4th Sem LIC Lab Manual

DESIGN EXAMPLE:-
Rf
For the Circuit, PB gain is AF = 1+
R1
For Butterworth response AF = 1.586
Let R1 = 10 k ,

R F = R 1 AF – R 1 = R 1 ( 1.586 – 1)
= 10 K x 0.586 = 5.86 k 
1
for f = 5 kHz fL =
2 RC
1
Let C = 0.01 F R=
2 x 5 k x 0.01 
R = 3.18 k 

FREQUENCY RESPONSE:-
Y – axis

AF
3 dB
Voltage gain 

0.707 AF

40 dB / dec

Stop Band Pass Band

X- axis

Fig (2a) fL = 5K [ Log Scale ]

Frequency 

Dept of ECE, PPGIT 41 4th Sem LIC Lab Manual

TABULAR COLUMN:-
CONSTANT Vin = 4 volts
Vo
f in Hz V o Volts AV = AV in dB
Vi

Dept of ECE, PPGIT 42 4th Sem LIC Lab Manual

 Experiment No. 10 Date:

ASTABLE & MONOSTABLE MULTIVIBRATORS USING

555 TIMER

AIM : To design and test Astable and Monostable Multivibrators for the
given specifications using 555 timer IC.

APPARATUS REQUIRED:
Sl.
Particulars Range Quantity
No.
1. IC 555 1

2. Diodes IN 4001 2

3. Capacitor 0.1 and 0.01 F 1

4. DCB, ASG, Base board 1

5. DRB

6. Resistors 1

7. Power supply +5V 1

8. CRO and Probes 1 set

9. Multimeter and probes 1 set

10. Adopters & wires 3 sets

PROCEDURES :-

I . Astable Multivibrators ( AMVs)

1. Connections are made as shown in the circuit of figure (1) and the power
supply is switched ON.
2. The output voltage waveform and the voltage across the timing capacitor are
observed and traced using a CRO.
3. All the relevant voltage levels like 1/3 Vcc , 2/3 Vcc are noted.

Dept of ECE, PPGIT 43 4th Sem LIC Lab Manual

 Ton and Toff are also measured and noted. The frequency of oscillation and

the duty cycle are calculated and verified against the theoretical values.
5. The above procedure is repeated for different duty cycles as shown in
circuits of figure (2 ) and ( 3).
II. Monostable Multivibrator:-
1. The MMV is designed for a particular ‘Pulse width’ as per the design shown
and the connections are made as shown in circuit of figure(4).
2. The input trigger signal’s frequency and duty cycle are set to appropriate values
and the output waveform is observed and verified for the required pulse width.
3. The following combinations of waveforms are observed together on a CRO
and traced. a) Trigger signal and output signal
b) Output waveform and Capacitor voltage
1) The pulse width is measured and noted
2) The above procedure is repeated for a different value of pulse width.

Gnd 1 8 Vcc

Trigger 2 7 Discharge

Output 3 6 Threshold

Reset 4 5 Control Vg

Fig (a) : PIN DIAGRAM OF 555 timer

Note :-
In the circuit diagrams that follow, only pin numbers are marked.
Referring to the pin diagram of Fig ( a) , specify the pin functions
accordingly for all the circuit diagrams.

Dept of ECE, PPGIT 44 4th Sem LIC Lab Manual

Circuit Diagrams, Waveforms and Designs:-

Design Example 1 : To Design an Astable multivibrator circuit using 555 timer for
f = 1 KHz, duty cycle = 70 % and Vout = 5 Volts.

+Vcc

4 8

1.33 k  RA
3 o/p to CRO
7

1k RB

6
+ 0.44 F
- C 1 5

0.01 F

Fig ( 1 ) : Circuit of Astable Multivibrator for duty cycle > 50 %

We Know that
T1 = 0.69 ( RA + RB) C and T2 = 0.69 RB C
T1 R  RB
and Duty Cycle =  A
T1  T2 R A  2R B
Given duty cycle= 70 %
RA  RB 70
   0.7
R A  2R B 100
or RA + RB = 0.7 RA + 1.4 RB
0.3 RA = 0.4 RB or RA = 1.33 RB
for RB = 1 k  , RA = 1.33 k 
T = T1 + T 2 & T = 0.69 (RA + 2RB) C

Dept of ECE, PPGIT 45 4th Sem LIC Lab Manual

 Given f = 1 KHz, therefore T = 1msec
1ms = 0.69 [ 1.33 K + ( 2 x 1 K ) ] x C
Therefore C = 0.44 F ( Use two numbers of 0.22 F in parallel )

Y
5V

Vo volts
time

2/3 Vcc

Vc (volts)
1/3 Vcc
T1 T2
time

Fig ( 1a ) : Waveforms in an Astable Multivibrator

Design Example 2 : To design an astable multivibrator circuit using 555 timer for
a frequency of 1 KHz, duty cycle = 50 % & Vout =5 Volts.
+5 V

4 8

RA 10 K
3 o/p
7
IN4001
RB 10 K

D1 IN4001
D2
2

6
C 0.01 F 1 5

0.01 F

Fig ( 2 ) : Circuit diagram of AMV for any duty cycle

Dept of ECE, PPGIT 46 4th Sem LIC Lab Manual

 5V

Vo Volts

time

2/3 Vcc

Vc (volts)
1/3 Vcc .
Tc Td
Fig(2a): time

T1 = 0.69 ( RA+ Rf1) C and T2 = 0.69 ( RB+ Rf2) C

Assuming that the diodes’ on- resistances Rf1 & Rf2 are same and neglecting
these, we get T1 = 0.69 ( RA) C and T2 = 0.69 ( RB) C
If RA = RB = 10 k , then duty cycle = { RA / (RA + RB ) } = 50 %
Given f = 1 kHz, and therefore T = 1ms. Further, T1= T2 = 0.5 msec
0.5ms = 0.69 x 10 k  x C  C = 0.072 F
Design Example 3: To design an AMV for 1 KHz, duty cycle = 0.8 & Vout =12 V
+12 V

4 8

RA 30 K
3 o/p
7

RB 10 K

6
C 36 nF
1 5

Dept of ECE, PPGIT 47 4th Sem LIC Lab Manual

 Fig ( 3 ) 0.01 F
T1 = 0.69 ( RA + RB) C and T2 = 0.69 RB C
Given., Duty cycle = 0.8
T1 RA  RB
But Duty cycle =   0.8
T1  T2 RA  2R B
 RA + R B = 0.8 RA + 1.6 RB
or 0.2 RA = 0.6 RB
R A = 3 RB
If RB = 10 K , then RA = 30 K

T = 0.69 ( RA + 2 RB) C
given f = 1 kHz, T = 1ms
Calculating., C = 36 nF.

Monostable Multivibrator ( MMV ):-

+5 V

IN4001 4 8
1 k R
R1

C1= 0.1 F 3 o/p

2
5 V trigger from Pulse Gen

6
C
1 5

0.01 F

Fig (4) :- Monostable multivibrator circuit using 555 timer IC

Dept of ECE, PPGIT 48 4th Sem LIC Lab Manual

Vtrig 5V
Trigger

0 time

V0 (V)
SS QS
tp time
2/3Vcc
VC (V)

time
Fig (4a ) :- Waveforms in a Monostable Multivibrator

NOTE : - SS : Stable State & QS : Quasi Stable State

Design Example 1 : To design a MMV for a pulse width of 1.25 msec

Pulse width = 1.11 RC
tp
RC =
1.11

Let C = 0.1 F ; tp = 1.25 ms

1.25 ms
R=  11.267 k  [ Use a 10 K and 1 K resistors in series.]
1.11x 0.1 

Design Example 2 : To design a MMV for a pulse width of 3.0 msec

1) Let C = 0.1 F
tp = 3ms
tp
R=
1.11 x C
3 x 10 -3 = R = 27.02 k [ Use 10 K + 10 K + 6.8 K in series ]
R=
1.11 x 0.1 x 10 -6

Dept of ECE, PPGIT 49 4th Sem LIC Lab Manual

 Experiment No. 11 Date:

DAC USING R-2R LADDER NETWORK

Aim : To rig up and test a 4-bit R-2R ladder network DAC .

Apparatus Required :

Sl. Particulars Range Quantity

No.
1 A741 IC 1
2. Resistors 2.2 k 18
3. Power supply  15 volts 1
0-5 volts 1
4. Multimeter and - 1 set
probes
5. Spring board, - 1
IC base board 1 set
6. Connecting wires - 1 set

PROCEDURE :
1) Connections are made as shown in fig (1) .
2) The digital inputs b1-b4 are connected to a switch box. The 4 bits are increased
in steps from 0000 to 1111 and at each step Vout is measured using a
multimeter.
3) The readings are tabulated.
4) A graph of digital i/p versus analog o/p voltage is plotted, and the different
parameters as shown in figure(2) are determined and recorded.

Dept of ECE, PPGIT 50 4th Sem LIC Lab Manual

Circuit Diagram:-

3R

2R R R R 2R 2 + 15V

2R 2R 2R 2R 3 4

LSB b0 b1 b2 b3 MSB +15 V Vout

Digital i/ps from switch box

R = 2.2K
Fig(1): Circuit diagram of R-2R DAC

Design :

Vr n1
Where, b  0 or1
Vout=

2 n b 2 i
i
i
i0

When all the digital i/p bits are 1 and Vr = +5 volts.

5
V = 3
b 2i
out
2
4 
i0
i

5
=
24
bo 20  b1 21  b 2 22  b 3 23 
5
=  x15 For a full scale input of 1111
24
Vout( full scale) = -4.6875 Volts

Tabular Column : -

b3 b2 b1 b0 Vout (Theoretical) volts Vout (Practical) Volts

0 0 0 0
0 0 0 1
0 0 1 0
0 1 1 1
0 1 0 0

Dept of ECE, PPGIT 51 4th Sem LIC Lab Manual

 0 1 0 1
0 1 1 0
. . . .
. . . .
. . . .
. . . .
1 1 1 1

Typical Converter Relationship :-

Vout
(Full scale)
gain error

Vout
Resolution or 1 LSB

offset error

0FH Digital i/p 

Fig (2): Typical Converter Relationship

Results:-
1) LSB or Resolution = Volts
2) Offset error = Volts
3) Vout (full scale) designed = Volts
4) Vout (full scale) obtained = Volts
5) Gain error = Volts

~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~

Dept of ECE, PPGIT 52 4th Sem LIC Lab Manual