Digital Integrated Circuits

CMOS Processing Technology

and Design Rules
Advisor: Prof. Yi-Chung Wu ([email protected])
Credited by: Shyh-Jye Jerry Jou
Institute of Electronics, National Yang Ming Chiao Tung University
 CMOS Fabrication
• CMOS transistors are fabricated on silicon wafer
• Lithography process similar to printing press
• On each step, different materials are deposited or etched
• Easiest to understand by viewing both top and cross-section of wafer in
a simplified manufacturing process

• https://www.youtube.com/watch?v=1Lad28K3Xi0

NYCU / ICSS Lab 2

 Inverter Cross-Section
• Typically use p-type substrate for NMOS transistors
• Requires N-Well for body of PMOS transistors

A
GND VDD
Y SiO2

n+ diffusion

p+ diffusion
n+ n+ p+ p+
polysilicon
n well
p substrate
metal1

nMOS transistor pMOS transistor

3
 Well and Substrate Taps
• Substrate must be tied to GND and n-well to VDD
• Use heavily doped well and substrate contacts / taps

A
GND VDD
Y

p+ n+ n+ p+ p+ n+

n well
p substrate

well
substrate tap
tap
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 Inverter Mask Set
• Transistors and wires are defined by masks
• Cross-section taken along dashed line

GND VDD

nMOS transistor pMOS transistor

substrate tap well tap
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 Detailed Mask Views
• Six masks
– n-well n well

– Polysilicon
– n+ diffusion
Polysilicon

– p+ diffusion
– Contact
n+ Diffusion

– Metal
p+ Diffusion

Contact

Metal

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 Fabrication
• Chips are built in huge factories called fabs
• Contain clean rooms as large as football fields

International Business
Machines Corporation. (IBM)
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 Fabrication Steps
• Start with blank wafer
• Build inverter from the bottom up
• First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where N-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2

p substrate

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 Oxidation
• Grow SiO2 on top of Si wafer
– 900-1200 C with H2O or O2 in oxidation furnace
– Si + O2 → SiO2;
– Si + 2H2O → SiO2 + 2H2

SiO2

p substrate

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 Photoresist
• Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light

Photoresist
SiO2

p substrate

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 Lithography
• Expose photoresist through n-well mask
• Strip off exposed photoresist

Photoresist
SiO2

p substrate

11
 Etch
• Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
• Only attacks oxide where resist has been exposed

Photoresist
SiO2

p substrate

12
 Strip Photoresist
• Strip off remaining photoresist
– Use mixture of acids called piranah etch
• Necessary so resist doesn’t melt in next step

SiO2

p substrate

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 n-well
• n-well is formed with diffusion or ion implantation
• Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
• Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si

SiO2

n well

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 Strip Oxide
• Strip off the remaining oxide using HF
• Back to bare wafer with n-well
• Subsequent steps involve similar series of steps

n well
p substrate

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 Polysilicon
• Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
• Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor

Polysilicon
Thin gate oxide

n well
p substrate

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 Polysilicon Patterning
• Use same lithography process to pattern polysilicon

Polysilicon

Polysilicon
Thin gate oxide

n well
p substrate

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 Self-Aligned Process
• Use oxide and masking to expose where n+ dopants should be diffused or
implanted
• N-diffusion forms NMOS source, drain, and n-well contact

n well
p substrate

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 N-diffusion
• Pattern oxide and form n+ regions
• Self-aligned process where gate blocks diffusion
• Polysilicon is better than metal for self-aligned gates because it doesn’t melt
during later processing

n+ Diffusion

n well
p substrate

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 N-diffusion cont.
• Historically dopants were diffused
• Usually ion implantation today
• But regions are still called diffusion

n+ n+ n+

n well
p substrate

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 N-diffusion cont.
• Strip off oxide to complete patterning step

n+ n+ n+

n well
p substrate

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 P-Diffusion
• Similar set of steps form p+ diffusion regions for PMOS source and drain
and substrate contact

p+ Diffusion

p+ n+ n+ p+ p+ n+

n well
p substrate

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 Contacts
• Now we need to wire together the devices
• Cover chip with thick field oxide
• Etch oxide where contact cuts are needed

Contact

Thick field oxide

p+ n+ n+ p+ p+ n+

n well
p substrate

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 Metalization
• Sputter on aluminum over whole wafer
• Pattern to remove excess metal, leaving wires

Metal

Metal
Thick field oxide
p+ n+ n+ p+ p+ n+

n well
p substrate

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 Metalization

Cross-section showing 11 levels of metallization. Image of wire cross-sections in Intel’s 45nm processes

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 Layout
• Chips are specified with set of masks
• Minimum dimensions of masks determine transistor size (and hence
speed, cost, and power)
• Feature size f = distance between source and drain
– Set by minimum width of polysilicon
• Feature size improves 30% every 3 years or so
• Normalize for feature size when describing design rules

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 Simplified Design Rules
• Conservative rules to get you started

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 Inverter Layout
• Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm long

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 CMOS Process Enhancement
• More layers for interconnect and passive capacitor → Increase
routability
– Double, triple level poly or MIM (Metal-Insulator-Metal) → Provide high
quality capacitors
– Refractory gates and polysilicon/refractory metal interconnect → Reduce
sheet resistance of poly line
– Top level metal layers have a coarser pitch as the topology of the silicon
surface is more varied.
– The ith layer metal to i-1th layer metal is connected by a via
• Multiple threshold voltage and oxide thickness → different leakage and
driving current for power and time delay issues.
• High-k gate dielectrics

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 The Triple-Well with Twin-Tub Process
• It provides the basis for separate optimization of p-types and n-types
transistors.
• Epi layer: high purity silicon layers of controlled thickness with accurately
determined dopant concentration distributed homogeneously throughout the
layer.

Twin-Tub process with Deep n-well cross-section and layout of an inverter

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 Latch-Up
• NPN, PNP BJT with resistors
– Larger Rsub and Rwell → more likely a structure is to latch-up
• Latch-Up Operation: Circuit Failure
– BJT turned on → positive feedback → Current flows from VDD to GND

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 Guard Ring
• Avoid Latch-Up
– Provide lower resistance for current
• Reduce Noise
– For analog or mixed-signal circuits
• ESD (Electro Static Discharge)
Protection
– Instant high voltage or large current
flows

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 Layout Design Rules
• The rules provide a necessary communication link between circuit designer
and process engineer during the manufacturing phase
• Design Rules → not correct or incorrect fabrication, but a tolerance that
ensures high probability of correct fabrication
• More aggressive rules → greater improvements in circuit performance
– May be at the expense of cost (due to low yield)
• One May find that a layout that violates design rules may still function
correctly and vice versa.

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 Origin of Rules
• The Rules are written in consideration of
– Electrical characteristics
• Punch-through break, latch-up, electron migration, antenna effect
– Mask line width variation
– Lithographic variation
– Mask alignment
– Exposure time
– Resistance variation: etching time variation, process variation

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