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DIC Lec5

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5 views10 pages

DIC Lec5

Uploaded by

郭之一
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Digital Integrated Circuits

Circuit Characterization and


Performance Estimation
Advisor: Prof. Yi-Chung Wu ([email protected])
Credited by: Shyh-Jye Jerry Jou
Institute of Electronics, National Yang Ming Chiao Tung University
Layout Design Rules
• Pitch = w + s
• Aspect ratio: AR = t/w
– Old processes had AR << 1
– Modern processes have AR  2
• Pack in many skinny wires
w s

h
2
• r = resistivity (W*m)
• t: thickness w w

• L: Conducting length
• W: conductor width l

r l l
R= =R
w

t w w
• Rs: sheet resistance l l

t t

1 Rectangular Block 4 Rectangular Blocks


R = R (L/W) W R = R (2L/2W) W
= R (L/W) W

3
Choice of Metals
• Until 180 nm generation, most wires were aluminum
• Contemporary processes normally use copper
– Cu atoms diffuse into silicon and damage FETs
– Must be surrounded by a diffusion barrier

Metal Bulk resistivity (mW • cm)


Silver (Ag) 1.6
Copper (Cu) 1.7
Gold (Au) 2.2
Aluminum (Al) 2.8
Tungsten (W) 5.3
Titanium (Ti) 43.0
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Copper Issue
• Copper is also prone to dishing during polishing
• Effective resistance is higher
r l
R=
( t − tdish − tbarrier ) ( w − 2tbarrier )

5
Resistance for Rectangular Conductors

6
Metal Layer: Wiring
• Modern processes: 6-10+ metal layers
• M1-M3: thin, narrow for high density cells
• M4-M6: thicker for longer wires
• M7-M9: thickest for VDD, GNS and Clock, Reset

Example of Intel 45nm

7
Contact Resistance
• Contacts and Vias also have 2-20W
• Use many contacts for lower R
– Many small contacts for current crowding around periphery

8
MOS Channel Resistance
• In linear region → Rc = K(L/W)
– Ids = β[ (Vgs-Vt)Vds -V ds2/2]
−1
  ox 
where K= m (V gs −V t )
 t ox 

– Neglect Vds2

9
Capacitance Estimation
• For conventional CMOS process, a capacitor can be formed using
– The gate and channel of an MOS transistor
– Has good capacitance per are but is relatively nonlinear if operated over
large voltage ranges
– A diffusion area (to ground or VDD): The diffusion capacitor cannot be
used for a floating capacitor (where two terminals are not connected to
fixed voltage supply like VDD/GND)
– A parallel metal plate capacitor (using stacked metal layers or finger
capacitors on the same layer)
A
• Parallel plate capacitor: C =  s o
d
• A: Area, d: separation, : dielectric constant

10

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