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Pipe Lining

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2 views12 pages

Pipe Lining

Uploaded by

ummehabeeba057
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Pipelining in Computer Organization

Introduction
Execution stage
Role of Cache Memory
Pipeline performance
Sequential Execution
The processor executes a program by fetching and executing instructions, one after the
other.
Let Fi and Ei refer to the fetch and execute steps for instruction I1.
Execution of a program consists of a sequence of fetch and execute steps.
Overcoming Sequential Execution
Now consider a computer that has two separate hardware units, one for fetching
instructions and another for executing them. The instruction fetched by the fetch unit is
deposited in an intermediate storage buffer, B1.
This buffer is needed to enable the execution unit to execute the instruction while the fetch
unit is fetching the next instruction.
The results of execution are deposited in the destination location specified by the
instruction.
Role of a Clock Cycle in Process Execution
The computer is controlled by a clock.
Any instruction fetch and execute steps completed in one clock cycle.
In the first clock cycle, the fetch unit fetches an instruction I1 (step F1) and stores it in
buffer B1 at the end of the clock cycle.
In the second clock cycle, the instruction fetch unit proceeds with the fetch operation for
instruction I2 (step F2). Meanwhile, the execution unit performs the operation specified by
instruction I1, which is available to it in buffer B1 (step E1).
Stages of Pipelining
FETCH
read the instruction from the memory.

DECODE
decode the instruction and fetch the
source operand(s)

EXECUTE
perform the operation specified by the instruction.

WRITE
store the result in the destination location.
Pipelining: Enhancing Process Execution
Four instructions are in progress at any given time.
This means that four distinct hardware units are needed.
These units must be capable of performing their tasks simultaneously and without
interfering with one another.
Information is passed from one unit to the next through a storage buffer.
Buffer B1 holds instruction I3, which was fetched in cycle 3 and is being
decoded by the instruction-decoding unit.
Buffer B2 holds both the source operands for instruction I2 and the specification of the
operation to be performed.
This is the information produced by the decoding hardware in cycle 3.
The buffer also holds the information needed for the write step of instruction I2 (stepW2).
Buffer B3 holds the results produced by the execution unit and the destination information
for instruction I1.
Role of Cache Memory
The use of cache memories solves the memory access problem.
In particular, when a cache is included on the same chip as the processor, access time to the
cache is usually the same as the time needed to perform other basic operations inside the
processor.
This makes it possible to divide instruction fetching and processing into steps that are more
or less equal in duration.
Each of these steps is performed by a different pipeline stage, and the clock period is chosen
to correspond to the longest one.
Pipeline Hazards and Their Impacts
Data Hazards

A data hazard is any condition in which either the source or the destination operands of an
instruction are not available at the time expected in the pipeline.
As a result some operation has to be delayed, and the pipeline stalls.
Instruction/Control Hazards
Control hazards or instruction hazards: The pipeline may also be stalled because of a delay
in the availability of an instruction.
For example, this may be a result of a miss in the cache
Structural Hazards
A third type of hazard known as a structural hazard:
This is the situation when two instructions require the use of a given hardware resource at
the same time.
Clock cycle 1 2 3 4 5 6 7 8
I
n
s I1 F1 D1 E1 M1 W1
t
r I2 F2 D2 E2 M2 W2
u
c
F3 D3 F3 M3 W3
t I3
i
o I4 F4 D4 E4 M4 W4
n
s
THANK YOU

Submitted by: Submitted to:


Umme Habeeba Dr. Shivasundara Pandian
1HK23CS181

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