PIC32MX5XX/6XX/7XX

32-bit Microcontrollers (up to 512 KB Flash and 128 KB SRAM)

with Graphics Interface, USB, CAN, and Ethernet

Operating Conditions Timers/Output Compare/Input Capture

• 2.3V to 3.6V, -40ºC to +105ºC, DC to 80 MHz • Five General Purpose Timers:
® ® - Five 16-bit and up to two 32-bit Timers/Counters
Core: 80 MHz/105 DMIPS MIPS32 M4K • Five Output Compare (OC) modules
• MIPS16e® mode for up to 40% smaller code size • Five Input Capture (IC) modules
• Code-efficient (C and Assembly) architecture • Real-Time Clock and Calendar (RTCC) module
• Single-cycle (MAC) 32x16 and two-cycle 32x32 multiply
Communication Interfaces
Clock Management • USB 2.0-compliant Full-Speed OTG controller
• 0.9% internal oscillator (on some variants) • 10/100 Mbps Ethernet MAC with MII and RMII interface
• Programmable PLLs and oscillator clock sources • CAN module:
• Fail-Safe Clock Monitor (FSCM) - 2.0B Active with DeviceNet™ addressing support
• Independent Watchdog Timer • Six UART modules (20 Mbps):
• Fast wake-up and start-up - Supports LIN 2.1 protocols and IrDA® support
Power Management • Up to four 4-wire SPI modules (25 Mbps)
• Up to five I2C modules (up to 1 Mbaud) with SMBus
• Low-power management modes (Sleep and Idle)
support
• Integrated Power-on Reset, Brown-out Reset
• Parallel Master Port (PMP)
• 0.5 mA/MHz dynamic current (typical)
• 41 µA IPD current (typical) Direct Memory Access (DMA)
• Up to eight channels of hardware DMA with automatic
Graphics Features
data size detection
• External graphics interface with up to 34 Parallel Master • 32-bit Programmable Cyclic Redundancy Check (CRC)
Port (PMP) pins:
• Six additional channels dedicated to USB, Ethernet and
- Interface to external graphics controller CAN modules
- Capable of driving LCD directly with DMA and
internal or external memory Input/Output
• 15 mA or 10 mA source/sink for standard VOH/VOL and
Analog Features up to 22 mA for non-standard VOH1
• ADC Module: • 5V-tolerant pins
- 10-bit 1 Msps rate with one Sample and Hold (S&H) • Selectable open drain and pull-ups
- 16 analog inputs • External interrupts
- Can operate during Sleep mode
• Flexible and independent ADC trigger sources Class B Support
• Comparators: • Class B Safety Library, IEC 60730
- Two dual-input Comparator modules
- Programmable references with 32 voltage points
Debugger Development Support
• In-circuit and in-application programming
• 4-wire MIPS® Enhanced JTAG interface
• Unlimited program and six complex data breakpoints
• IEEE 1149.2-compatible (JTAG) boundary scan
Packages
Type QFN TQFP TFBGA VTLA
Pin Count 64 64 100 100 121 124
I/O Pins (up to) 51 51 83 83 83 83
Contact/Lead Pitch 0.50 0.50 0.40 0.50 0.80 0.50
Dimensions 9x9x0.9 10x10x1 12x12x1 14x14x1 10x10x1.1 9x9x0.9
Note: All dimensions are in millimeters (mm) unless specified.

 2009-2019 Microchip Technology Inc. DS60001156K-page 1

PIC32MX5XX/6XX/7XX
TABLE 1: PIC32MX5XX USB AND CAN FEATURES
USB and CAN

10-bit 1 Msps ADC (Channels)

(Programmable/Dedicated)
Timers/Capture/Compare
Program Memory (KB)

Data Memory (KB)

DMA Channels

Comparators

Packages(4)
PMP/PSP
UART(2,3)
Device

SPI(3)

Trace
JTAG
I2C(3)
CAN
Pins

USB
PT,
PIC32MX534F064H 64 64 + 12(1) 16 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX564F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX564F128H 64 128 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX575F256H 64 256 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX575F512H 64 512 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX534F064L 100 64 + 12(1) 16 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PF,
BG
PT,
PIC32MX564F064L 100 64 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PF,
BG
PT,
PIC32MX564F128L 100 128 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes PF,
BG
PT,
PIC32MX575F256L 100 256 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PF,
BG
PT,
PIC32MX575F512L 100 512 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes PF,
BG
Legend: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA(5)
Note 1: This device features 12 KB boot Flash memory.
2: CTS and RTS pins may not be available for all UART modules. Refer to the “Device Pin Tables” section for more
information.
3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Device Pin Tables” section for more
information.
4: Refer to 34.0 “Packaging Information” for more information.
5: 100-pin devices in the VTLA package are available upon request. Please contact your local Microchip Sales Office for
details.

DS60001156K-page 2  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 2: PIC32MX6XX USB AND ETHERNET FEATURES
USB and Ethernet

10-bit 1 Msps ADC (Channels)

(Programmable/Dedicated)
Timers/Capture/Compare
Program Memory (KB)

Data Memory (KB)

DMA Channels

Comparators

Packages(4)
PMP/PSP
UART(2,3)
Ethernet
Device

Trace
SPI(3)

JTAG
I2C(3)
Pins

USB
PT,
PIC32MX664F064H 64 64 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX664F128H 64 128 + 12(1) 32 1 1 5/5/5 4/4 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX675F256H 64 256 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX675F512H 64 512 + 12(1) 64 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX695F512H 64 512 + 12(1) 128 1 1 5/5/5 8/4 6 3 4 16 2 Yes Yes No
MR
PT, PF,
PIC32MX664F064L 100 64 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes
BG
PT, PF,
PIC32MX664F128L 100 128 + 12(1) 32 1 1 5/5/5 4/4 6 4 5 16 2 Yes Yes Yes
BG
PT, PF,
PIC32MX675F256L 100 256 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes
BG
PT, PF,
PIC32MX675F512L 100 512 + 12(1) 64 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes
BG, TL
PT, PF,
PIC32MX695F512L 100 512 + 12(1) 128 1 1 5/5/5 8/4 6 4 5 16 2 Yes Yes Yes
BG, TL
Legend: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA(5)
Note 1: This device features 12 KB boot Flash memory.
2: CTS and RTS pins may not be available for all UART modules. Refer to the “Device Pin Tables” section for more
information.
3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Device Pin Tables” section for
more information.
4: Refer to 34.0 “Packaging Information” for more information.
5: 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local
Microchip Sales Office for details.

 2009-2019 Microchip Technology Inc. DS60001156K-page 3

PIC32MX5XX/6XX/7XX
TABLE 3: PIC32MX7XX USB, ETHERNET, AND CAN FEATURES
USB, Ethernet, and CAN

10-bit 1 Msps ADC (Channels)

(Programmable/Dedicated)
Timers/Capture/Compare
Program Memory (KB)

Data Memory (KB)

DMA Channels

Comparators

Packages(4)
PMP/PSP
UART(2,3)
Ethernet
Device

SPI(3)

Trace
JTAG
I2C(3)
CAN
Pins

USB

PT,
PIC32MX764F128H 64 128 + 12(1) 32 1 1 1 5/5/5 4/8 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX775F256H 64 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX775F512H 64 512 + 12(1) 64 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No
MR
PT,
PIC32MX795F512H 64 512 + 12(1) 128 1 1 2 5/5/5 8/8 6 3 4 16 2 Yes Yes No
MR
PT, PF,
PIC32MX764F128L 100 128 + 12(1) 32 1 1 1 5/5/5 4/6 6 4 5 16 2 Yes Yes Yes
BG
PT, PF,
PIC32MX775F256L 100 256 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes
BG
PT, PF,
PIC32MX775F512L 100 512 + 12(1) 64 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes
BG
PT, PF,
PIC32MX795F512L 100 512 + 12(1) 128 1 1 2 5/5/5 8/8 6 4 5 16 2 Yes Yes Yes
BG, TL
Legend: PF, PT = TQFP MR = QFN BG = TFBGA TL = VTLA(5)
Note 1: This device features 12 KB boot Flash memory.
2: CTS and RTS pins may not be available for all UART modules. Refer to the “Device Pin Tables” section for more
information.
3: Some pins between the UART, SPI and I2C modules may be shared. Refer to the “Device Pin Tables” section for
more information.
4: Refer to Section 34.0 “Packaging Information” for more information.
5: 100-pin devices other than those listed here are available in the VTLA package upon request. Please contact your local
Microchip Sales Office for details.

DS60001156K-page 4  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
Device Pin Tables
TABLE 4: PIN NAMES FOR 64-PIN USB AND CAN DEVICES

64-PIN QFN(2) AND TQFP (TOP VIEW)

PIC32MX534F064H
PIC32MX564F064H
PIC32MX564F128H
PIC32MX575F256H
64 1
PIC32MX575F512H
QFN(2) 64
1
TQFP
Pin # Full Pin Name Pin # Full Pin Name

1 PMD5/RE5 33 USBID/RF3
2 PMD6/RE6 34 VBUS
3 PMD7/RE7 35 VUSB3V3
4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 36 D-/RG3
5 SDA4/SDI2/U3RX/PMA4/CN9/RG7 37 D+/RG2
6 SCL4/SDO2/U3TX/PMA3/CN10/RG8 38 VDD
7 MCLR 39 OSC1/CLKI/RC12
8 SS2/U6RX/U3CTS/PMA2/CN11/RG9 40 OSC2/CLKO/RC15
9 VSS 41 Vss
10 VDD 42 RTCC/IC1/INT1/RD8
11 AN5/C1IN+/VBUSON/CN7/RB5 43 SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
12 AN4/C1IN-/CN6/RB4 44 SCL1/IC3/PMCS2/PMA15/INT3/RD10
13 AN3/C2IN+/CN5/RB3 45 IC4/PMCS1/PMA14/INT4/RD11
14 AN2/C2IN-/CN4/RB2 46 OC1/INT0/RD0
15 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 47 SOSCI/CN1/RC13
16 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 48 SOSCO/T1CK/CN0/RC14
17 PGEC2/AN6/OCFA/RB6 49 SCK3/U4TX/U1RTS/OC2/RD1
18 PGED2/AN7/RB7 50 SDA3/SDI3/U1RX/OC3/RD2
19 AVDD 51 SCL3/SDO3/U1TX/OC4/RD3
20 AVSS 52 OC5/IC5/PMWR/CN13/RD4
21 AN8/SS4/U5RX/U2CTS/C1OUT/RB8 53 PMRD/CN14/RD5
22 AN9/C2OUT/PMA7/RB9 54 CN15/RD6
23 TMS/AN10/CVREFOUT/PMA13/RB10 55 CN16/RD7
24 TDO/AN11/PMA12/RB11 56 VCAP
25 VSS 57 VDD
26 VDD 58 C1RX/RF0
27 TCK/AN12/PMA11/RB12 59 C1TX/RF1
28 TDI/AN13/PMA10/RB13 60 PMD0/RE0
29 AN14/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 61 PMD1/RE1
30 AN15/OCFB/PMALL/PMA0/CN12/RB15 62 PMD2/RE2
31 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 63 PMD3/RE3
32 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 64 PMD4/RE4
Note 1: Shaded pins are 5V tolerant.
2: The metal plane at the bottom of the device is not connected to any pins and is recommended to be connected to VSS externally.

 2009-2019 Microchip Technology Inc. DS60001156K-page 5

PIC32MX5XX/6XX/7XX
TABLE 5: PIN NAMES FOR 64-PIN USB AND ETHERNET DEVICES

64-PIN QFN(2) AND TQFP (TOP VIEW)

PIC32MX664F064H
PIC32MX664F128H
PIC32MX675F256H
PIC32MX675F512H
PIC32MX695F512H 64 1

QFN(2) 64
1
TQFP
Pin # Full Pin Name Pin # Full Pin Name

1 ETXEN/PMD5/RE5 33 USBID/RF3
2 ETXD0/PMD6/RE6 34 VBUS
3 ETXD1/PMD7/RE7 35 VUSB3V3
4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 36 D-/RG3
5 SDA4/SDI2/U3RX/PMA4/CN9/RG7 37 D+/RG2
6 SCL4/SDO2/U3TX/PMA3/CN10/RG8 38 VDD
7 MCLR 39 OSC1/CLKI/RC12
8 SS2/U6RX/U3CTS/PMA2/CN11/RG9 40 OSC2/CLKO/RC15
9 VSS 41 Vss
10 VDD 42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8
11 AN5/C1IN+/VBUSON/CN7/RB5 43 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
12 AN4/C1IN-/CN6/RB4 44 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
13 AN3/C2IN+/CN5/RB3 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
14 AN2/C2IN-/CN4/RB2 46 OC1/INT0/RD0
15 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 47 SOSCI/CN1/RC13
16 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 48 SOSCO/T1CK/CN0/RC14
17 PGEC2/AN6/OCFA/RB6 49 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
18 PGED2/AN7/RB7 50 SDA3/SDI3/U1RX/OC3/RD2
19 AVDD 51 SCL3/SDO3/U1TX/OC4/RD3
20 AVSS 52 OC5/IC5/PMWR/CN13/RD4
21 AN8/SS4/U5RX/U2CTS/C1OUT/RB8 53 PMRD/CN14/RD5
22 AN9/C2OUT/PMA7/RB9 54 AETXEN/ETXERR/CN15/RD6
23 TMS/AN10/CVREFOUT/PMA13/RB10 55 ETXCLK/AERXERR/CN16/RD7
24 TDO/AN11/PMA12/RB11 56 VCAP
25 VSS 57 VDD
26 VDD 58 AETXD1/ERXD3/RF0
27 TCK/AN12/PMA11/RB12 59 AETXD0/ERXD2/RF1
28 TDI/AN13/PMA10/RB13 60 ERXD1/PMD0/RE0
29 AN14/SCK4/U5TX/U2RTSU2RTS/PMALH/PMA1/RB14 61 ERXD0/PMD1/RE1
30 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 62 ERXDV/ECRSDV/PMD2/RE2
31 SDA5/SDI4/U2RX/PMA9/CN17/RF4 63 ERXCLK/EREFCLK/PMD3/RE3
32 SCL5/SDO4/U2TX/PMA8/CN18/RF5 64 ERXERR/PMD4/RE4
Note 1: Shaded pins are 5V tolerant.
2: The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS externally.

DS60001156K-page 6  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 6: PIN NAMES FOR 64-PIN USB, ETHERNET, AND CAN DEVICES

64-PIN QFN(3) AND TQFP (TOP VIEW)

PIC32MX764F128H
PIC32MX775F256H
PIC32MX775F512H
PIC32MX795F512H
64 1

QFN(3) 64
1
TQFP

Pin # Full Pin Name Pin # Full Pin Name

1 ETXEN/PMD5/RE5 33 USBID/RF3
2 ETXD0/PMD6/RE6 34 VBUS
3 ETXD1/PMD7/RE7 35 VUSB3V3
4 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 36 D-/RG3
5 SDA4/SDI2/U3RX/PMA4/CN9/RG7 37 D+/RG2
6 SCL4/SDO2/U3TX/PMA3/CN10/RG8 38 VDD
7 MCLR 39 OSC1/CLKI/RC12
8 SS2/U6RX/U3CTS/PMA2/CN11/RG9 40 OSC2/CLKO/RC15
9 VSS 41 Vss
10 VDD 42 RTCC/AERXD1/ETXD3/IC1/INT1/RD8
11 AN5/C1IN+/VBUSON/CN7/RB5 43 AERXD0/ETXD2/SS3/U4RX/U1CTS/SDA1/IC2/INT2/RD9
12 AN4/C1IN-/CN6/RB4 44 ECOL/AECRSDV/SCL1/IC3/PMCS2/PMA15/INT3/RD10
13 AN3/C2IN+/CN5/RB3 45 ECRS/AEREFCLK/IC4/PMCS1/PMA14/INT4/RD11
14 AN2/C2IN-/CN4/RB2 46 OC1/INT0/RD0
15 PGEC1/AN1/VREF-/CVREF-/CN3/RB1 47 SOSCI/CN1/RC13
16 PGED1/AN0/VREF+/CVREF+/PMA6/CN2/RB0 48 SOSCO/T1CK/CN0/RC14
17 PGEC2/AN6/OCFA/RB6 49 EMDIO/AEMDIO/SCK3/U4TX/U1RTS/OC2/RD1
18 PGED2/AN7/RB7 50 SDA3/SDI3/U1RX/OC3/RD2
19 AVDD 51 SCL3/SDO3/U1TX/OC4/RD3
20 AVSS 52 OC5/IC5/PMWR/CN13/RD4
21 AN8/C2TX(2)/SS4/U5RX/U2CTS/C1OUT/RB8 53 PMRD/CN14/RD5
22 AN9/C2OUT/PMA7/RB9 54 AETXEN/ETXERR/CN15/RD6
23 TMS/AN10/CVREFOUT/PMA13/RB10 55 ETXCLK/AERXERR/CN16/RD7
24 TDO/AN11/PMA12/RB11 56 VCAP
25 VSS 57 VDD
26 VDD 58 C1RX/AETXD1/ERXD3/RF0
27 TCK/AN12/PMA11/RB12 59 C1TX/AETXD0/ERXD2/RF1
28 TDI/AN13/PMA10/RB13 60 ERXD1/PMD0/RE0
29 AN14/C2RX(2)/SCK4/U5TX/U2RTS/PMALH/PMA1/RB14 61 ERXD0/PMD1/RE1
30 AN15/EMDC/AEMDC/OCFB/PMALL/PMA0/CN12/RB15 62 ERXDV/ECRSDV/PMD2/RE2
31 AC1TX/SDA5/SDI4/U2RX/PMA9/CN17/RF4 63 ERXCLK/EREFCLKPMD3/RE3
32 AC1RX/SCL5/SDO4/U2TX/PMA8/CN18/RF5 64 ERXERR/PMD4/RE4
Note 1: Shaded pins are 5V tolerant.
2: This pin is not available on PIC32MX765F128H devices.
3: The metal plane at the bottom of the QFN device is not connected to any pins and is recommended to be connected to VSS externally.

 2009-2019 Microchip Technology Inc. DS60001156K-page 7

PIC32MX5XX/6XX/7XX
TABLE 7: PIN NAMES FOR 100-PIN USB AND CAN DEVICES

100-PIN TQFP (TOP VIEW)

PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX575F512L
PIC32MX575F256L
100
1

Pin # Full Pin Name Pin # Full Pin Name

1 RG15 36 VSS
2 VDD 37 VDD
3 PMD5/RE5 38 TCK/RA1
4 PMD6/RE6 39 AC1TX/SCK4/U5TX/U2RTS/RF13
5 PMD7/RE7 40 AC1RX/SS4/U5RX/U2CTS/RF12
6 T2CK/RC1 41 AN12/PMA11/RB12
7 T3CK/RC2 42 AN13/PMA10/RB13
8 T4CK/RC3 43 AN14/PMALH/PMA1/RB14
9 T5CK/SDI1/RC4 44 AN15/OCFB/PMALL/PMA0/CN12/RB15
10 SCK2/U6TX/U3RTS/PMA5/CN8/RG6 45 VSS
11 SDA4/SDI2/U3RX/PMA4/CN9/RG7 46 VDD
12 SCL4/SDO2/U3TX/PMA3/CN10/RG8 47 SS3/U4RX/U1CTS/CN20/RD14
13 MCLR 48 SCK3/U4TX/U1RTS/CN21/RD15
14 SS2/U6RX/U3CTS/PMA2/CN11/RG9 49 SDA5/SDI4/U2RX/PMA9/CN17/RF4
15 VSS 50 SCL5/SDO4/U2TX/PMA8/CN18/RF5
16 VDD 51 USBID/RF3
17 TMS/RA0 52 SDA3/SDI3/U1RX/RF2
18 INT1/RE8 53 SCL3/SDO3/U1TX/RF8
19 INT2/RE9 54 VBUS
20 AN5/C1IN+/VBUSON/CN7/RB5 55 VUSB3V3
21 AN4/C1IN-/CN6/RB4 56 D-/RG3
22 AN3/C2IN+/CN5/RB3 57 D+/RG2
23 AN2/C2IN-/CN4/RB2 58 SCL2/RA2
24 PGEC1/AN1/CN3/RB1 59 SDA2/RA3
25 PGED1/AN0/CN2/RB0 60 TDI/RA4
26 PGEC2/AN6/OCFA/RB6 61 TDO/RA5
27 PGED2/AN7/RB7 62 VDD
28 VREF-/CVREF-/PMA7/RA9 63 OSC1/CLKI/RC12
29 VREF+/CVREF+/PMA6/RA10 64 OSC2/CLKO/RC15
30 AVDD 65 VSS
31 AVSS 66 SCL1/INT3/RA14
32 AN8/C1OUT/RB8 67 SDA1/INT4/RA15
33 AN9/C2OUT/RB9 68 RTCC/IC1/RD8
34 AN10/CVREFOUT/PMA13/RB10 69 SS1/IC2/RD9
35 AN11/PMA12/RB11 70 SCK1/IC3/PMCS2/PMA15/RD10
Note 1: Shaded pins are 5V tolerant.

DS60001156K-page 8  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 7: PIN NAMES FOR 100-PIN USB AND CAN DEVICES (CONTINUED)

100-PIN TQFP (TOP VIEW)

PIC32MX534F064L
PIC32MX564F064L
PIC32MX564F128L
PIC32MX575F512L
PIC32MX575F256L
100
1

Pin # Full Pin Name Pin # Full Pin Name

71 IC4/PMCS1/PMA14/RD11 86 VDD
72 SDO1/OC1/INT0/RD0 87 C1RX/PMD11/RF0
73 SOSCI/CN1/RC13 88 C1TX/PMD10/RF1
74 SOSCO/T1CK/CN0/RC14 89 PMD9/RG1
75 VSS 90 PMD8/RG0
76 OC2/RD1 91 TRCLK/RA6
77 OC3/RD2 92 TRD3/RA7
78 OC4/RD3 93 PMD0/RE0
79 IC5/PMD12/RD12 94 PMD1/RE1
80 PMD13/CN19/RD13 95 TRD2/RG14
81 OC5/PMWR/CN13/RD4 96 TRD1/RG12
82 PMRD/CN14/RD5 97 TRD0/RG13
83 PMD14/CN15/RD6 98 PMD2/RE2
84 PMD15/CN16/RD7 99 PMD3/RE3
85 VCAP 100 PMD4/RE4
Note 1: Shaded pins are 5V tolerant.

 2009-2019 Microchip Technology Inc. DS60001156K-page 9

PIC32MX5XX/6XX/7XX
TABLE 8: PIN NAMES FOR 100-PIN USB AND ETHERNET DEVICES

100-PIN TQFP (TOP VIEW)

PIC32MX664F064L
PIC32MX664F128L
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L

100
1

Pin # Full Pin Name Pin # Full Pin Name

1 AERXERR/RG15 36 VSS
2 VDD 37 VDD
3 PMD5/RE5 38 TCK/RA1
4 PMD6/RE6 39 SCK4/U5TX/U2RTS/RF13
5 PMD7/RE7 40 SS4/U5RX/U2CTS/RF12
6 T2CK/RC1 41 AN12/ERXD0/AECRS/PMA11/RB12
7 T3CK/RC2 42 AN13/ERXD1/AECOL/PMA10/RB13
8 T4CK/RC3 43 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
9 T5CK/SDI1/RC4 44 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
10 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 45 VSS
11 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 46 VDD
12 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 47 AETXD0/SS3/U4RX/U1CTS/CN20/RD14
13 MCLR 48 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
14 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 49 SDA5/SDI4/U2RX/PMA9/CN17/RF4
15 VSS 50 SCL5/SDO4/U2TX/PMA8/CN18/RF5
16 VDD 51 USBID/RF3
17 TMS/RA0 52 SDA3/SDI3/U1RX/RF2
18 AERXD0/INT1/RE8 53 SCL3/SDO3/U1TX/RF8
19 AERXD1/INT2/RE9 54 VBUS
20 AN5/C1IN+/VBUSON/CN7/RB5 55 VUSB3V3
21 AN4/C1IN-/CN6/RB4 56 D-/RG3
22 AN3/C2IN+/CN5/RB3 57 D+/RG2
23 AN2/C2IN-/CN4/RB2 58 SCL2/RA2
24 PGEC1/AN1/CN3/RB1 59 SDA2/RA3
25 PGED1/AN0/CN2/RB0 60 TDI/RA4
26 PGEC2/AN6/OCFA/RB6 61 TDO/RA5
27 PGED2/AN7/RB7 62 VDD
28 VREF-/CVREF-/AERXD2/PMA7/RA9 63 OSC1/CLKI/RC12
29 VREF+/CVREF+/AERXD3/PMA6/RA10 64 OSC2/CLKO/RC15
30 AVDD 65 VSS
31 AVSS 66 AETXCLK/SCL1/INT3/RA14
32 AN8/C1OUT/RB8 67 AETXEN/SDA1/INT4/RA15
33 AN9/C2OUT/RB9 68 RTCC/EMDIO/AEMDIO/IC1/RD8
34 AN10/CVREFOUT/PMA13/RB10 69 SS1/IC2/RD9
35 AN11/ERXERR/AETXERR/PMA12/RB11 70 SCK1/IC3/PMCS2/PMA15/RD10
Note 1: Shaded pins are 5V tolerant.

DS60001156K-page 10  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 8: PIN NAMES FOR 100-PIN USB AND ETHERNET DEVICES (CONTINUED)

100-PIN TQFP (TOP VIEW)

PIC32MX664F064L
PIC32MX664F128L
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L

100
1

Pin # Full Pin Name Pin # Full Pin Name

71 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 86 VDD
72 SDO1/OC1/INT0/RD0 87 ETXD1/PMD11/RF0
73 SOSCI/CN1/RC13 88 ETXD0/PMD10/RF1
74 SOSCO/T1CK/CN0/RC14 89 ETXERR/PMD9/RG1
75 VSS 90 PMD8/RG0
76 OC2/RD1 91 TRCLK/RA6
77 OC3/RD2 92 TRD3/RA7
78 OC4/RD3 93 PMD0/RE0
79 ETXD2/IC5/PMD12/RD12 94 PMD1/RE1
80 ETXD3/PMD13/CN19/RD13 95 TRD2/RG14
81 OC5/PMWR/CN13/RD4 96 TRD1/RG12
82 PMRD/CN14/RD5 97 TRD0/RG13
83 ETXEN/PMD14/CN15/RD6 98 PMD2/RE2
84 ETXCLK/PMD15/CN16/RD7 99 PMD3/RE3
85 VCAP/VDDCORE 100 PMD4/RE4
Note 1: Shaded pins are 5V tolerant.

 2009-2019 Microchip Technology Inc. DS60001156K-page 11

PIC32MX5XX/6XX/7XX
TABLE 9: PIN NAMES FOR 100-PIN USB, ETHERNET, AND CAN DEVICES

100-PIN TQFP (TOP VIEW)

PIC32MX764F128L
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L

100
1

Pin # Full Pin Name Pin # Full Pin Name

1 AERXERR/RG15 36 VSS
2 VDD 37 VDD
3 PMD5/RE5 38 TCK/RA1
4 PMD6/RE6 39 AC1TX/SCK4/U5TX/U2RTS/RF13
5 PMD7/RE7 40 AC1RX/SS4/U5RX/U2CTS/RF12
6 T2CK/RC1 41 AN12/ERXD0/AECRS/PMA11/RB12
7 T3CK/AC2TX(1)/RC2 42 AN13/ERXD1/AECOL/PMA10/RB13
8 T4CK/AC2RX(1)/RC3 43 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
9 T5CK/SDI1/RC4 44 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
10 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 45 VSS
11 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7 46 VDD
12 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 47 AETXD0/SS3/U4RX/U1CTS/CN20/RD14
13 MCLR 48 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
14 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 49 SDA5/SDI4/U2RX/PMA9/CN17/RF4
15 VSS 50 SCL5/SDO4/U2TX/PMA8/CN18/RF5
16 VDD 51 USBID/RF3
17 TMS/RA0 52 SDA3/SDI3/U1RX/RF2
18 AERXD0/INT1/RE8 53 SCL3/SDO3/U1TX/RF8
19 AERXD1/INT2/RE9 54 VBUS
20 AN5/C1IN+/VBUSON/CN7/RB5 55 VUSB3V3
21 AN4/C1IN-/CN6/RB4 56 D-/RG3
22 AN3/C2IN+/CN5/RB3 57 D+/RG2
23 AN2/C2IN-/CN4/RB2 58 SCL2/RA2
24 PGEC1/AN1/CN3/RB1 59 SDA2/RA3
25 PGED1/AN0/CN2/RB0 60 TDI/RA4
26 PGEC2/AN6/OCFA/RB6 61 TDO/RA5
27 PGED2/AN7/RB7 62 VDD
28 VREF-/CVREF-/AERXD2/PMA7/RA9 63 OSC1/CLKI/RC12
29 VREF+/CVREF+/AERXD3/PMA6/RA10 64 OSC2/CLKO/RC15
30 AVDD 65 VSS
31 AVSS 66 AETXCLK/SCL1/INT3/RA14
32 AN8/C1OUT/RB8 67 AETXEN/SDA1/INT4/RA15
33 AN9/C2OUT/RB9 68 RTCC/EMDIO/AEMDIO/IC1/RD8
34 AN10/CVREFOUT/PMA13/RB10 69 SS1/IC2/RD9
35 AN11/ERXERR/AETXERR/PMA12/RB11 70 SCK1/IC3/PMCS2/PMA15/RD10
Note 1: This pin is not available on PIC32MX764F128L devices.
2: Shaded pins are 5V tolerant.

DS60001156K-page 12  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 9: PIN NAMES FOR 100-PIN USB, ETHERNET, AND CAN DEVICES (CONTINUED)

100-PIN TQFP (TOP VIEW)

PIC32MX764F128L
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L

100
1

Pin # Full Pin Name Pin # Full Pin Name

71 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 86 VDD
72 SDO1/OC1/INT0/RD0 87 C1RX/ETXD1/PMD11/RF0
73 SOSCI/CN1/RC13 88 C1TX/ETXD0/PMD10/RF1
74 SOSCO/T1CK/CN0/RC14 89 C2TX(1)/ETXERR/PMD9/RG1
75 VSS 90 C2RX(1)/PMD8/RG0
76 OC2/RD1 91 TRCLK/RA6
77 OC3/RD2 92 TRD3/RA7
78 OC4/RD3 93 PMD0/RE0
79 ETXD2/IC5/PMD12/RD12 94 PMD1/RE1
80 ETXD3/PMD13/CN19/RD13 95 TRD2/RG14
81 OC5/PMWR/CN13/RD4 96 TRD1/RG12
82 PMRD/CN14/RD5 97 TRD0/RG13
83 ETXEN/PMD14/CN15/RD6 98 PMD2/RE2
84 ETXCLK/PMD15/CN16/RD7 99 PMD3/RE3
85 VCAP/VDDCORE 100 PMD4/RE4
Note 1: This pin is not available on PIC32MX764F128L devices.
2: Shaded pins are 5V tolerant.

 2009-2019 Microchip Technology Inc. DS60001156K-page 13

PIC32MX5XX/6XX/7XX
TABLE 10: PIN NAMES FOR USB AND CAN DEVICES
121-PIN TFBGA (BOTTOM VIEW) L11

PIC32MX534F064L L1
PIC32MX564F064L A11
PIC32MX564F128L
PIC32MX575F256L
PIC32MX575F512L

Note: The TFBGA package skips from row “H” to row “J” and has no “I” row. A1

Pin # Full Pin Name Pin # Full Pin Name

A1 PMD4/RE4 E2 T4CK/RC3
A2 PMD3/RE3 E3 SCK2/U6TXU6TX/U3RTS/PMA5/CN8/RG6
A3 TRD0/RG13 E4 T3CK/RC2
A4 PMD0/RE0 E5 VDD
A5 PMD8/RG0 E6 PMD9/RG1
A6 C1TX/PMD10/RF1 E7 VSS
A7 VDD E8 SDA1/INT4/RA15
A8 VSS E9 RTCC/IC1/RD8
A9 IC5/PMD12/RD12 E10 SS1/IC2/RD9
A10 OC3/RD2 E11 SCL1/INT3/RA14
A11 OC2/RD1 F1 MCLR
B1 No Connect (NC) F2 SCL4/SDO2/U3TX/PMA3/CN10/RG8
B2 RG15 F3 SS2/U6RX/U3CTS/PMA2/CN11/RG9
B3 PMD2/RE2 F4 SDA4/SDI2/U3RX/PMA4/CN9/RG7
B4 PMD1/RE1 F5 VSS
B5 TRD3/RA7 F6 No Connect (NC)
B6 C1RX/PMD11/RF0 F7 No Connect (NC)
B7 VCAP F8 VDD
B8 PMRD/CN14/RD5 F9 OSC1/CLKI/RC12
B9 OC4/RD3 F10 VSS
B10 VSS F11 OSC2/CLKO/RC15
B11 SOSCO/T1CK/CN0/RC14 G1 INT1/RE8
C1 PMD6/RE6 G2 INT2/RE9
C2 VDD G3 TMS/RA0
C3 TRD1/RG12 G4 No Connect (NC)
C4 TRD2/RG14 G5 VDD
C5 TRCLK/RA6 G6 VSS
C6 No Connect (NC) G7 VSS
C7 PMD15/CN16/RD7 G8 No Connect (NC)
C8 OC5/PMWR/CN13/RD4 G9 TDO/RA5
C9 VDD G10 SDA2/RA3
C10 SOSCI/CN1/RC13 G11 TDI/RA4
C11 IC4/PMCS1/PMA14/RD11 H1 AN5/C1IN+/VBUSON/CN7/RB5
D1 T2CK/RC1 H2 AN4/C1IN-/CN6/RB4
D2 PMD7/RE7 H3 VSS
D3 PMD5/RE5 H4 VDD
D4 VSS H5 No Connect (NC)
D5 VSS H6 VDD
D6 No Connect (NC) H7 No Connect (NC)
D7 PMD14/CN15/RD6 H8 VBUS
D8 PMD13/CN19/RD13 H9 VUSB3V3
D9 SDO1/OC1/INT0/RD0 H10 D+/RG2
D10 No Connect (NC) H11 SCL2/RA2
D11 SCK1/IC3/PMCS2/PMA15/RD10 J1 AN3/C2IN+/CN5/RB3
E1 T5CK/SDI1/RC4 J2 AN2/C2IN-/CN4/RB2
Note 1: Shaded pins are 5V tolerant.

DS60001156K-page 14  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 10: PIN NAMES (CONTINUED)FOR USB AND CAN DEVICES
121-PIN TFBGA (BOTTOM VIEW) L11

PIC32MX534F064L L1
PIC32MX564F064L A11
PIC32MX564F128L
PIC32MX575F256L
PIC32MX575F512L

Note: The TFBGA package skips from row “H” to row “J” and has no “I” row. A1

Pin # Full Pin Name Pin # Full Pin Name

J3 PGED2/AN7/RB7 K8 VDD
J4 AVDD K9 SCK3/U4TX/U1RTS/CN21/RD15
J5 AN11/PMA12/RB11 K10 USBID/RF3
J6 TCK/RA1 K11 SDA3/SDI3/U1RX/RF2
J7 AN12/PMA11/RB12 L1 PGEC2/AN6/OCFA/RB6
J8 No Connect (NC) L2 VREF-/CVREF-/PMA7/RA9
J9 No Connect (NC) L3 AVSS
J10 SCL3/SDO3/U1TX/RF8 L4 AN9/C2OUT/RB9
J11 D-/RG3 L5 AN10/CVREFOUT/PMA13/RB10
K1 PGEC1/AN1/CN3/RB1 L6 AC1TX/SCK4/U5TX/U2RTS/RF13
K2 PGED1/AN0/CN2/RB0 L7 AN13/PMA10/RB13
K3 VREF+/CVREF+/PMA6/RA10 L8 AN15/OCFB/PMALL/PMA0/CN12/RB15
K4 AN8/C1OUT/RB8 L9 SS3/U4RX/U1CTS/CN20/RD14
K5 No Connect (NC) L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4
K6 AC1RX/SS4/U5RX/U2CTS/RF12 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5
K7 AN14/PMALH/PMA1/RB14
Note 1: Shaded pins are 5V tolerant.

 2009-2019 Microchip Technology Inc. DS60001156K-page 15

PIC32MX5XX/6XX/7XX
TABLE 11: PIN NAMES FOR USB AND ETHERNET DEVICES
121-PIN TFBGA (BOTTOM VIEW) L11

PIC32MX664F064L L1
PIC32MX664F128L A11
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
A1
Note: The TFBGA package skips from row “H” to row “J” and has no “I” row.

Pin # Full Pin Name Pin # Full Pin Name

A1 PMD4/RE4 E2 T4CK/RC3
A2 PMD3/RE3 E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
A3 TRD0/RG13 E4 T3CK/RC2
A4 PMD0/RE0 E5 VDD
A5 PMD8/RG0 E6 ETXERR/PMD9/RG1
A6 ETXD0/PMD10/RF1 E7 VSS
A7 VDD E8 AETXEN/SDA1/INT4/RA15
A8 VSS E9 RTCC/EMDIO/AEMDIO/IC1/RD8
A9 ETXD2/IC5/PMD12/RD12 E10 SS1/IC2/RD9
A10 OC3/RD2 E11 AETXCLK/SCL1/INT3/RA14
A11 OC2/RD1 F1 MCLR
B1 No Connect (NC) F2 ERXDV/AERXDV/ECRSDV/AECRSDV//SCL4/SDO2/U3TX/PMA3/CN10/RG8
B2 AERXERR/RG15 F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
B3 PMD2/RE2 F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
B4 PMD1/RE1 F5 VSS
B5 TRD3/RA7 F6 No Connect (NC)
B6 ETXD1/PMD11/RF0 F7 No Connect (NC)
B7 VCAP F8 VDD
B8 PMRD/CN14/RD5 F9 OSC1/CLKI/RC12
B9 OC4/RD3 F10 VSS
B10 VSS F11 OSC2/CLKO/RC15
B11 SOSCO/T1CK/CN0/RC14 G1 AERXD0/INT1/RE8
C1 PMD6/RE6 G2 AERXD1/INT2/RE9
C2 VDD G3 TMS/RA0
C3 TRD1/RG12 G4 No Connect (NC)
C4 TRD2/RG14 G5 VDD
C5 TRCLK/RA6 G6 VSS
C6 No Connect (NC) G7 VSS
C7 ETXCLK/PMD15/CN16/RD7 G8 No Connect (NC)
C8 OC5/PMWR/CN13/RD4 G9 TDO/RA5
C9 VDD G10 SDA2/RA3
C10 SOSCI/CN1/RC13 G11 TDI/RA4
C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H1 AN5/C1IN+/VBUSON/CN7/RB5
D1 T2CK/RC1 H2 AN4/C1IN-/CN6/RB4
D2 PMD7/RE7 H3 VSS
D3 PMD5/RE5 H4 VDD
D4 VSS H5 No Connect (NC)
D5 VSS H6 VDD
D6 No Connect (NC) H7 No Connect (NC)
D7 ETXEN/PMD14/CN15/RD6 H8 VBUS
D8 ETXD3/PMD13/CN19/RD13 H9 VUSB3V3
D9 SDO1/OC1/INT0/RD0 H10 D+/RG2
D10 No Connect (NC) H11 SCL2/RA2
D11 SCK1/IC3/PMCS2/PMA15/RD10 J1 AN3/C2IN+/CN5/RB3
E1 T5CK/SDI1/RC4 J2 AN2/C2IN-/CN4/RB2
Note 1: Shaded pins are 5V tolerant.

DS60001156K-page 16  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 11: PIN NAMES FOR USB AND ETHERNET DEVICES (CONTINUED)
121-PIN TFBGA (BOTTOM VIEW) L11

PIC32MX664F064L L1
PIC32MX664F128L A11
PIC32MX675F256L
PIC32MX675F512L
PIC32MX695F512L
A1
Note: The TFBGA package skips from row “H” to row “J” and has no “I” row.

Pin # Full Pin Name Pin # Full Pin Name

J3 PGED2/AN7/RB7 K8 VDD
J4 AVDD K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
J5 AN11/ERXERR/AETXERR/PMA12/RB11 K10 USBID/RF3
J6 TCK/RA1 K11 SDA3/SDI3/U1RX/RF2
J7 AN12/ERXD0/AECRS/PMA11/RB12 L1 PGEC2/AN6/OCFA/RB6
J8 No Connect (NC) L2 VREF-/CVREF-/AERXD2/PMA7/RA9
J9 No Connect (NC) L3 AVSS
J10 SCL3/SDO3/U1TX/RF8 L4 AN9/C2OUT/RB9
J11 D-/RG3 L5 AN10/CVREFOUT/PMA13/RB10
K1 PGEC1/AN1/CN3/RB1 L6 SCK4/U5TX/U2RTS/RF13
K2 PGED1/AN0/CN2/RB0 L7 AN13/ERXD1/AECOL/PMA10/RB13
K3 VREF+/CVREF+/AERXD3/PMA6/RA10 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K4 AN8/C1OUT/RB8 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14
K5 No Connect (NC) L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4
K6 SS4/U5RX/U2CTS/RF12 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5
K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
Note 1: Shaded pins are 5V tolerant.

 2009-2019 Microchip Technology Inc. DS60001156K-page 17

PIC32MX5XX/6XX/7XX
TABLE 12: PIN NAMES FOR USB, ETHERNET, AND CAN DEVICES

121-PIN TFBGA (BOTTOM VIEW) L11

L1
PIC32MX764F128L A11
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
Note: The TFBGA package skips from row “H” to row “J” and has no “I” row. A1

Pin # Full Pin Name Pin # Full Pin Name

(1)
A1 PMD4/RE4 E2 T4CK/AC2RX /RC3
A2 PMD3/RE3 E3 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6
A3 TRD0/RG13 E4 T3CK/AC2TX(1)/RC2
A4 PMD0/RE0 E5 VDD
A5 C2RX(1)/PMD8/RG0 E6 C2TX(1)/ETXERR/PMD9/RG1
A6 C1TX/ETXD0/PMD10/RF1 E7 VSS
A7 VDD E8 AETXEN/SDA1/INT4/RA15
A8 VSS E9 RTCC/EMDIO/AEMDIO/IC1/RD8
A9 ETXD2/IC5/PMD12/RD12 E10 SS1/IC2/RD9
A10 OC3/RD2 E11 AETXCLK/SCL1/INT3/RA14
A11 OC2/RD1 F1 MCLR
B1 No Connect (NC) F2 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8
B2 AERXERR/RG15 F3 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9
B3 PMD2/RE2 F4 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
B4 PMD1/RE1 F5 VSS
B5 TRD3/RA7 F6 No Connect (NC)
B6 C1RX/ETXD1/PMD11/RF0 F7 No Connect (NC)
B7 VCAP F8 VDD
B8 PMRD/CN14/RD5 F9 OSC1/CLKI/RC12
B9 OC4/RD3 F10 VSS
B10 VSS F11 OSC2/CLKO/RC15
B11 SOSCO/T1CK/CN0/RC14 G1 AERXD0/INT1/RE8
C1 PMD6/RE6 G2 AERXD1/INT2/RE9
C2 VDD G3 TMS/RA0
C3 TRD1/RG12 G4 No Connect (NC)
C4 TRD2/RG14 G5 VDD
C5 TRCLK/RA6 G6 VSS
C6 No Connect (NC) G7 VSS
C7 ETXCLK/PMD15/CN16/RD7 G8 No Connect (NC)
C8 OC5/PMWR/CN13/RD4 G9 TDO/RA5
C9 VDD G10 SDA2/RA3
C10 SOSCI/CN1/RC13 G11 TDI/RA4
C11 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11 H1 AN5/C1IN+/VBUSON/CN7/RB5
D1 T2CK/RC1 H2 AN4/C1IN-/CN6/RB4
D2 PMD7/RE7 H3 VSS
D3 PMD5/RE5 H4 VDD
D4 VSS H5 No Connect (NC)
D5 VSS H6 VDD
D6 No Connect (NC) H7 No Connect (NC)
D7 ETXEN/PMD14/CN15/RD6 H8 VBUS
D8 ETXD3/PMD13/CN19/RD13 H9 VUSB3V3
D9 SDO1/OC1/INT0/RD0 H10 D+/RG2
D10 No Connect (NC) H11 SCL2/RA2
D11 SCK1/IC3/PMCS2/PMA15/RD10 J1 AN3/C2IN+/CN5/RB3
E1 T5CK/SDI1/RC4 J2 AN2/C2IN-/CN4/RB2
Note 1: This pin is not available on PIC32MX764F128L devices.
2: Shaded pins are 5V tolerant.

DS60001156K-page 18  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 12: PIN NAMES FOR USB, ETHERNET, AND CAN DEVICES (CONTINUED)

121-PIN TFBGA (BOTTOM VIEW) L11

L1
PIC32MX764F128L A11
PIC32MX775F256L
PIC32MX775F512L
PIC32MX795F512L
Note: The TFBGA package skips from row “H” to row “J” and has no “I” row. A1

Pin # Full Pin Name Pin # Full Pin Name

J3 PGED2/AN7/RB7 K8 VDD
J4 AVDD K9 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15
J5 AN11/ERXERR/AETXERR/PMA12/RB11 K10 USBID/RF3
J6 TCK/RA1 K11 SDA3/SDI3/U1RX/RF2
J7 AN12/ERXD0/AECRS/PMA11/RB12 L1 PGEC2/AN6/OCFA/RB6
J8 No Connect (NC) L2 VREF-/CVREF-/AERXD2/PMA7/RA9
J9 No Connect (NC) L3 AVSS
J10 SCL3/SDO3/U1TX/RF8 L4 AN9/C2OUT/RB9
J11 D-/RG3 L5 AN10/CVREFOUT/PMA13/RB10
K1 PGEC1/AN1/CN3/RB1 L6 AC1TX/SCK4/U5TX/U2RTS/RF13
K2 PGED1/AN0/CN2/RB0 L7 AN13/ERXD1/AECOL/PMA10/RB13
K3 VREF+/CVREF+/AERXD3/PMA6/RA10 L8 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15
K4 AN8/C1OUT/RB8 L9 AETXD0/SS3/U4RX/U1CTS/CN20/RD14
K5 No Connect (NC) L10 SDA5/SDI4/U2RX/PMA9/CN17/RF4
K6 AC1RX/SS4/U5RX/U2CTS/RF12 L11 SCL5/SDO4/U2TX/PMA8/CN18/RF5
K7 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14
Note 1: This pin is not available on PIC32MX764F128L devices.
2: Shaded pins are 5V tolerant.

 2009-2019 Microchip Technology Inc. DS60001156K-page 19

PIC32MX5XX/6XX/7XX
TABLE 13: PIN NAMES FOR 124-PIN USB, ETHERNET, AND CAN DEVICES

124-PIN VTLA (BOTTOM VIEW)(2,3) A34

A17
B13 B29
Conductive
Thermal Pad

PIC32MX675F512L B41
B1
PIC32MX695F512L B56
PIC32MX795F512L A51

A1
A68
Polarity Indicator
Package Package
Full Pin Name Full Pin Name
Bump # Bump #
A1 No Connect (NC) A38 D-/RG3
A2 AERXERR/RG15 A39 SCL2/RA2
A3 VSS A40 TDI/RA4
A4 PMD6/RE6 A41 VDD
A5 T2CK/RC1 A42 OSC2/CLKO/RC15
A6 T4CK/AC2RX(1)/RC3 A43 VSS
A7 ECOL/SCK2/U6TX/U3RTS/PMA5/CN8/RG6 A44 AETXEN/SDA1/INT4/RA15
A8 ERXDV/AERXDV/ECRSDV/AECRSDV/SCL4/SDO2/U3TX/PMA3/CN10/RG8 A45 SS1/IC2/RD9
A9 ERXCLK/AERXCLK/EREFCLK/AEREFCLK/SS2/U6RX/U3CTS/PMA2/CN11/RG9 A46 EMDC/AEMDC/IC4/PMCS1/PMA14/RD11
A10 VDD A47 SOSCI/CN1/RC13
A11 AERXD0/INT1/RE8 A48 VDD
A12 AN5/C1IN+/VBUSON/CN7/RB5 A49 No Connect (NC)
A13 AN3/C2IN+/CN5/RB3 A50 No Connect (NC)
A14 VDD A51 No Connect (NC)
A15 PGEC1/AN1/CN3/RB1 A52 OC2/RD1
A16 No Connect (NC) A53 OC4/RD3
A17 No Connect (NC) A54 ETXD3/PMD13/CN19/RD13
A18 No Connect (NC) A55 PMRD/CN14/RD5
A19 No Connect (NC) A56 ETXCLK/PMD15/CN16/RD7
A20 PGEC2/AN6/OCFA/RB6 A57 No Connect (NC)
A21 VREF-/CVREF-/AERXD2/PMA7/RA9 A58 No Connect (NC)
A22 AVDD A59 VDD
A23 AN8/C1OUT/RB8 A60 C1TX/ETXD0/PMD10/RF1
A24 AN10/CVREFOUT/PMA13/RB10 A61 C2RX(1)/PMD8/RG0
A25 VSS A62 TRD3/RA7
A26 TCK/RA1 A63 VSS
A27 AC1RX(1)/SS4/U5RX/U2CTS/RF12 A64 PMD1/RE1
A28 AN13/ERXD1/AECOL/PMA10/RB13 A65 TRD1/RG12
A29 AN15/ERXD3/AETXD2/OCFB/PMALL/PMA0/CN12/RB15 A66 PMD2/RE2
A30 VDD A67 PMD4/RE4
A31 AETXD1/SCK3/U4TX/U1RTS/CN21/RD15 A68 No Connect (NC)
A32 SCL5/SDO4/U2TX/PMA8/CN18/RF5 B1 VDD
A33 No Connect (NC) B2 PMD5/RE5
A34 No Connect (NC) B3 PMD7/RE7
A35 USBID/RF3 B4 T3CK/AC2TX(1)/RC2
A36 SDA3/SDI3/U1RX/RF2 B5 T5CK/SDI1/RC4
A37 VBUS B6 ECRS/SDA4/SDI2/U3RX/PMA4/CN9/RG7
B7 MCLR B32 SDA2/RA3
Note 1: This pin is only available on PIC32MX795F512L devices.
2: Shaded package bumps are 5V tolerant.
3: It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the
package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout.

DS60001156K-page 20  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 13: PIN NAMES FOR 124-PIN USB, ETHERNET, AND CAN DEVICES (CONTINUED)

124-PIN VTLA (BOTTOM VIEW)(2,3) A34

A17
B13 B29
Conductive
Thermal Pad

PIC32MX675F512L B41
B1
PIC32MX695F512L B56
PIC32MX795F512L A51

A1
A68
Polarity Indicator
Package Package
Full Pin Name Full Pin Name
Bump # Bump #
B8 VSS B33 TDO/RA5
B9 TMS/RA0 B34 OSC1/CLKI/RC12
B10 AERXD1/INT2/RE9 B35 No Connect (NC)
B11 AN4/C1IN-/CN6/RB4 B36 AETXCLK/SCL1/INT3/RA14
B12 VSS B37 RTCC/EMDIO/AEMDIO/IC1/RD8
B13 AN2/C2IN-/CN4/RB2 B38 SCK1/IC3/PMCS2/PMA15/RD10
B14 PGED1/AN0/CN2/RB0 B39 SDO1/OC1/INT0/RD0
B15 No Connect (NC) B40 SOSCO/T1CK/CN0/RC14
B16 PGED2/AN7/RB7 B41 VSS
B17 VREF+/CVREF+/AERXD3/PMA6/RA10 B42 OC3/RD2
B18 AVSS B43 ETXD2/IC5/PMD12/RD12
B19 AN9/C2OUT/RB9 B44 OC5/PMWR/CN13/RD4
B20 AN11/ERXERR/AETXERR/PMA12/RB11 B45 ETXEN/PMD14/CN15/RD6
B21 VDD B46 VSS
B22 AC1TX/SCK4/U5TX/U2RTS/RF13 B47 No Connect (NC)
B23 AN12/ERXD0/AECRS/PMA11/RB12 B48 VCAP
B24 AN14/ERXD2/AETXD3/PMALH/PMA1/RB14 B49 C1RX(1)/ETXD1/PMD11/RF0
B25 VSS B50 C2TX(1)/ETXERR/PMD9/RG1
B26 AETXD0/SS3/U4RX/U1CTS/CN20/RD14 B51 TRCLK/RA6
B27 SDA5/SDI4/U2RX/PMA9/CN17/RF4 B52 PMD0/RE0
B28 No Connect (NC) B53 VDD
B29 SCL3/SDO3/U1TX/RF8 B54 TRD2/RG14
B30 VUSB3V3 B55 TRD0/RG13
B31 D+/RG2 B56 PMD3/RE3
Note 1: This pin is only available on PIC32MX795F512L devices.
2: Shaded package bumps are 5V tolerant.
3: It is recommended that the user connect the printed circuit board (PCB) ground to the conductive thermal pad on the bottom of the
package. And to not run non-Vss PCB traces under the conductive thermal pad on the same side of the PCB layout.

 2009-2019 Microchip Technology Inc. DS60001156K-page 21

PIC32MX5XX/6XX/7XX
Table of Contents
1.0 Device Overview ........................................................................................................................................................................ 25
2.0 Guidelines for Getting Started with 32-bit MCUs........................................................................................................................ 37
3.0 CPU ............................................................................................................................................................................................ 45
4.0 Memory Organization ................................................................................................................................................................. 51
5.0 Flash Program Memory .............................................................................................................................................................. 67
6.0 Resets ........................................................................................................................................................................................ 73
7.0 Interrupt Controller ..................................................................................................................................................................... 77
8.0 Oscillator Configuration .............................................................................................................................................................. 99
9.0 Prefetch Cache......................................................................................................................................................................... 105
10.0 Direct Memory Access (DMA) Controller ................................................................................................................................. 115
11.0 USB On-The-Go (OTG)............................................................................................................................................................ 137
12.0 I/O Ports ................................................................................................................................................................................... 161
13.0 Timer1 ...................................................................................................................................................................................... 171
14.0 Timer2/3, Timer4/5 ................................................................................................................................................................... 175
15.0 Watchdog Timer (WDT) ........................................................................................................................................................... 181
16.0 Input Capture............................................................................................................................................................................ 185
17.0 Output Compare ....................................................................................................................................................................... 189
18.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 193
19.0 Inter-Integrated Circuit (I2C) ..................................................................................................................................................... 199
20.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 207
21.0 Parallel Master Port (PMP)....................................................................................................................................................... 215
22.0 Real-Time Clock and Calendar (RTCC) ................................................................................................................................... 225
23.0 10-bit Analog-to-Digital Converter (ADC) ................................................................................................................................. 235
24.0 Controller Area Network (CAN) ................................................................................................................................................ 245
25.0 Ethernet Controller ................................................................................................................................................................... 283
26.0 Comparator .............................................................................................................................................................................. 327
27.0 Comparator Voltage Reference (CVREF).................................................................................................................................. 331
28.0 Power-Saving Features ........................................................................................................................................................... 335
29.0 Special Features ...................................................................................................................................................................... 337
30.0 Instruction Set .......................................................................................................................................................................... 349
31.0 Development Support............................................................................................................................................................... 351
32.0 Electrical Characteristics .......................................................................................................................................................... 355
33.0 DC and AC Device Characteristics Graphs.............................................................................................................................. 403
34.0 Packaging Information.............................................................................................................................................................. 405
The Microchip Web Site ..................................................................................................................................................................... 443
Customer Change Notification Service .............................................................................................................................................. 443
Customer Support .............................................................................................................................................................................. 443
Product Identification System............................................................................................................................................................. 444

DS60001156K-page 22  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX

TO OUR VALUED CUSTOMERS

It is our intention to provide our valued customers with the best documentation possible to ensure successful use of
your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our pub-
lications will be refined and enhanced as new volumes and updates are introduced.
If you have any questions or comments regarding this publication, please contact the Marketing Communications
Department via E-mail at [email protected] or fax the Reader Response Form in the back of this data
sheet to (480) 792-4150. We welcome your feedback.

Most Current Data Sheet

To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at:
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You can determine the version of a data sheet by examining its literature number found on the bottom outside corner
of any page. The last character of the literature number is the version number, (e.g., DS30000000A is version A of
document DS30000000).

Errata
An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may
exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The
errata will specify the revision of silicon and revision of document to which it applies.
To determine if an errata sheet exists for a particular device, please check with one of the following:
• Microchip’s Worldwide Web site; http://www.microchip.com
• Your local Microchip sales office (see last page)
When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature
number) you are using.

Customer Notification System

Register on our web site at www.microchip.com to receive the most current information on all of our products.

 2009-2019 Microchip Technology Inc. DS60001156K-page 23

PIC32MX5XX/6XX/7XX
Referenced Sources
This device data sheet is based on the following
individual chapters of the “PIC32 Family Reference
Manual”. These documents should be considered as
the general reference for the operation of a particular
module or device feature.
Note 1: To access the documents listed below,
browse to the documentation section of
the PIC32MX795F512L product page on
the Microchip web site
(www.microchip.com) or select a family
reference manual section from the
following list.
In addition to parameters, features, and
other documentation, the resulting page
provides links to the related family
reference manual sections.

• Section 1. “Introduction” (DS60001127)

• Section 2. “CPU” (DS60001113)
• Section 4. “Prefetch Cache” (DS60001119)
• Section 3. “Memory Organization” (DS60001115)
• Section 5. “Flash Program Memory” (DS60001121)
• Section 6. “Oscillator Configuration” (DS60001112)
• Section 7. “Resets” (DS60001118)
• Section 8. “Interrupt Controller” (DS60001108)
• Section 9. “Watchdog Timer and Power-up Timer (DS60001114)
• Section 10. “Power-Saving Features” (DS60001130)
• Section 12. “I/O Ports” (DS60001120)
• Section 13. “Parallel Master Port (PMP)” (DS60001128)
• Section 14. “Timers” (DS60001105)
• Section 15. “Input Capture” (DS60001122)
• Section 16. “Output Capture” (DS60001111)
• Section 17. “10-bit Analog-to-Digital Converter (ADC)” (DS60001104)
• Section 19. “Comparator” (DS60001110)
• Section 20. “Comparator Voltage Reference (CVREF)” (DS60001109)
• Section 21. “Universal Asynchronous Receiver Transmitter (UART)” (DS60001107)
• Section 23. “Serial Peripheral Interface (SPI)” (DS60001106)
• Section 24. “Inter-Integrated Circuit (I2C)” (DS60001116)
• Section 27. “USB On-The-Go (OTG)” (DS60001126)
• Section 29. “Real-Time Clock and Calendar (RTCC)” (DS60001125)
• Section 31. “Direct Memory Access (DMA) Controller” (DS60001117)
• Section 32. “Configuration” (DS60001124)
• Section 33. “Programming and Diagnostics” (DS60001129)
• Section 34. “Controller Area Network (CAN)” (DS60001154)
• Section 35. “Ethernet Controller” (DS60001155)

DS60001156K-page 24  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
1.0 DEVICE OVERVIEW This document contains device-specific information for
PIC32MX5XX/6XX/7XX devices.
Note: This data sheet summarizes the features Figure 1-1 illustrates a general block diagram of the
of the PIC32MX5XX/6XX/7XX family of core and peripheral modules in the PIC32MX5XX/6XX/
devices. It is not intended to be a 7XX family of devices.
comprehensive reference source. To
complement the information in this data Table 1-1 lists the functions of the various pins shown
sheet, refer to the documents listed in the in the pinout diagrams.
Documentation > Reference Manual
section of the Microchip PIC32 web site
(www.microchip.com/pic32).

FIGURE 1-1: BLOCK DIAGRAM(1,2)

VCAP
OSC2/CLKO OSC/SOSC
OSC1/CLKI Oscillators Power-up VDD, VSS
Timer
FRC/LPRC MCLR
Oscillators Voltage Oscillator
Regulator Start-up Timer
PLL
Power-on
Precision Reset
Dividers Band Gap
Reference
PLL-USB Watchdog
USBCLK Timer
SYSCLK Brown-out
Timing Reset
Generation PBCLK

Peripheral Bus Clocked by SYSCLK

CN1-22
PORTA
Timer1-5
Priority
JTAG Interrupt
BSCAN Controller PWM
CAN1, CAN2

Peripheral Bus Clocked by PBCLK

ETHERNET

PORTB OC1-5
DMAC
USB

ICD

EJTAG INT 32

MIPS32® M4K® IC1-5

PORTC CPU Core
IS DS
32 32 32 32 32
32 SPI1-4
32 32
PORTD
Bus Matrix

32 32 32 I2C1-5

PORTE 32
Prefetch
Peripheral Bridge
Module Data RAM
PMP

PORTF 10-bit ADC

128
UART1-6
Controller

128-bit Wide
Flash

PORTG Program Flash Memory RTCC

Comparators
Note 1: Some features are not available on all devices.
2: BOR functionality is provided when the on-board voltage regulator is enabled.

 2009-2019 Microchip Technology Inc. DS60001156K-page 25

PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
AN0 16 25 K2 B14 I Analog Analog input channels
AN1 15 24 K1 A15 I Analog
AN2 14 23 J2 B13 I Analog
AN3 13 22 J1 A13 I Analog
AN4 12 21 H2 B11 I Analog
AN5 11 20 H1 A12 I Analog
AN6 17 26 L1 A20 I Analog
AN7 18 27 J3 B16 I Analog
AN8 21 32 K4 A23 I Analog
AN9 22 33 L4 B19 I Analog
AN10 23 34 L5 A24 I Analog
AN11 24 35 J5 B20 I Analog
AN12 27 41 J7 B23 I Analog
AN13 28 42 L7 A28 I Analog
AN14 29 43 K7 B24 I Analog
AN15 30 44 L8 A29 I Analog
ST/ External clock source input. Always
CLKI 39 63 F9 B34 I
CMOS associated with OSC1 pin function.
Oscillator crystal output. Connects to
crystal or resonator in Crystal Oscillator
CLKO 40 64 F11 A42 O — mode. Optionally functions as CLKO in
RC and EC modes. Always associated
with OSC2 pin function.
Oscillator crystal input. ST buffer when
ST/
OSC1 39 63 F9 B34 I configured in RC mode; CMOS
CMOS
otherwise.
Oscillator crystal output. Connects to
crystal or resonator in Crystal Oscillator
OSC2 40 64 F11 A42 I/O —
mode. Optionally functions as CLKO in
RC and EC modes.
ST/ 32.768 kHz low-power oscillator crystal
SOSCI 47 73 C10 A47 I
CMOS input; CMOS otherwise
32.768 kHz low-power oscillator crystal
SOSCO 48 74 B11 B40 O —
output
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

DS60001156K-page 26  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
CN0 48 74 B11 B40 I ST Change notification inputs. Can be
CN1 47 73 C10 A47 I ST software programmed for internal weak
pull-ups on all inputs.
CN2 16 25 K2 B14 I ST
CN3 15 24 K1 A15 I ST
CN4 14 23 J2 B13 I ST
CN5 13 22 J1 A13 I ST
CN6 12 21 H2 B11 I ST
CN7 11 20 H1 A12 I ST
CN8 4 10 E3 A7 I ST
CN9 5 11 F4 B6 I ST
CN10 6 12 F2 A8 I ST
CN11 8 14 F3 A9 I ST
CN12 30 44 L8 A29 I ST
CN13 52 81 C8 B44 I ST
CN14 53 82 B8 A55 I ST
CN15 54 83 D7 B45 I ST
CN16 55 84 C7 A56 I ST
CN17 31 49 L10 B27 I ST
CN18 32 50 L11 A32 I ST
CN19 — 80 D8 A54 I ST
CN20 — 47 L9 B26 I ST
CN21 — 48 K9 A31 I ST
IC1 42 68 E9 B37 I ST Capture Inputs 1-5
IC2 43 69 E10 A45 I ST
IC3 44 70 D11 B38 I ST
IC4 45 71 C11 A46 I ST
IC5 52 79 A9 A60 I ST
OCFA 17 26 L1 A20 I ST Output Compare Fault A Input
OC1 46 72 D9 B39 O — Output Compare Output 1
OC2 49 76 A11 A52 O — Output Compare Output 2
OC3 50 77 A10 B42 O — Output Compare Output 3
OC4 51 78 B9 A53 O — Output Compare Output 4
OC5 52 81 C8 B44 O — Output Compare Output 5
OCFB 30 44 L8 A29 I ST Output Compare Fault B Input
INT0 46 72 D9 B39 I ST External Interrupt 0
INT1 42 18 G1 A11 I ST External Interrupt 1
INT2 43 19 G2 B10 I ST External Interrupt 2
INT3 44 66 E11 B36 I ST External Interrupt 3
INT4 45 67 E8 A44 I ST External Interrupt 4
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

 2009-2019 Microchip Technology Inc. DS60001156K-page 27

PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
RA0 — 17 G3 B9 I/O ST PORTA is a bidirectional I/O port
RA1 — 38 J6 A26 I/O ST
RA2 — 58 H11 A39 I/O ST
RA3 — 59 G10 B32 I/O ST
RA4 — 60 G11 A40 I/O ST
RA5 — 61 G9 B33 I/O ST
RA6 — 91 C5 B51 I/O ST
RA7 — 92 B5 A62 I/O ST
RA9 — 28 L2 A21 I/O ST
RA10 — 29 K3 B17 I/O ST
RA14 — 66 E11 B36 I/O ST
RA15 — 67 E8 A44 I/O ST
RB0 16 25 K2 B14 I/O ST PORTB is a bidirectional I/O port
RB1 15 24 K1 A15 I/O ST
RB2 14 23 J2 B13 I/O ST
RB3 13 22 J1 A13 I/O ST
RB4 12 21 H2 B11 I/O ST
RB5 11 20 H1 A12 I/O ST
RB6 17 26 L1 A20 I/O ST
RB7 18 27 J3 B16 I/O ST
RB8 21 32 K4 A23 I/O ST
RB9 22 33 L4 B19 I/O ST
RB10 23 34 L5 A24 I/O ST
RB11 24 35 J5 B20 I/O ST
RB12 27 41 J7 B23 I/O ST
RB13 28 42 L7 A28 I/O ST
RB14 29 43 K7 B24 I/O ST
RB15 30 44 L8 A29 I/O ST
RC1 — 6 D1 A5 I/O ST PORTC is a bidirectional I/O port
RC2 — 7 E4 B4 I/O ST
RC3 — 8 E2 A6 I/O ST
RC4 — 9 E1 B5 I/O ST
RC12 39 63 F9 B34 I/O ST
RC13 47 73 C10 A47 I/O ST
RC14 48 74 B11 B40 I/O ST
RC15 40 64 F11 A42 I/O ST
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

DS60001156K-page 28  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
RD0 46 72 D9 B39 I/O ST PORTD is a bidirectional I/O port
RD1 49 76 A11 A52 I/O ST
RD2 50 77 A10 B42 I/O ST
RD3 51 78 B9 A53 I/O ST
RD4 52 81 C8 B44 I/O ST
RD5 53 82 B8 A55 I/O ST
RD6 54 83 D7 B45 I/O ST
RD7 55 84 C7 A56 I/O ST
RD8 42 68 E9 B37 I/O ST
RD9 43 69 E10 A45 I/O ST
RD10 44 70 D11 B38 I/O ST
RD11 45 71 C11 A46 I/O ST
RD12 — 79 A9 B43 I/O ST
RD13 — 80 D8 A54 I/O ST
RD14 — 47 L9 B26 I/O ST
RD15 — 48 K9 A31 I/O ST
RE0 60 93 A4 B52 I/O ST PORTE is a bidirectional I/O port
RE1 61 94 B4 A64 I/O ST
RE2 62 98 B3 A66 I/O ST
RE3 63 99 A2 B56 I/O ST
RE4 64 100 A1 A67 I/O ST
RE5 1 3 D3 B2 I/O ST
RE6 2 4 C1 A4 I/O ST
RE7 3 5 D2 B3 I/O ST
RE8 — 18 G1 A11 I/O ST
RE9 — 19 G2 B10 I/O ST
RF0 58 87 B6 B49 I/O ST PORTF is a bidirectional I/O port
RF1 59 88 A6 A60 I/O ST
RF2 — 52 K11 A36 I/O ST
RF3 33 51 K10 A35 I/O ST
RF4 31 49 L10 B27 I/O ST
RF5 32 50 L11 A32 I/O ST
RF8 — 53 J10 B29 I/O ST
RF12 — 40 K6 A27 I/O ST
RF13 — 39 L6 B22 I/O ST
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

 2009-2019 Microchip Technology Inc. DS60001156K-page 29

PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
RG0 — 90 A5 A61 I/O ST PORTG is a bidirectional I/O port
RG1 — 89 E6 B50 I/O ST
RG6 4 10 E3 A7 I/O ST
RG7 5 11 F4 B6 I/O ST
RG8 6 12 F2 A8 I/O ST
RG9 8 14 F3 A9 I/O ST
RG12 — 96 C3 A65 I/O ST
RG13 — 97 A3 B55 I/O ST
RG14 — 95 C4 B54 I/O ST
RG15 — 1 B2 A2 I/O ST
RG2 37 57 H10 B31 I ST PORTG input pins
RG3 36 56 J11 A38 I ST
T1CK 48 74 B11 B40 I ST Timer1 external clock input
T2CK — 6 D1 A5 I ST Timer2 external clock input
T3CK — 7 E4 B4 I ST Timer3 external clock input
T4CK — 8 E2 A6 I ST Timer4 external clock input
T5CK — 9 E1 B5 I ST Timer5 external clock input
U1CTS 43 47 L9 B26 I ST UART1 clear to send
U1RTS 49 48 K9 A31 O — UART1 ready to send
U1RX 50 52 K11 A36 I ST UART1 receive
U1TX 51 53 J10 B29 O — UART1 transmit
U3CTS 8 14 F3 A9 I ST UART3 clear to send
U3RTS 4 10 E3 A7 O — UART3 ready to send
U3RX 5 11 F4 B6 I ST UART3 receive
U3TX 6 12 F2 A8 O — UART3 transmit
U2CTS 21 40 K6 A27 I ST UART2 clear to send
U2RTS 29 39 L6 B22 O — UART2 ready to send
U2RX 31 49 L10 B27 I ST UART2 receive
U2TX 32 50 L11 A32 O — UART2 transmit
U4RX 43 47 L9 B26 I ST UART4 receive
U4TX 49 48 K9 A31 O — UART4 transmit
U6RX 8 14 F3 A9 I ST UART6 receive
U6TX 4 10 E3 A7 O — UART6 transmit
U5RX 21 40 K6 A27 I ST UART5 receive
U5TX 29 39 L6 B22 O — UART5 transmit
Synchronous serial clock input/output
SCK1 — 70 D11 B38 I/O ST
for SPI1
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

DS60001156K-page 30  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
SDI1 — 9 E1 B5 I ST SPI1 data in
SDO1 — 72 D9 B39 O — SPI1 data out
SPI1 slave synchronization or frame
SS1 — 69 E10 A45 I/O ST
pulse I/O
Synchronous serial clock input/output
SCK3 49 48 K9 A31 I/O ST
for SPI3
SDI3 50 52 K11 A36 I ST SPI3 data in
SDO3 51 53 J10 B29 O — SPI3 data out
SPI3 slave synchronization or frame
SS3 43 47 L9 B26 I/O ST
pulse I/O
Synchronous serial clock input/output
SCK2 4 10 E3 A7 I/O ST
for SPI2
SDI2 5 11 F4 B6 I ST SPI2 data in
SDO2 6 12 F2 A8 O — SPI2 data out
SPI2 slave synchronization or frame
SS2 8 14 F3 A9 I/O ST
pulse I/O
Synchronous serial clock input/output
SCK4 29 39 L6 B22 I/O ST
for SPI4
SDI4 31 49 L10 B27 I ST SPI4 data in
SDO4 32 50 L11 A32 O — SPI4 data out
SPI4 slave synchronization or frame
SS4 21 40 K6 A27 I/O ST
pulse I/O
Synchronous serial clock input/output
SCL1 44 66 E11 B36 I/O ST
for I2C1
Synchronous serial data input/output
SDA1 43 67 E8 A44 I/O ST
for I2C1
Synchronous serial clock input/output
SCL3 51 53 J10 B29 I/O ST
for I2C3
Synchronous serial data input/output
SDA3 50 52 K11 A36 I/O ST
for I2C3
Synchronous serial clock input/output
SCL2 — 58 H11 A39 I/O ST
for I2C2
Synchronous serial data input/output
SDA2 — 59 G10 B32 I/O ST
for I2C2
Synchronous serial clock input/output
SCL4 6 12 F2 A8 I/O ST
for I2C4
Synchronous serial data input/output
SDA4 5 11 F4 B6 I/O ST
for I2C4
Synchronous serial clock input/output
SCL5 32 50 L11 A32 I/O ST
for I2C5
Synchronous serial data input/output
SDA5 31 49 L10 B27 I/O ST
for I2C5
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

 2009-2019 Microchip Technology Inc. DS60001156K-page 31

PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
TMS 23 17 G3 B9 I ST JTAG Test mode select pin
TCK 27 38 J6 A26 I ST JTAG test clock input pin
TDI 28 60 G11 A40 I ST JTAG test data input pin
TDO 24 61 G9 B33 O — JTAG test data output pin
RTCC 42 68 E9 B37 O — Real-Time Clock alarm output
CVREF- 15 28 L2 A21 I Analog Comparator Voltage Reference (low)
CVREF+ 16 29 K3 B17 I Analog Comparator Voltage Reference (high)
CVREFOUT 23 34 L5 A24 O Analog Comparator Voltage Reference output
C1IN- 12 21 H2 B11 I Analog Comparator 1 negative input
C1IN+ 11 20 H1 A12 I Analog Comparator 1 positive input
C1OUT 21 32 K4 A23 O — Comparator 1 output
C2IN- 14 23 J2 B13 I Analog Comparator 2 negative input
C2IN+ 13 22 J1 A13 I Analog Comparator 2 positive input
C2OUT 22 33 L4 B19 O — Comparator 2 output
Parallel Master Port Address bit 0 input
PMA0 30 44 L8 A29 I/O TTL/ST (Buffered Slave modes) and output
(Master modes)
Parallel Master Port Address bit 1 input
PMA1 29 43 K7 B24 I/O TTL/ST (Buffered Slave modes) and output
(Master modes)
PMA2 8 14 F3 A9 O — Parallel Master Port address
PMA3 6 12 F2 A8 O — (Demultiplexed Master modes)
PMA4 5 11 F4 B6 O —
PMA5 4 10 E3 A7 O —
PMA6 16 29 K3 B17 O —
PMA7 22 28 L2 A21 O —
PMA8 32 50 L11 A32 O —
PMA9 31 49 L10 B27 O —
PMA10 28 42 L7 A28 O —
PMA11 27 41 J7 B23 O —
PMA12 24 35 J5 B20 O —
PMA13 23 34 L5 A24 O —
PMA14 45 71 C11 A46 O —
PMA15 44 70 D11 B38 O —
Parallel Master Port Chip Select 1
PMCS1 45 71 C11 A46 O —
strobe
Parallel Master Port Chip Select 2
PMCS2 44 70 D11 B38 O —
strobe
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

DS60001156K-page 32  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
PMD0 60 93 A4 B52 I/O TTL/ST Parallel Master Port data
PMD1 61 94 B4 A64 I/O TTL/ST (Demultiplexed Master mode) or
address/data (Multiplexed Master
PMD2 62 98 B3 A66 I/O TTL/ST
modes)
PMD3 63 99 A2 B56 I/O TTL/ST
PMD4 64 100 A1 A67 I/O TTL/ST
PMD5 1 3 D3 B2 I/O TTL/ST
PMD6 2 4 C1 A4 I/O TTL/ST
PMD7 3 5 D2 B3 I/O TTL/ST
PMD8 — 90 A5 A61 I/O TTL/ST
PMD9 — 89 E6 B50 I/O TTL/ST
PMD10 — 88 A6 A60 I/O TTL/ST
PMD11 — 87 B6 B49 I/O TTL/ST
PMD12 — 79 A9 B43 I/O TTL/ST
PMD13 — 80 D8 A54 I/O TTL/ST
PMD14 — 83 D7 B45 I/O TTL/ST
PMD15 — 84 C7 A56 I/O TTL/ST
Parallel Master Port address latch
PMALL 30 44 L8 A29 O — enable low byte (Multiplexed Master
modes)
Parallel Master Port address latch
PMALH 29 43 K7 B24 O — enable high byte (Multiplexed Master
modes)
PMRD 53 82 B8 A55 O — Parallel Master Port read strobe
PMWR 52 81 C8 B44 O — Parallel Master Port write strobe
VBUS 34 54 H8 A37 I Analog USB bus power monitor
USB internal transceiver supply. If the
VUSB3V3 35 55 H9 B30 P — USB module is not used, this pin must
be connected to VDD.
USB Host and OTG bus power control
VBUSON 11 20 H1 A12 O —
output
D+ 37 57 H10 B31 I/O Analog USB D+
D- 36 56 J11 A38 I/O Analog USB D-
USBID 33 51 K10 A35 I ST USB OTG ID detect
C1RX 58 87 B6 B49 I ST CAN1 bus receive pin
C1TX 59 88 A6 A60 O — CAN1 bus transmit pin
AC1RX 32 40 K6 A27 I ST Alternate CAN1 bus receive pin
AC1TX 31 39 L6 B22 O — Alternate CAN1 bus transmit pin
C2RX 29 90 A5 A61 I ST CAN2 bus receive pin
C2TX 21 89 E6 B50 O — CAN2 bus transmit pin
AC2RX — 8 E2 A6 1 ST Alternate CAN2 bus receive pin
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

 2009-2019 Microchip Technology Inc. DS60001156K-page 33

PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
AC2TX — 7 E4 B4 O — Alternate CAN2 bus transmit pin
ERXD0 61 41 J7 B23 I ST Ethernet Receive Data 0(2)
ERXD1 60 42 L7 A28 I ST Ethernet Receive Data 1(2)
ERXD2 59 43 K7 B24 I ST Ethernet Receive Data 2(2)
ERXD3 58 44 L8 A29 I ST Ethernet Receive Data 3(2)
ERXERR 64 35 J5 B20 I ST Ethernet receive error input(2)
ERXDV 62 12 F2 A8 I ST Ethernet receive data valid(2)
ECRSDV 62 12 F2 A8 I ST Ethernet carrier sense data valid(2)
ERXCLK 63 14 F3 A9 I ST Ethernet receive clock(2)
EREFCLK 63 14 F3 A9 I ST Ethernet reference clock(2)
ETXD0 2 88 A6 A60 O — Ethernet Transmit Data 0(2)
ETXD1 3 87 B6 B49 O — Ethernet Transmit Data 1(2)
ETXD2 43 79 A9 B43 O — Ethernet Transmit Data 2(2)
ETXD3 42 80 D8 A54 O — Ethernet Transmit Data 3(2)
ETXERR 54 89 E6 B50 O — Ethernet transmit error(2)
ETXEN 1 83 D7 B45 O — Ethernet transmit enable(2)
ETXCLK 55 84 C7 A56 I ST Ethernet transmit clock(2)
ECOL 44 10 E3 A7 I ST Ethernet collision detect(2)
ECRS 45 11 F4 B6 I ST Ethernet carrier sense(2)
EMDC 30 71 C11 A46 O — Ethernet management data clock(2)
EMDIO 49 68 E9 B37 I/O — Ethernet management data(2)
AERXD0 43 18 G1 A11 I ST Alternate Ethernet Receive Data 0(2)
AERXD1 42 19 G2 B10 I ST Alternate Ethernet Receive Data 1(2)
AERXD2 — 28 L2 A21 I ST Alternate Ethernet Receive Data 2(2)
AERXD3 — 29 K3 B17 I ST Alternate Ethernet Receive Data 3(2)
AERXERR 55 1 B2 A2 I ST Alternate Ethernet receive error input(2)
AERXDV — 12 F2 A8 I ST Alternate Ethernet receive data valid(2)
Alternate Ethernet carrier sense data
AECRSDV 44 12 F2 A8 I ST
valid(2)
AERXCLK — 14 F3 A9 I ST Alternate Ethernet receive clock(2)
AEREFCLK 45 14 F3 A9 I ST Alternate Ethernet reference clock(2)
AETXD0 59 47 L9 B26 O — Alternate Ethernet Transmit Data 0(2)
AETXD1 58 48 K9 A31 O — Alternate Ethernet Transmit Data 1(2)
AETXD2 — 44 L8 A29 O — Alternate Ethernet Transmit Data 2(2)
AETXD3 — 43 K7 B24 O — Alternate Ethernet Transmit Data 3(2)
AETXERR — 35 J5 B20 O — Alternate Ethernet transmit error(2)
AETXEN 54 67 E8 A44 O — Alternate Ethernet transmit enable(2)
AETXCLK — 66 E11 B36 I ST Alternate Ethernet transmit clock(2)
AECOL — 42 L7 A28 I ST Alternate Ethernet collision detect(2)
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

DS60001156K-page 34  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 1-1: PINOUT I/O DESCRIPTIONS (CONTINUED)
Pin Number(1)
Pin Buffer
Pin Name 64-Pin 100-Pin 121-Pin 124-pin Description
Type Type
QFN/TQFP TQFP TFBGA VTLA
AECRS — 41 J7 B23 I ST Alternate Ethernet carrier sense(2)
Alternate Ethernet Management Data
AEMDC 30 71 C11 A46 O —
clock(2)
AEMDIO 49 68 E9 B37 I/O — Alternate Ethernet Management Data(2)
TRCLK — 91 C5 B51 O — Trace clock
TRD0 — 97 A3 B55 O — Trace Data bits 0-3
TRD1 — 96 C3 A65 O —
TRD2 — 95 C4 B54 O —
TRD3 — 92 B5 A62 O —
Data I/O pin for Programming/
PGED1 16 25 K2 B14 I/O ST
Debugging Communication Channel 1
Clock input pin for Programming/
PGEC1 15 24 K1 A15 I ST
Debugging Communication Channel 1
Data I/O pin for Programming/
PGED2 18 27 J3 B16 I/O ST
Debugging Communication Channel 2
Clock input pin for Programming/
PGEC2 17 26 L1 A20 I ST
Debugging Communication Channel 2
Master Clear (Reset) input. This pin is
MCLR 7 13 F1 B7 I/P ST
an active-low Reset to the device.
Positive supply for analog modules.
AVDD 19 30 J4 A22 P P
This pin must be connected at all times.
AVSS 20 31 L3 B18 P P Ground reference for analog modules
A7, C2, A10, A14, Positive supply for peripheral logic and
C9, E5, A30, A41, I/O pins
10, 26, 38, 2, 16, 37,
VDD K8, F8, A48, A59, P —
57 46, 62, 86
G5, H4, B1, B21,
H6 B53
VCAP 56 85 B7 B48 P — Capacitor for Internal Voltage Regulator
A8, B10, A3, A25, Ground reference for logic and I/O pins.
D4, D5, A43, A63, This pin must be connected at all times.
15, 36, 45,
VSS 9, 25, 41 E7, F5, B8, B12, P —
65, 75
F10, G6, B25, B41,
G7, H3 B46
VREF+ 16 29 K3 B17 I Analog Analog voltage reference (high) input
VREF- 15 28 L2 A21 I Analog Analog voltage reference (low) input
Legend: CMOS = CMOS compatible input or output Analog = Analog input P = Power
ST = Schmitt Trigger input with CMOS levels O = Output I = Input
TTL = TTL input buffer
Note 1: Pin numbers are only provided for reference. See the “Device Pin Tables” section for device pin
availability.
2: See 25.0 “Ethernet Controller” for more information.

 2009-2019 Microchip Technology Inc. DS60001156K-page 35

PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 36  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
2.0 GUIDELINES FOR GETTING 2.2 Decoupling Capacitors
STARTED WITH 32-BIT MCUS The use of decoupling capacitors on power supply
Note: This data sheet summarizes the features pins, such as VDD, VSS, AVDD and AVSS is required.
of the PIC32MX5XX/6XX/7XX family of See Figure 2-1.
devices. It is not intended to be a Consider the following criteria when using decoupling
comprehensive reference source. To capacitors:
complement the information in this data
sheet, refer to the related section of the • Value and type of capacitor: A value of 0.1 µF
“PIC32 Family Reference Manual”, which (100 nF), 10-20V is recommended. The capacitor
is available from the Microchip web site should be a low Equivalent Series Resistance
(www.microchip.com/PIC32). (low-ESR) capacitor and have resonance fre-
quency in the range of 20 MHz and higher. It is
2.1 Basic Connection Requirements further recommended to use ceramic capacitors.
• Placement on the printed circuit board: The
Getting started with the PIC32MX5XX/6XX/7XX family
decoupling capacitors should be placed as close
of 32-bit Microcontrollers (MCUs) requires attention to
to the pins as possible. It is recommended that
a minimal set of device pin connections before pro-
the capacitors be placed on the same side of
ceeding with development. The following is a list of pin
the board as the device. If space is constricted,
names, which must always be connected:
the capacitor can be placed on another layer on
• All VDD and VSS pins (see 2.2 “Decoupling the PCB using a via; however, ensure that the
Capacitors”) trace length from the pin to the capacitor is
• All AVDD and AVSS pins even if the ADC module is within one-quarter inch (6 mm) in length.
not used (see 2.2 “Decoupling Capacitors”) • Handling high frequency noise: If the board is
• VCAP pin (see 2.3 “Capacitor on Internal Voltage experiencing high frequency noise, upward of
Regulator (VCAP)”) tens of MHz, add a second ceramic-type capacitor
• MCLR pin (see 2.4 “Master Clear (MCLR) Pin”) in parallel to the above described decoupling
• PGECx/PGEDx pins used for In-Circuit Serial capacitor. The value of the second capacitor can
Programming™ (ICSP™) and debugging purposes be in the range of 0.01 µF to 0.001 µF. Place this
(see 2.5 “ICSP Pins”) second capacitor next to the primary decoupling
• OSC1 and OSC2 pins when external oscillator capacitor. In high-speed circuit designs, consider
source is used (see 2.8 “External Oscillator Pins”) implementing a decade pair of capacitances as
close to the power and ground pins as possible.
The following pin may be required, as well: VREF+/
For example, 0.1 µF in parallel with 0.001 µF.
VREF- pins used when external voltage reference for
ADC module is implemented. • Maximizing performance: On the board layout
from the power supply circuit, run the power and
Note: The AVDD and AVSS pins must be return traces to the decoupling capacitors first,
connected, regardless of the ADC use and then to the device pins. This ensures that the
and the ADC voltage reference source. decoupling capacitors are first in the power chain.
Equally important is to keep the trace length
between the capacitor and the power pins to a
minimum, thereby reducing PCB track
inductance.

 2009-2019 Microchip Technology Inc. DS60001156K-page 37

PIC32MX5XX/6XX/7XX
FIGURE 2-1: RECOMMENDED 2.4 Master Clear (MCLR) Pin
MINIMUM CONNECTION The MCLR pin provides two specific device
Tantalum or 0.1 µF functions:
VDD ceramic 10 µF Ceramic • Device Reset
ESR  3(3)
• Device Programming and Debugging
R

VSS
VDD
VCAP
R1 Pulling The MCLR pin low generates a device Reset.
MCLR Figure 2-2 illustrates a typical MCLR circuit. During
device programming and debugging, the resistance
C VUSB3V3(1) and capacitance that can be added to the pin must
be considered. Device programmers and debuggers
PIC32 VDD drive the MCLR pin. Consequently, specific voltage
levels (VIH and VIL) and fast signal transitions must
VSS VSS
0.1 µF
not be adversely affected. Therefore, specific values
Ceramic of R and C will need to be adjusted based on the
VDD
0.1 µF application and PCB requirements.
AVDD

AVSS

VDD

VSS

Ceramic
For example, as illustrated in Figure 2-2, it is
Connect(2) recommended that the capacitor C, be isolated from
0.1 µF 0.1 µF
Ceramic Ceramic
the MCLR pin during programming and debugging
operations.
L1(2)
Place the components illustrated in Figure 2-2 within
Note 1: If the USB module is not used, this pin must be one-quarter inch (6 mm) from the MCLR pin.
connected to VDD.
2: As an option, instead of a hard-wired connection, an FIGURE 2-2: EXAMPLE OF MCLR PIN
inductor (L1) can be substituted between VDD and CONNECTIONS
AVDD to improve ADC noise rejection. The inductor
impedance should be less than 3 and the inductor VDD
capacity greater than 10 mA.

Where: R 10k
R1(1)
MCLR
F CNV 0.1 µF(2) 1 k
f = -------------- (i.e., ADC conversion rate/2) C
2 PIC32
1
f = ----------------------- 1
 2 LC  5
PGECx(3)
4
ICSP™

2 PGEDx(3)
1 - 2
L =  --------------------- VDD
3
  2f C  6
VSS
NC
3: Aluminum or electrolytic capacitors should not be
used. ESR  3 from -40ºC to 125ºC @ SYSCLK Note 1: 470  R1  1k will limit any current flowing into
frequency (i.e., MIPS). MCLR from the external capacitor C, in the event of
MCLR pin breakdown, due to Electrostatic Discharge
2.2.1 BULK CAPACITORS (ESD) or Electrical Overstress (EOS). Ensure that the
MCLR pin VIH and VIL specifications are met without
The use of a bulk capacitor is recommended to improve interfering with the Debug/Programmer tools.
power supply stability. Typical values range from 4.7 µF 2: The capacitor can be sized to prevent unintentional
to 47 µF. This capacitor should be located as close to Resets from brief glitches or to extend the device
Reset period during POR.
the device as possible.
3: No pull-ups or bypass capacitors are allowed on
active debug/program PGECx/PGEDx pins.
2.3 Capacitor on Internal Voltage
Regulator (VCAP)
2.3.1 INTERNAL REGULATOR MODE
A low-ESR (1 ohm) capacitor is required on the VCAP
pin, which is used to stabilize the internal voltage regu-
lator output. The VCAP pin must not be connected to
VDD, and must have a CEFC capacitor, with at least a
6V rating, connected to ground. The type can be
ceramic or tantalum. Refer to Section 32.0 “Electrical
Characteristics” for additional information on CEFC
specifications.

DS60001156K-page 38  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
2.5 ICSP Pins 2.7 Trace
The PGECx and PGEDx pins are used for In-Circuit The trace pins can be connected to a hardware-trace-
Serial Programming™ (ICSP™) and debugging. It is enabled programmer to provide a compress real time
recommended to keep the trace length between the instruction trace. When used for trace the TRD3,
ICSP connector and the ICSP pins on the device as TRD2, TRD1, TRD0 and TRCLK pins should be
short as possible. If the ICSP connector is expected to dedicated for this use. The trace hardware requires
experience an ESD event, a series resistor is a 22 series resistor between the trace pins and the
recommended, with the value in the range of a few tens trace connector.
of Ohms, not to exceed 100 Ohms.
Pull-up resistors, series diodes and capacitors on the 2.8 External Oscillator Pins
PGECx and PGEDx pins are not recommended as they
Many MCUs have options for at least two oscillators: a
will interfere with the programmer/debugger communi-
high-frequency primary oscillator and a low-frequency
cations to the device. If such discrete components are
secondary oscillator. Refer to Section 8.0 “Oscillator
an application requirement, they should be removed
Configuration” for details.
from the circuit during programming and debugging.
Alternatively, refer to the AC/DC characteristics and The oscillator circuit should be placed on the same side
timing requirements information in the respective of the board as the device. Also, place the oscillator cir-
device Flash programming specification for information cuit close to the respective oscillator pins, not exceed-
on capacitive loading limits and pin input voltage high ing one-half inch (12 mm) distance between them. The
(VIH) and input low (VIL) requirements. load capacitors should be placed next to the oscillator
itself, on the same side of the board. Use a grounded
Ensure that the “Communication Channel Select” (i.e.,
copper pour around the oscillator circuit to isolate them
PGECx/PGEDx pins) programmed into the device
from surrounding circuits. The grounded copper pour
matches the physical connections for the ICSP to
should be routed directly to the MCU ground. Do not
MPLAB® ICD 3 or MPLAB® REAL ICE™.
run any signal traces or power traces inside the ground
For more information on ICD 3 and REAL ICE connec- pour. Also, if using a two-sided board, avoid any traces
tion requirements, refer to the following documents that on the other side of the board where the crystal is
are available on the Microchip web site. placed. A suggested layout is illustrated in Figure 2-3.
• “Using MPLAB® ICD 3” (poster) (DS50001765)
• “MPLAB® ICD 3 Design Advisory” (DS50001764) FIGURE 2-3: SUGGESTED OSCILLATOR
• “MPLAB® REAL ICE™ In-Circuit Emulator User’s CIRCUIT PLACEMENT
Guide” (DS50001616)
• “Using MPLAB® REAL ICE™ Emulator” (poster)
(DS50001749)

Oscillator
2.6 JTAG Secondary

The TMS, TDO, TDI and TCK pins are used for testing
Guard Trace
and debugging according to the Joint Test Action
Group (JTAG) standard. It is recommended to keep the
trace length between the JTAG connector and the Guard Ring
JTAG pins on the device as short as possible. If the
JTAG connector is expected to experience an ESD Main Oscillator
event, a series resistor is recommended, with the value
in the range of a few tens of Ohms, not to exceed 100
Ohms.
Pull-up resistors, series diodes and capacitors on the
TMS, TDO, TDI and TCK pins are not recommended
as they will interfere with the programmer/debugger
communications to the device. If such discrete compo-
nents are an application requirement, they should be
removed from the circuit during programming and
debugging. Alternatively, refer to the AC/DC character-
istics and timing requirements information in the
respective device Flash programming specification for
information on capacitive loading limits and pin input
voltage high (VIH) and input low (VIL) requirements.

 2009-2019 Microchip Technology Inc. DS60001156K-page 39

PIC32MX5XX/6XX/7XX
2.9 Configuration of Analog and
Digital Pins During ICSP
Operations
If MPLAB ICD 3 or REAL ICE is selected as a
debugger, it automatically initializes all of the Analog-
to-Digital input pins (ANx) as “digital” pins by setting
all bits in the AD1PCFG register.
The bits in this register that correspond to the Analog-
to-Digital pins that are initialized by MPLAB ICD 3 or
REAL ICE, must not be cleared by the user application
firmware; otherwise, communication errors will result
between the debugger and the device.
If your application needs to use certain ADC pins as
analog input pins during the debug session, the user
application must clear the corresponding bits in the
AD1PCFG register during initialization of the ADC
module.
When MPLAB ICD 3 or REAL ICE is used as a pro-
grammer, the user application firmware must correctly
configure the AD1PCFG register. Automatic initializa-
tion of this register is only done during debugger oper-
ation. Failure to correctly configure the register(s) will
result in all ADC pins being recognized as analog input
pins, resulting in the port value being read as a logic ‘0’,
which may affect user application functionality.

2.10 Unused I/Os

Unused I/O pins should not be allowed to float as
inputs. They can be configured as outputs and driven
to a logic-low state.
Alternatively, inputs can be reserved by connecting the
pin to VSS through a 1k to 10k resistor and configuring
the pin as an input.

DS60001156K-page 40  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
2.11 Considerations When Interfacing the respective injection current specifications defined
to Remotely Powered Circuits by parameters DI60a, DI60b, and DI60c in TABLE 36-
10: “DC Characteristics: I/O Pin Input Injection cur-
2.11.1 NON-5V TOLERANT INPUT PINS rent Specifications”. Figure 2-4 shows an example of
a remote circuit using an independent power source,
A quick review of the absolute maximum rating section which is powered while connected to a PIC32 non-5V
in 36.0 “Electrical Characteristics” will indicate that tolerant circuit that is not powered.
the voltage on any non-5v tolerant pin may not exceed
VDD + 0.3V unless the input current is limited to meet

FIGURE 2-4: PIC32 NON-5V TOLERANT CIRCUIT EXAMPLE

Note: When VDD power is OFF. PIC32 On/Off

VDD
Non-5V Tolerant
Pin Architecture

ANSEL

I/O IN

Remote AN2/RB0 PIC32

0.3V dVIH d 3.6V I/O OUT POWER

CPU LOGIC
SUPPLY
Remote
GND
TRIS

Current Flow

VSS

Without proper signal isolation, on non-5V tolerant TABLE 2-1: EXAMPLES OF DIGITAL/
pins, the remote signal can power the PIC32 device ANALOG ISOLATORS WITH
through the high side ESD protection diodes. OPTIONAL LEVEL
Besides violating the absolute maximum rating TRANSLATION
specification when VDD of the PIC32 device is
Analog/Digital Switch
Capacitive Coupling

restored and ramping up or ramping down, it can

Inductive Coupling

also negatively affect the internal Power-on Reset

Opto Coupling

(POR) and Brown-out Reset (BOR) circuits, which

can lead to improper initialization of internal PIC32 Example Digital/Analog
logic circuits. In these cases, it is recommended to Signal Isolation Circuits
implement digital or analog signal isolation as
depicted in Figure 2-5, as appropriate. This is
indicative of all industry microcontrollers and not just
Microchip products.
ADuM7241 / 40 ARZ (1 Mbps) X — — —
ADuM7241 / 40 CRZ (25 Mbps) X — — —
ISO721 — X — —
LTV-829S (2 Channel) — — X —
LTV-849S (4 Channel) — — X —
FSA266 / NC7WB66 — — — X

 2009-2019 Microchip Technology Inc. DS60001156K-page 41

PIC32MX5XX/6XX/7XX
FIGURE 2-5: EXAMPLE DIGITAL/ANALOG SIGNAL ISOLATION CIRCUITS

Digital Isolator PIC32 VDD

Conn

PIC32 VDD External VDD

Digital Isolator
External VDD REMOTE_IN IN1

IN PIC32
REMOTE_IN PIC32 REMOTE_OUT OUT1

VSS
VSS

PIC32 VDD PIC32 VDD

Analog / Digital Isolator
Opto Digital
ISOLATOR Conn ENB
IN1 Analog_IN2
Analog_OUT2
External VDD
PIC32 External_VDD1 ENB
PIC32
Analog_IN1

S
REMOTE_IN Analog Switch
VSS

VSS

2.11.2 5V TOLERANT INPUT PINS

The internal high side diode on 5v tolerant pins are
bussed to an internal floating node, rather than being
connected to VDD, as shown in Figure 2-6. Voltages
on these pins, if VDD < 2.3V, should not exceed
roughly 3.2V relative to VSS of the PIC32 device.
Voltage of 3.6V or higher will violate the absolute
maximum specification, and will stress the oxide
layer separating the high side floating node, which
impacts device reliability. If a remotely powered
“digital-only” signal can be guaranteed to always be
 3.2V relative to Vss on the PIC32 device side, a
5V tolerant pin could be used without the need for a
digital isolator. This is assuming there is not a
ground loop issue, logic ground of the two circuits
not at the same absolute level, and a remote logic
low input is not less than VSS - 0.3V.

DS60001156K-page 42  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 2-6: PIC32 5V TOLERANT PIN ARCHITECTURE EXAMPLE
PIC32 On/Off
VDD
5V Tolerant Pin
Architecture

Floating Bus
Oxide BV = 3.6V OXIDE
if VDD < 2.3V ANSEL

I/O IN
Remote
VIH = 2.5V RG10 PIC32
I/O OUT POWER

CPU LOGIC
SUPPLY
Remote
GND
TRIS

VSS

FIGURE 2-7: EMI/EMC/EFT

SUPPRESSION CIRCUIT
2.12 EMI/EMC/EFT (IEC 61000-4-4 and
Ferrite Chip SMD
IEC 61000-4-2) Suppression DCR = 0.15ȍ (max)
Considerations 600 ma ISAT
300ȍ @ 100 MHz
PN#: 1-1624117-3
The use of LDO regulators is preferred to reduce VDD
overall system noise and provide a cleaner power Ferrite 0.01 µF
source. However, when utilizing switching Buck/ Chips
Boost regulators as the local power source for PIC32 0.1 µF 0.1 µF
devices, as well as in electrically noisy environ-
ments or test conditions required for IEC 61000-4-4
VDD
VSS

VDD
VSS

and IEC 61000-4-2, users should evaluate the use of

VSS
T-Filters (i.e., L-C-L) on the power pins, as shown in VSS VDD
Figure 2-7. In addition to a more stable power VDD
source, use of this type of T-Filter can greatly reduce 0.1 µF VSS 0.1 µF

susceptibility to EMI sources and events. PIC32 VDD

VSS 0.1 µF
VSS
VDD VUSB3V3
0.1 µF
AVDD
AVSS

VDD
VSS

0.1 µF

0.1 µF 0.1 µF Ferrite

Chips
VDD
0.01 µF

 2009-2019 Microchip Technology Inc. DS60001156K-page 43

PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 44  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
3.0 CPU • MIPS16e® code compression
- 16-bit encoding of 32-bit instructions to
Note: This data sheet summarizes the features improve code density
of the PIC32MX5XX/6XX/7XX family of - Special PC-relative instructions for efficient
devices. It is not intended to be a loading of addresses and constants
comprehensive reference source. To - SAVE and RESTORE macro instructions for
complement the information in this data setting up and tearing down stack frames
sheet, refer to Section 2. “CPU” within subroutines
(DS60001113) in the “PIC32 Family - Improved support for handling 8-bit and 16-bit
Reference Manual”, which is available data types
from the Microchip web site (www.micro-
• Simple Fixed Mapping Translation (FMT)
chip.com/PIC32). Resources for the
mechanism
MIPS32® M4K® Processor Core are
• Simple dual bus interface
available at http://www.imgtec.com.
- Independent 32-bit address and data busses
The MIPS32® M4K® Processor core is the heart of the - Transactions can be aborted to improve
PIC32MX5XX/6XX/7XX family processor. The CPU interrupt latency
fetches instructions, decodes each instruction, fetches • Autonomous multiply/divide unit
source operands, executes each instruction and writes
- Maximum issue rate of one 32x16 multiply
the results of instruction execution to the proper
per clock
destinations.
- Maximum issue rate of one 32x32 multiply
every other clock
3.1 Features
- Early-in iterative divide. Minimum 11 and
• 5-stage pipeline maximum 33 clock latency (dividend (rs) sign
• 32-bit address and data paths extension-dependent)
• MIPS32 Enhanced Architecture (Release 2) • Power control
- Multiply-accumulate and multiply-subtract - Minimum frequency: 0 MHz
instructions - Low-Power mode (triggered by WAIT
- Targeted multiply instruction instruction)
- Zero/One detect instructions - Extensive use of local gated clocks
- WAIT instruction • EJTAG debug and instruction trace
- Conditional move instructions (MOVN, MOVZ) - Support for single stepping
- Vectored interrupts - Virtual instruction and data address/value
- Programmable exception vector base - Breakpoints
- Atomic interrupt enable/disable - PC tracing with trace compression
- GPR shadow registers to minimize latency
for interrupt handlers
- Bit field manipulation instructions

FIGURE 3-1: MIPS32® M4K® PROCESSOR CORE BLOCK DIAGRAM

CPU
EJTAG
MDU

TAP Off-chip Debug Interface

Execution Core
FMT Bus Interface Dual Bus Interface Bus Matrix
(RF/ALU/Shift)

System Power
Co-processor Management

 2009-2019 Microchip Technology Inc. DS60001156K-page 45

PIC32MX5XX/6XX/7XX
3.2 Architecture Overview 3.2.2 MULTIPLY/DIVIDE UNIT (MDU)
The MIPS32 M4K processor core contains several MIPS32 M4K processor core includes a Multiply/Divide
logic blocks working together in parallel, providing an Unit (MDU) that contains a separate pipeline for multi-
efficient high-performance computing engine. The ply and divide operations. This pipeline operates in par-
following blocks are included with the core: allel with the Integer Unit (IU) pipeline and does not stall
when the IU pipeline stalls. This allows MDU opera-
• Execution Unit
tions to be partially masked by system stalls and/or
• Multiply/Divide Unit (MDU) other integer unit instructions.
• System Control Coprocessor (CP0)
The high-performance MDU consists of a 32x16 booth
• Fixed Mapping Translation (FMT)
recoded multiplier, result/accumulation registers (HI
• Dual Internal Bus interfaces and LO), a divide state machine, and the necessary
• Power Management multiplexers and control logic. The first number shown
• MIPS16e® Support (‘32’ of 32x16) represents the rs operand. The second
• Enhanced JTAG (EJTAG) Controller number (‘16’ of 32x16) represents the rt operand. The
PIC32 core only checks the value of the latter (rt)
3.2.1 EXECUTION UNIT operand to determine how many times the operation
The MIPS32 M4K processor core execution unit imple- must pass through the multiplier. The 16x16 and 32x16
ments a load/store architecture with single-cycle ALU operations pass through the multiplier once. A 32x32
operations (logical, shift, add, subtract) and an autono- operation passes through the multiplier twice.
mous multiply/divide unit. The core contains thirty-two The MDU supports execution of one 16x16 or 32x16
32-bit General Purpose Registers (GPRs) used for multiply operation every clock cycle; 32x32 multiply
integer operations and address calculation. One addi- operations can be issued every other clock cycle.
tional register file shadow set (containing thirty-two reg- Appropriate interlocks are implemented to stall the
isters) is added to minimize context switching overhead
issuance of back-to-back 32x32 multiply operations.
during interrupt/exception processing. The register file
The multiply operand size is automatically determined
consists of two read ports and one write port and is fully
by logic built into the MDU.
bypassed to minimize operation latency in the pipeline.
The execution unit includes: Divide operations are implemented with a simple 1 bit
per clock iterative algorithm. An early-in detection
• 32-bit adder used for calculating the data address checks the sign extension of the dividend (rs) operand.
• Address unit for calculating the next instruction If rs is 8 bits wide, 23 iterations are skipped. For a 16 bit
address wide rs, 15 iterations are skipped and for a 24 bit wide rs,
• Logic for branch determination and branch target 7 iterations are skipped. Any attempt to issue a
address calculation subsequent MDU instruction while a divide is still active
• Load aligner causes an IU pipeline stall until the divide operation is
• Bypass multiplexers used to avoid stalls when completed.
executing instruction streams where data Table 3-1 lists the repeat rate (peak issue rate of cycles
producing instructions are followed closely by until the operation can be reissued) and latency (num-
consumers of their results ber of cycles until a result is available) for the PIC32
• Leading Zero/One detect unit for implementing core multiply and divide instructions. The approximate
the CLZ and CLO instructions latency and repeat rates are listed in terms of pipeline
• Arithmetic Logic Unit (ALU) for performing bit-wise clocks.
logical operations
• Shifter and store aligner

TABLE 3-1: MIPS32® M4K® CORE HIGH-PERFORMANCE INTEGER MULTIPLY/DIVIDE UNIT

LATENCIES AND REPEAT RATES
Opcode Operand Size (mul rt) (div rs) Latency Repeat Rate
MULT/MULTU, MADD/MADDU, 16 bits 1 1
MSUB/MSUBU 32 bits 2 2
MUL 16 bits 2 1
32 bits 3 2
DIV/DIVU 8 bits 12 11
16 bits 19 18
24 bits 26 25
32 bits 33 32

DS60001156K-page 46  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
The MIPS architecture defines that the result of a 3.2.3 SYSTEM CONTROL
multiply or divide operation be placed in the HI and LO COPROCESSOR (CP0)
registers. Using the Move-From-HI (MFHI) and Move-
In the MIPS architecture, CP0 is responsible for the
From-LO (MFLO) instructions, these values can be
virtual-to-physical address translation, the exception
transferred to the General Purpose Register file.
control system, the processor’s diagnostics capability,
In addition to the HI/LO targeted operations, the the operating modes (Kernel, User and Debug) and
MIPS32 architecture also defines a multiply instruction, whether interrupts are enabled or disabled. Configura-
MUL, which places the least significant results in the pri- tion information, such as presence of options like
mary register file instead of the HI/LO register pair. By MIPS16e, is also available by accessing the CP0
avoiding the explicit MFLO instruction required when registers, listed in Table 3-2.
using the LO register, and by supporting multiple desti-
nation registers, the throughput of multiply-intensive
operations is increased.
Two other instructions, Multiply-Add (MADD) and
Multiply-Subtract (MSUB), are used to perform the
multiply-accumulate and multiply-subtract operations.
The MADD instruction multiplies two numbers and then
adds the product to the current contents of the HI and
LO registers. Similarly, the MSUB instruction multiplies
two operands and then subtracts the product from the
HI and LO registers. The MADD and MSUB operations
are commonly used in DSP algorithms.

TABLE 3-2: COPROCESSOR 0 REGISTERS

Register Register
Function
Number Name
0-6 Reserved Reserved.
7 HWREna Enables access via the RDHWR instruction to selected hardware registers.
8 BadVAddr(1) Reports the address for the most recent address-related exception.
9 Count(1) Processor cycle count.
10 Reserved Reserved.
11 Compare(1) Timer interrupt control.
12 Status(1) Processor status and control.
12 IntCtl(1) Interrupt system status and control.
12 SRSCtl(1) Shadow register set status and control.
12 SRSMap(1) Provides mapping from vectored interrupt to a shadow set.
13 Cause(1) Cause of last general exception.
14 EPC(1) Program counter at last exception.
15 PRId Processor identification and revision.
15 Ebase Exception vector base register.
16 Config Configuration register.
16 Config1 Configuration Register 1.
16 Config2 Configuration Register 2.
16 Config3 Configuration Register 3.
17-22 Reserved Reserved.
23 Debug(2) Debug control and exception status.
24 DEPC(2) Program counter at last debug exception.
25-29 Reserved Reserved.
30 ErrorEPC(1) Program counter at last error.
31 DESAVE(2) Debug handler scratchpad register.
Note 1: Registers used in exception processing.
2: Registers used during debug.

 2009-2019 Microchip Technology Inc. DS60001156K-page 47

PIC32MX5XX/6XX/7XX
Coprocessor 0 also contains the logic for identifying
and managing exceptions. Exceptions can be caused
by a variety of sources, including alignment errors in
data, external events or program errors. Table 3-3 lists
the exception types in order of priority.

TABLE 3-3: PIC32MX5XX/6XX/7XX FAMILY CORE EXCEPTION TYPES

Exception Description

Reset Assertion MCLR or a Power-on Reset (POR).

DSS EJTAG debug single step.
DINT EJTAG debug interrupt. Caused by the assertion of the external EJ_DINT input or by setting the
EjtagBrk bit in the ECR register.
NMI Assertion of NMI signal.
Interrupt Assertion of unmasked hardware or software interrupt signal.
DIB EJTAG debug hardware instruction break matched.
AdEL Fetch address alignment error.
Fetch reference to protected address.
IBE Instruction fetch bus error.
DBp EJTAG breakpoint (execution of SDBBP instruction).
Sys Execution of SYSCALL instruction.
Bp Execution of BREAK instruction.
RI Execution of a reserved instruction.
CpU Execution of a coprocessor instruction for a coprocessor that is not enabled.
CEU Execution of a CorExtend instruction when CorExtend is not enabled.
Ov Execution of an arithmetic instruction that overflowed.
Tr Execution of a trap (when trap condition is true).
DDBL/DDBS EJTAG Data Address Break (address only) or EJTAG data value break on store (address + value).
AdEL Load address alignment error.
Load reference to protected address.
AdES Store address alignment error.
Store to protected address.
DBE Load or store bus error.
DDBL EJTAG data hardware breakpoint matched in load data compare.

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 PIC32MX5XX/6XX/7XX
3.3 Power Management 3.4 EJTAG Debug Support
The MIPS32 M4K Processor core offers a number of The MIPS32 M4K Processor core provides for an
power management features, including low-power Enhanced JTAG (EJTAG) interface for use in the
design, active power management and power-down software debug of application and kernel code. In
modes of operation. The core is a static design that addition to standard User mode and Kernel modes of
supports slowing or halting the clocks, which reduces operation, the MIPS M4K core provides a Debug mode
system power consumption during idle periods. that is entered after a debug exception (derived from a
hardware breakpoint, single-step exception, etc.) is
3.3.1 INSTRUCTION-CONTROLLED taken and continues until a Debug Exception Return
POWER MANAGEMENT (DERET) instruction is executed. During this time, the
The mechanism for invoking Power-Down mode is processor executes the debug exception handler rou-
through execution of the WAIT instruction. For more tine.
information on power management, see Section 28.0 The EJTAG interface operates through the Test Access
“Power-Saving Features”. Port (TAP), a serial communication port used for
transferring test data in and out of the MIPS32 M4K
3.3.2 LOCAL CLOCK GATING processor core. In addition to the standard JTAG
The majority of the power consumed by the PIC32MX- instructions, special instructions defined in the EJTAG
5XX/6XX/7XX family core is in the clock tree and clock- specification define which registers are selected and
ing registers. The PIC32 family uses extensive use of how they are used.
local gated clocks to reduce this dynamic power con-
sumption.

 2009-2019 Microchip Technology Inc. DS60001156K-page 49

PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 50  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
4.0 MEMORY ORGANIZATION 4.1 Memory Layout
Note: This data sheet summarizes the features PIC32MX5XX/6XX/7XX microcontrollers implement
of the PIC32MX5XX/6XX/7XX family of two address schemes: virtual and physical. All
devices. It is not intended to be a hardware resources, such as program memory, data
comprehensive reference source. For memory and peripherals, are located at their respective
detailed information, refer to Section 3. physical addresses. Virtual addresses are exclusively
“Memory Organization” (DS60001115) used by the CPU to fetch and execute instructions as
in the “PIC32 Family Reference Manual”, well as access peripherals. Physical addresses are
which is available from the Microchip used by bus master peripherals, such as DMA and the
web site (www.microchip.com/PIC32). Flash controller, that access memory independently of
the CPU.
PIC32MX5XX/6XX/7XX microcontrollers provide 4 GB The memory maps for the PIC32MX5XX/6XX/7XX
of unified virtual memory address space. All memory devices are illustrated in Figure 4-1 through Figure 4-6.
regions, including program, data memory, SFRs and Table 4-1 provides memory map information for the
Configuration registers, reside in this address space at Special Function Registers (SFRs).
their respective unique addresses. The program and
data memories can be optionally partitioned into user
and kernel memories. In addition, the data memory can
be made executable, allowing PIC32MX5XX/6XX/7XX
devices to execute from data memory.
Key features include:
• 32-bit native data width
• Separate User (KUSEG) and Kernel (KSEG0/
KSEG1) mode address space
• Flexible program Flash memory partitioning
• Flexible data RAM partitioning for data and
program space
• Separate boot Flash memory for protected code
• Robust bus exception handling to intercept
runaway code
• Simple memory mapping with Fixed Mapping
Translation (FMT) unit
• Cacheable (KSEG0) and non-cacheable (KSEG1)
address regions

 2009-2019 Microchip Technology Inc. DS60001156K-page 51

PIC32MX5XX/6XX/7XX
FIGURE 4-1: MEMORY MAP ON RESET FOR PIC32MX564F064H, PIC32MX564F064L,
PIC32MX664F064H AND PIC32MX664F064L DEVICES
Virtual Physical
Memory Map(1) Memory Map(1)
0xFFFFFFFF 0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF Device
Configuration
0xBFC02FF0 Registers
0xBFC02FEF
Boot Flash
0xBFC00000

Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1

0xBF800000

Reserved
0xBD010000
0xBD00FFFF
Program Flash(2)
0xBD000000

Reserved
0xA0008000
0xA0007FFF
RAM(2)
0xA0000000 0x1FC03000
Device 0x1FC02FFF
Reserved
0x9FC03000 Configuration
0x9FC02FFF Device Registers 0x1FC02FF0
Configuration 0x1FC02FEF
Registers
0x9FC02FF0 Boot Flash
0x9FC02FEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0

0x9D010000 0x1F800000
0x9D00FFFF
Program Flash(2) Reserved
0x9D000000 0x1D010000
0x1D00FFFF
Reserved
0x80008000 Program Flash(2)
0x80007FFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00008000
0x00007FFF
Reserved RAM(2)
0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).

DS60001156K-page 52  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 4-2: MEMORY MAP ON RESET FOR PIC32MX534F064H AND PIC32MX534F064L
DEVICES
Virtual Physical
Memory Map(1) Memory Map(1)
0xFFFFFFFF 0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF Device
Configuration
0xBFC02FF0 Registers
0xBFC02FEF
Boot Flash
0xBFC00000

Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1

0xBF800000

Reserved
0xBD010000
0xBD00FFFF
Program Flash(2)
0xBD000000

Reserved
0xA0004000
0xA0003FFF
RAM(2)
0xA0000000 0x1FC03000
Device 0x1FC02FFF
Reserved
0x9FC03000 Configuration
0x9FC02FFF Device Registers 0x1FC02FF0
Configuration 0x1FC02FEF
0x9FC02FF0 Registers Boot Flash
0x9FC02FEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0

0x9D010000 0x1F800000
0x9D00FFFF
Program Flash(2) Reserved
0x9D000000 0x1D010000
0x1D00FFFF
Reserved
0x80004000 Program Flash(2)
0x80003FFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00004000
0x00003FFF
Reserved RAM(2)
0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).

 2009-2019 Microchip Technology Inc. DS60001156K-page 53

PIC32MX5XX/6XX/7XX
FIGURE 4-3: MEMORY MAP ON RESET FOR PIC32MX564F128H, PIC32MX564F128L,
PIC32MX664F128H, PIC32MX664F128L, PIC32MX764F128H AND
PIC32MX764F128L DEVICES
Virtual Physical
Memory Map(1) Memory Map(1)
0xFFFFFFFF 0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF Device
Configuration
0xBFC02FF0 Registers
0xBFC02FEF
Boot Flash
0xBFC00000

Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1

0xBF800000

Reserved
0xBD020000
0xBD01FFFF
Program Flash(2)
0xBD000000

Reserved
0xA0008000
0xA0007FFF
RAM(2)
0xA0000000 0x1FC03000
Device 0x1FC02FFF
Reserved
0x9FC03000 Configuration
0x9FC02FFF Device Registers 0x1FC02FF0
Configuration 0x1FC02FEF
Registers
0x9FC02FF0 Boot Flash
0x9FC02FEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0

0x9D020000 0x1F800000
0x9D01FFFF
Program Flash(2) Reserved
0x9D000000 0x1D020000
0x1D01FFFF
Reserved
0x80008000 Program Flash(2)
0x80007FFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00008000
0x00007FFF
Reserved RAM(2)
0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).

DS60001156K-page 54  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 4-4: MEMORY MAP ON RESET FOR PIC32MX575F256H, PIC32MX575F256L,
PIC32MX675F256H, PIC32MX675F256L, PIC32MX775F256H AND
PIC32MX775F256L DEVICES
Virtual Physical
Memory Map(1) Memory Map(1)
0xFFFFFFFF 0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF Device
Configuration
0xBFC02FF0 Registers
0xBFC02FEF
Boot Flash
0xBFC00000

Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1

0xBF800000

Reserved
0xBD040000
0xBD03FFFF
Program Flash(2)
0xBD000000

Reserved
0xA0010000
0xA000FFFF
RAM(2)
0xA0000000 0x1FC03000
Device 0x1FC02FFF
Reserved
0x9FC03000 Configuration
0x9FC02FFF Device Registers 0x1FC02FF0
Configuration 0x1FC02FEF
0x9FC02FF0 Registers Boot Flash
0x9FC02FEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0

0x9D040000 0x1F800000
0x9D03FFFF
Program Flash(2) Reserved
0x9D000000 0x1D040000
0x1D03FFFF
Reserved
0x80008000 Program Flash(2)
0x8000FFFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00010000
0x0000FFFF
Reserved RAM(2)
0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).

 2009-2019 Microchip Technology Inc. DS60001156K-page 55

PIC32MX5XX/6XX/7XX
FIGURE 4-5: MEMORY MAP ON RESET FOR PIC32MX575F512H, PIC32MX575F512L,
PIC32MX675F512H, PIC32MX675F512L, PIC32MX775F512H AND
PIC32MX775F512L DEVICES
Virtual Physical
Memory Map(1) Memory Map(1)
0xFFFFFFFF 0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF Device
Configuration
0xBFC02FF0 Registers
0xBFC02FEF
Boot Flash
0xBFC00000

Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1

0xBF800000

Reserved
0xBD080000
0xBD07FFFF
Program Flash(2)
0xBD000000

Reserved
0xA0010000
0xA000FFFF
RAM(2)
0xA0000000 0x1FC03000
Device 0x1FC02FFF
Reserved
0x9FC03000 Configuration
0x9FC02FFF Device Registers 0x1FC02FF0
Configuration 0x1FC02FEF
0x9FC02FF0 Registers Boot Flash
0x9FC02FEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0

0x9D080000 0x1F800000
0x9D07FFFF
Program Flash(2) Reserved
0x9D000000 0x1D080000
0x1D07FFFF
Reserved
0x80010000 Program Flash(2)
0x8000FFFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00010000
0x0000FFFF
Reserved RAM(2)
0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).

DS60001156K-page 56  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 4-6: MEMORY MAP ON RESET FOR PIC32MX695F512H, PIC32MX695F512L,
PIC32MX795F512H AND PIC32MX795F512L DEVICES

Virtual Physical
Memory Map(1) Memory Map(1)
0xFFFFFFFF 0xFFFFFFFF
Reserved
0xBFC03000
0xBFC02FFF Device
Configuration
0xBFC02FF0 Registers
0xBFC02FEF
Boot Flash
0xBFC00000

Reserved
0xBF900000
0xBF8FFFFF
SFRs Reserved
KSEG1

0xBF800000

Reserved
0xBD080000
0xBD07FFFF
Program Flash(2)
0xBD000000

Reserved
0xA0020000
0xA001FFFF
RAM(2)
0xA0000000 0x1FC03000
Device 0x1FC02FFF
Reserved
0x9FC03000 Configuration
0x9FC02FFF Device Registers 0x1FC02FF0
Configuration 0x1FC02FEF
Registers
0x9FC02FF0 Boot Flash
0x9FC02FEF 0x1FC00000
Boot Flash
Reserved
0x9FC00000 0x1F900000
0x1F8FFFFF
Reserved SFRs
KSEG0

0x9D080000 0x1F800000
0x9D07FFFF
Program Flash(2) Reserved
0x9D000000 0x1D080000
0x1D07FFFF
Reserved
0x80020000 Program Flash(2)
0x8001FFFF 0x1D000000
RAM(2)
Reserved
0x80000000 0x00020000
0x0001FFFF
Reserved RAM(2)
0x00000000 0x00000000

Note 1: Memory areas are not shown to scale.

2: The size of this memory region is programmable (see Section 3. “Memory Organization”
(DS60001115)) and can be changed by initialization code provided by end user
development tools (refer to the specific development tool documentation for information).

 2009-2019 Microchip Technology Inc. DS60001156K-page 57

PIC32MX5XX/6XX/7XX
TABLE 4-1: SFR MEMORY MAP
Virtual Address
Peripheral Offset
Base
Start
Watchdog Timer 0x0000
RTCC 0x0200
Timer1-Timer5 0x0600
Input Capture 1-5 0x2000
Output Compare 1-5 0x3000
I2C1-I2C5 0x5000
SPI1-SPI4 0x5800
UART1-UART6 0x6000
0xBF80
PMP 0x7000
ADC 0x9000
CVREF 0x9800
Comparator 0xA000
Oscillator 0xF000
Device and Revision ID 0xF200
Flash Controller 0xF400
Reset 0xF600
Interrupts 0x1000
Bus Matrix 0x2000
DMA 0x3000
Prefetch 0xBF88 0x4000
USB 0x5040
PORTA-PORTG 0x6000
Ethernet 0x9000
Configuration 0xBFC0 0x2FF0

DS60001156K-page 58  2009-2019 Microchip Technology Inc.

 4.2 Control Registers
 2009-2019 Microchip Technology Inc.

Register 4-1 through Register 4-8 are used for setting the RAM and Flash memory partitions for data and code.

TABLE 4-2: BUS MATRIX REGISTER MAP

Virtual Address

Bits

Bit Range
(BF88_#)

Register

Resets
Name

All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — BMXCHEDMA — — — — — BMXERRIXI BMXERRICD BMXERRDMA BMXERRDS BMXERRIS 001F

2000 BMXCON(1)
15:0 — — — — — — — — — BMXWSDRM — — — BMXARB<2:0> 0041
31:16 — — — — — — — — — — — — — — — — 0000
2010 BMXDKPBA(1)
15:0 BMXDKPBA<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
2020 BMXDUDBA(1)
15:0 BMXDUDBA<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
2030 BMXDUPBA(1)
15:0 BMXDUPBA<15:0> 0000
31:16 xxxx
2040 BMXDRMSZ BMXDRMSZ<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — BMXPUPBA<19:16> 0000
2050 BMXPUPBA(1)
15:0 BMXPUPBA<15:0> 0000
31:16 xxxx
2060 BMXPFMSZ BMXPFMSZ<31:0>

PIC32MX5XX/6XX/7XX
15:0 xxxx
31:16 0000
2070 BMXBOOTSZ BMXBOOTSZ<31:0>
15:0 3000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DS60001156K-page 59
PIC32MX5XX/6XX/7XX
REGISTER 4-1: BMXCON: BUS MATRIX CONFIGURATION REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
23:16 BMX BMX BMX BMX BMX
— — —
ERRIXI ERRICD ERRDMA ERRDS ERRIS
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 R/W-1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1
7:0 BMX
— — — — BMXARB<2:0>
WSDRM

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared

bit 31-21 Unimplemented: Read as ‘0’

bit 20 BMXERRIXI: Enable Bus Error from IXI bit
1 = Enable bus error exceptions for unmapped address accesses initiated from IXI shared bus
0 = Disable bus error exceptions for unmapped address accesses initiated from IXI shared bus
bit 19 BMXERRICD: Enable Bus Error from ICD Debug Unit bit
1 = Enable bus error exceptions for unmapped address accesses initiated from ICD
0 = Disable bus error exceptions for unmapped address accesses initiated from ICD
bit 18 BMXERRDMA: Bus Error from DMA bit
1 = Enable bus error exceptions for unmapped address accesses initiated from DMA
0 = Disable bus error exceptions for unmapped address accesses initiated from DMA
bit 17 BMXERRDS: Bus Error from CPU Data Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU data access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU data access
bit 16 BMXERRIS: Bus Error from CPU Instruction Access bit (disabled in Debug mode)
1 = Enable bus error exceptions for unmapped address accesses initiated from CPU instruction access
0 = Disable bus error exceptions for unmapped address accesses initiated from CPU instruction access
bit 15-7 Unimplemented: Read as ‘0’
bit 6 BMXWSDRM: CPU Instruction or Data Access from Data RAM Wait State bit
1 = Data RAM accesses from CPU have one wait state for address setup
0 = Data RAM accesses from CPU have zero wait states for address setup
bit 5-3 Unimplemented: Read as ‘0’
bit 2-0 BMXARB<2:0>: Bus Matrix Arbitration Mode bits
111 = Reserved (using these Configuration modes will produce undefined behavior)
•
•
•
011 = Reserved (using these Configuration modes will produce undefined behavior)
010 = Arbitration Mode 2
001 = Arbitration Mode 1 (default)
000 = Arbitration Mode 0

DS60001156K-page 60  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 4-2: BMXDKPBA: DATA RAM KERNEL PROGRAM BASE ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
15:8
BMXDKPBA<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
BMXDKPBA<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-10 BMXDKPBA<15:10>: DRM Kernel Program Base Address bits
When non-zero, this value selects the relative base address for kernel program space in RAM
bit 9-0 BMXDKPBA<9:0>: DRM Kernel Program Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.

 2009-2019 Microchip Technology Inc. DS60001156K-page 61

PIC32MX5XX/6XX/7XX
REGISTER 4-3: BMXDUDBA: DATA RAM USER DATA BASE ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
15:8
BMXDUDBA<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
BMXDUDBA<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-10 BMXDUDBA<15:10>: DRM User Data Base Address bits
When non-zero, the value selects the relative base address for User mode data space in RAM, the value
must be greater than BMXDKPBA.
bit 9-0 BMXDUDBA<9:0>: DRM User Data Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.

DS60001156K-page 62  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 4-4: BMXDUPBA: DATA RAM USER PROGRAM BASE ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0
15:8
BMXDUPBA<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
BMXDUPBA<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-10 BMXDUPBA<15:10>: DRM User Program Base Address bits
When non-zero, the value selects the relative base address for User mode program space in RAM,
BMXDUPBA must be greater than BMXDUDBA.
bit 9-0 BMXDUPBA<9:0>: DRM User Program Base Address Read-Only bits
Value is always ‘0’, which forces 1 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXDRMSZ.

 2009-2019 Microchip Technology Inc. DS60001156K-page 63

PIC32MX5XX/6XX/7XX
REGISTER 4-5: BMXDRMSZ: DATA RAM SIZE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R R R R R R R R
31:24
BMXDRMSZ<31:24>
R R R R R R R R
23:16
BMXDRMSZ<23:16>
R R R R R R R R
15:8
BMXDRMSZ<15:8>
R R R R R R R R
7:0
BMXDRMSZ<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXDRMSZ<31:0>: Data RAM Memory (DRM) Size bits

Static value that indicates the size of the Data RAM in bytes:
0x00004000 = device has 16 KB RAM
0x00008000 = device has 32 KB RAM
0x00010000 = device has 64 KB RAM

REGISTER 4-6: BMXPUPBA: PROGRAM FLASH (PFM) USER PROGRAM BASE ADDRESS
REGISTER(1,2)
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
— — — — BMXPUPBA<19:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 R-0
15:8
BMXPUPBA<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
BMXPUPBA<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-20 Unimplemented: Read as ‘0’

bit 19-11 BMXPUPBA<19:11>: Program Flash (PFM) User Program Base Address bits
bit 10-0 BMXPUPBA<10:0>: Program Flash (PFM) User Program Base Address Read-Only bits
Value is always ‘0’, which forces 2 KB increments

Note 1: At Reset, the value in this register is forced to zero, which causes all of the RAM to be allocated to Kernal
mode data usage.
2: The value in this register must be less than or equal to BMXPFMSZ.

DS60001156K-page 64  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 4-7: BMXPFMSZ: PROGRAM FLASH (PFM) SIZE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R R R R R R R R
31:24
BMXPFMSZ<31:24>
R R R R R R R R
23:16
BMXPFMSZ<23:16>
R R R R R R R R
15:8
BMXPFMSZ<15:8>
R R R R R R R R
7:0
BMXPFMSZ<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXPFMSZ<31:0>: Program Flash Memory (PFM) Size bits

Static value that indicates the size of the PFM in bytes:
0x00010000 = device has 64 KB Flash
0x00020000 = device has 128 KB Flash
0x00040000 = device has 256 KB Flash
0x00080000 = device has 512 KB Flash

REGISTER 4-8: BMXBOOTSZ: BOOT FLASH (IFM) SIZE REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R R R R R R R R
31:24
BMXBOOTSZ<31:24>
R R R R R R R R
23:16
BMXBOOTSZ<23:16>
R R R R R R R R
15:8
BMXBOOTSZ<15:8>
R R R R R R R R
7:0
BMXBOOTSZ<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 BMXBOOTSZ<31:0>: Boot Flash Memory (BFM) Size bits

Static value that indicates the size of the Boot PFM in bytes:
0x00003000 = device has 12 KB boot Flash

 2009-2019 Microchip Technology Inc. DS60001156K-page 65

PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 66  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
5.0 FLASH PROGRAM MEMORY PIC32MX5XX/6XX/7XX devices contain an internal
Flash program memory for executing user code. There
Note: This data sheet summarizes the features are three methods by which the user can program this
of the PIC32MX5XX/6XX/7XX family of memory:
devices. It is not intended to be a • Run-Time Self-Programming (RTSP)
comprehensive reference source. To
• EJTAG Programming
complement the information in this data
sheet, refer to Section 5. “Flash • In-Circuit Serial Programming™ (ICSP™)
Program Memory” (DS60001121) in the RTSP is performed by software executing from either
“PIC32 Family Reference Manual”, which Flash or RAM memory. Information about RTSP
is available from the Microchip web site techniques is available in Section 5. “Flash Program
(www.microchip.com/PIC32). Memory” (DS60001121) in the “PIC32 Family
Reference Manual”.
EJTAG is performed using the EJTAG port of the
device and an EJTAG capable programmer.
ICSP is performed using a serial data connection to the
device and allows much faster programming times than
RTSP.
The EJTAG and ICSP methods are described in the
“PIC32 Flash Programming Specification”
(DS60001145), which can be downloaded from the
Microchip web site.
Note: For PIC32MX5XX/6XX/7XX devices, the
Flash page size is 4 KB and the row size
is 512 bytes (1024 IW and 128 IW,
respectively).

 2009-2019 Microchip Technology Inc. DS60001156K-page 67

DS60001156K-page 68
5.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 5-1: FLASH CONTROLLER REGISTER MAP
Virtual Address Bits

All Resets
Bit Range
(BF80_#)

Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
F400 NVMCON(1)
15:0 WR WREN WRERR LVDERR LVDSTAT — — — — — — — NVMOP<3:0> 0000
31:16 0000
F410 NVMKEY NVMKEY<31:0>
15:0 0000
(1) 31:16 0000
F420 NVMADDR NVMADDR<31:0>
15:0 0000
31:16 0000
F430 NVMDATA NVMDATA<31:0>
15:0 0000
NVMSRC 31:16 0000
F440 NVMSRCADDR<31:0>
ADDR 15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 5-1: NVMCON: PROGRAMMING CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0, HC R/W-0 R-0, HS R-0, HS R-0, HSC U-0 U-0 U-0
15:8
WR WREN WRERR(1) LVDERR(1) LVDSTAT (1)
— — —
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — — NVMOP<3:0>

Legend: U = Unimplemented bit, read as ‘0’ HSC = Set and Cleared by hardware
R = Readable bit W = Writable bit HS = Set by hardware HC = Cleared by hardware
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 WR: Write Control bit
This bit is writable when WREN = 1 and the unlock sequence is followed.
1 = Initiate a Flash operation. Hardware clears this bit when the operation completes
0 = Flash operation complete or inactive
bit 14 WREN: Write Enable bit
1 = Enable writes to WR bit and enables LVD circuit
0 = Disable writes to WR bit and disables LVD circuit
Note: This is the only bit in this register that is reset by a device Reset.
bit 13 WRERR: Write Error bit(1)
This bit is read-only and is automatically set by hardware.
1 = Program or erase sequence did not complete successfully
0 = Program or erase sequence completed normally
bit 12 LVDERR: Low-Voltage Detect Error bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set by hardware.
1 = Low-voltage detected (possible data corruption, if WRERR is set)
0 = Voltage level is acceptable for programming
bit 11 LVDSTAT: Low-Voltage Detect Status bit (LVD circuit must be enabled)(1)
This bit is read-only and is automatically set, and cleared, by hardware.
1 = Low-voltage event is active
0 = Low-voltage event is not active
bit 10-4 Unimplemented: Read as ‘0’
bit 3-0 NVMOP<3:0>: NVM Operation bits
These bits are writable when WREN = 0.
1111 = Reserved
•
•
•
0111 = Reserved
0110 = No operation
0101 = Program Flash (PFM) erase operation: erases PFM if all pages are not write-protected
0100 = Page erase operation: erases page selected by NVMADDR if it is not write-protected
0011 = Row program operation: programs row selected by NVMADDR if it is not write-protected
0010 = No operation
0001 = Word program operation: programs word selected by NVMADDR if it is not write-protected
0000 = No operation

Note 1: This bit is cleared by setting NVMOP == 0000b, and initiating a Flash operation (i.e., WR).

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PIC32MX5XX/6XX/7XX
REGISTER 5-2: NVMKEY: PROGRAMMING UNLOCK REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
31:24
NVMKEY<31:24>
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
23:16
NVMKEY<23:16>
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
15:8
NVMKEY<15:8>
W-0 W-0 W-0 W-0 W-0 W-0 W-0 W-0
7:0
NVMKEY<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMKEY<31:0>: Unlock Register bits

These bits are write-only, and read as ‘0’ on any read.

Note: This register is used as part of the unlock sequence to prevent inadvertent writes to the PFM.

REGISTER 5-3: NVMADDR: FLASH ADDRESS REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
NVMADDR<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
NVMADDR<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
NVMADDR<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
NVMADDR<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMADDR<31:0>: Flash Address bits

Bulk/Chip/PFM Erase: Address is ignored.
Page Erase: Address identifies the page to erase.
Row Program: Address identifies the row to program.
Word Program: Address identifies the word to program.

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 PIC32MX5XX/6XX/7XX
REGISTER 5-4: NVMDATA: FLASH PROGRAM DATA REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
NVMDATA<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
NVMDATA<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
NVMDATA<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
NVMDATA<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMDATA<31:0>: Flash Programming Data bits

Note: The bits in this register are only reset by a Power-on Reset (POR).

REGISTER 5-5: NVMSRCADDR: SOURCE DATA ADDRESS REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
NVMSRCADDR<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
NVMSRCADDR<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
NVMSRCADDR<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
NVMSRCADDR<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 NVMSRCADDR<31:0>: Source Data Address bits

The system physical address of the data to be programmed into the Flash when the NVMOP<3:0> bits
(NVMCON<3:0>) are set to perform row programming.

 2009-2019 Microchip Technology Inc. DS60001156K-page 71

PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 72  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
6.0 RESETS • Power-on Reset (POR)
• Master Clear Reset pin (MCLR)
Note: This data sheet summarizes the features • Software Reset (SWR)
of the PIC32MX5XX/6XX/7XX family of
• Watchdog Timer Reset (WDTR)
devices. It is not intended to be a
comprehensive reference source. To • Brown-out Reset (BOR)
complement the information in this data • Configuration Mismatch Reset (CMR)
sheet, refer to Section 7. “Resets” A simplified block diagram of the Reset module is
(DS60001118) in the “PIC32 Family Ref- illustrated in Figure 6-1.
erence Manual”, which is available from
the Microchip web site
(www.microchip.com/PIC32).

The Reset module combines all Reset sources and

controls the device Master Reset signal, SYSRST. The
following is a list of device Reset sources:

FIGURE 6-1: SYSTEM RESET BLOCK DIAGRAM

MCLR
MCLR
Glitch Filter

Sleep or Idle WDTR

Voltage WDT
Time-out
Regulator
Enabled
Power-up POR
Timer SYSRST
VDD
VDD Rise
Detect

Brown-out BOR
Reset
Configuration
Mismatch
Reset CMR
SWR
Software Reset

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DS60001156K-page 74
6.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 6-1:
Virtual Address
RESETS REGISTER MAP
Bits

All Resets(2)
Bit Range
(BF80_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
F600 RCON
15:0 — — — — — — CMR VREGS EXTR SWR — WDTO SLEEP IDLE BOR POR 0000
31:16 — — — — — — — — — — — — — — — — 0000
F610 RSWRST
15:0 — — — — — — — — — — — — — — — SWRST 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 6-1: RCON: RESET CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0, HS R/W-0
15:8
— — — — — — CMR VREGS
R/W-0, HS R/W-0, HS U-0 R/W-0, HS R/W-0, HS R/W-0, HS R/W-1, HS R/W-1, HS
7:0 (1) (1)
EXTR SWR — WDTO SLEEP IDLE BOR POR

Legend: HS = Set by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-10 Unimplemented: Read as ‘0’

bit 9 CMR: Configuration Mismatch Reset Flag bit
1 = Configuration mismatch Reset has occurred
0 = Configuration mismatch Reset has not occurred
bit 8 VREGS: Voltage Regulator Standby Enable bit
1 = Regulator is enabled and is on during Sleep mode
0 = Regulator is set to Stand-by Tracking mode
bit 7 EXTR: External Reset (MCLR) Pin Flag bit
1 = Master Clear (pin) Reset has occurred
0 = Master Clear (pin) Reset has not occurred
bit 6 SWR: Software Reset Flag bit
1 = Software Reset was executed
0 = Software Reset was not executed
bit 5 Unimplemented: Read as ‘0’
bit 4 WDTO: Watchdog Timer Time-out Flag bit
1 = WDT Time-out has occurred
0 = WDT Time-out has not occurred
bit 3 SLEEP: Wake From Sleep Flag bit
1 = Device was in Sleep mode
0 = Device was not in Sleep mode
bit 2 IDLE: Wake From Idle Flag bit
1 = Device was in Idle mode
0 = Device was not in Idle mode
bit 1 BOR: Brown-out Reset Flag bit(1)
1 = Brown-out Reset has occurred
0 = Brown-out Reset has not occurred
bit 0 POR: Power-on Reset Flag bit(1)
1 = Power-on Reset has occurred
0 = Power-on Reset has not occurred

Note 1: User software must clear this bit to view the next detection.

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PIC32MX5XX/6XX/7XX
REGISTER 6-2: RSWRST: SOFTWARE RESET REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 W-0, HC
7:0
— — — — — — — SWRST(1)

Legend: HC = Cleared by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-1 Unimplemented: Read as ‘0’

bit 0 SWRST: Software Reset Trigger bit(1)
1 = Enable software Reset event
0 = No effect

Note 1: The system unlock sequence must be performed before the SWRST bit can be written. Refer to Section
6. “Oscillator” (DS60001112) in the “PIC32 Family Reference Manual” for details.

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 PIC32MX5XX/6XX/7XX
7.0 INTERRUPT CONTROLLER The Interrupt Controller module includes the following
features:
Note: This data sheet summarizes the features • Up to 96 interrupt sources
of the PIC32MX5XX/6XX/7XX family of
• Up to 64 interrupt vectors
devices. It is not intended to be a
comprehensive reference source. To • Single and multi-vector mode operations
complement the information in this data • Five external interrupts with edge polarity control
sheet, refer to Section 8. “Interrupts” • Interrupt proximity timer
(DS60001108) in the “PIC32 Family Ref- • Seven user-selectable priority levels for each vector
erence Manual”, which is available from
• Four user-selectable sub-priority levels within each
the Microchip web site
priority
(www.microchip.com/PIC32).
• Dedicated shadow set for user-selectable priority
PIC32MX5XX/6XX/7XX devices generate interrupt level
requests in response to interrupt events from peripheral • Software can generate any interrupt
modules. The interrupt control module exists externally • User-configurable interrupt vector table location
to the CPU logic and prioritizes the interrupt events
• User-configurable interrupt vector spacing
before presenting them to the CPU.
A simplified block diagram of the Interrupt Controller
module is illustrated in Figure 7-1.

FIGURE 7-1: INTERRUPT CONTROLLER MODULE

Vector Number

Interrupt Requests
Interrupt Controller CPU Core
Priority Level

Shadow Set Number

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PIC32MX5XX/6XX/7XX
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION
IRQ Vector Interrupt Bit Location
Interrupt Source(1)
Number Number Flag Enable Priority Sub-Priority
Highest Natural Order Priority
CT – Core Timer Interrupt 0 0 IFS0<0> IEC0<0> IPC0<4:2> IPC0<1:0>
CS0 – Core Software Interrupt 0 1 1 IFS0<1> IEC0<1> IPC0<12:10> IPC0<9:8>
CS1 – Core Software Interrupt 1 2 2 IFS0<2> IEC0<2> IPC0<20:18> IPC0<17:16>
INT0 – External Interrupt 0 3 3 IFS0<3> IEC0<3> IPC0<28:26> IPC0<25:24>
T1 – Timer1 4 4 IFS0<4> IEC0<4> IPC1<4:2> IPC1<1:0>
IC1 – Input Capture 1 5 5 IFS0<5> IEC0<5> IPC1<12:10> IPC1<9:8>
OC1 – Output Compare 1 6 6 IFS0<6> IEC0<6> IPC1<20:18> IPC1<17:16>
INT1 – External Interrupt 1 7 7 IFS0<7> IEC0<7> IPC1<28:26> IPC1<25:24>
T2 – Timer2 8 8 IFS0<8> IEC0<8> IPC2<4:2> IPC2<1:0>
IC2 – Input Capture 2 9 9 IFS0<9> IEC0<9> IPC2<12:10> IPC2<9:8>
OC2 – Output Compare 2 10 10 IFS0<10> IEC0<10> IPC2<20:18> IPC2<17:16>
INT2 – External Interrupt 2 11 11 IFS0<11> IEC0<11> IPC2<28:26> IPC2<25:24>
T3 – Timer3 12 12 IFS0<12> IEC0<12> IPC3<4:2> IPC3<1:0>
IC3 – Input Capture 3 13 13 IFS0<13> IEC0<13> IPC3<12:10> IPC3<9:8>
OC3 – Output Compare 3 14 14 IFS0<14> IEC0<14> IPC3<20:18> IPC3<17:16>
INT3 – External Interrupt 3 15 15 IFS0<15> IEC0<15> IPC3<28:26> IPC3<25:24>
T4 – Timer4 16 16 IFS0<16> IEC0<16> IPC4<4:2> IPC4<1:0>
IC4 – Input Capture 4 17 17 IFS0<17> IEC0<17> IPC4<12:10> IPC4<9:8>
OC4 – Output Compare 4 18 18 IFS0<18> IEC0<18> IPC4<20:18> IPC4<17:16>
INT4 – External Interrupt 4 19 19 IFS0<19> IEC0<19> IPC4<28:26> IPC4<25:24>
T5 – Timer5 20 20 IFS0<20> IEC0<20> IPC5<4:2> IPC5<1:0>
IC5 – Input Capture 5 21 21 IFS0<21> IEC0<21> IPC5<12:10> IPC5<9:8>
OC5 – Output Compare 5 22 22 IFS0<22> IEC0<22> IPC5<20:18> IPC5<17:16>
SPI1E – SPI1 Fault 23 23 IFS0<23> IEC0<23> IPC5<28:26> IPC5<25:24>
SPI1RX – SPI1 Receive Done 24 23 IFS0<24> IEC0<24> IPC5<28:26> IPC5<25:24>
SPI1TX – SPI1 Transfer Done 25 23 IFS0<25> IEC0<25> IPC5<28:26> IPC5<25:24>
U1E – UART1 Error
SPI3E – SPI3 Fault 26 24 IFS0<26> IEC0<26> IPC6<4:2> IPC6<1:0>
I2C3B – I2C3 Bus Collision Event
U1RX – UART1 Receiver
SPI3RX – SPI3 Receive Done 27 24 IFS0<27> IEC0<27> IPC6<4:2> IPC6<1:0>
I2C3S – I2C3 Slave Event
U1TX – UART1 Transmitter
SPI3TX – SPI3 Transfer Done 28 24 IFS0<28> IEC0<28> IPC6<4:2> IPC6<1:0>
I2C3M – I2C3 Master Event
I2C1B – I2C1 Bus Collision Event 29 25 IFS0<29> IEC0<29> IPC6<12:10> IPC6<9:8>
I2C1S – I2C1 Slave Event 30 25 IFS0<30> IEC0<30> IPC6<12:10> IPC6<9:8>
I2C1M – I2C1 Master Event 31 25 IFS0<31> IEC0<31> IPC6<12:10> IPC6<9:8>
CN – Input Change Interrupt 32 26 IFS1<0> IEC1<0> IPC6<20:18> IPC6<17:16>
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX5XX USB and CAN
Features”, TABLE 2: “PIC32MX6XX USB and Ethernet Features” and TABLE 3: “PIC32MX7XX USB,
Ethernet, and CAN Features” for the list of available peripherals.

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 PIC32MX5XX/6XX/7XX
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
IRQ Vector Interrupt Bit Location
Interrupt Source(1)
Number Number Flag Enable Priority Sub-Priority
AD1 – ADC1 Convert Done 33 27 IFS1<1> IEC1<1> IPC6<28:26> IPC6<25:24>
PMP – Parallel Master Port 34 28 IFS1<2> IEC1<2> IPC7<4:2> IPC7<1:0>
CMP1 – Comparator Interrupt 35 29 IFS1<3> IEC1<3> IPC7<12:10> IPC7<9:8>
CMP2 – Comparator Interrupt 36 30 IFS1<4> IEC1<4> IPC7<20:18> IPC7<17:16>
U2E – UART2 Error
SPI2E – SPI2 Fault 37 31 IFS1<5> IEC1<5> IPC7<28:26> IPC7<25:24>
I2C4B – I2C4 Bus Collision Event
U2RX – UART2 Receiver
SPI2RX – SPI2 Receive Done 38 31 IFS1<6> IEC1<6> IPC7<28:26> IPC7<25:24>
I2C4S – I2C4 Slave Event
U2TX – UART2 Transmitter
SPI2TX – SPI2 Transfer Done 39 31 IFS1<7> IEC1<7> IPC7<28:26> IPC7<25:24>
IC4M – I2C4 Master Event
U3E – UART3 Error
SPI4E – SPI4 Fault 40 32 IFS1<8> IEC1<8> IPC8<4:2> IPC8<1:0>
I2C5B – I2C5 Bus Collision Event
U3RX – UART3 Receiver
SPI4RX – SPI4 Receive Done 41 32 IFS1<9> IEC1<9> IPC8<4:2> IPC8<1:0>
I2C5S – I2C5 Slave Event
U3TX – UART3 Transmitter
SPI4TX – SPI4 Transfer Done 42 32 IFS1<10> IEC1<10> IPC8<4:2> IPC8<1:0>
IC5M – I2C5 Master Event
I2C2B – I2C2 Bus Collision Event 43 33 IFS1<11> IEC1<11> IPC8<12:10> IPC8<9:8>
I2C2S – I2C2 Slave Event 44 33 IFS1<12> IEC1<12> IPC8<12:10> IPC8<9:8>
I2C2M – I2C2 Master Event 45 33 IFS1<13> IEC1<13> IPC8<12:10> IPC8<9:8>
FSCM – Fail-Safe Clock Monitor 46 34 IFS1<14> IEC1<14> IPC8<20:18> IPC8<17:16>
RTCC – Real-Time Clock and
47 35 IFS1<15> IEC1<15> IPC8<28:26> IPC8<25:24>
Calendar
DMA0 – DMA Channel 0 48 36 IFS1<16> IEC1<16> IPC9<4:2> IPC9<1:0>
DMA1 – DMA Channel 1 49 37 IFS1<17> IEC1<17> IPC9<12:10> IPC9<9:8>
DMA2 – DMA Channel 2 50 38 IFS1<18> IEC1<18> IPC9<20:18> IPC9<17:16>
DMA3 – DMA Channel 3 51 39 IFS1<19> IEC1<19> IPC9<28:26> IPC9<25:24>
DMA4 – DMA Channel 4 52 40 IFS1<20> IEC1<20> IPC10<4:2> IPC10<1:0>
DMA5 – DMA Channel 5 53 41 IFS1<21> IEC1<21> IPC10<12:10> IPC10<9:8>
DMA6 – DMA Channel 6 54 42 IFS1<22> IEC1<22> IPC10<20:18> IPC10<17:16>
DMA7 – DMA Channel 7 55 43 IFS1<23> IEC1<23> IPC10<28:26> IPC10<25:24>
FCE – Flash Control Event 56 44 IFS1<24> IEC1<24> IPC11<4:2> IPC11<1:0>
USB – USB Interrupt 57 45 IFS1<25> IEC1<25> IPC11<12:10> IPC11<9:8>
CAN1 – Control Area Network 1 58 46 IFS1<26> IEC1<26> IPC11<20:18> IPC11<17:16>
CAN2 – Control Area Network 2 59 47 IFS1<27> IEC1<27> IPC11<28:26> IPC11<25:24>
ETH – Ethernet Interrupt 60 48 IFS1<28> IEC1<28> IPC12<4:2> IPC12<1:0>
IC1E – Input Capture 1 Error 61 5 IFS1<29> IEC1<29> IPC1<12:10> IPC1<9:8>
IC2E – Input Capture 2 Error 62 9 IFS1<30> IEC1<30> IPC2<12:10> IPC2<9:8>
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX5XX USB and CAN
Features”, TABLE 2: “PIC32MX6XX USB and Ethernet Features” and TABLE 3: “PIC32MX7XX USB,
Ethernet, and CAN Features” for the list of available peripherals.

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PIC32MX5XX/6XX/7XX
TABLE 7-1: INTERRUPT IRQ, VECTOR AND BIT LOCATION (CONTINUED)
IRQ Vector Interrupt Bit Location
Interrupt Source(1)
Number Number Flag Enable Priority Sub-Priority
IC3E – Input Capture 3 Error 63 13 IFS1<31> IEC1<31> IPC3<12:10> IPC3<9:8>
IC4E – Input Capture 4 Error 64 17 IFS2<0> IEC2<0> IPC4<12:10> IPC4<9:8>
IC5E – Input Capture 5 Error 65 21 IFS2<1> IEC2<1> IPC5<12:10> IPC5<9:8>
PMPE – Parallel Master Port Error 66 28 IFS2<2> IEC2<2> IPC7<4:2> IPC7<1:0>
U4E – UART4 Error 67 49 IFS2<3> IEC2<3> IPC12<12:10> IPC12<9:8>
U4RX – UART4 Receiver 68 49 IFS2<4> IEC2<4> IPC12<12:10> IPC12<9:8>
U4TX – UART4 Transmitter 69 49 IFS2<5> IEC2<5> IPC12<12:10> IPC12<9:8>
U6E – UART6 Error 70 50 IFS2<6> IEC2<6> IPC12<20:18> IPC12<17:16>
U6RX – UART6 Receiver 71 50 IFS2<7> IEC2<7> IPC12<20:18> IPC12<17:16>
U6TX – UART6 Transmitter 72 50 IFS2<8> IEC2<8> IPC12<20:18> IPC12<17:16>
U5E – UART5 Error 73 51 IFS2<9> IEC2<9> IPC12<28:26> IPC12<25:24>
U5RX – UART5 Receiver 74 51 IFS2<10> IEC2<10> IPC12<28:26> IPC12<25:24>
U5TX – UART5 Transmitter 75 51 IFS2<11> IEC2<11> IPC12<28:26> IPC12<25:24>
(Reserved) — — — — — —
Lowest Natural Order Priority
Note 1: Not all interrupt sources are available on all devices. See TABLE 1: “PIC32MX5XX USB and CAN
Features”, TABLE 2: “PIC32MX6XX USB and Ethernet Features” and TABLE 3: “PIC32MX7XX USB,
Ethernet, and CAN Features” for the list of available peripherals.

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 7.1 Control Registers
 2009-2019 Microchip Technology Inc.

TABLE 7-2: INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND
PIC32MX575F512H DEVICES
Bits
Virtual Address

Bit Range
(BF88_#)

Register
Name(1)

Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT(3)
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
31:16 0000
1020 IPTMR IPTMR<31:0>
15:0 0000
U1TXIF U1RXIF U1EIF
31:16 I2C1MIF I2C1SIF I2C1BIF SPI3TXIF SPI3RXIF SPI3EIF — — — OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000
1030 IFS0
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
31:16 IC3EIF IC2EIF IC1EIF — — CAN1IF USBIF FCEIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000
U3TXIF U3RXIF U3EIF U2TXIF U2RXIF U2EIF
1040 IFS1
15:0 RTCCIF FSCMIF — — — SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF

PIC32MX5XX/6XX/7XX
0000
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
15:0 — — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000
U1TXIE U1RXIE U1EIE
31:16 I2C1MIE I2C1SIE I2C1BIE SPI3TXIE SPI3RXIE SPI3EIE — — — OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000
1060 IEC0
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
31:16 IC3EIE IC2EIE IC1EIE — — CAN1IE USBIE FCEIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000
U3TXIE U3RXIE U3EIE U2TXIE U2RXIE U2EIE
1070 IEC1
15:0 RTCCIE FSCMIE — — — SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
15:0 — — — — U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
DS60001156K-page 81

31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000

1090 IPC0
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET
and INV Registers” for more information.
2: These bits are not available on PIC32MX534/564/664/764 devices.
3: This register does not have associated CLR, SET, and INV registers.
DS60001156K-page 82
TABLE 7-2: INTERRUPT REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H AND

PIC32MX5XX/6XX/7XX
PIC32MX575F512H DEVICES (CONTINUED)
Bits
Virtual Address

Bit Range
(BF88_#)

Register
Name(1)

Resets
All
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000

10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000
10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000
10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
10F0 IPC6
15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — SPI3IP<2:0> SPI3IS<1:0> 0000
I2C3IP<2:0> I2C3IS<1:0>
U2IP<2:0> U2IS<1:0>
31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000
1100 IPC7
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
U3IP<2:0> U3IS<1:0>
1110 IPC8
15:0 — — — — — — — — — — — SPI4IP<2:0> SPI4IS<1:0> 0000
I2C5IP<2:0> I2C5IS<1:0>
31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
 2009-2019 Microchip Technology Inc.

1120 IPC9
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
31:16 — — — DMA7IP<2:0>(2) DMA7IS<1:0>(2) — — — DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
1130 IPC10
15:0 — — — DMA5IP<2:0>(2) DMA5IS<1:0>(2) — — — DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
31:16 — — — — — — — — — — — CAN1IP<2:0> CAN1IS<1:0> 0000
1140 IPC11
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
1150 IPC12
15:0 — — — U4IP<2:0> U4IS<1:0> — — — — — — — — 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET
and INV Registers” for more information.
2: These bits are not available on PIC32MX534/564/664/764 devices.
3: This register does not have associated CLR, SET, and INV registers.
 2009-2019 Microchip Technology Inc.

TABLE 7-3: INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND
Virtual Address
PIC32MX695F512H DEVICES
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT(3)
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
31:16 0000
1020 IPTMR IPTMR<31:0>
15:0 0000
U1TXIF U1RXIF U1EIF
31:16 I2C1MIF I2C1SIF I2C1BIF SPI3TXIF SPI3RXIF SPI3EIF — — — OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000
1030 IFS0
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
31:16 IC3EIF IC2EIF IC1EIF ETHIF — — USBIF FCEIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000
U3TXIF U3RXIF U3EIF U2TXIF U2RXIF U2EIF
1040 IFS1
15:0 RTCCIF FSCMIF — — — SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
31:16 — — — — — — — — — — — — — — 0000
1050 IFS2
15:0 — — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000

PIC32MX5XX/6XX/7XX
U1TXIE U1RXIE U1EIE
31:16 I2C1MIE I2C1SIE I2C1BIE SPI3TXIE SPI3RXIE SPI3EIE — — — OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000
1060 IEC0
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
31:16 IC3EIE IC2EIE IC1EIE ETHIE — — USBIE FCEIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000
U3TXIE U3RXIE U3EIE U2TXIE U2RXIE U2EIE
1070 IEC1
15:0 RTCCIE FSCMIE — — — SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
15:0 — — — — U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
1090 IPC0
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000
DS60001156K-page 83

10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX664 devices.
3: This register does not have associated CLR, SET, and INV registers.
DS60001156K-page 84
TABLE 7-3: INTERRUPT REGISTER MAP FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H AND

PIC32MX5XX/6XX/7XX
PIC32MX695F512H DEVICES (CONTINUED)

Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
10F0 IPC6
15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — SPI3IP<2:0> SPI3IS<1:0> 0000
I2C3IP<2:0> I2C3IS<1:0>
U2IP<2:0> U2IS<1:0>
31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000
1100 IPC7
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
U3IP<2:0> U3IS<1:0>
1110 IPC8
15:0 — — — — — — — — — — — SPI4IP<2:0> SPI4IS<1:0> 0000
I2C5IP<2:0> I2C5IS<1:0>
31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
1120 IPC9
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
31:16 — — — DMA7IP<2:0>(2) DMA7IS<1:0>(2) — — — DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
1130 IPC10
15:0 — — — DMA5IP<2:0>(2) DMA5IS<1:0>(2) — — — DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
31:16 — — — — — — — — — — — — — — — — 0000
1140 IPC11
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
1150 IPC12
15:0 — — — U4IP<2:0> U4IS<1:0> — — — ETHIP<2:0> ETHIS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2009-2019 Microchip Technology Inc.

Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX664 devices.
3: This register does not have associated CLR, SET, and INV registers.
 2009-2019 Microchip Technology Inc.

TABLE 7-4: INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND
Virtual Address
PIC32MX795F512H DEVICES
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
(3) 31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
31:16 0000
1020 IPTMR IPTMR<31:0>
15:0 0000
U1TXIF U1RXIF U1EIF
31:16 I2C1MIF I2C1SIF I2C1BIF SPI3TXIF SPI3RXIF SPI3EIF — — — OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000
1030 IFS0
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
31:16 IC3EIF IC2EIF IC1EIF ETHIF CAN2IF(2) CAN1IF USBIF FCEIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000
U3TXIF U3RXIF U3EIF U2TXIF U2RXIF U2EIF
1040 IFS1
15:0 RTCCIF FSCMIF — — — SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
15:0 — — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000

PIC32MX5XX/6XX/7XX
U1TXIE U1RXIE U1EIE
31:16 I2C1MIE I2C1SIE I2C1BIE SPI3TXIE SPI3RXIE SPI3EIE — — — OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000
1060 IEC0
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
31:16 IC3EIE IC2EIE IC1EIE ETHIE CAN2IE(2) CAN1IE USBIE FCEIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000
U3TXIE U3RXIE U3EIE U2TXIE U2RXIE U2EIE
1070 IEC1
15:0 RTCCIE FSCMIE — — — SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
15:0 — — — — U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
1090 IPC0
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
DS60001156K-page 85

31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000

10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128H device.
3: This register does not have associated CLR, SET, and INV registers.
DS60001156K-page 86
TABLE 7-4: INTERRUPT REGISTER MAP FOR PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND

PIC32MX5XX/6XX/7XX
PIC32MX795F512H DEVICES (CONTINUED)

Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — — — — — — — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
10F0 IPC6
15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — SPI3IP<2:0> SPI3IS<1:0> 0000
I2C3IP<2:0> I2C3IS<1:0>
U2IP<2:0> U2IS<1:0>
31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000
1100 IPC7
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
U3IP<2:0> U3IS<1:0>
1110 IPC8
15:0 — — — — — — — — — — — SPI4IP<2:0> SPI4IS<1:0> 0000
I2C5IP<2:0> I2C5IS<1:0>
31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
1120 IPC9
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
31:16 — — — DMA7IP<2:0>(2) DMA7IS<1:0>(2) — — — DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
1130 IPC10
15:0 — — — DMA5IP<2:0>(2) DMA5IS<1:0>(2) — — — DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
31:16 — — — CAN2IP<2:0>(2) CAN2IS<1:0>(2) — — — CAN1IP<2:0> CAN1IS<1:0> 0000
1140 IPC11
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
1150 IPC12
15:0 — — — U4IP<2:0> U4IS<1:0> — — — ETHIP<2:0> ETHIS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2009-2019 Microchip Technology Inc.

Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128H device.
3: This register does not have associated CLR, SET, and INV registers.
 2009-2019 Microchip Technology Inc.

TABLE 7-5: INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND
Virtual Address
PIC32MX575F256L DEVICES
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
(3) 31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
31:16 0000
1020 IPTMR IPTMR<31:0>
15:0 0000
U1TXIF U1RXIF U1EIF
31:16 I2C1MIF I2C1SIF I2C1BIF SPI3TXIF SPI3RXIF SPI3EIF SPI1TXIF SPI1RXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000
1030 IFS0
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
31:16 IC3EIF IC2EIF IC1EIF — — CAN1IF USBIF FCEIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000
U3TXIF U3RXIF U3EIF U2TXIF U2RXIF U2EIF
1040 IFS1
15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
15:0 — — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000

PIC32MX5XX/6XX/7XX
U1TXIE U1RXIE U1EIE
31:16 I2C1MIE I2C1SIE I2C1BIE SPI3TXIE SPI3RXIE SPI3EIE SPI1TXIE SPI1RXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000
1060 IEC0
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
31:16 IC3EIE IC2EIE IC1EIE — — CAN1IE USBIE FCEIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000
U3TXIE U3RXIE U3EIE U2TXIE U2RXIE U2EIE
1070 IEC1
15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
15:0 — — — — U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
1090 IPC0
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
DS60001156K-page 87

31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000

10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX534/564 devices.
3: This register does not have associated CLR, SET, and INV registers.
DS60001156K-page 88
TABLE 7-5: INTERRUPT REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L AND

PIC32MX5XX/6XX/7XX
PIC32MX575F256L DEVICES (CONTINUED)

Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
10F0 IPC6
15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — SPI3IP<2:0> SPI3IS<1:0> 0000
I2C3IP<2:0> I2C3IS<1:0>
U2IP<2:0> U2IS<1:0>
31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000
1100 IPC7
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
U3IP<2:0> U3IS<1:0>
1110 IPC8
15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — SPI4IP<2:0> SPI4IS<1:0> 0000
I2C5IP<2:0> I2C5IS<1:0>
31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
1120 IPC9
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
31:16 — — — DMA7IP<2:0>(2) DMA7IS<1:0>(2) — — — DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
1130 IPC10
15:0 — — — DMA5IP<2:0>(2) DMA5IS<1:0>(2) — — — DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
31:16 — — — — — — — — — — — CAN1IP<2:0> CAN1IS<1:0> 0000
1140 IPC11
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
1150 IPC12
15:0 — — — U4IP<2:0> U4IS<1:0> — — — — — — — — 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2009-2019 Microchip Technology Inc.

Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX534/564 devices.
3: This register does not have associated CLR, SET, and INV registers.
 2009-2019 Microchip Technology Inc.

TABLE 7-6: INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND
Virtual Address PIC32MX695F512L DEVICES
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
(3) 31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
31:16 0000
1020 IPTMR IPTMR<31:0>
15:0 0000
U1TXIF U1RXIF U1EIF
31:16 I2C1MIF I2C1SIF I2C1BIF SPI3TXIF SPI3RXIF SPI3EIF SPI1TXIF SPI1RXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000
1030 IFS0
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
31:16 IC3EIF IC2EIF IC1EIF ETHIF — — USBIF FCEIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000
U3TXIF U3RXIF U3EIF U2TXIF U2RXIF U2EIF
1040 IFS1
15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
15:0 — — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000

PIC32MX5XX/6XX/7XX
U1TXIE U1RXIE U1EIE
31:16 I2C1MIE I2C1SIE I2C1BIE SPI3TXIE SPI3RXIE SPI3EIE SPI1TXIE SPI1RXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000
1060 IEC0
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
31:16 IC3EIE IC2EIE IC1EIE ETHIE — — USBIE FCEIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000
U3TXIE U3RXIE U3EIE U2TXIE U2RXIE U2EIE
1070 IEC1
15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
15:0 — — — — U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
1090 IPC0
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
DS60001156K-page 89

31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000

10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX664 devices.
3: This register does note have associated CLR, SET, and INV registers.
DS60001156K-page 90
TABLE 7-6: INTERRUPT REGISTER MAP FOR PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L AND

PIC32MX5XX/6XX/7XX
PIC32MX695F512L DEVICES (CONTINUED)

Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
10F0 IPC6
15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — SPI3IP<2:0> SPI3IS<1:0> 0000
I2C3IP<2:0> I2C3IS<1:0>
U2IP<2:0> U2IS<1:0>
31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000
1100 IPC7
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
U3IP<2:0> U3IS<1:0>
1110 IPC8
15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — SPI4IP<2:0> SPI4IS<1:0> 0000
I2C5IP<2:0> I2C5IS<1:0>
31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
1120 IPC9
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
31:16 — — — DMA7IP<2:0>(2) DMA7IS<1:0>(2) — — — DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
1130 IPC10
15:0 — — — DMA5IP<2:0>(2) DMA5IS<1:0>(2) — — — DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
31:16 — — — — — — — — — — — — — — — — 0000
1140 IPC11
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
1150 IPC12
15:0 — — — U4IP<2:0> U4IS<1:0> — — — ETHIP<2:0> ETHIS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2009-2019 Microchip Technology Inc.

Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: These bits are not available on PIC32MX664 devices.
3: This register does note have associated CLR, SET, and INV registers.
 2009-2019 Microchip Technology Inc.

TABLE 7-7: INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND
Virtual Address PIC32MX795F512L DEVICES
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — SS0 0000

1000 INTCON
15:0 — — — MVEC — TPC<2:0> — — — INT4EP INT3EP INT2EP INT1EP INT0EP 0000
(3) 31:16 — — — — — — — — — — — — — — — — 0000
1010 INTSTAT
15:0 — — — — — SRIPL<2:0> — — VEC<5:0> 0000
31:16 0000
1020 IPTMR IPTMR<31:0>
15:0 0000
U1TXIF U1RXIF U1EIF
31:16 I2C1MIF I2C1SIF I2C1BIF SPI3TXIF SPI3RXIF SPI3EIF SPI1TXIF SPI1RXIF SPI1EIF OC5IF IC5IF T5IF INT4IF OC4IF IC4IF T4IF 0000
1030 IFS0
I2C3MIF I2C3SIF I2C3BIF
15:0 INT3IF OC3IF IC3IF T3IF INT2IF OC2IF IC2IF T2IF INT1IF OC1IF IC1IF T1IF INT0IF CS1IF CS0IF CTIF 0000
31:16 IC3EIF IC2EIF IC1EIF ETHIF CAN2IF(2) CAN1IF USBIF FCEIF DMA7IF(2) DMA6IF(2) DMA5IF(2) DMA4IF(2) DMA3IF DMA2IF DMA1IF DMA0IF 0000
U3TXIF U3RXIF U3EIF U2TXIF U2RXIF U2EIF
1040 IFS1
15:0 RTCCIF FSCMIF I2C2MIF I2C2SIF I2C2BIF SPI4TXIF SPI4RXIF SPI4EIF SPI2TXIF SPI2RXIF SPI2EIF CMP2IF CMP1IF PMPIF AD1IF CNIF 0000
I2C5MIF I2C5SIF I2C5BIF I2C4MIF I2C4SIF I2C4BIF
31:16 — — — — — — — — — — — — — — — — 0000
1050 IFS2
15:0 — — — — U5TXIF U5RXIF U5EIF U6TXIF U6RXIF U6EIF U4TXIF U4RXIF U4EIF PMPEIF IC5EIF IC4EIF 0000

PIC32MX5XX/6XX/7XX
U1TXIE U1RXIE U1EIE
31:16 I2C1MIE I2C1SIE I2C1BIE SPI3TXIE SPI3RXIE SPI3EIE SPI1TXIE SPI1RXIE SPI1EIE OC5IE IC5IE T5IE INT4IE OC4IE IC4IE T4IE 0000
1060 IEC0
I2C3MIE I2C3SIE I2C3BIE
15:0 INT3IE OC3IE IC3IE T3IE INT2IE OC2IE IC2IE T2IE INT1IE OC1IE IC1IE T1IE INT0IE CS1IE CS0IE CTIE 0000
31:16 IC3EIE IC2EIE IC1EIE ETHIE CAN2IE(2) CAN1IE USBIE FCEIE DMA7IE(2) DMA6IE(2) DMA5IE(2) DMA4IE(2) DMA3IE DMA2IE DMA1IE DMA0IE 0000
U3TXIE U3RXIE U3EIE U2TXIE U2RXIE U2EIE
1070 IEC1
15:0 RTCCIE FSCMIE I2C2MIE I2C2SIE I2C2BIE SPI4TXIE SPI4RXIE SPI4EIE SPI2TXIE SPI2RXIE SPI2EIE CMP2IE CMP1IE PMPIE AD1IE CNIE 0000
I2C5MIE I2C5SIE I2C5BIE I2C4MIE I2C4SIE I2C4BIE
31:16 — — — — — — — — — — — — — — — — 0000
1080 IEC2
15:0 — — — — U5TXIE U5RXIE U5EIE U6TXIE U6RXIE U6EIE U4TXIE U4RXIE U4EIE PMPEIE IC5EIE IC4EIE 0000
31:16 — — — INT0IP<2:0> INT0IS<1:0> — — — CS1IP<2:0> CS1IS<1:0> 0000
1090 IPC0
15:0 — — — CS0IP<2:0> CS0IS<1:0> — — — CTIP<2:0> CTIS<1:0> 0000
31:16 — — — INT1IP<2:0> INT1IS<1:0> — — — OC1IP<2:0> OC1IS<1:0> 0000
10A0 IPC1
15:0 — — — IC1IP<2:0> IC1IS<1:0> — — — T1IP<2:0> T1IS<1:0> 0000
DS60001156K-page 91

31:16 — — — INT2IP<2:0> INT2IS<1:0> — — — OC2IP<2:0> OC2IS<1:0> 0000

10B0 IPC2
15:0 — — — IC2IP<2:0> IC2IS<1:0> — — — T2IP<2:0> T2IS<1:0> 0000
31:16 — — — INT3IP<2:0> INT3IS<1:0> — — — OC3IP<2:0> OC3IS<1:0> 0000
10C0 IPC3
15:0 — — — IC3IP<2:0> IC3IS<1:0> — — — T3IP<2:0> T3IS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128L device.
3: This register does not have associated CLR, SET, and INV registers.
DS60001156K-page 92
TABLE 7-7: INTERRUPT REGISTER MAP FOR PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND

PIC32MX5XX/6XX/7XX
PIC32MX795F512L DEVICES (CONTINUED)

Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — INT4IP<2:0> INT4IS<1:0> — — — OC4IP<2:0> OC4IS<1:0> 0000

10D0 IPC4
15:0 — — — IC4IP<2:0> IC4IS<1:0> — — — T4IP<2:0> T4IS<1:0> 0000
31:16 — — — SPI1IP<2:0> SPI1IS<1:0> — — — OC5IP<2:0> OC5IS<1:0> 0000
10E0 IPC5
15:0 — — — IC5IP<2:0> IC5IS<1:0> — — — T5IP<2:0> T5IS<1:0> 0000
31:16 — — — AD1IP<2:0> AD1IS<1:0> — — — CNIP<2:0> CNIS<1:0> 0000
U1IP<2:0> U1IS<1:0>
10F0 IPC6
15:0 — — — I2C1IP<2:0> I2C1IS<1:0> — — — SPI3IP<2:0> SPI3IS<1:0> 0000
I2C3IP<2:0> I2C3IS<1:0>
U2IP<2:0> U2IS<1:0>
31:16 — — — SPI2IP<2:0> SPI2IS<1:0> — — — CMP2IP<2:0> CMP2IS<1:0> 0000
1100 IPC7
I2C4IP<2:0> I2C4IS<1:0>
15:0 — — — CMP1IP<2:0> CMP1IS<1:0> — — — PMPIP<2:0> PMPIS<1:0> 0000
31:16 — — — RTCCIP<2:0> RTCCIS<1:0> — — — FSCMIP<2:0> FSCMIS<1:0> 0000
U3IP<2:0> U3IS<1:0>
1110 IPC8
15:0 — — — I2C2IP<2:0> I2C2IS<1:0> — — — SPI4IP<2:0> SPI4IS<1:0> 0000
I2C5IP<2:0> I2C5IS<1:0>
31:16 — — — DMA3IP<2:0> DMA3IS<1:0> — — — DMA2IP<2:0> DMA2IS<1:0> 0000
1120 IPC9
15:0 — — — DMA1IP<2:0> DMA1IS<1:0> — — — DMA0IP<2:0> DMA0IS<1:0> 0000
31:16 — — — DMA7IP<2:0>(2) DMA7IS<1:0>(2) — — — DMA6IP<2:0>(2) DMA6IS<1:0>(2) 0000
1130 IPC10
15:0 — — — DMA5IP<2:0>(2) DMA5IS<1:0>(2) — — — DMA4IP<2:0>(2) DMA4IS<1:0>(2) 0000
31:16 — — — CAN2IP<2:0>(2) CAN2IS<1:0>(2) — — — CAN1IP<2:0> CAN1IS<1:0> 0000
1140 IPC11
15:0 — — — USBIP<2:0> USBIS<1:0> — — — FCEIP<2:0> FCEIS<1:0> 0000
31:16 — — — U5IP<2:0> U5IS<1:0> — — — U6IP<2:0> U6IS<1:0> 0000
1150 IPC12
15:0 — — — U4IP<2:0> U4IS<1:0> — — — ETHIP<2:0> ETHIS<1:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
 2009-2019 Microchip Technology Inc.

Note 1: Except where noted, all registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV
Registers” for more information.
2: This bit is unimplemented on PIC32MX764F128L device.
3: This register does not have associated CLR, SET, and INV registers.
 PIC32MX5XX/6XX/7XX
REGISTER 7-1: INTCON: INTERRUPT CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
23:16
— — — — — — — SS0
U-0 U-0 U-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0
15:8
— — — MVEC — TPC<2:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — INT4EP INT3EP INT2EP INT1EP INT0EP

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-17 Unimplemented: Read as ‘0’

bit 16 SS0: Single Vector Shadow Register Set bit
1 = Single vector is presented with a shadow register set
0 = Single vector is not presented with a shadow register set
bit 15-13 Unimplemented: Read as ‘0’
bit 12 MVEC: Multiple Vector Configuration bit
1 = Interrupt controller configured for Multi-vector mode
0 = Interrupt controller configured for Single-vector mode
bit 11 Unimplemented: Read as ‘0’
bit 10-8 TPC<2:0>: Interrupt Proximity Timer Control bits
111 = Interrupts of group priority 7 or lower start the Interrupt Proximity timer
110 = Interrupts of group priority 6 or lower start the Interrupt Proximity timer
101 = Interrupts of group priority 5 or lower start the Interrupt Proximity timer
100 = Interrupts of group priority 4 or lower start the Interrupt Proximity timer
011 = Interrupts of group priority 3 or lower start the Interrupt Proximity timer
010 = Interrupts of group priority 2 or lower start the Interrupt Proximity timer
001 = Interrupts of group priority 1 start the Interrupt Proximity timer
000 = Disables Interrupt Proximity timer
bit 7-5 Unimplemented: Read as ‘0’
bit 4 INT4EP: External Interrupt 4 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 3 INT3EP: External Interrupt 3 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 2 INT2EP: External Interrupt 2 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 1 INT1EP: External Interrupt 1 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge
bit 0 INT0EP: External Interrupt 0 Edge Polarity Control bit
1 = Rising edge
0 = Falling edge

 2009-2019 Microchip Technology Inc. DS60001156K-page 93

PIC32MX5XX/6XX/7XX
REGISTER 7-2: INTSTAT: INTERRUPT STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
— — — — — RIPL<2:0>(1)
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — VEC<5:0>(1)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-11 Unimplemented: Read as ‘0’

bit 10-8 RIPL<2:0>: Requested Priority Level bits(1)
111-000 = The priority level of the latest interrupt presented to the CPU
bit 7-6 Unimplemented: Read as ‘0’
bit 5-0 VEC<5:0>: Interrupt Vector bits(1)
11111-00000 = The interrupt vector that is presented to the CPU

Note 1: This value should only be used when the interrupt controller is configured for Single-vector mode.

REGISTER 7-3: TPTMR: TEMPORAL PROXIMITY TIMER REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
TPTMR<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
TPTMR<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
TPTMR<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
TPTMR<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 TPTMR<31:0>: Temporal Proximity Timer Reload bits

Used by the Temporal Proximity Timer as a reload value when the Temporal Proximity timer is triggered by
an interrupt event.

DS60001156K-page 94  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 7-4: IFSx: INTERRUPT FLAG STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
IFS31 IFS30 IFS29 IFS28 IFS27 IFS26 IFS25 IFS24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
IFS23 IFS22 IFS21 IFS20 IFS19 IFS18 IFS17 IFS16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
IFS15 IFS14 IFS13 IFS12 IFS11 IFS10 IFS09 IFS08
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
IFS07 IFS06 IFS05 IFS04 IFS03 IFS02 IFS01 IFS00

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IFS31-IFS00: Interrupt Flag Status bits

1 = Interrupt request has occurred
0 = Interrupt request has not occurred

Note: This register represents a generic definition of the IFSx register. Refer to Table 7-1 for the exact bit
definitions.

REGISTER 7-5: IECx: INTERRUPT ENABLE CONTROL REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
IEC31 IEC30 IEC29 IEC28 IEC27 IEC26 IEC25 IEC24
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
IEC23 IEC22 IEC21 IEC20 IEC19 IEC18 IEC17 IEC16
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
IEC15 IEC14 IEC13 IEC12 IEC11 IEC10 IEC09 IEC08
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
IEC07 IEC06 IEC05 IEC04 IEC03 IEC02 IEC01 IEC00

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 IEC31-IEC00: Interrupt Enable bits

1 = Interrupt is enabled
0 = Interrupt is disabled

Note: This register represents a generic definition of the IECx register. Refer to Table 7-1 for the exact bit
definitions.

 2009-2019 Microchip Technology Inc. DS60001156K-page 95

PIC32MX5XX/6XX/7XX
REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
— — — IP03<2:0> IS03<1:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
— — — IP02<2:0> IS02<1:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
— — — IP01<2:0> IS01<1:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — IP00<2:0> IS00<1:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-26 IP03<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 25-24 IS03<1:0>: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
bit 23-21 Unimplemented: Read as ‘0’
bit 20-18 IP02<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 17-16 IS02<1:0>: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
bit 15-13 Unimplemented: Read as ‘0’

Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.

DS60001156K-page 96  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 7-6: IPCx: INTERRUPT PRIORITY CONTROL REGISTER (CONTINUED)
bit 12-10 IP01<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 9-8 IS01<1:0>: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0
bit 7-5 Unimplemented: Read as ‘0’
bit 4-2 IP00<2:0>: Interrupt Priority bits
111 = Interrupt priority is 7
•
•
•
010 = Interrupt priority is 2
001 = Interrupt priority is 1
000 = Interrupt is disabled
bit 1-0 IS00<1:0>: Interrupt Sub-priority bits
11 = Interrupt sub-priority is 3
10 = Interrupt sub-priority is 2
01 = Interrupt sub-priority is 1
00 = Interrupt sub-priority is 0

Note: This register represents a generic definition of the IPCx register. Refer to Table 7-1 for the exact bit
definitions.

 2009-2019 Microchip Technology Inc. DS60001156K-page 97

PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 98  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
8.0 OSCILLATOR The Oscillator module has the following features:
CONFIGURATION • A total of four external and internal oscillator
options as clock sources
Note: This data sheet summarizes the features • On-chip PLL with user-selectable input divider,
of the PIC32MX5XX/6XX/7XX family of multiplier and output divider to boost operating
devices. It is not intended to be a frequency on select internal and external
comprehensive reference source. To oscillator sources
complement the information in this data • On-chip user-selectable divisor postscaler on
sheet, refer to Section 6. “Oscillator” select oscillator sources
(DS60001112) in the “PIC32 Family Ref- • Software-controllable switching between
erence Manual”, which is available from various clock sources
the Microchip web site (www.micro- • A Fail-Safe Clock Monitor (FSCM) that detects
chip.com/PIC32). clock failure and permits safe application recovery
or shutdown
• Dedicated On-Chip PLL for USB peripheral
Figure 8-1shows the Oscillator module block diagram.

FIGURE 8-1: OSCILLATOR BLOCK DIAGRAM

USB PLL

UFIN USB Clock (48 MHz)

div x PLL x24 div 2
UFRCEN
Primary Oscillator UFIN 4 MHz
(POSC) To Internal UPLLEN
UPLLIDIV<2:0>
Logic
C1(3) OSC1 XT, HS, EC
4 MHz  FIN  5 MHz XTPLL, HSPLL,
XTAL RF(2) Postscaler Peripherals
FIN ECPLL, FRCPLL
RP(1) div x PLL div y div x PBCLK
Enable
RS(1)
PLL Input Divider PLL Output Divider
C2(3) FPLLIDIV<2:0> PLLODIV<2:0> PBDIV<1:0>
OSC2(4)
FRC COSC<2:0> PLL Multiplier
Oscillator (001 = FRC, PLLMULT<2:0>
8 MHz typical 011 = POSC) FRC

div 16 FRC/16
TUN<5:0>
CPU and Select Peripherals
FRCDIV
Postscaler
SYSCLK

FRCDIV<2:0>
LPRC LPRC
Oscillator
31.25 kHz typical

Secondary Oscillator (SOSC)

SOSCO 32.768 kHz SOSC
COSC<2:0>
SOSCEN and FSOSCEN
Clock Control Logic
Fail-Safe FSCM INT
SOSCI Clock
Monitor FSCM Event

Notes: 1. A series resistor, RS, may be required for AT strip cut crystals or eliminate
clipping. Alternately, to increase oscillator circuit gain, add a parallel
NOSC<2:0>
resistor, RP, with a value of 1 M
COSC<2:0>
2. The internal feedback resistor, RF, is typically in the range of 2 to 10 M
3. Refer to the “PIC32 Family Reference Manual” Section 6. “Oscillator FSCMEN<1:0> OSWEN
Configuration” (DS60001112) for help determining the best oscillator WDT, PWRT
components. Timer1, RTCC
4. PBCLK out is available on the OSC2 pin in certain clock modes.

 2009-2019 Microchip Technology Inc. DS60001156K-page 99

DS60001156K-page 100
8.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 8-1:
Virtual Address
OSCILLATOR REGISTER MAP
Bits

All Resets(2)
Bit Range
(BF80_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — PLLODIV<2:0> FRCDIV<2:0> — SOSCRDY — PBDIV<1:0> PLLMULT<2:0> 0000

F000 OSCCON
15:0 — COSC<2:0> — NOSC<2:0> CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN SOSCEN OSWEN 0000
31:16 — — — — — — — — — — — — — — — — 0000
F010 OSCTUN
15:0 — — — — — — — — — — TUN<5:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 R/W-y R/W-y R/W-y R/W-0 R/W-0 R/W-1
31:24
— — PLLODIV<2:0> FRCDIV<2:0>
U-0 R-0 R-1 R/W-y R/W-y R/W-y R/W-y R/W-y
23:16
— SOSCRDY PBDIVRDY PBDIV<1:0> PLLMULT<2:0>
U-0 R-0 R-0 R-0 U-0 R/W-y R/W-y R/W-y
15:8
— COSC<2:0> — NOSC<2:0>
R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-y R/W-0
7:0
CLKLOCK ULOCK SLOCK SLPEN CF UFRCEN SOSCEN OSWEN

Legend: y = Value set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29-27 PLLODIV<2:0>: Output Divider for PLL
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 26-24 FRCDIV<2:0>: Internal Fast RC (FRC) Oscillator Clock Divider bits
111 = FRC divided by 256
110 = FRC divided by 64
101 = FRC divided by 32
100 = FRC divided by 16
011 = FRC divided by 8
010 = FRC divided by 4
001 = FRC divided by 2 (default setting)
000 = FRC divided by 1
bit 23 Unimplemented: Read as ‘0’
bit 22 SOSCRDY: Secondary Oscillator (SOSC) Ready Indicator bit
1 = Indicates that the Secondary Oscillator is running and is stable
0 = Secondary Oscillator is still warming up or is turned off
bit 21 PBDIVRDY: Peripheral Bus Clock (PBCLK) Divisor Ready bit
1 = PBDIV<1:0> bits can be written
0 = PBDIV<1:0> bits cannot be written
bit 20-19 PBDIV<1:0>: Peripheral Bus Clock (PBCLK) Divisor bits
11 = PBCLK is SYSCLK divided by 8 (default)
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1

Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.

 2009-2019 Microchip Technology Inc. DS60001156K-page 101

PIC32MX5XX/6XX/7XX
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 18-16 PLLMULT<2:0>: Phase-Locked Loop (PLL) Multiplier bits
111 = Clock is multiplied by 24
110 = Clock is multiplied by 21
101 = Clock is multiplied by 20
100 = Clock is multiplied by 19
011 = Clock is multiplied by 18
010 = Clock is multiplied by 17
001 = Clock is multiplied by 16
000 = Clock is multiplied by 15
bit 15 Unimplemented: Read as ‘0’
bit 14-12 COSC<2:0>: Current Oscillator Selection bits
111 = Internal Fast RC (FRC) Oscillator divided by OSCCON<FRCDIV> bits
110 = Internal Fast RC (FRC) Oscillator divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (POSC) with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (POSC) (XT, HS or EC)
001 = Internal Fast RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast RC (FRC) Oscillator
bit 11 Unimplemented: Read as ‘0’
bit 10-8 NOSC<2:0>: New Oscillator Selection bits
111 = Internal Fast RC Oscillator (FRC) divided by OSCCON<FRCDIV> bits
110 = Internal Fast RC Oscillator (FRC) divided by 16
101 = Internal Low-Power RC (LPRC) Oscillator
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator with PLL module (XTPLL, HSPLL or ECPLL)
010 = Primary Oscillator (XT, HS or EC)
001 = Internal Fast Internal RC Oscillator with PLL module via Postscaler (FRCPLL)
000 = Internal Fast Internal RC Oscillator (FRC)
On Reset, these bits are set to the value of the FNOSC Configuration bits (DEVCFG1<2:0>).
bit 7 CLKLOCK: Clock Selection Lock Enable bit
If clock switching and monitoring is disabled (FCKSM<1:0> = 1x):
1 = Clock and PLL selections are locked
0 = Clock and PLL selections are not locked and may be modified

If clock switching and monitoring is enabled (FCKSM<1:0> = 0x):

Clock and PLL selections are never locked and may be modified.
bit 6 ULOCK: USB PLL Lock Status bit
1 = Indicates that the USB PLL module is in lock or USB PLL module start-up timer is satisfied
0 = Indicates that the USB PLL module is out of lock or USB PLL module start-up timer is in progress or
USB PLL is disabled
bit 5 SLOCK: PLL Lock Status bit
1 = PLL module is in lock or PLL module start-up timer is satisfied
0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled
bit 4 SLPEN: Sleep Mode Enable bit
1 = Device will enter Sleep mode when a WAIT instruction is executed
0 = Device will enter Idle mode when a WAIT instruction is executed
bit 3 CF: Clock Fail Detect bit
1 = FSCM has detected a clock failure
0 = No clock failure has been detected

Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.

DS60001156K-page 102  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 8-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED)
bit 2 UFRCEN: USB FRC Clock Enable bit
1 = Enable FRC as the clock source for the USB clock source
0 = Use the Primary Oscillator or USB PLL as the USB clock source
bit 1 SOSCEN: Secondary Oscillator (SOSC) Enable bit
1 = Enable Secondary Oscillator
0 = Disable Secondary Oscillator
bit 0 OSWEN: Oscillator Switch Enable bit
1 = Initiate an oscillator switch to selection specified by NOSC<2:0> bits
0 = Oscillator switch is complete

Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.

 2009-2019 Microchip Technology Inc. DS60001156K-page 103

PIC32MX5XX/6XX/7XX
REGISTER 8-2: OSCTUN: FRC TUNING REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0 (1)
— — TUN<5:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-6 Unimplemented: Read as ‘0’

bit 5-0 TUN<5:0>: FRC Oscillator Tuning bits(1)
100000 = Center frequency -12.5% for PIC32MX575/595/675/695/775/795 devices
100000 = Center frequency -1.5% for PIC32MX534/564/664/764 devices
100001 =
•
•
•
111111 =
000000 = Center frequency; Oscillator runs at nominal frequency (8 MHz)
000001 =
•
•
•
011110 =
011111 = Center frequency +12.5% for PIC32MX575/595/675/695/775/795 devices
011111 = Center frequency +1.5% for PIC32MX534/564/664/764 devices

Note 1: OSCTUN functionality has been provided to help customers compensate for temperature effects on the
FRC frequency over a wide range of temperatures. The tuning step size is an approximation, and is neither
characterized nor tested.

Note: Writes to this register require an unlock sequence. Refer to Section 6. “Oscillator” (DS60001112) in the
“PIC32 Family Reference Manual” for details.

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 PIC32MX5XX/6XX/7XX
9.0 PREFETCH CACHE 9.1 Features
Note: This data sheet summarizes the features • 16 fully-associative lockable cache lines
of the PIC32MX5XX/6XX/7XX family of • 16-byte cache lines
devices. It is not intended to be a • Up to four cache lines allocated to data
comprehensive reference source. To • Two cache lines with address mask to hold
complement the information in this data repeated instructions
sheet, refer to Section 4. “Prefetch
• Pseudo-LRU replacement policy
Cache” (DS60001119) in the “PIC32
Family Reference Manual”, which is avail- • All cache lines are software writable
able from the Microchip web site • 16-byte parallel memory fetch
(www.microchip.com/PIC32). • Predictive instruction prefetch

Prefetch cache increases performance for applications A simplified block diagram of the Prefetch Cache
executing out of the cacheable program Flash memory module is illustrated in Figure 9-1.
regions by implementing instruction caching, constant
data caching and instruction prefetching.

FIGURE 9-1: PREFETCH CACHE MODULE BLOCK DIAGRAM

FSM CTRL

Tag Logic Cache Line

BMX/CPU

CTRL

BMX/CPU
Bus Control
Cache Control
Prefetch Control Cache
Hit LRU Line
RDATA
Address
Miss LRU Encode

Hit Logic

Prefetch Prefetch

CTRL RDATA

PFM

 2009-2019 Microchip Technology Inc. DS60001156K-page 105

DS60001156K-page 106
9.2 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 9-1:
Virtual Address
PREFETCH REGISTER MAP
Bits

All Resets
Bit Range
(BF88_#)

Register
Name 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — CHECOH 0000

4000 CHECON(1,2)
15:0 — — — — — — DCSZ<1:0> — — PREFEN<1:0> — PFMWS<2:0> 0007
(1) 31:16 CHEWEN — — — — — — — — — — — — — — — 0000
4010 CHEACC
15:0 — — — — — — — — — — — — CHEIDX<3:0> 0000
31:16 LTAGBOOT — — — — — — — LTAG<23:16> 00xx
4020 CHETAG(1)
15:0 LTAG<15:4> LVALID LLOCK LTYPE — xxx2
31:16 — — — — — — — — — — — — — — — — 0000
4030 CHEMSK(1)
15:0 LMASK<15:5> — — — — — 0000
31:16 xxxx
4040 CHEW0 CHEW0<31:0>
15:0 xxxx
31:16 xxxx
4050 CHEW1 CHEW1<31:0>
15:0 xxxx
31:16 xxxx
4060 CHEW2 CHEW2<31:0>
15:0 xxxx
31:16 xxxx
4070 CHEW3 CHEW3<31:0>
15:0 xxxx
31:16 — — — — — — — CHELRU<24:16> 0000
4080 CHELRU
15:0 CHELRU<15:0> 0000
31:16 xxxx
4090 CHEHIT CHEHIT<31:0>
15:0 xxxx
31:16 xxxx
40A0 CHEMIS CHEMIS<31:0>
15:0 xxxx
31:16 xxxx
40C0 CHEPFABT CHEPFABT<31:0>
 2009-2019 Microchip Technology Inc.

15:0 xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2: Reset value is dependent on DEVCFGx configuration.
 PIC32MX5XX/6XX/7XX
REGISTER 9-1: CHECON: CACHE CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
23:16
— — — — — — — CHECOH
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
— — — — — — DCSZ<1:0>
U-0 U-0 R/W-0 R/W-0 U-0 R/W-1 R/W-1 R/W-1
7:0
— — PREFEN<1:0> — PFMWS<2:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-17 Unimplemented: Write ‘0’; ignore read

bit 16 CHECOH: Cache Coherency Setting on a PFM Program Cycle bit
1 = Invalidate all data and instruction lines
0 = Invalidate all data lnes and instruction lines that are not locked
bit 15-10 Unimplemented: Write ‘0’; ignore read
bit 9-8 DCSZ<1:0>: Data Cache Size in Lines bits
Changing these bits causes all lines to be reinitialized to the “invalid” state.
11 = Enable data caching with a size of 4 lines
10 = Enable data caching with a size of 2 lines
01 = Enable data caching with a size of 1 line
00 = Disable data caching
bit 7-6 Unimplemented: Write ‘0’; ignore read
bit 5-4 PREFEN<1:0>: Predictive Prefetch Enable bits
11 = Enable predictive prefetch for both cacheable and non-cacheable regions
10 = Enable predictive prefetch only for non-cacheable regions
01 = Enable predictive prefetch only for cacheable regions
00 = Disable predictive prefetch
bit 3 Unimplemented: Write ‘0’; ignore read
bit 2-0 PFMWS<2:0>: PFM Access Time Defined in Terms of SYSLK Wait States bits
111 = Seven Wait states
110 = Six Wait states
101 = Five Wait states
100 = Four Wait states
011 = Three Wait states
010 = Two Wait states
001 = One Wait state
000 = Zero Wait state

 2009-2019 Microchip Technology Inc. DS60001156K-page 107

PIC32MX5XX/6XX/7XX
REGISTER 9-2: CHEACC: CACHE ACCESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
CHEWEN — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — — CHEIDX<3:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 CHEWEN: Cache Access Enable bits

These bits apply to registers CHETAG, CHEMSK, CHEW0, CHEW1, CHEW2, and CHEW3.
1 = The cache line selected by CHEIDX<3:0> is writeable
0 = The cache line selected by CHEIDX<3:0> is not writeable
bit 30-4 Unimplemented: Write ‘0’; ignore read
bit 3-0 CHEIDX<3:0>: Cache Line Index bits
The value selects the cache line for reading or writing.

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 PIC32MX5XX/6XX/7XX
REGISTER 9-3: CHETAG: CACHE TAG REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
LTAGBOOT — — — — — — —
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
LTAG<19:12>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
LTAG<11:4>
R/W-x R/W-x R/W-x R/W-x R/W-0 R/W-0 R/W-1 U-0
7:0
LTAG<3:0> LVALID LLOCK LTYPE —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 LTAGBOOT: Line Tag Address Boot bit

1 = The line is in the 0x1D000000 (physical) area of memory
0 = The line is in the 0x1FC00000 (physical) area of memory
bit 30-24 Unimplemented: Write ‘0’; ignore read
bit 23-4 LTAG<19:0>: Line Tag Address bits
LTAG<19:0> bits are compared against physical address to determine a hit. Because its address range and
position of PFM in kernel space and user space, the LTAG PFM address is identical for virtual addresses,
(system) physical addresses, and PFM physical addresses.
bit 3 LVALID: Line Valid bit
1 = The line is valid and is compared to the physical address for hit detection
0 = The line is not valid and is not compared to the physical address for hit detection
bit 2 LLOCK: Line Lock bit
1 = The line is locked and will not be replaced
0 = The line is not locked and can be replaced
bit 1 LTYPE: Line Type bit
1 = The line caches instruction words
0 = The line caches data words
bit 0 Unimplemented: Write ‘0’; ignore read

 2009-2019 Microchip Technology Inc. DS60001156K-page 109

PIC32MX5XX/6XX/7XX
REGISTER 9-4: CHEMSK: CACHE TAG MASK REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
LMASK<10:3>
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
7:0
LMASK<2:0> — — — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Write ‘0’; ignore read

bit 15-5 LMASK<10:0>: Line Mask bits
1 = Enables mask logic to force a match on the corresponding bit position in LTAG<19:0> bits
(CHETAG<23:4>) and the physical address
0 = Only writeable for values of CHEIDX<3:0> bits (CHEACC<3:0>) equal to 0x0A and 0x0B
(disables mask logic)
bit 4-0 Unimplemented: Write ‘0’; ignore read

REGISTER 9-5: CHEW0: CACHE WORD 0

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
CHEW0<31:24>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
CHEW0<23:16>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
CHEW0<15:8>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7:0
CHEW0<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHEW0<31:0>: Word 0 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.

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 PIC32MX5XX/6XX/7XX
REGISTER 9-6: CHEW1: CACHE WORD 1
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
CHEW1<31:24>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
CHEW1<23:16>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
CHEW1<15:8>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7:0
CHEW1<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHEW1<31:0>: Word 1 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.

REGISTER 9-7: CHEW2: CACHE WORD 2

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
CHEW2<31:24>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
CHEW2<23:16>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
CHEW2<15:8>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7:0
CHEW2<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHEW2<31:0>: Word 2 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.

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PIC32MX5XX/6XX/7XX
REGISTER 9-8: CHEW3: CACHE WORD 3
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
CHEW3<31:24>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
CHEW3<23:16>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
CHEW3<15:8>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7:0
CHEW3<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHEW3<31:0>: Word 3 of the cache line selected by CHEIDX<3:0> bits (CHEACC<3:0>)
Readable only if the device is not code-protected.

Note: This register is a window into the cache data array and is only readable if the device is not code-protected.

REGISTER 9-9: CHELRU: CACHE LRU REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0
31:24
— — — — — — — CHELRU<24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
CHELRU<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
CHELRU<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
CHELRU<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-25 Unimplemented: Write ‘0’; ignore read

bit 24-0 CHELRU<24:0>: Cache Least Recently Used State Encoding bits
Indicates the pseudo-LRU state of the cache.

DS60001156K-page 112  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 9-10: CHEHIT: CACHE HIT STATISTICS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
CHEHIT<31:24>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
CHEHIT<23:16>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
CHEHIT<15:8>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7:0
CHEHIT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHEHIT<31:0>: Cache Hit Count bits

Incremented each time the processor issues an instruction fetch or load that hits the prefetch cache from a
cacheable region. Non-cacheable accesses do not modify this value.

REGISTER 9-11: CHEMIS: CACHE MISS STATISTICS REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
CHEMIS<31:24>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
CHEMIS<23:16>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
CHEMIS<15:8>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7:0
CHEMIS<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHEMIS<31:0>: Cache Miss Count bits

Incremented each time the processor issues an instruction fetch from a cacheable region that misses the
prefetch cache. Non-cacheable accesses do not modify this value.

 2009-2019 Microchip Technology Inc. DS60001156K-page 113

PIC32MX5XX/6XX/7XX
REGISTER 9-12: CHEPFABT: PREFETCH CACHE ABORT STATISTICS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
CHEPFABT<31:24>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
CHEPFABT<23:16>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
CHEPFABT<15:8>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7:0
CHEPFABT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHEPFABT<31:0>: Prefab Abort Count bits

Incremented each time an automatic prefetch cache is aborted due to a non-sequential instruction fetch, load
or store.

DS60001156K-page 114  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
10.0 DIRECT MEMORY ACCESS • Automatic word-size detection:
(DMA) CONTROLLER - Transfer granularity, down to byte level
- Bytes need not be word-aligned at source and
Note: This data sheet summarizes the features destination
of the PIC32MX5XX/6XX/7XX family of • Fixed priority channel arbitration
devices. It is not intended to be a • Flexible DMA channel operating modes:
comprehensive reference source. To - Manual (software) or automatic (interrupt) DMA
complement the information in this data requests
sheet, refer to Section 31. “Direct Mem-
- One-Shot or Auto-Repeat Block Transfer modes
ory Access (DMA) Controller”
- Channel-to-channel chaining
(DS60001117) in the “PIC32 Family Ref-
erence Manual”, which is available from • Flexible DMA requests:
the Microchip web site - A DMA request can be selected from any of the
(www.microchip.com/PIC32). peripheral interrupt sources
- Each channel can select any (appropriate)
The Direct Memory Access (DMA) controller is a bus observable interrupt as its DMA request source
master module useful for data transfers between - A DMA transfer abort can be selected from any of
different devices without CPU intervention. The source the peripheral interrupt sources
and destination of a DMA transfer can be any of the - Pattern (data) match transfer termination
memory mapped modules existent in the PIC32 (such
• Multiple DMA channel status interrupts:
as SPI, UART, PMP, etc.) or memory itself.
- DMA channel block transfer complete
Following are some of the key features of the DMA
- Source empty or half empty
controller module:
- Destination full or half full
• Four identical channels, each featuring: - DMA transfer aborted due to an external event
- Auto-increment source and destination address - Invalid DMA address generated
registers
• DMA debug support features:
- Source and destination pointers
- Most recent address accessed by a DMA channel
- Memory to memory and memory to
peripheral transfers - Most recent DMA channel to transfer data
• CRC Generation module:
- CRC module can be assigned to any of the
available channels
- CRC module is highly configurable

FIGURE 10-1: DMA BLOCK DIAGRAM

INT Controller System IRQ

SE
L
Peripheral Bus Address Decoder Channel 0 Control I0

Channel 1 Control I1 Y Bus Interface Device Bus + Bus Arbitration

I2

Global Control Channel ‘n’ Control In

(DMACON) L
SE

Channel Priority
Arbitration

 2009-2019 Microchip Technology Inc. DS60001156K-page 115

DS60001156K-page 116
10.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 10-1: DMA GLOBAL REGISTER MAP
Virtual Address Bits

All Resets
Bit Range
(BF88_#)

Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
3000 DMACON(1)
15:0 ON — — SUSPEND DMABUSY — — — — — — — — — — — 0000
31:16 — — — — — — — — — — — — — — — — 0000
3010 DMASTAT
15:0 — — — — — — — — — — — — RDWR DMACH<2:0>(2) 0000
31:16 0000
3020 DMAADDR DMAADDR<31:0>
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
2: DMACH<3> bit is not available on PIC32MX534/564/664/764 devices.

TABLE 10-2: DMA CRC REGISTER MAP(1)

Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — BYTO<1:0> WBO — — BITO — — — — — — — — 0000

3030 DCRCCON
15:0 — — — PLEN<4:0> CRCEN CRCAPP CRCTYP — — CRCCH<2:0> 0000
31:16 0000
3040 DCRCDATA DCRCDATA<31:0>
15:0 0000
31:16 0000
3050 DCRCXOR DCRCXOR<31:0>
15:0 0000
 2009-2019 Microchip Technology Inc.

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 2009-2019 Microchip Technology Inc.

TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP

Virtual Address Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
3060 DCH0CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
3070 DCH0ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
3080 DCH0INT
15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
3090 DCH0SSA CHSSA<31:0>
15:0 0000
31:16 0000
30A0 DCH0DSA CHDSA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
30B0 DCH0SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
30C0 DCH0DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
30D0 DCH0SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000

PIC32MX5XX/6XX/7XX
30E0 DCH0DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
30F0 DCH0CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3100 DCH0CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3110 DCH0DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3120 DCH1CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
3130 DCH1ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
3140 DCH1INT
15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
3150 DCH1SSA CHSSA<31:0>
DS60001156K-page 117

15:0 0000
31:16 0000
3160 DCH1DSA CHDSA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
3170 DCH1SSIZ
15:0 CHSSIZ<15:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
DS60001156K-page 118
TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)

PIC32MX5XX/6XX/7XX
Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
3180 DCH1DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3190 DCH1SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31A0 DCH1DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31B0 DCH1CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31C0 DCH1CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31D0 DCH1DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
31E0 DCH2CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
31F0 DCH2ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
3200 DCH2INT
15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
3210 DCH2SSA CHSSA<31:0>
15:0 0000
31:16 0000
3220 DCH2DSA CHDSA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
3230 DCH2SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3240 DCH2DSIZ
15:0 CHDSIZ<15:0> 0000
 2009-2019 Microchip Technology Inc.

31:16 — — — — — — — — — — — — — — — — 0000
3250 DCH2SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3260 DCH2DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3270 DCH2CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3280 DCH2CPTR
15:0 CHCPTR<15:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
 TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
 2009-2019 Microchip Technology Inc.

Virtual Address Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
3290 DCH2DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
32A0 DCH3CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
32B0 DCH3ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
32C0 DCH3INT
15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
32D0 DCH3SSA CHSSA<31:0>
15:0 0000
31:16 0000
32E0 DCH3DSA CHDSA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
32F0 DCH3SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3300 DCH3DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000

PIC32MX5XX/6XX/7XX
3310 DCH3SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3320 DCH3DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3330 DCH3CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3340 DCH3CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3350 DCH3DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3360 DCH4CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
3370 DCH4ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
3380 DCH4INT
DS60001156K-page 119

15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
3390 DCH4SSA CHSSA<31:0>
15:0 0000
31:16 0000
33A0 DCH4DSA CHDSA<31:0>
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
DS60001156K-page 120
TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)

PIC32MX5XX/6XX/7XX
Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
33B0 DCH4SSIZ
15:0 CHSSIZ15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
33C0 DCH4DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
33D0 DCH4SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
33E0 DCH4DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
33F0 DCH4CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3400 DCH4CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3410 DCH4DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3420 DCH5CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
3430 DCH5ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
3440 DCH5INT
15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
3450 DCH5SSA CHSSA<31:0>
15:0 0000
31:16 0000
3460 DCH5DSA CHDSA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
3470 DCH5SSIZ
15:0 CHSSIZ<15:0> 0000
 2009-2019 Microchip Technology Inc.

31:16 — — — — — — — — — — — — — — — — 0000
3480 DCH5DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3490 DCH5SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
34A0 DCH5DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
34B0 DCH5CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
34C0 DCH5CPTR
15:0 CHCPTR<15:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
 TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)
 2009-2019 Microchip Technology Inc.

Virtual Address Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
34D0 DCH5DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
34E0 DCH6CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
34F0 DCH6ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
3500 DCH6INT
15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
3510 DCH6SSA CHSSA<31:0>
15:0 0000
31:16 0000
3520 DCH6DSA CHDSA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
3530 DCH6SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3540 DCH6DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3550 DCH6SPTR

PIC32MX5XX/6XX/7XX
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3560 DCH6DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3570 DCH6CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3580 DCH6CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3590 DCH6DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
35A0 DCH7CON
15:0 CHBUSY — — — — — — CHCHNS CHEN CHAED CHCHN CHAEN — CHEDET CHPRI<1:0> 0000
31:16 — — — — — — — — CHAIRQ<7:0> 00FF
35B0 DCH7ECON
15:0 CHSIRQ<7:0> CFORCE CABORT PATEN SIRQEN AIRQEN — — — FF00
31:16 — — — — — — — — CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE 0000
35C0 DCH7INT
DS60001156K-page 121

15:0 — — — — — — — — CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF 0000
31:16 0000
35D0 DCH7SSA CHSSA<31:0>
15:0 0000
31:16 0000
35E0 DCH7DSA CHDSA<31:0>
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
DS60001156K-page 122
TABLE 10-3: DMA CHANNELS 0-7 REGISTER MAP (CONTINUED)

PIC32MX5XX/6XX/7XX
Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
35F0 DCH7SSIZ
15:0 CHSSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3600 DCH7DSIZ
15:0 CHDSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3610 DCH7SPTR
15:0 CHSPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3620 DCH7DPTR
15:0 CHDPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3630 DCH7CSIZ
15:0 CHCSIZ<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3640 DCH7CPTR
15:0 CHCPTR<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
3650 DCH7DAT
15:0 — — — — — — — — CHPDAT<7:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: DMA channels 4-7 are not available on PIC32MX534/564/664/764 devices.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 10-1: DMACON: DMA CONTROLLER CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 U-0 U-0
15:8
ON(1) — — SUSPEND DMABUSY — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0
— — — — — — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: DMA On bit(1)
1 = DMA module is enabled
0 = DMA module is disabled
bit 14-13 Unimplemented: Read as ‘0’
bit 12 SUSPEND: DMA Suspend bit
1 = DMA transfers are suspended to allow CPU uninterrupted access to data bus
0 = DMA operates normally
bit 11 DMABUSY: DMA Module Busy bit
1 = DMA module is active
0 = DMA module is disabled and not actively transferring data
bit 10-0 Unimplemented: Read as ‘0’

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

 2009-2019 Microchip Technology Inc. DS60001156K-page 123

PIC32MX5XX/6XX/7XX
REGISTER 10-2: DMASTAT: DMA STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 R-0 R-0 R-0 R-0
7:0
— — — — RDWR DMACH<2:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3 RDWR: Read/Write Status bit
1 = Last DMA bus access was a read
0 = Last DMA bus access was a write
bit 2-0 DMACH<2:0>: DMA Channel bits
These bits contain the value of the most recent active DMA channel.

REGISTER 10-3: DMAADDR: DMA ADDRESS REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
DMAADDR<31:24>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
DMAADDR<23:16>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
DMAADDR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
DMAADDR<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DMAADDR<31:0>: DMA Module Address bits

These bits contain the address of the most recent DMA access.

DS60001156K-page 124  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0
31:24 (1)
— — BYTO<1:0> WBO — — BITO
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
— — — PLEN<4:0>
R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
7:0
CRCEN CRCAPP(1) CRCTYP — — CRCCH<2:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-30 Unimplemented: Read as ‘0’

bit 29-28 BYTO<1:0>: CRC Byte Order Selection bits
11 = Endian byte swap on half-word boundaries (source half-word order with reverse source byte order
per half-word)
10 = Swap half-words on word boundaries (reverse source half-word order with source byte order
per half-word)
01 = Endian byte swap on word boundaries (reverse source byte order)
00 = No swapping (source byte order)
bit 27 WBO: CRC Write Byte Order Selection bit(1)
1 = Source data is written to the destination re-ordered as defined by BYTO<1:0>
0 = Source data is written to the destination unaltered
bit 26-25 Unimplemented: Read as ‘0’
bit 24 BITO: CRC Bit Order Selection bit
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
1 = The IP header checksum is calculated Least Significant bit (LSb) first (reflected)
0 = The IP header checksum is calculated Most Significant bit (MSb) first (not reflected)

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = The LFSR CRC is calculated Least Significant bit first (reflected)
0 = The LFSR CRC is calculated Most Significant bit first (not reflected)
bit 23-13 Unimplemented: Read as ‘0’
bit 12-8 PLEN<4:0>: Polynomial Length bits(1)
When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
These bits are unused.

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

Denotes the length of the polynomial – 1.
bit 7 CRCEN: CRC Enable bit
1 = CRC module is enabled and channel transfers are routed through the CRC module
0 = CRC module is disabled and channel transfers proceed normally

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

 2009-2019 Microchip Technology Inc. DS60001156K-page 125

PIC32MX5XX/6XX/7XX
REGISTER 10-4: DCRCCON: DMA CRC CONTROL REGISTER (CONTINUED)
bit 6 CRCAPP: CRC Append Mode bit(1)
1 = The DMA transfers data from the source into the CRC but not to the destination. When a block transfer
completes the DMA writes the calculated CRC value to the location given by CHxDSA
0 = The DMA transfers data from the source through the CRC obeying WBO as it writes the data to the
destination
bit 5 CRCTYP: CRC Type Selection bit
1 = The CRC module will calculate an IP header checksum
0 = The CRC module will calculate a LFSR CRC
bit 4-3 Unimplemented: Read as ‘0’
bit 2-0 CRCCH<2:0>: CRC Channel Select bits
111 = CRC is assigned to Channel 7
110 = CRC is assigned to Channel 6
101 = CRC is assigned to Channel 5
100 = CRC is assigned to Channel 4
011 = CRC is assigned to Channel 3
010 = CRC is assigned to Channel 2
001 = CRC is assigned to Channel 1
000 = CRC is assigned to Channel 0

Note 1: When WBO = 1, unaligned transfers are not supported and the CRCAPP bit cannot be set.

DS60001156K-page 126  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 10-5: DCRCDATA: DMA CRC DATA REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
DCRCDATA<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
DCRCDATA<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
DCRCDATA<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
DCRCDATA<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DCRCDATA<31:0>: CRC Data Register bits

Writing to this register will seed the CRC generator. Reading from this register will return the current value of
the CRC. Bits greater than PLEN will return ‘0’ on any read.

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):

Only the lower 16 bits contain IP header checksum information. The upper 16 bits are always ‘0’. Data written
to this register is converted and read back in 1’s complement form (current IP header checksum value).

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

Bits greater than PLEN will return ‘0’ on any read.

REGISTER 10-6: DCRCXOR: DMA CRCXOR ENABLE REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
DCRCXOR<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
DCRCXOR<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
DCRCXOR<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
DCRCXOR<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 DCRCXOR<31:0>: CRC XOR Register bits

When CRCTYP (DCRCCON<15>) = 1 (CRC module is in IP Header mode):
This register is unused.

When CRCTYP (DCRCCON<15>) = 0 (CRC module is in LFSR mode):

1 = Enable the XOR input to the Shift register
0 = Disable the XOR input to the Shift register; data is shifted in directly from the previous stage in
the register

 2009-2019 Microchip Technology Inc. DS60001156K-page 127

PIC32MX5XX/6XX/7XX
REGISTER 10-7: DCHxCON: DMA CHANNEL ‘x’ CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
15:8
CHBUSY — — — — — — CHCHNS(1)
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R-0 R/W-0 R/W-0
7:0
CHEN(2) CHAED CHCHN CHAEN — CHEDET CHPRI<1:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 CHBUSY: Channel Busy bit
1 = Channel is active or has been enabled
0 = Channel is inactive or has been disabled
bit 14-9 Unimplemented: Read as ‘0’
bit 8 CHCHNS: Chain Channel Selection bit(1)
1 = Chain to channel lower in natural priority (CH1 will be enabled by CH2 transfer complete)
0 = Chain to channel higher in natural priority (CH1 will be enabled by CH0 transfer complete)
bit 7 CHEN: Channel Enable bit(2)
1 = Channel is enabled
0 = Channel is disabled
bit 6 CHAED: Channel Allow Events If Disabled bit
1 = Channel start/abort events will be registered, even if the channel is disabled
0 = Channel start/abort events will be ignored if the channel is disabled
bit CHCHN: Channel Chain Enable bit
1 = Allow channel to be chained
0 = Do not allow channel to be chained
bit 4 CHAEN: Channel Automatic Enable bit
1 = Channel is continuously enabled, and not automatically disabled after a block transfer is complete
0 = Channel is disabled on block transfer complete
bit 3 Unimplemented: Read as ‘0’
bit 2 CHEDET: Channel Event Detected bit
1 = An event has been detected
0 = No events have been detected
bit 1-0 CHPRI<1:0>: Channel Priority bits
11 = Channel has priority 3 (highest)
10 = Channel has priority 2
01 = Channel has priority 1
00 = Channel has priority 0

Note 1: The chain selection bit takes effect when chaining is enabled (CHCHN = 1).
2: When the channel is suspended by clearing this bit, the user application should poll the CHBUSY bit (if
available on the device variant) to see when the channel is suspended, as it may take some clock cycles
to complete a current transaction before the channel is suspended.

DS60001156K-page 128  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 10-8: DCHxECON: DMA CHANNEL ‘x’ EVENT CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
23:16 (1)
CHAIRQ<7:0>
R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1
15:8
CHSIRQ<7:0>(1)
S-0 S-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
7:0
CFORCE CABORT PATEN SIRQEN AIRQEN — — —

Legend: S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-16 CHAIRQ<7:0>: Channel Transfer Abort IRQ bits(1)
11111111 = Interrupt 255 will abort any transfers in progress and set CHAIF flag
•
•
•
00000001 = Interrupt 1 will abort any transfers in progress and set CHAIF flag
00000000 = Interrupt 0 will abort any transfers in progress and set CHAIF flag
bit 15-8 CHSIRQ<7:0>: Channel Transfer Start IRQ bits(1)
11111111 = Interrupt 255 will initiate a DMA transfer
•
•
•
00000001 = Interrupt 1 will initiate a DMA transfer
00000000 = Interrupt 0 will initiate a DMA transfer
bit 7 CFORCE: DMA Forced Transfer bit
1 = A DMA transfer is forced to begin when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 6 CABORT: DMA Abort Transfer bit
1 = A DMA transfer is aborted when this bit is written to a ‘1’
0 = This bit always reads ‘0’
bit 5 PATEN: Channel Pattern Match Abort Enable bit
1 = Abort transfer and clear CHEN on pattern match
0 = Pattern match is disabled
bit 4 SIRQEN: Channel Start IRQ Enable bit
1 = Start channel cell transfer if an interrupt matching CHSIRQ occurs
0 = Interrupt number CHSIRQ is ignored and does not start a transfer
bit 3 AIRQEN: Channel Abort IRQ Enable bit
1 = Channel transfer is aborted if an interrupt matching CHAIRQ occurs
0 = Interrupt number CHAIRQ is ignored and does not terminate a transfer
bit 2-0 Unimplemented: Read as ‘0’

Note 1: See Table 7-1: “Interrupt IRQ, Vector and Bit Location” for the list of available interrupt IRQ sources.

 2009-2019 Microchip Technology Inc. DS60001156K-page 129

PIC32MX5XX/6XX/7XX
REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CHSDIE CHSHIE CHDDIE CHDHIE CHBCIE CHCCIE CHTAIE CHERIE
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CHSDIF CHSHIF CHDDIF CHDHIF CHBCIF CHCCIF CHTAIF CHERIF

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23 CHSDIE: Channel Source Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 22 CHSHIE: Channel Source Half Empty Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 21 CHDDIE: Channel Destination Done Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 20 CHDHIE: Channel Destination Half Full Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 19 CHBCIE: Channel Block Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 18 CHCCIE: Channel Cell Transfer Complete Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 17 CHTAIE: Channel Transfer Abort Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 16 CHERIE: Channel Address Error Interrupt Enable bit
1 = Interrupt is enabled
0 = Interrupt is disabled
bit 15-8 Unimplemented: Read as ‘0’
bit 7 CHSDIF: Channel Source Done Interrupt Flag bit
1 = Channel Source Pointer has reached end of source (CHSPTR = CHSSIZ)
0 = No interrupt is pending
bit 6 CHSHIF: Channel Source Half Empty Interrupt Flag bit
1 = Channel Source Pointer has reached midpoint of source (CHSPTR = CHSSIZ/2)
0 = No interrupt is pending

DS60001156K-page 130  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 10-9: DCHxINT: DMA CHANNEL ‘x’ INTERRUPT CONTROL REGISTER (CONTINUED)
bit 5 CHDDIF: Channel Destination Done Interrupt Flag bit
1 = Channel Destination Pointer has reached end of destination (CHDPTR = CHDSIZ)
0 = No interrupt is pending
bit 4 CHDHIF: Channel Destination Half Full Interrupt Flag bit
1 = Channel Destination Pointer has reached midpoint of destination (CHDPTR = CHDSIZ/2)
0 = No interrupt is pending
bit 3 CHBCIF: Channel Block Transfer Complete Interrupt Flag bit
1 = A block transfer has been completed (the larger of CHSSIZ/CHDSIZ bytes has been transferred), or a
pattern match event occurs
0 = No interrupt is pending
bit 2 CHCCIF: Channel Cell Transfer Complete Interrupt Flag bit
1 = A cell transfer has been completed (CHCSIZ bytes have been transferred)
0 = No interrupt is pending
bit 1 CHTAIF: Channel Transfer Abort Interrupt Flag bit
1 = An interrupt matching CHAIRQ has been detected and the DMA transfer has been aborted
0 = No interrupt is pending
bit 0 CHERIF: Channel Address Error Interrupt Flag bit
1 = A channel address error has been detected (either the source or the destination address is invalid)
0 = No interrupt is pending

 2009-2019 Microchip Technology Inc. DS60001156K-page 131

PIC32MX5XX/6XX/7XX
REGISTER 10-10: DCHxSSA: DMA CHANNEL ‘x’ SOURCE START ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
CHSSA<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CHSSA<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CHSSA<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CHSSA<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHSSA<31:0> Channel Source Start Address bits

Channel source start address.
Note: This must be the physical address of the source.

REGISTER 10-11: DCHxDSA: DMA CHANNEL ‘x’ DESTINATION START ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
CHDSA<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CHDSA<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CHDSA<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CHDSA<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CHDSA<31:0>: Channel Destination Start Address bits

Channel destination start address.
Note: This must be the physical address of the destination.

DS60001156K-page 132  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 10-12: DCHxSSIZ: DMA CHANNEL ‘x’ SOURCE SIZE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CHSSIZ<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CHSSIZ<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHSSIZ<15:0>: Channel Source Size bits
1111111111111111 = 65,535 byte source size
•
•
•
0000000000000010 = 2 byte source size
0000000000000001 = 1 byte source size
0000000000000000 = 65,536 byte source size

REGISTER 10-13: DCHxDSIZ: DMA CHANNEL ‘x’ DESTINATION SIZE REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CHDSIZ<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CHDSIZ<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHDSIZ<15:0>: Channel Destination Size bits
1111111111111111 = 65,535 byte destination size
•
•
•
0000000000000010 = 2 byte destination size
0000000000000001 = 1 byte destination size
0000000000000000 = 65,536 byte destination size

 2009-2019 Microchip Technology Inc. DS60001156K-page 133

PIC32MX5XX/6XX/7XX
REGISTER 10-14: DCHxSPTR: DMA CHANNEL ‘x’ SOURCE POINTER REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
CHSPTR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
CHSPTR<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHSPTR<15:0>: Channel Source Pointer bits
1111111111111111 = Points to byte 65,535 of the source
•
•
•
0000000000000001 = Points to byte 1 of the source
0000000000000000 = Points to byte 0 of the source

Note: When in Pattern Detect mode, this register is reset on a pattern detect.

REGISTER 10-15: DCHxDPTR: DMA CHANNEL ‘x’ DESTINATION POINTER REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
CHDPTR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
CHDPTR<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHDPTR<15:0>: Channel Destination Pointer bits
1111111111111111 = Points to byte 65,535 of the destination
•
•
•
0000000000000001 = Points to byte 1 of the destination
0000000000000000 = Points to byte 0 of the destination

DS60001156K-page 134  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 10-16: DCHxCSIZ: DMA CHANNEL ‘x’ CELL-SIZE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CHCSIZ<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CHCSIZ<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHCSIZ<15:0>: Channel Cell-Size bits
1111111111111111 = 65,535 bytes transferred on an event
•
•
•
0000000000000010 = 2 bytes transferred on an event
0000000000000001 = 1 byte transferred on an event
0000000000000000 = 65,536 bytes transferred on an event

REGISTER 10-17: DCHxCPTR: DMA CHANNEL ‘x’ CELL POINTER REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
CHCPTR<15:8>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
CHCPTR<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CHCPTR<7:0>: Channel Cell Progress Pointer bits
1111111111111111 = 65,535 bytes have been transferred since the last event
•
•
•
0000000000000001 = 1 byte has been transferred since the last event
0000000000000000 = 0 bytes have been transferred since the last event

Note: When in Pattern Detect mode, this register is reset on a pattern detect.

 2009-2019 Microchip Technology Inc. DS60001156K-page 135

PIC32MX5XX/6XX/7XX
REGISTER 10-18: DCHxDAT: DMA CHANNEL ‘x’ PATTERN DATA REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CHPDAT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 CHPDAT<7:0>: Channel Data Register bits
Pattern Terminate mode:
Data to be matched must be stored in this register to allow terminate on match.

All other modes:

Unused.

DS60001156K-page 136  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
11.0 USB ON-THE-GO (OTG) The clock generator provides the 48 MHz clock
required for USB full-speed and low-speed communi-
Note: This data sheet summarizes the features cation. The voltage comparators monitor the voltage on
of the PIC32MX5XX/6XX/7XX family of the VBUS pin to determine the state of the bus. The
devices. It is not intended to be a transceiver provides the analog translation between
comprehensive reference source. To the USB bus and the digital logic. The SIE is a state
complement the information in this data machine that transfers data to and from the endpoint
sheet, refer to Section 27. “USB On-The- buffers and generates the hardware protocol for data
Go (OTG)” (DS60001126) in the “PIC32 transfers. The USB DMA controller transfers data
Family Reference Manual”, which is avail- between the data buffers in RAM and the SIE. The inte-
able from the Microchip web site grated pull-up and pull-down resistors eliminate the
(www.microchip.com/PIC32). need for external signaling components. The register
interface allows the CPU to configure and
The Universal Serial Bus (USB) module contains communicate with the module.
analog and digital components to provide a USB 2.0
full-speed and low-speed embedded Host, full-speed The USB module includes the following features:
Device or OTG implementation with a minimum of • USB Full-speed support for host and device
external components. This module in Host mode is • Low-speed host support
intended for use as an embedded host and therefore • USB OTG support
does not implement a UHCI or OHCI controller.
• Integrated signaling resistors
The USB module consists of the clock generator, the • Integrated analog comparators for VBUS
USB voltage comparators, the transceiver, the Serial monitoring
Interface Engine (SIE), a dedicated USB DMA control-
• Integrated USB transceiver
ler, pull-up and pull-down resistors, and the register
interface. A block diagram of the PIC32 USB OTG • Transaction handshaking performed by hardware
module is presented in Figure 11-1. • Endpoint buffering anywhere in system RAM
• Integrated DMA to access system RAM and Flash
Note: The implementation and use of the USB
specifications, as well as other third party
specifications or technologies, may
require licensing; including, but not limited
to, USB Implementers Forum, Inc. (also
referred to as USB-IF). The user is fully
responsible for investigating and
satisfying any applicable licensing
obligations.

 2009-2019 Microchip Technology Inc. DS60001156K-page 137

PIC32MX5XX/6XX/7XX
FIGURE 11-1: PIC32MX5XX/6XX/7XX FAMILY USB INTERFACE DIAGRAM

USBEN
FRC
USB Suspend Oscillator
8 MHz Typical

CPU Clock Not POSC

Sleep TUN<5:0>(4)

Primary Oscillator
(POSC)
UFIN(5)
Div x PLL Div 2
UFRCEN(3)
OSC1
UPLLIDIV(6) UPLLEN(6)
USB Suspend To Clock Generator for Core and Peripherals
OSC2 Sleep or Idle
(PB Out)(1)
USB Module

USB
SRP Charge Voltage
Bus Comparators
SRP Discharge

48 MHz USB Clock(7)

Full-Speed Pull-up

D+(2)
Registers
and
Control
Host Pull-down Interface
SIE
Transceiver
Low-Speed Pull-up

D-(2)
DMA System
RAM
Host Pull-down

ID Pull-up

ID(8)

VBUSON(8)

VUSB3V3 Transceiver Power 3.3V

Note 1: PB clock is only available on this pin for select EC modes.

2: Pins can be used as digital inputs when USB is not enabled.
3: This bit field is contained in the OSCCON register.
4: This bit field is contained in the OSCTRM register.
5: USB PLL UFIN requirements: 4 MHz.
6: This bit field is contained in the DEVCFG2 register.
7: A 48 MHz clock is required for proper USB operation.
8: Pins can be used as GPIO when the USB module is disabled.

DS60001156K-page 138  2009-2019 Microchip Technology Inc.

 11.1 Control Registers
 2009-2019 Microchip Technology Inc.

TABLE 11-1:
Virtual Address
USB REGISTER MAP
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
5040 U1OTGIR(2)
15:0 — — — — — — — — IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5050 U1OTGIE
15:0 — — — — — — — — IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE 0000
31:16 — — — — — — — — — — — — — — — — 0000
5060 U1OTGSTAT(3)
15:0 — — — — — — — — ID — LSTATE — SESVD SESEND — VBUSVD 0000
31:16 — — — — — — — — — — — — — — — — 0000
5070 U1OTGCON
15:0 — — — — — — — — DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS 0000
31:16 — — — — — — — — — — — — — — — — 0000
5080 U1PWRC
15:0 — — — — — — — — UACTPND(4) — — USLPGRD USBBUSY — USUSPEND USBPWR 0000
31:16 — — — — — — — — — — — — — — — — 0000
5200 U1IR(2) URSTIF 0000
15:0 — — — — — — — — STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF
DETACHIF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5210 U1IE URSTIE 0000

PIC32MX5XX/6XX/7XX
15:0 — — — — — — — — STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE
DETACHIE 0000
31:16 — — — — — — — — — — — — — — — — 0000
5220 U1EIR(2) CRC5EF 0000
15:0 — — — — — — — — BTSEF BMXEF DMAEF BTOEF DFN8EF CRC16EF PIDEF
EOFEF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5230 U1EIE CRC5EE 0000
15:0 — — — — — — — — BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE PIDEE
EOFEE 0000
31:16 — — — — — — — — — — — — — — — — 0000
5240 U1STAT(3)
15:0 — — — — — — — — ENDPT<3:0>(4) DIR PPBI — — 0000
31:16 — — — — — — — — — — — — — — — — 0000
5250 U1CON (4) (4) PKTDIS USBEN 0000
15:0 — — — — — — — — JSTATE SE0 USBRST HOSTEN RESUME PPBRST
TOKBUSY SOFEN 0000
31:16 — — — — — — — — — — — — — — — — 0000
5260 U1ADDR
15:0 — — — — — — — — LSPDEN DEVADDR<6:0> 0000
DS60001156K-page 139

31:16 — — — — — — — — — — — — — — — — 0000
5270 U1BDTP1
15:0 — — — — — — — — BDTPTRL<7:1> — 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
2: This register does not have associated SET and INV registers.
3: This register does not have associated CLR, SET and INV registers.
4: Reset value for this bit is undefined.
DS60001156K-page 140
TABLE 11-1: USB REGISTER MAP (CONTINUED)

PIC32MX5XX/6XX/7XX
Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
5280 U1FRML(3)
15:0 — — — — — — — — FRML<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5290 U1FRMH(3)
15:0 — — — — — — — — — — — — — FRMH<2:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52A0 U1TOK
15:0 — — — — — — — — PID<3:0> EP<3:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52B0 U1SOF
15:0 — — — — — — — — CNT<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52C0 U1BDTP2
15:0 — — — — — — — — BDTPTRH<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52D0 U1BDTP3
15:0 — — — — — — — — BDTPTRU<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
52E0 U1CNFG1
15:0 — — — — — — — — UTEYE UOEMON — USBSIDL — — — UASUSPND 0001
31:16 — — — — — — — — — — — — — — — — 0000
5300 U1EP0
15:0 — — — — — — — — LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5310 U1EP1
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5320 U1EP2
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5330 U1EP3
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5340 U1EP4
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5350 U1EP5
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
 2009-2019 Microchip Technology Inc.

31:16 — — — — — — — — — — — — — — — — 0000
5360 U1EP6
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5370 U1EP7
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5380 U1EP8
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
5390 U1EP9
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
2: This register does not have associated SET and INV registers.
3: This register does not have associated CLR, SET and INV registers.
4: Reset value for this bit is undefined.
 TABLE 11-1: USB REGISTER MAP (CONTINUED)
 2009-2019 Microchip Technology Inc.

Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
53A0 U1EP10
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
53B0 U1EP11
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
53C0 U1EP12
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
53D0 U1EP13
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
53E0 U1EP14
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
31:16 — — — — — — — — — — — — — — — — 0000
53F0 U1EP15
15:0 — — — — — — — — — — — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (except as noted) have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC respectively. See Section 12.1.1 “CLR, SET and INV Registers” for
more information.
2: This register does not have associated SET and INV registers.
3: This register does not have associated CLR, SET and INV registers.
4: Reset value for this bit is undefined.

PIC32MX5XX/6XX/7XX
DS60001156K-page 141
PIC32MX5XX/6XX/7XX
REGISTER 11-1: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS U-0 R/WC-0, HS
7:0
IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF — VBUSVDIF

Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 IDIF: ID State Change Indicator bit
1 = Change in ID state detected
0 = No change in ID state detected
bit 6 T1MSECIF: 1 Millisecond Timer bit
1 = 1 millisecond timer has expired
0 = 1 millisecond timer has not expired
bit 5 LSTATEIF: Line State Stable Indicator bit
1 = USB line state has been stable for 1 ms, but different from last time
0 = USB line state has not been stable for 1 ms
bit 4 ACTVIF: Bus Activity Indicator bit
1 = Activity on the D+, D-, ID or VBUS pins has caused the device to wake-up
0 = Activity has not been detected
bit 3 SESVDIF: Session Valid Change Indicator bit
1 = VBUS voltage has dropped below the session end level
0 = VBUS voltage has not dropped below the session end level
bit 2 SESENDIF: B-Device VBUS Change Indicator bit
1 = A change on the session end input was detected
0 = No change on the session end input was detected
bit 1 Unimplemented: Read as ‘0’
bit 0 VBUSVDIF: A-Device VBUS Change Indicator bit
1 = Change on the session valid input detected
0 = No change on the session valid input detected

DS60001156K-page 142  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 11-2: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0
7:0
IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE — VBUSVDIE

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 IDIE: ID Interrupt Enable bit
1 = ID interrupt enabled
0 = ID interrupt disabled
bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit
1 = 1 millisecond timer interrupt enabled
0 = 1 millisecond timer interrupt disabled
bit 5 LSTATEIE: Line State Interrupt Enable bit
1 = Line state interrupt enabled
0 = Line state interrupt disabled
bit 4 ACTVIE: Bus ACTIVITY Interrupt Enable bit
1 = ACTIVITY interrupt enabled
0 = ACTIVITY interrupt disabled
bit 3 SESVDIE: Session Valid Interrupt Enable bit
1 = Session valid interrupt enabled
0 = Session valid interrupt disabled
bit 2 SESENDIE: B-Session End Interrupt Enable bit
1 = B-session end interrupt enabled
0 = B-session end interrupt disabled
bit 1 Unimplemented: Read as ‘0’
bit 0 VBUSVDIE: A-VBUS Valid Interrupt Enable bit
1 = A-VBUS valid interrupt enabled
0 = A-VBUS valid interrupt disabled

 2009-2019 Microchip Technology Inc. DS60001156K-page 143

PIC32MX5XX/6XX/7XX
REGISTER 11-3: U1OTGSTAT: USB OTG STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R-0 U-0 R-0 U-0 R-0 R-0 U-0 R-0
7:0
ID — LSTATE — SESVD SESEND — VBUSVD

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 ID: ID Pin State Indicator bit
1 = No cable is attached or a “type B” cable has been inserted into the USB receptacle
0 = A “type A” OTG cable has been inserted into the USB receptacle
bit 6 Unimplemented: Read as ‘0’
bit 5 LSTATE: Line State Stable Indicator bit
1 = USB line state (SE0 (U1CON<6> and JSTATE (U1CON<7>) has been stable for the previous 1 ms
0 = USB line state (SE0 (U1CON<6> and JSTATE (U1CON<7>) has not been stable for the previous 1 ms
bit 4 Unimplemented: Read as ‘0’
bit 3 SESVD: Session Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A or B device
0 = VBUS voltage is below Session Valid on the A or B device
bit 2 SESEND: B-Device Session End Indicator bit
1 = VBUS voltage is below Session Valid on the B device
0 = VBUS voltage is above Session Valid on the B device
bit 1 Unimplemented: Read as ‘0’
bit 0 VBUSVD: A-Device VBUS Valid Indicator bit
1 = VBUS voltage is above Session Valid on the A device
0 = VBUS voltage is below Session Valid on the A device

DS60001156K-page 144  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 11-4: U1OTGCON: USB OTG CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
DPPULUP DMPULUP DPPULDWN DMPULDWN VBUSON OTGEN VBUSCHG VBUSDIS

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 DPPULUP: D+ Pull-Up Enable bit
1 = D+ data line pull-up resistor is enabled
0 = D+ data line pull-up resistor is disabled
bit 6 DMPULUP: D- Pull-Up Enable bit
1 = D- data line pull-up resistor is enabled
0 = D- data line pull-up resistor is disabled
bit 5 DPPULDWN: D+ Pull-Down Enable bit
1 = D+ data line pull-down resistor is enabled
0 = D+ data line pull-down resistor is disabled
bit 4 DMPULDWN: D- Pull-Down Enable bit
1 = D- data line pull-down resistor is enabled
0 = D- data line pull-down resistor is disabled
bit 3 VBUSON: VBUS Power-on bit
1 = VBUS line is powered
0 = VBUS line is not powered
bit 2 OTGEN: OTG Functionality Enable bit
1 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under software control
0 = DPPULUP, DMPULUP, DPPULDWN and DMPULDWN bits are under USB hardware control
bit 1 VBUSCHG: VBUS Charge Enable bit
1 = VBUS line is charged through a pull-up resistor
0 = VBUS line is not charged through a resistor
bit 0 VBUSDIS: VBUS Discharge Enable bit
1 = VBUS line is discharged through a pull-down resistor
0 = VBUS line is not discharged through a resistor

 2009-2019 Microchip Technology Inc. DS60001156K-page 145

PIC32MX5XX/6XX/7XX
REGISTER 11-5: U1PWRC: USB POWER CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R-0 U-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
7:0
UACTPND — — USLPGRD USBBUSY — USUSPEND USBPWR

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 UACTPND: USB Activity Pending bit
1 = USB bus activity has been detected; but an interrupt is pending, it has not been generated yet
0 = An interrupt is not pending
bit 6-5 Unimplemented: Read as ‘0’
bit 4 USLPGRD: USB Sleep Entry Guard bit
1 = Sleep entry is blocked if USB bus activity is detected or if a notification is pending
0 = USB module does not block Sleep entry
bit 3 USBBUSY: USB Module Busy bit
1 = USB module is active or disabled, but not ready to be enabled
0 = USB module is not active and is ready to be enabled
Note: When USBPWR = 0 and USBBUSY = 1, status from all other registers is invalid and writes to all
USB module registers produce undefined results.
bit 2 Unimplemented: Read as ‘0’
bit 1 USUSPEND: USB Suspend Mode bit
1 = USB module is placed in Suspend mode
(The 48 MHz USB clock will be gated off. The transceiver is placed in a low-power state.)
0 = USB module operates normally
bit 0 USBPWR: USB Operation Enable bit
1 = USB module is turned on
0 = USB module is disabled
(Outputs held inactive, device pins not used by USB, analog features are shut down to reduce power
consumption.)

DS60001156K-page 146  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 11-6: U1IR: USB INTERRUPT REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R-0 R/WC-0, HS
(5)
7:0 URSTIF
STALLIF ATTACHIF(1) RESUMEIF(2) IDLEIF TRNIF(3) SOFIF UERRIF(4)
DETACHIF(6)

Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 STALLIF: STALL Handshake Interrupt bit
1 = In Host mode a STALL handshake was received during the handshake phase of the transaction. In
Device mode, a STALL handshake was transmitted during the handshake phase of the transaction.
0 = STALL handshake has not been sent
bit 6 ATTACHIF: Peripheral Attach Interrupt bit(1)
1 = Peripheral attachment was detected by the USB module
0 = Peripheral attachment was not detected
bit 5 RESUMEIF: Resume Interrupt bit(2)
1 = K-State is observed on the D+ or D- pin for 2.5 µs
0 = K-State is not observed
bit 4 IDLEIF: Idle Detect Interrupt bit
1 = Idle condition detected (constant Idle state of 3 ms or more)
0 = No Idle condition detected
bit 3 TRNIF: Token Processing Complete Interrupt bit(3)
1 = Processing of current token is complete; a read of the U1STAT register will provide endpoint information
0 = Processing of current token not complete
bit 2 SOFIF: SOF Token Interrupt bit
1 = SOF token received by the peripheral or the SOF threshold reached by the host
0 = SOF token was not received nor threshold reached
bit 1 UERRIF: USB Error Condition Interrupt bit(4)
1 = Unmasked error condition has occurred
0 = Unmasked error condition has not occurred
bit 0 URSTIF: USB Reset Interrupt bit (Device mode)(5)
1 = Valid USB Reset has occurred
0 = No USB Reset has occurred
DETACHIF: USB Detach Interrupt bit (Host mode)(6)
1 = Peripheral detachment was detected by the USB module
0 = Peripheral detachment was not detected

Note 1: This bit is only valid if the HOSTEN bit is set (see Register 11-11), there is no activity on the USB for
2.5 µs, and the current bus state is not SE0.
2: When not in Suspend mode, this interrupt should be disabled.
3: Clearing this bit will cause the STAT FIFO to advance.
4: Only error conditions enabled through the U1EIE register will set this bit.
5: Device mode.
6: Host mode.

 2009-2019 Microchip Technology Inc. DS60001156K-page 147

PIC32MX5XX/6XX/7XX
REGISTER 11-7: U1IE: USB INTERRUPT ENABLE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7:0 URSTIE(2)
STALLIE ATTACHIE RESUMEIE IDLEIE TRNIE SOFIE UERRIE(1)
DETACHIE(3)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 STALLIE: STALL Handshake Interrupt Enable bit
1 = STALL interrupt is enabled
0 = STALL interrupt is disabled
bit 6 ATTACHIE: ATTACH Interrupt Enable bit
1 = ATTACH interrupt is enabled
0 = ATTACH interrupt is disabled
bit 5 RESUMEIE: RESUME Interrupt Enable bit
1 = RESUME interrupt is enabled
0 = RESUME interrupt is disabled
bit 4 IDLEIE: Idle Detect Interrupt Enable bit
1 = Idle interrupt is enabled
0 = Idle interrupt is disabled
bit 3 TRNIE: Token Processing Complete Interrupt Enable bit
1 = TRNIF interrupt is enabled
0 = TRNIF interrupt is disabled
bit 2 SOFIE: SOF Token Interrupt Enable bit
1 = SOFIF interrupt is enabled
0 = SOFIF interrupt is disabled
bit 1 UERRIE: USB Error Interrupt Enable bit(1)
1 = USB Error interrupt is enabled
0 = USB Error interrupt is disabled
bit 0 URSTIE: USB Reset Interrupt Enable bit(2)
1 = URSTIF interrupt is enabled
0 = URSTIF interrupt is disabled
DETACHIE: USB Detach Interrupt Enable bit(3)
1 = DATTCHIF interrupt is enabled
0 = DATTCHIF interrupt is disabled

Note 1: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.
2: Device mode.
3: Host mode.

DS60001156K-page 148  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 11-8: U1EIR: USB ERROR INTERRUPT STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS R/WC-0, HS
(4)
7:0 CRC5EF
BTSEF BMXEF DMAEF(1) BTOEF(2) DFN8EF CRC16EF PIDEF
EOFEF(3,5)

Legend: WC = Write ‘1’ to clear HS = Hardware Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 BTSEF: Bit Stuff Error Flag bit
1 = Packet is rejected due to bit stuff error
0 = Packet is accepted
bit 6 BMXEF: Bus Matrix Error Flag bit
1 = Invalid base address of the BDT, or the address of an individual buffer pointed to by a BDT entry
0 = No address error
bit 5 DMAEF: DMA Error Flag bit(1)
1 = USB DMA error condition detected
0 = No DMA error
bit 4 BTOEF: Bus Turnaround Time-Out Error Flag bit(2)
1 = Bus turnaround time-out has occurred
0 = No bus turnaround time-out
bit 3 DFN8EF: Data Field Size Error Flag bit
1 = Data field received is not an integral number of bytes
0 = Data field received is an integral number of bytes
bit 2 CRC16EF: CRC16 Failure Flag bit
1 = Data packet is rejected due to CRC16 error
0 = Data packet is accepted
bit 1 CRC5EF: CRC5 Host Error Flag bit(4)
1 = Token packet is rejected due to CRC5 error
0 = Token packet is accepted
EOFEF: EOF Error Flag bit(3,5)
1 = EOF error condition is detected
0 = No EOF error condition
bit 0 PIDEF: PID Check Failure Flag bit
1 = PID check is failed
0 = PID check is passed

Note 1: This type of error occurs when the module’s request for the DMA bus is not granted in time to service the
module’s demand for memory, resulting in an overflow or underflow condition, and/or the allocated buffer
size is not sufficient to store the received data packet causing it to be truncated.
2: This type of error occurs when more than 16-bit-times of Idle from the previous End-of-Packet (EOP)
has elapsed.
3: This type of error occurs when the module is transmitting or receiving data and the SOF counter has
reached zero.
4: Device mode.
5: Host mode.

 2009-2019 Microchip Technology Inc. DS60001156K-page 149

PIC32MX5XX/6XX/7XX
REGISTER 11-9: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0 CRC5EE(1)
BTSEE BMXEE DMAEE BTOEE DFN8EE CRC16EE PIDEE
EOFEE(2)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit
1 = BTSEF interrupt is enabled
0 = BTSEF interrupt is disabled
bit 6 BMXEE: Bus Matrix Error Interrupt Enable bit
1 = BMXEF interrupt is enabled
0 = BMXEF interrupt is disabled
bit 5 DMAEE: DMA Error Interrupt Enable bit
1 = DMAEF interrupt is enabled
0 = DMAEF interrupt is disabled
bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit
1 = BTOEF interrupt is enabled
0 = BTOEF interrupt is disabled
bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit
1 = DFN8EF interrupt is enabled
0 = DFN8EF interrupt is disabled
bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit
1 = CRC16EF interrupt is enabled
0 = CRC16EF interrupt is disabled
bit 1 CRC5EE: CRC5 Host Error Interrupt Enable bit(1)
1 = CRC5EF interrupt is enabled
0 = CRC5EF interrupt is disabled
EOFEE: EOF Error Interrupt Enable bit(2)
1 = EOF interrupt is enabled
0 = EOF interrupt is disabled
bit 0 PIDEE: PID Check Failure Interrupt Enable bit
1 = PIDEF interrupt is enabled
0 = PIDEF interrupt is disabled

Note 1: Device mode.

2: Host mode.

Note: For an interrupt to propagate USBIF, the UERRIE bit (U1IE<1>) must be set.

DS60001156K-page 150  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 11-10: U1STAT: USB STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R-x R-x R-x R-x R-x R-x U-0 U-0
7:0
ENDPT<3:0> DIR PPBI — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-4 ENDPT<3:0>: Encoded Number of Last Endpoint Activity bits
(Represents the number of the BDT, updated by the last USB transfer.)
1111 = Endpoint 15
1110 = Endpoint 14
•
•
•
0001 = Endpoint 1
0000 = Endpoint 0
bit 3 DIR: Last Buffer Descriptor Direction Indicator bit
1 = Last transaction was a transmit transfer (TX)
0 = Last transaction was a receive transfer (RX)
bit 2 PPBI: Ping-Pong Buffer Descriptor Pointer Indicator bit
1 = The last transaction was to the Odd buffer descriptor bank
0 = The last transaction was to the Even buffer descriptor bank
bit 1-0 Unimplemented: Read as ‘0’

Note: The U1STAT register is a window into a 4-byte FIFO maintained by the USB module. U1STAT value is only
valid when U1IR<TRNIF> is active. Clearing the U1IR<TRNIF> bit advances the FIFO. Data in register is
invalid when U1IR<TRNIF> = 0.

 2009-2019 Microchip Technology Inc. DS60001156K-page 151

PIC32MX5XX/6XX/7XX
REGISTER 11-11: U1CON: USB CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R-x R-x R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7:0 PKTDIS(4) USBEN(4)

JSTATE SE0 USBRST HOSTEN(2) RESUME(3) PPBRST
TOKBUSY(1,5) SOFEN(5)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 JSTATE: Live Differential Receiver JSTATE flag bit
1 = JSTATE was detected on the USB
0 = JSTATE was not detected
bit 6 SE0: Live Single-Ended Zero flag bit
1 = Single-ended zero was detected on the USB
0 = Single-ended zero was not detected
bit 5 PKTDIS: Packet Transfer Disable bit(4)
1 = Token and packet processing disabled (set upon SETUP token received)
0 = Token and packet processing enabled
TOKBUSY: Token Busy Indicator bit(1,5)
1 = Token being executed by the USB module
0 = No token being executed
bit 4 USBRST: Module Reset bit(5)
1 = USB reset is generated
0 = USB reset is terminated
bit 3 HOSTEN: Host Mode Enable bit(2)
1 = USB host capability is enabled
0 = USB host capability is disabled
bit 2 RESUME: RESUME Signaling Enable bit(3)
1 = RESUME signaling is activated
0 = RESUME signaling is disabled

Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 11-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to
enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME
signaling when this bit is cleared.
4: Device mode.
5: Host mode.

DS60001156K-page 152  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 11-11: U1CON: USB CONTROL REGISTER (CONTINUED)
bit 1 PPBRST: Ping-Pong Buffers Reset bit
1 = Reset all Even/Odd buffer pointers to the Even buffer descriptor banks
0 = Even/Odd buffer pointers are not reset
bit 0 USBEN: USB Module Enable bit(4)
1 = USB module and supporting circuitry is enabled
0 = USB module and supporting circuitry is disabled
SOFEN: SOF Enable bit(5)
1 = SOF token is sent every 1 ms
0 = SOF token is disabled

Note 1: Software is required to check this bit before issuing another token command to the U1TOK register (see
Register 11-15).
2: All host control logic is reset any time that the value of this bit is toggled.
3: Software must set RESUME for 10 ms in Device mode, or for 25 ms in Host mode, and then clear it to
enable remote wake-up. In Host mode, the USB module will append a low-speed EOP to the RESUME
signaling when this bit is cleared.
4: Device mode.
5: Host mode.

 2009-2019 Microchip Technology Inc. DS60001156K-page 153

PIC32MX5XX/6XX/7XX
REGISTER 11-12: U1ADDR: USB ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
LSPDEN DEVADDR<6:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 LSPDEN: Low-Speed Enable Indicator bit
1 = Next token command to be executed at low-speed
0 = Next token command to be executed at full-speed
bit 6-0 DEVADDR<6:0>: 7-bit USB Device Address bits

REGISTER 11-13: U1FRML: USB FRAME NUMBER LOW REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
FRML<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 FRML<7:0>: 11-bit Frame Number Lower bits
The register bits are updated with the current frame number whenever a SOF TOKEN is received.

DS60001156K-page 154  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 11-14: U1FRMH: USB FRAME NUMBER HIGH REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
7:0
— — — — — FRMH<2:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-3 Unimplemented: Read as ‘0’

bit 2-0 FRMH<2:0>: Upper 3 bits of the Frame Numbers bits
These register bits are updated with the current frame number whenever a SOF TOKEN is received.

REGISTER 11-15: U1TOK: USB TOKEN REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
PID<3:0> EP<3:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-4 PID<3:0>: Token Type Indicator bits(1)
1101 = SETUP (TX) token type transaction
1001 = IN (RX) token type transaction
0001 = OUT (TX) token type transaction
Note: All other values not listed, are Reserved and must not be used.
bit 3-0 EP<3:0>: Token Command Endpoint Address bits
The four bit value must specify a valid endpoint.

 2009-2019 Microchip Technology Inc. DS60001156K-page 155

PIC32MX5XX/6XX/7XX
REGISTER 11-16: U1SOF: USB SOF THRESHOLD REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CNT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 CNT<7:0>: SOF Threshold Value bits
Typical values of the threshold are:
01001010 = 64-byte packet
00101010 = 32-byte packet
00011010 = 16-byte packet
00010010 = 8-byte packet

REGISTER 11-17: U1BDTP1: USB BUFFER DESCRIPTOR TABLE PAGE 1 REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0
7:0
BDTPTRL<15:9> —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-1 BDTPTRL<15:9>: BDT Base Address bits
This 7-bit value provides address bits 15 through 9 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.
bit 0 Unimplemented: Read as ‘0’

DS60001156K-page 156  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 11-18: U1BDTP2: USB BUFFER DESCRIPTOR TABLE PAGE 2 REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
BDTPTRH<23:16>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 BDTPTRH<23:16>: BDT Base Address bits
This 8-bit value provides address bits 23 through 16 of the BDT base address, which defines the starting
location of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.

REGISTER 11-19: U1BDTP3: USB BUFFER DESCRIPTOR TABLE PAGE 3 REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
BDTPTRU<31:24>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7-0 BDTPTRU<31:24>: BDT Base Address bits
This 8-bit value provides address bits 31 through 24 of the BDT base address, defines the starting location
of the BDT in system memory.
The 32-bit BDT base address is 512-byte aligned.

 2009-2019 Microchip Technology Inc. DS60001156K-page 157

PIC32MX5XX/6XX/7XX
REGISTER 11-20: U1CNFG1: USB CONFIGURATION 1 REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0
7:0
UTEYE UOEMON — USBSIDL — — — UASUSPND

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 UTEYE: USB Eye-Pattern Test Enable bit
1 = Eye-Pattern Test is enabled
0 = Eye-Pattern Test is disabled
bit 6 UOEMON: USB OE Monitor Enable bit
1 = OE signal is active; it indicates intervals during which the D+/D- lines are driving
0 = OE signal is inactive
bit 5 Unimplemented: Read as ‘0’
bit 4 USBSIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 3-1 Unimplemented: Read as ‘0’
bit 0 UASUSPND: Automatic Suspend Enable bit
1 = USB module automatically suspends upon entry to Sleep mode. See the USUSPEND bit
(U1PWRC<1>) in Register 11-5.
0 = USB module does not automatically suspend upon entry to Sleep mode. Software must use the
USUSPEND bit (U1PWRC<1>) to suspend the module, including the USB 48 MHz clock.

DS60001156K-page 158  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 11-21: U1EP0-U1EP15: USB ENDPOINT CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
LSPD RETRYDIS — EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-8 Unimplemented: Read as ‘0’

bit 7 LSPD: Low-Speed Direct Connection Enable bit (Host mode and U1EP0 only)
1 = Direct connection to a low-speed device enabled
0 = Direct connection to a low-speed device disabled; hub required with PRE_PID
bit 6 RETRYDIS: Retry Disable bit (Host mode and U1EP0 only)
1 = Retry NACK’d transactions disabled
0 = Retry NACK’d transactions enabled; retry done in hardware
bit 5 Unimplemented: Read as ‘0’
bit 4 EPCONDIS: Bidirectional Endpoint Control bit
If EPTXEN = 1 and EPRXEN = 1:
1 = Disable Endpoint ‘n’ from control transfers; only TX and RX transfers are allowed
0 = Enable Endpoint ‘n’ for control (SETUP) transfers; TX and RX transfers are also allowed
Otherwise, this bit is ignored.
bit 3 EPRXEN: Endpoint Receive Enable bit
1 = Endpoint ’n’ receive is enabled
0 = Endpoint ’n’ receive is disabled
bit 2 EPTXEN: Endpoint Transmit Enable bit
1 = Endpoint ’n’ transmit is enabled
0 = Endpoint ’n’ transmit is disabled
bit 1 EPSTALL: Endpoint Stall Status bit
1 = Endpoint ’n’ was stalled
0 = Endpoint ’n’ was not stalled
bit 0 EPHSHK: Endpoint Handshake Enable bit
1 = Endpoint Handshake is enabled
0 = Endpoint Handshake is disabled (typically used for isochronous endpoints)

 2009-2019 Microchip Technology Inc. DS60001156K-page 159

PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 160  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
12.0 I/O PORTS Following are some of the key features of this module:
• Individual output pin open-drain enable/disable
Note: This data sheet summarizes the features
• Individual input pin weak pull-up enable/disable
of the PIC32MX5XX/6XX/7XX family of
• Monitor selective inputs and generate interrupt
devices. It is not intended to be a
when change in pin state is detected
comprehensive reference source. To
complement the information in this data • Operation during Sleep and Idle modes
sheet, refer to Section 12. “I/O Ports” • Fast bit manipulation using CLR, SET and INV
(DS60001120) in the “PIC32 Family registers
Reference Manual”, which is available Figure 12-1 illustrates a block diagram of a typical
from the Microchip web site multiplexed I/O port.
(www.microchip.com/PIC32).

General purpose I/O pins are the simplest of peripher-

als. They allow the PIC32 MCU to monitor and control
other devices. To add flexibility and functionality, some
pins are multiplexed with alternate function(s). These
functions depend on which peripheral features are on
the device. In general, when a peripheral is functioning,
that pin may not be used as a general purpose I/O pin.

FIGURE 12-1: BLOCK DIAGRAM OF A TYPICAL MULTIPLEXED PORT STRUCTURE

Peripheral Module
Peripheral Module Enable
Peripheral Output Enable
Peripheral Output Data
PIO Module
RD ODC

Data Bus D Q
PBCLK CK ODC
EN Q
WR ODC
1 I/O Cell
RD TRIS 0
0
1
D Q
TRIS 1
CK
EN Q 0
WR TRIS
Output Multiplexers
D Q
CK LAT I/O Pin
EN Q
WR LAT
WR PORT

RD LAT
1
RD PORT
Q D Q D
0

Sleep Q CK Q CK

PBCLK
Synchronization
Peripheral Input R
Peripheral Input Buffer

Legend: R = Peripheral input buffer types may vary. Refer to Table 1-1 for peripheral details.
Note: This block diagram is a general representation of a shared port/peripheral structure is only for illustration purposes. The actual structure
for any specific port/peripheral combination may be different than it is shown here.

 2009-2019 Microchip Technology Inc. DS60001156K-page 161

PIC32MX5XX/6XX/7XX
12.1 Parallel I/O (PIO) Ports The maximum input voltage allowed on the input pins
is the same as the maximum VIH specification. Refer to
All port pins have three registers (TRIS, LAT and Section 32.0 “Electrical Characteristics” for VIH
PORT) that are directly associated with their operation. specification details.
TRIS is a Data Direction or Tri-State Control register
Note: Analog levels on any pin that is defined as
that determines whether a digital pin is an input or an
a digital input (including the ANx pins)
output. Setting a TRISx register bit = 1, configures the
may cause the input buffer to consume
corresponding I/O pin as an input; setting a TRISx
current that exceeds the device
register bit = 0, configures the corresponding I/O pin as
specifications.
an output. All port I/O pins are defined as inputs after a
device Reset. Certain I/O pins are shared with analog
12.1.3 ANALOG INPUTS
peripherals and default to analog inputs after a device
Reset. Certain pins can be configured as analog inputs used
by the ADC and comparator modules. Setting the
PORT is a register used to read the current state of the
corresponding bits in the AD1PCFG register = 0
signal applied to the port I/O pins. Writing to a PORTx
enables the pin as an analog input pin and must have
register performs a write to the port’s latch, LATx
the corresponding TRIS bit set = 1 (input). If the TRIS
register, latching the data to the port’s I/O pins.
bit is cleared = 0 (output), the digital output level (VOH
LAT is a register used to write data to the port I/O pins. or VOL) will be converted. Any time a port I/O pin is
The LATx Latch register holds the data written to either configured as analog, its digital input is disabled and
the LATx or PORTx registers. Reading the LATx Latch the corresponding PORTx register bit will read ‘0’. The
register reads the last value written to the AD1PCFG register has a default value of 0x0000;
corresponding PORT or Latch register. therefore, all pins that share ANx functions are analog
Not all port I/O pins are implemented on some devices, (not digital) by default.
therefore, the corresponding PORTx, LATx and TRISx
register bits will read as zeros. 12.1.4 DIGITAL OUTPUTS
Pins are configured as digital outputs by setting the
12.1.1 CLR, SET AND INV REGISTERS corresponding TRIS register bits = 0. When configured
Every I/O module register has a corresponding Clear as digital outputs, these pins are CMOS drivers or can
(CLR), Set (SET) and Invert (INV) register designed to be configured as open-drain outputs by setting the
provide fast atomic bit manipulations. As the name of corresponding bits in the Open-Drain Configuration
the register implies, a value written to a SET, CLR or (ODCx) register.
INV register effectively performs the implied operation, The open-drain feature allows generation of outputs
but only on the corresponding base register and only higher than VDD (e.g., 5V) on any desired 5V tolerant
bits specified as ‘1’ are modified. Bits specified as ‘0’ pins by using external pull-up resistors. The maximum
are not modified. open-drain voltage allowed is the same as the
Reading SET, CLR and INV registers returns undefined maximum VIH specification.
values. To see the affects of a write operation to a SET, See the “Device Pin Tables” section for the available
CLR or INV register, the base register must be read. pins and their functionality.

Note: Using a PORTxINV register to toggle a bit 12.1.5 ANALOG OUTPUTS

is recommended because the operation is Certain pins can be configured as analog outputs, such
performed in hardware atomically, using as the CVREF output voltage used by the comparator
fewer instructions, as compared to the module. Configuring the comparator reference module
traditional read-modify-write method, as to provide this output will present the analog output
follows: voltage on the pin, independent of the TRIS register
PORTC ^ = 0x0001; setting for the corresponding pin.

12.1.2 DIGITAL INPUTS 12.1.6 INPUT CHANGE NOTIFICATION

Pins are configured as digital inputs by setting the The input change notification function of the I/O ports
corresponding TRIS register bits = 1. When configured (CNx) allows devices to generate interrupt requests in
as inputs, they are either TTL buffers or Schmitt response to change-of-state on selected pin.
Triggers. Several digital pins share functionality with Each CNx pin also has a weak pull-up, which acts as a
analog inputs and default to the analog inputs at POR. current source connected to the pin. The pull-ups are
Setting the corresponding bit in the AD1PCFG enabled by setting the corresponding bit in the CNPUE
register = 1 enables the pin as a digital pin. register.

DS60001156K-page 162  2009-2019 Microchip Technology Inc.

 12.2 Control Registers
 2009-2019 Microchip Technology Inc.

TABLE 12-1: PORTA REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6000 TRISA
15:0 TRISA15 TRISA14 — — — TRISA10 TRISA9 — TRISA7 TRISA6 TRISA5 TRISA4 TRISA3 TRISA2 TRISA1 TRISA0 C6FF
31:16 — — — — — — — — — — — — — — — — 0000
6010 PORTA
15:0 RA15 RA14 — — — RA10 RA9 — RA7 RA6 RA5 RA4 RA3 RA2 RA1 RA0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6020 LATA
15:0 LATA15 LATA14 — — — LATA10 LATA9 — LATA7 LATA6 LATA5 LATA4 LATA3 LATA2 LATA1 LATA0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6030 ODCA
15:0 ODCA15 ODCA14 — — — ODCA10 ODCA9 — ODCA7 ODCA6 ODCA5 ODCA4 ODCA3 ODCA2 ODCA1 ODCA0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.

PIC32MX5XX/6XX/7XX
TABLE 12-2: PORTB REGISTER MAP
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6040 TRISB
15:0 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 TRISB10 TRISB9 TRISB8 TRISB7 TRISB6 TRISB5 TRISB4 TRISB3 TRISB2 TRISB1 TRISB0 FFFF
31:16 — — — — — — — — — — — — — — — — 0000
6050 PORTB
15:0 RB15 RB14 RB13 RB12 RB11 RB10 RB9 RB8 RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6060 LATB
15:0 LATB15 LATB14 LATB13 LATB12 LATB11 LATB10 LATB9 LATB8 LATB7 LATB6 LATB5 LATB4 LATB3 LATB2 LATB1 LATB0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
DS60001156K-page 163

6070 ODCB
15:0 ODCB15 ODCB14 ODCB13 ODCB12 ODCB11 ODCB10 ODCB9 ODCB8 ODCB7 ODCB6 ODCB5 ODCB4 ODCB3 ODCB2 ODCB1 ODCB0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DS60001156K-page 164

PIC32MX5XX/6XX/7XX
TABLE 12-3: PORTC REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6080 TRISC
15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — — — — — — F000
31:16 — — — — — — — — — — — — — — — — 0000
6090 PORTC
15:0 RC15 RC14 RC13 RC12 — — — — — — — — — — — — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60A0 LATC
15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — — — — — — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60B0 ODCC
15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — — — — — — 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.

TABLE 12-4: PORTC REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6080 TRISC
 2009-2019 Microchip Technology Inc.

15:0 TRISC15 TRISC14 TRISC13 TRISC12 — — — — — — — TRISC4 TRISC3 TRISC2 TRISC1 — F00F
31:16 — — — — — — — — — — — — — — — — 0000
6090 PORTC
15:0 RC15 RC14 RC13 RC12 — — — — — — — RC4 RC3 RC2 RC1 — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60A0 LATC
15:0 LATC15 LATC14 LATC13 LATC12 — — — — — — — LATC4 LATC3 LATC2 LATC1 — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60B0 ODCC
15:0 ODCC15 ODCC14 ODCC13 ODCC12 — — — — — — — ODCC4 ODCC3 ODCC2 ODCC1 — 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 2009-2019 Microchip Technology Inc.

TABLE 12-5: PORTD REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
60C0 TRISD
15:0 — — — — TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 0FFF
31:16 — — — — — — — — — — — — — — — — 0000
60D0 PORTD
15:0 — — — — RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60E0 LATD
15:0 — — — — LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60F0 ODCD
15:0 — — — — ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.

TABLE 12-6: PORTD REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,

PIC32MX5XX/6XX/7XX
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
60C0 TRISD
15:0 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 TRISD9 TRISD8 TRISD7 TRISD6 TRISD5 TRISD4 TRISD3 TRISD2 TRISD1 TRISD0 FFFF
31:16 — — — — — — — — — — — — — — — — 0000
60D0 PORTD
15:0 RD15 RD14 RD13 RD12 RD11 RD10 RD9 RD8 RD7 RD6 RD5 RD4 RD3 RD2 RD1 RD0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
60E0 LATD
15:0 LAT15 LAT14 LAT13 LAT12 LATD11 LATD10 LATD9 LATD8 LATD7 LATD6 LATD5 LATD4 LATD3 LATD2 LATD1 LATD0 xxxx
DS60001156K-page 165

31:16 — — — — — — — — — — — — — — — — 0000
60F0 ODCD
15:0 ODCD15 ODCD14 ODCD13 ODCD12 ODCD11 ODCD10 ODCD9 ODCD8 ODCD7 ODCD6 ODCD5 ODCD4 ODCD3 ODCD2 ODCD1 ODCD0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DS60001156K-page 166

PIC32MX5XX/6XX/7XX
TABLE 12-7: PORTE REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6100 TRISE
15:0 — — — — — — — — TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 00FF
31:16 — — — — — — — — — — — — — — — — 0000
6110 PORTE
15:0 — — — — — — — — RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6120 LATE
15:0 — — — — — — — — LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6130 ODCE
15:0 — — — — — — — — ODCE7 0DCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.

TABLE 12-8: PORTE REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6100 TRISE
 2009-2019 Microchip Technology Inc.

15:0 — — — — — — TRISE9 TRISE8 TRISE7 TRISE6 TRISE5 TRISE4 TRISE3 TRISE2 TRISE1 TRISE0 03FF
31:16 — — — — — — — — — — — — — — — — 0000
6110 PORTE
15:0 — — — — — — RE9 RE8 RE7 RE6 RE5 RE4 RE3 RE2 RE1 RE0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6120 LATE
15:0 — — — — — — LATE9 LATE8 LATE7 LATE6 LATE5 LATE4 LATE3 LATE2 LATE1 LATE0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6130 ODCE
15:0 — — — — — — ODCE9 ODCE8 ODCE7 0DCE6 ODCE5 ODCE4 ODCE3 ODCE2 ODCE1 ODCE0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 2009-2019 Microchip Technology Inc.

TABLE 12-9: PORTF REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6140 TRISF
15:0 — — — — — — — — — — TRISF5 TRISF4 TRISF3 — TRISF1 TRISF0 003B
31:16 — — — — — — — — — — — — — — — — 0000
6150 PORTF
15:0 — — — — — — — — — — RF5 RF4 RF3 — RF1 RF0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6160 LATF
15:0 — — — — — — — — — — LATF5 LATF4 LATF3 — LATF1 LATF0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6170 ODCF
15:0 — — — — — — — — — — ODCF5 ODCF4 ODCF3 — ODCF1 ODCF0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.

TABLE 12-10: PORTF REGISTER MAP PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L,
PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L, PIC32MX775F256L,

PIC32MX5XX/6XX/7XX
PIC32MX764F128L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6140 TRISF
15:0 — — TRISF13 TRISF12 — — — TRISF8 — — TRISF5 TRISF4 TRISF3 TRISF2 TRISF1 TRISF0 313F
31:16 — — — — — — — — — — — — — — — — 0000
6150 PORTF
15:0 — — RF13 RF12 — — — RF8 — — RF5 RF4 RF3 RF2 RF1 RF0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
6160 LATF
15:0 — — LATF13 LATF12 — — — LATF8 — — LATF5 LATF4 LATF3 LATF2 LATF1 LATF0 xxxx
DS60001156K-page 167

31:16 — — — — — — — — — — — — — — — — 0000
6170 ODCF
15:0 — — ODCF13 ODCF12 — — — ODCF8 — — ODCF5 ODCF4 ODCF3 ODCF2 ODCF1 ODCF0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DS60001156K-page 168

PIC32MX5XX/6XX/7XX
TABLE 12-11: PORTG REGISTER MAP FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX664F064H, PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H,
PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6180 TRISG
15:0 — — — — — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 — — 03CC
31:16 — — — — — — — — — — — — — — — — 0000
6190 PORTG
15:0 — — — — — — RG9 RG8 RG7 RG6 — — RG3 RG2 — — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
61A0 LATG
15:0 — — — — — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 — — xxxx
31:16 — — — — — — — — — — — — — — — — 0000
61B0 ODCG
15:0 — — — — — — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 — — 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.

TABLE 12-12: PORTG REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L,
PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX695F512L,
PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6180 TRISG
 2009-2019 Microchip Technology Inc.

15:0 TRISG15 TRISG14 TRISG13 TRISG12 — — TRISG9 TRISG8 TRISG7 TRISG6 — — TRISG3 TRISG2 TRISG1 TRISG0 F3CF
31:16 — — — — — — — — — — — — — — — — 0000
6190 PORTG
15:0 RG15 RG14 RG13 RG12 — — RG9 RG8 RG7 RG6 — — RG3 RG2 RG1 RG0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
61A0 LATG
15:0 LATG15 LATG14 LATG13 LATG12 — — LATG9 LATG8 LATG7 LATG6 — — LATG3 LATG2 LATG1 LATG0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
61B0 ODCG
15:0 ODCG15 ODCG14 ODCG13 ODCG12 — — ODCG9 ODCG8 ODCG7 ODCG6 — — ODCG3 ODCG2 ODCG1 ODCG0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 2009-2019 Microchip Technology Inc.

TABLE 12-13: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX534F064L, PIC32MX564F064L, PIC32MX564F128L,
PIC32MX575F256L, PIC32MX575F512L, PIC32MX664F064L, PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L,
PIC32MX695F512L, PIC32MX764F128L, PIC32MX775F256L, PIC32MX775F512 AND PIC32MX795F512L DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
61C0 CNCON
15:0 ON — SIDL — — — — — — — — — — — — — 0000
31:16 — — — — — — — — — — CNEN21 CNEN20 CNEN19 CNEN18 CNEN17 CNEN16 0000
61D0 CNEN
15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000
31:16 — — — — — — — — — — CNPUE21 CNPUE20 CNPUE19 CNPUE18 CNPUE17 CNPUE16 0000
61E0 CNPUE
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.

TABLE 12-14: CHANGE NOTICE AND PULL-UP REGISTER MAP FOR PIC32MX575F256H, PIC32MX575F512H, PIC32MX675F256H,
PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H AND PIC32MX795F512H DEVICES
Virtual Address

Bits

PIC32MX5XX/6XX/7XX
All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
61C0 CNCON
15:0 ON — SIDL — — — — — — — — — — — — — 0000
31:16 — — — — — — — — — — — — — CNEN18 CNEN17 CNEN16 0000
61D0 CNEN
15:0 CNEN15 CNEN14 CNEN13 CNEN12 CNEN11 CNEN10 CNEN9 CNEN8 CNEN7 CNEN6 CNEN5 CNEN4 CNEN3 CNEN2 CNEN1 CNEN0 0000
31:16 — — — — — — — — — — — — — CNPUE18 CNPUE17 CNPUE16 0000
61E0 CNPUE
15:0 CNPUE15 CNPUE14 CNPUE13 CNPUE12 CNPUE11 CNPUE10 CNPUE9 CNPUE8 CNPUE7 CNPUE6 CNPUE5 CNPUE4 CNPUE3 CNPUE2 CNPUE1 CNPUE0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DS60001156K-page 169
PIC32MX5XX/6XX/7XX

REGISTER 12-1: CNCON: CHANGE NOTICE CONTROL REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
15:8
ON — SIDL — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0
— — — — — — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Change Notice (CN) Control ON bit
1 = CN is enabled
0 = CN is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Control bit
1 = Idle mode halts CN operation
0 = Idle mode does not affect CN operation
bit 12-0 Unimplemented: Read as ‘0’

DS60001156K-page 170  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
13.0 TIMER1 13.1 Additional Supported Features
Note: This data sheet summarizes the features • Selectable clock prescaler
of the PIC32MX5XX/6XX/7XX family of • Timer operation during Idle and Sleep mode
devices. It is not intended to be a • Fast bit manipulation using CLR, SET and INV
comprehensive reference source. To registers
complement the information in this data • Asynchronous mode can be used with the SOSC
sheet, refer to Section 14. “Timers” to function as a Real-Time Clock (RTC)
(DS60001105) in the “PIC32 Family
Reference Manual”, which is available A simplified block diagram of the Timer1 module is
from the Microchip web site illustrated in Figure 13-1.
(www.microchip.com/PIC32).

This family of PIC32 devices features one synchronous/

asynchronous 16-bit timer that can operate as a free-run-
ning interval timer for various timing applications and
counting external events. This timer can also be used
with the low-power Secondary Oscillator (SOSC) for
Real-Time Clock (RTC) applications. The following
modes are supported:
• Synchronous Internal Timer
• Synchronous Internal Gated Timer
• Synchronous External Timer
• Asynchronous External Timer

FIGURE 13-1: TIMER1 BLOCK DIAGRAM

PR1

Equal
16-bit Comparator TSYNC (T1CON<2>)

1 Sync
TMR1
Reset
0
0
T1IF
Event Flag 1 Q D TGATE (T1CON<7>)
Q
TCS (T1CON<1>)
TGATE (T1CON<7>)
ON (T1CON<15>)

SOSCO/T1CK x1

Gate Prescaler
SOSCEN(1)
Sync 10 1, 8, 64, 256
SOSCI
PBCLK 00
2
TCKPS<1:0>
(T1CON<5:4>)

Note 1: The default state of the SOSCEN (OSCCON<1>) during a device Reset is controlled by the FSOSCEN bit in
Configuration Word, DEVCFG1.

 2009-2019 Microchip Technology Inc. DS60001156K-page 171

DS60001156K-page 172
13.2 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 13-1: TIMER1 REGISTER MAP
Virtual Address Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
0600 T1CON
15:0 ON — SIDL TWDIS TWIP — — — TGATE — TCKPS<1:0> — TSYNC TCS — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0610 TMR1
15:0 TMR1<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0620 PR1
15:0 PR1<15:0> FFFF
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 R/W-0 R-0 U-0 U-0 U-0
15:8
ON(1) — SIDL TWDIS TWIP — — —
R/W-0 U-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0
7:0
TGATE — TCKPS<1:0> — TSYNC TCS —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Timer On bit(1)
1 = Timer is enabled
0 = Timer is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation when device is in Idle mode
bit 12 TWDIS: Asynchronous Timer Write Disable bit
1 = Writes to TMR1 are ignored until pending write operation completes
0 = Back-to-back writes are enabled (Legacy Asynchronous Timer functionality)
bit 11 TWIP: Asynchronous Timer Write in Progress bit
In Asynchronous Timer mode:
1 = Asynchronous write to TMR1 register in progress
0 = Asynchronous write to TMR1 register complete
In Synchronous Timer mode:
This bit is read as ‘0’.
bit 10-8 Unimplemented: Read as ‘0’
bit 7 TGATE: Timer Gated Time Accumulation Enable bit
When TCS = 1:
This bit is ignored.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6 Unimplemented: Read as ‘0’

bit 5-4 TCKPS<1:0>: Timer Input Clock Prescale Select bits

11 = 1:256 prescale value
10 = 1:64 prescale value
01 = 1:8 prescale value
00 = 1:1 prescale value
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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PIC32MX5XX/6XX/7XX
REGISTER 13-1: T1CON: TYPE A TIMER CONTROL REGISTER (CONTINUED)
bit 3 Unimplemented: Read as ‘0’
bit 2 TSYNC: Timer External Clock Input Synchronization Selection bit
When TCS = 1:
1 = External clock input is synchronized
0 = External clock input is not synchronized
When TCS = 0:
This bit is ignored.
bit 1 TCS: Timer Clock Source Select bit
1 = External clock from TxCKI pin
0 = Internal peripheral clock
bit 0 Unimplemented: Read as ‘0’

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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 PIC32MX5XX/6XX/7XX
14.0 TIMER2/3, TIMER4/5 Two 32-bit synchronous timers are available by
combining Timer2 with Timer3 and Timer4 with Timer5.
Note: This data sheet summarizes the features The 32-bit timers can operate in three modes:
of the PIC32MX5XX/6XX/7XX family of • Synchronous Internal 32-bit Timer
devices. It is not intended to be a
• Synchronous Internal 32-bit Gated Timer
comprehensive reference source. To
complement the information in this data • Synchronous External 32-bit Timer
sheet, refer to Section 14. “Timers” Note: In this chapter, references to registers,
(DS60001105) of the “PIC32 Family Ref- TxCON, TMRx and PRx, use ‘x’ to
erence Manual”, which is available from represent Timer2 through Timer5 in 16-bit
the Microchip web site (www.micro- modes. In 32-bit modes, ‘x’ represents
chip.com/PIC32). Timer2 or Timer4; ‘y’ represents Timer3 or
Timer5.
This family of PIC32 devices features four synchronous
16-bit timers (default) that can operate as a free-
running interval timer for various timing applications 14.1 Additional Supported Features
and counting external events. The following modes are
• Selectable clock prescaler
supported:
• Timers operational during CPU idle
• Synchronous Internal 16-bit Timer
• Time base for Input Capture and Output Compare
• Synchronous Internal 16-bit Gated Timer modules (only Timer2 and Timer3)
• Synchronous External 16-bit Timer • ADC event trigger (only Timer3)
• Fast bit manipulation using CLR, SET and INV
registers

FIGURE 14-1: TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (16-BIT)

TMRx Sync

ADC Event
Trigger(1) Comparator x 16
Equal

PRx
Reset

0
TxIF
Event Flag 1 Q D TGATE (TxCON<7>)
Q TCS (TxCON<1>)
TGATE (TxCON<7>)
ON (TxCON<15>)

TxCK(2) x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256

PBCLK 00
3
TCKPS (TxCON<6:4>)

Note 1: ADC event trigger is only available on Timer3.

2: TxCK pins are not available on 64-pin devices.

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PIC32MX5XX/6XX/7XX
FIGURE 14-2: TIMER2/3 AND TIMER4/5 BLOCK DIAGRAM (32-BIT)

Reset
TMRy TMRx Sync

MS Half Word LS Half Word

ADC Event
Trigger(3) 32-bit Comparator
Equal

PRy PRx

TyIF Event 0
Flag
1 Q D TGATE (TxCON<7>)
Q TCS (TxCON<1>)
TGATE (TxCON<7>)
ON (TxCON<15>)

TxCK(2) x1
Prescaler
Gate 1, 2, 4, 8, 16,
Sync 10
32, 64, 256

PBCLK 00
3
TCKPS (TxCON<6:4>)

Note 1: In this diagram, the use of ‘x’ in registers, TxCON, TMRx, PRx and TxCK, refers to either Timer2 or Timer4; the use
of ‘y’ in registers, TyCON, TMRy, PRy, TyIF, refers to either Timer3 or Timer5.
2: TxCK pins are not available on 64-pin devices.
3: ADC event trigger is only available on the Timer2/3 pair.

DS60001156K-page 176  2009-2019 Microchip Technology Inc.

 14.2 Control Registers
 2009-2019 Microchip Technology Inc.

TABLE 14-1:
Virtual Address
TIMER2 THROUGH TIMER5 REGISTER MAP
Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
0800 T2CON
15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> T32 — TCS(2) — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0810 TMR2
15:0 TMR2<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0820 PR2
15:0 PR2<15:0> FFFF
31:16 — — — — — — — — — — — — — — — — 0000
0A00 T3CON
15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> — — TCS(2) — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0A10 TMR3
15:0 TMR3<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0A20 PR3
15:0 PR3<15:0> FFFF
31:16 — — — — — — — — — — — — — — — — 0000
0C00 T4CON
15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> T32 — TCS(2) — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0C10 TMR4

PIC32MX5XX/6XX/7XX
15:0 TMR4<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0C20 PR4
15:0 PR4<15:0> FFFF
31:16 — — — — — — — — — — — — — — — — 0000
0E00 T5CON
15:0 ON — SIDL — — — — — TGATE TCKPS<2:0> — — TCS(2) — 0000
31:16 — — — — — — — — — — — — — — — — 0000
0E10 TMR5
15:0 TMR5<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
0E20 PR5
15:0 PR5<15:0> FFFF
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: These bits are not available on 64-pin devices.
DS60001156K-page 177
PIC32MX5XX/6XX/7XX
REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
15:8
ON(1,3) — SIDL(4) — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0
7:0
TGATE(3) TCKPS<2:0>(3) T32(2) — TCS(3) —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Timer On bit(1,3)
1 = Module is enabled
0 = Module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit(4)
1 = Discontinue operation when device enters Idle mode
0 = Continue operation when device is in Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 TGATE: Timer Gated Time Accumulation Enable bit(3)
When TCS = 1:
This bit is ignored and is read as ‘0’.
When TCS = 0:
1 = Gated time accumulation is enabled
0 = Gated time accumulation is disabled
bit 6-4 TCKPS<2:0>: Timer Input Clock Prescale Select bits(3)
111 = 1:256 prescale value
110 = 1:64 prescale value
101 = 1:32 prescale value
100 = 1:16 prescale value
011 = 1:8 prescale value
010 = 1:4 prescale value
001 = 1:2 prescale value
000 = 1:1 prescale value

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is only available on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Tim-
er5). All timer functions are set through the even numbered timers.
4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.

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 PIC32MX5XX/6XX/7XX
REGISTER 14-1: TXCON: TYPE B TIMER CONTROL REGISTER (CONTINUED)
bit 3 T32: 32-Bit Timer Mode Select bit(2)
1 = Odd numbered and even numbered timers form a 32-bit timer
0 = Odd numbered and even numbered timers form a separate 16-bit timer
bit 2 Unimplemented: Read as ‘0’
bit 1 TCS: Timer Clock Source Select bit(3)
1 = External clock from TxCK pin
0 = Internal peripheral clock
bit 0 Unimplemented: Read as ‘0’

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is only available on even numbered timers (Timer2 and Timer4).
3: While operating in 32-bit mode, this bit has no effect for odd numbered timers (Timer1, Timer3, and Tim-
er5). All timer functions are set through the even numbered timers.
4: While operating in 32-bit mode, this bit must be cleared on odd numbered timers to enable the 32-bit timer
in Idle mode.

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PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 180  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
15.0 WATCHDOG TIMER (WDT) This section describes the operation of the WDT and
Power-up Timer of the PIC32MX5XX/6XX/7XX.
Note: This data sheet summarizes the features The WDT, when enabled, operates from the internal
of the PIC32MX5XX/6XX/7XX family of Low-Power Oscillator (LPRC) clock source and can be
devices. However, it is not intended to be used to detect system software malfunctions by reset-
a comprehensive reference source. To ting the device if the WDT is not cleared periodically in
complement the information in this data software. Various WDT time-out periods can be
sheet, refer to Section 8. “Watchdog selected using the WDT postscaler. The WDT can also
Timer and Power-up Timer” be used to wake the device from Sleep or Idle mode.
(DS60001114) in the “PIC32 Family
Reference Manual”, which is available The following are key features of the WDT module:
from the Microchip web site • Configuration or software controlled
(www.microchip.com/PIC32). • User-configurable time-out period
• Can wake the device from Sleep or Idle mode

FIGURE 15-1: WATCHDOG TIMER AND POWER-UP TIMER BLOCK DIAGRAM

PWRT Enable LPRC

WDT Enable Control
PWRT Enable
1:64 Output
LPRC PWRT
Oscillator
1

Clock
25-bit Counter
WDTCLR = 1
WDT Enable 25
Wake 0 Device Reset
WDT Counter Reset
WDT Enable 1 NMI (Wake-up)
Reset Event
Power Save
Decoder

FWDTPS<4:0> (DEVCFG1<20:16>)

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DS60001156K-page 182
15.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 15-1: WATCHDOG TIMER REGISTER MAP
Virtual Address Bits

All Resets(2)
Bit Range
(BF80_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
0000 WDTCON
15:0 ON — — — — — — — — SWDTPS<4:0> — WDTCLR 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
2: Reset values are dependent on the DEVCFGx Configuration bits and the type of Reset.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 15-1: WDTCON: WATCHDOG TIMER CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
ON(1,2) — — — — — — —
U-0 R-y R-y R-y R-y R-y R/W-0 R/W-0
7:0
— SWDTPS<4:0> WDTWINEN WDTCLR

Legend: y = Values set from Configuration bits on POR

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Watchdog Timer Enable bit(1,2)
1 = Enables the WDT if it is not enabled by the device configuration
0 = Disable the WDT if it was enabled in software
bit 14-7 Unimplemented: Read as ‘0’
bit 6-2 SWDTPS<4:0>: Shadow Copy of Watchdog Timer Postscaler Value from Device Configuration bits
On reset, these bits are set to the values of the WDTPS <4:0> Configuration bits.
bit 1 WDTWINEN: Watchdog Timer Window Enable bit
1 = Enable windowed Watchdog Timer
0 = Disable windowed Watchdog Timer
bit 0 WDTCLR: Watchdog Timer Reset bit
1 = Writing a ‘1’ will clear the WDT
0 = Software cannot force this bit to a ‘0’

Note 1: A read of this bit results in a ‘1’ if the Watchdog Timer is enabled by the device configuration or software.
2: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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PIC32MX5XX/6XX/7XX
NOTES:

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 PIC32MX5XX/6XX/7XX
16.0 INPUT CAPTURE • Capture timer value on every edge (rising and
falling)
Note: This data sheet summarizes the features • Capture timer value on every edge (rising and
of the PIC32MX5XX/6XX/7XX family of falling), specified edge first.
devices. It is not intended to be a • Prescaler capture event modes:
comprehensive reference source. To
- Capture timer value on every 4th rising edge of
complement the information in this data
input at ICx pin
sheet, refer to Section 15. “Input Cap-
ture” (DS60001122) of the “PIC32 Family - Capture timer value on every 16th rising edge of
Reference Manual”, which is available input at ICx pin
from the Microchip web site Each input capture channel can select between one of
(www.microchip.com/PIC32). two 16-bit timers (Timer2 or Timer3) for the time base,
or two 16-bit timers (Timer2 and Timer3) together to
The Input Capture module is useful in applications form a 32-bit timer. The selected timer can use either
requiring frequency (period) and pulse measurement. an internal or external clock.
The Input Capture module captures the 16-bit or 32-bit Other operational features include:
value of the selected Time Base registers when an
event occurs at the ICx pin. The following events cause • Device wake-up from capture pin during Sleep and
capture events: Idle modes
• Interrupt on input capture event
• Simple capture event modes:
• 4-word FIFO buffer for capture values
- Capture timer value on every falling edge of input
Interrupt optionally generated after 1, 2, 3 or 4 buffer
at ICx pin
locations are filled
- Capture timer value on every rising edge of input
• Input Capture module can also be used to provide
at ICx pin
additional sources of external interrupts

FIGURE 16-1: INPUT CAPTURE BLOCK DIAGRAM

ICx Input Timer3 Timer2

ICTMR
0 1
C32

FIFO Control
ICxBUF<31:16> ICxBUF<15:0>

Prescaler
Edge Detect
1, 4, 16

ICM<2:0>
ICM<2:0> FEDGE
ICBNE
ICOV
Interrupt
ICxCON Event
ICI<1:0> Generation

Data Space Interface

Interrupt Peripheral Data Bus

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DS60001156K-page 186
16.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 16-1: INPUT CAPTURE 1-INPUT CAPTURE 5 REGISTER MAP
Virtual Address Bits

All Resets
Bit Range
(BF80_#)

Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
2000 IC1CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2010 IC1BUF IC1BUF<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
2200 IC2CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2210 IC2BUF IC2BUF<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
2400 IC3CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2410 IC3BUF IC3BUF<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
2600 IC4CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2610 IC4BUF IC4BUF<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
2800 IC5CON(1)
15:0 ON — SIDL — — — FEDGE C32 ICTMR ICI<1:0> ICOV ICBNE ICM<2:0> 0000
31:16 xxxx
2810 IC5BUF IC5BUF<31:0>
15:0 xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 16-1: ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
ON(1) — SIDL — — — FEDGE C32
R/W-0 R/W-0 R/W-0 R-0 R-0 R/W-0 R/W-0 R/W-0
7:0
ICTMR ICI<1:0> ICOV ICBNE ICM<2:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Input Capture Module Enable bit(1)
1 = Module is enabled
0 = Disable and reset module, disable clocks, disable interrupt generation and allow SFR modifications
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Control bit
1 = Halt in Idle mode
0 = Continue to operate in Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9 FEDGE: First Capture Edge Select bit (only used in mode 6, ICM<2:0> = 110)
1 = Capture rising edge first
0 = Capture falling edge first
bit 8 C32: 32-bit Capture Select bit
1 = 32-bit timer resource capture
0 = 16-bit timer resource capture
bit 7 ICTMR: Timer Select bit (Does not affect timer selection when C32 (ICxCON<8>) is ‘1’)
1 = Timer2 is the counter source for capture
0 = Timer3 is the counter source for capture
bit 6-5 ICI<1:0>: Interrupt Control bits
11 = Interrupt on every fourth capture event
10 = Interrupt on every third capture event
01 = Interrupt on every second capture event
00 = Interrupt on every capture event
bit 4 ICOV: Input Capture Overflow Status Flag bit (read-only)
1 = Input capture overflow is occurred
0 = No input capture overflow is occurred
bit 3 ICBNE: Input Capture Buffer Not Empty Status bit (read-only)
1 = Input capture buffer is not empty; at least one more capture value can be read
0 = Input capture buffer is empty

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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PIC32MX5XX/6XX/7XX
REGISTER 16-1: ICXCON: INPUT CAPTURE ‘X’ CONTROL REGISTER (CONTINUED)
bit 2-0 ICM<2:0>: Input Capture Mode Select bits
111 = Interrupt-Only mode (only supported while in Sleep mode or Idle mode)
110 = Simple Capture Event mode – every edge, specified edge first and every edge thereafter
101 = Prescaled Capture Event mode – every sixteenth rising edge
100 = Prescaled Capture Event mode – every fourth rising edge
011 = Simple Capture Event mode – every rising edge
010 = Simple Capture Event mode – every falling edge
001 = Edge Detect mode – every edge (rising and falling)
000 = Input Capture module is disabled

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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 PIC32MX5XX/6XX/7XX
17.0 OUTPUT COMPARE The following are key features of the Output Compare
module:
Note: This data sheet summarizes the features • Multiple Output Compare modules in a device
of the PIC32MX5XX/6XX/7XX family of
• Programmable interrupt generation on compare
devices. It is not intended to be a
event
comprehensive reference source. To
complement the information in this data • Single and Dual Compare modes
sheet, refer to Section 16. “Output Com- • Single and continuous output pulse generation
pare” (DS60001111) in the “PIC32 Family • Pulse-Width Modulation (PWM) mode
Reference Manual”, which is available • Hardware-based PWM Fault detection and
from the Microchip web site automatic output disable
(www.microchip.com/PIC32).
• Programmable selection of 16-bit or 32-bit time
The Output Compare module is used to generate a bases
single pulse or a series of pulses in response to • Can operate from either of two available 16-bit
selected time base events. For all modes of operation, time bases or a single 32-bit time base
the Output Compare module compares the values
stored in the OCxR and/or the OCxRS registers to the
value in the selected timer. When a match occurs, the
Output Compare module generates an event based on
the selected mode of operation.

FIGURE 17-1: OUTPUT COMPARE MODULE BLOCK DIAGRAM

Set Flag bit

OCxIF(1)

OCxRS(1)

Output S Q
OCxR(1) OCx(1)
Logic R

Output Output Enable

3 Logic
Enable
OCM<2:0>
Mode Select OCFA or OCFB(2)
Comparator

0 1 OCTSEL 0 1

16 16

TMR Register Inputs Period Match Signals

from Time Bases(3) from Time Bases(3)

Note 1: Where ‘x’ is shown, reference is made to the registers associated with the respective output compare channels,
1 through 5.
2: The OCFA pin controls the OC1-OC4 channels. The OCFB pin controls the OC5 channel.
3: Each output compare channel can use one of two selectable 16-bit time bases or a single 32-bit timer base.

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DS60001156K-page 190
17.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 17-1: OUTPUT COMPARE 1-OUTPUT COMPARE 5 REGISTER MAP
Virtual Address Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
3000 OC1CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3010 OC1R OC1R<31:0>
15:0 xxxx
31:16 xxxx
3020 OC1RS OC1RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3200 OC2CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3210 OC2R OC2R<31:0>
15:0 xxxx
31:16 xxxx
3220 OC2RS OC2RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3400 OC3CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3410 OC3R OC3R<31:0>
15:0 xxxx
31:16 xxxx
3420 OC3RS OC3RS<31:0>
15:0 xxxx
31:16 — — — — — — — — — — — — — — — — 0000
3600 OC4CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3610 OC4R OC4R<31:0>
15:0 xxxx
31:16 xxxx
3620 OC4RS OC4RS<31:0>
15:0 xxxx
 2009-2019 Microchip Technology Inc.

31:16 — — — — — — — — — — — — — — — — 0000
3800 OC5CON
15:0 ON — SIDL — — — — — — — OC32 OCFLT OCTSEL OCM<2:0> 0000
31:16 xxxx
3810 OC5R OC5R<31:0>
15:0 xxxx
31:16 xxxx
3820 OC5RS OC5RS<31:0>
15:0 xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 PIC32MX5XX/6XX/7XX
REGISTER 17-1: OCxCON: OUTPUT COMPARE ‘x’ CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
15:8
ON(1) — SIDL — — — — —
U-0 U-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — OC32 OCFLT(2) OCTSEL OCM<2:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Output Compare Module On bit(1)
1 = Output Compare module is enabled
0 = Output Compare module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters Idle mode
0 = Continue operation when CPU is in Idle mode
bit 12-6 Unimplemented: Read as ‘0’
bit 5 OC32: 32-bit Compare Mode bit
1 = OCxR<31:0> and/or OCxRS<31:0> are used for comparisons to the 32-bit timer source
0 = OCxR<15:0> and OCxRS<15:0> are used for comparisons to the 16-bit timer source
bit 4 OCFLT: PWM Fault Condition Status bit(2)
1 = PWM Fault condition has occurred (only cleared in hardware)
0 = PWM Fault condition has not occurred
bit 3 OCTSEL: Output Compare Timer Select bit
1 = Timer3 is the clock source for this Output Compare module
0 = Timer2 is the clock source for this Output Compare module
bit 2-0 OCM<2:0>: Output Compare Mode Select bits
111 = PWM mode on OCx; Fault pin enabled
110 = PWM mode on OCx; Fault pin disabled
101 = Initialize OCx pin low; generate continuous output pulses on OCx pin
100 = Initialize OCx pin low; generate single output pulse on OCx pin
011 = Compare event toggles OCx pin
010 = Initialize OCx pin high; compare event forces OCx pin low
001 = Initialize OCx pin low; compare event forces OCx pin high
000 = Output compare peripheral is disabled but continues to draw current

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit is only used when OCM<2:0> = 111. It is read as ‘0’ in all other modes.

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PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 192  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
18.0 SERIAL PERIPHERAL The following are some of the key features of the SPI
module:
INTERFACE (SPI)
• Master mode and Slave mode support
Note: This data sheet summarizes the features • Four different clock formats
of the PIC32MX5XX/6XX/7XX family of
• Enhanced Framed SPI protocol support
devices. It is not intended to be a
comprehensive reference source. To com- • User-configurable 8-bit, 16-bit and 32-bit data
plement the information in this data sheet, width
refer to Section 23. “Serial Peripheral • Separate SPI FIFO buffers for receive and transmit
Interface (SPI)” (DS60001106) in the - FIFO buffers act as 4/8/16-level deep FIFOs
“PIC32 Family Reference Manual”, which based on 32/16/8-bit data width
is available from the Microchip web site • Programmable interrupt event on every 8-bit,
(www.microchip.com/PIC32). 16-bit and 32-bit data transfer
The SPI module is a synchronous serial interface that • Operation during Sleep and Idle modes
is useful for communicating with external peripherals • Fast bit manipulation using CLR, SET and INV
and other microcontroller devices. These peripheral registers
devices may be Serial EEPROMs, Shift registers, dis-
play drivers, Analog-to-Digital Converters, etc. The
PIC32 SPI module is compatible with Motorola® SPI
and SIOP interfaces.

FIGURE 18-1: SPI MODULE BLOCK DIAGRAM

Internal
Data Bus

SPIxBUF

Read Write
FIFOs Share Address SPIxBUF

SPIxRXB FIFO SPIxTXB FIFO

Transmit

Receive

SPIxSR
SDIx bit 0

SDOx Shift
Control
Slave Select Clock Edge
and Frame Control Select
SSx/FSYNC Sync Control

Baud Rate
PBCLK
Generator
SCKx

Enable Master Clock

Note: Access SPIxTXB and SPIxRXB FIFOs via SPIxBUF register.

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18.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 18-1: SPI1 THROUGH SPI4 REGISTER MAP
Virtual Address
Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> — — — — — — SPIFE ENHBUF 0000
5E00 SPI1CON(2)
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0> 0000
31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000
5E10 SPI1STAT(2)
15:0 — — — — SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
31:16 0000
5E20 SPI1BUF(2) DATA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5E30 SPI1BRG(2)
15:0 — — — — — — — BRG<8:0> 0000
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> — — — — — — SPIFE ENHBUF 0000
5800 SPI3CON
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0> 0000
31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000
5810 SPI3STAT
15:0 — — — — SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
31:16 0000
5820 SPI3BUF DATA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5830 SPI3BRG
15:0 — — — — — — — BRG<8:0> 0000
31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> — — — — — — SPIFE ENHBUF 0000
5A00 SPI2CON
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0> 0000
31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000
5A10 SPI2STAT
15:0 — — — — SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
31:16 0000
5A20 SPI2BUF DATA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5A30 SPI2BRG
 2009-2019 Microchip Technology Inc.

15:0 — — — — — — — BRG<8:0> 0000

31:16 FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0> — — — — — — SPIFE ENHBUF 0000
5C00 SPI4CON
15:0 ON — SIDL DISSDO MODE32 MODE16 SMP CKE SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0> 0000
31:16 — — — RXBUFELM<4:0> — — — TXBUFELM<4:0> 0000
5C10 SPI4STAT
15:0 — — — — SPIBUSY — — SPITUR SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF 0008
31:16 0000
5C20 SPI4BUF DATA<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
5C30 SPI4BRG
15:0 — — — — — — — BRG<8:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except SPIxBUF have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
2: This register is not available on 64-pin devices.
 PIC32MX5XX/6XX/7XX
REGISTER 18-1: SPIxCON: SPI CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FRMEN FRMSYNC FRMPOL MSSEN FRMSYPW FRMCNT<2:0>
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
23:16
— — — — — — SPIFE ENHBUF(2)
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
ON(1) — SIDL DISSDO MODE32 MODE16 SMP CKE(3)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
SSEN CKP MSTEN — STXISEL<1:0> SRXISEL<1:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FRMEN: Framed SPI Support bit

1 = Framed SPI support is enabled (SSx pin used as FSYNC input/output)
0 = Framed SPI support is disabled
bit 30 FRMSYNC: Frame Sync Pulse Direction Control on SSx pin bit (only Framed SPI mode)
1 = Frame sync pulse input (Slave mode)
0 = Frame sync pulse output (Master mode)
bit 29 FRMPOL: Frame Sync/Slave Select Polarity bit (Framed SPI or Master Transmit modes only)
1 = Frame pulse or SSx pin is active-high
0 = Frame pulse or SSx pin is active-low
bit 28 MSSEN: Master Mode Slave Select Enable bit
1 = Slave select SPI support enabled. The SS pin is automatically driven during transmission in
Master mode. Polarity is determined by the FRMPOL bit.
0 = Slave select SPI support is disabled.
bit 27 FRMSYPW: Frame Sync Pulse Width bit
1 = Frame sync pulse is one character wide
0 = Frame sync pulse is one clock wide
bit 26-24 FRMCNT<2:0>: Frame Sync Pulse Counter bits. Controls the number of data characters transmitted per
pulse. This bit is only valid in Framed Sync mode.
111 = Reserved
110 = Reserved
101 = Generate a frame sync pulse on every 32 data characters
100 = Generate a frame sync pulse on every 16 data characters
011 = Generate a frame sync pulse on every 8 data characters
010 = Generate a frame sync pulse on every 4 data characters
001 = Generate a frame sync pulse on every 2 data characters
000 = Generate a frame sync pulse on every data character
bit 23-18 Unimplemented: Read as ‘0’
bit 17 SPIFE: Frame Sync Pulse Edge Select bit (only Framed SPI mode)
1 = Frame synchronization pulse coincides with the first bit clock
0 = Frame synchronization pulse precedes the first bit clock

bit 16 ENHBUF: Enhanced Buffer Enable bit(2)

1 = Enhanced Buffer mode is enabled
0 = Enhanced Buffer mode is disabled
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).

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PIC32MX5XX/6XX/7XX
REGISTER 18-1: SPIxCON: SPI CONTROL REGISTER (CONTINUED)
bit 15 ON: SPI Peripheral On bit(1)
1 = SPI Peripheral is enabled
0 = SPI Peripheral is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when CPU enters in Idle mode
0 = Continue operation in Idle mode
bit 12 DISSDO: Disable SDOx pin bit
1 = SDOx pin is not used by the module (pin is controlled by associated PORT register)
0 = SDOx pin is controlled by the module
bit 11-10 MODE<32,16>: 32/16-Bit Communication Select bits
MODE32 MODE16 Communication
1 x 32-bit
0 1 16-bit
0 0 8-bit
bit 9 SMP: SPI Data Input Sample Phase bit
Master mode (MSTEN = 1):
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
Slave mode (MSTEN = 0):
SMP value is ignored when SPI is used in Slave mode. The module always uses SMP = 0.
bit 8 CKE: SPI Clock Edge Select bit(3)
1 = Serial output data changes on transition from active clock state to Idle clock state (see CKP bit)
0 = Serial output data changes on transition from Idle clock state to active clock state (see CKP bit)
bit 7 SSEN: Slave Select Enable (Slave mode) bit
1 = SSx pin used for Slave mode
0 = SSx pin not used for Slave mode (pin is controlled by port function)
bit 6 CKP: Clock Polarity Select bit
1 = Idle state for clock is a high level; active state is a low level
0 = Idle state for clock is a low level; active state is a high level
bit 5 MSTEN: Master Mode Enable bit
1 = Master mode
0 = Slave mode
bit 4 Unimplemented: Read as ‘0’
bit 3-2 STXISEL<1:0>: SPI Transmit Buffer Empty Interrupt Mode bits
11 = Interrupt is generated when the buffer is not full (has one or more empty elements)
10 = Interrupt is generated when the buffer is empty by one-half or more
01 = Interrupt is generated when the buffer is completely empty
00 = Interrupt is generated when the last transfer is shifted out of SPISR and transmit operations are
complete
bit 1-0 SRXISEL<1:0>: SPI Receive Buffer Full Interrupt Mode bits
11 = Interrupt is generated when the buffer is full
10 = Interrupt is generated when the buffer is full by one-half or more
01 = Interrupt is generated when the buffer is not empty
00 = Interrupt is generated when the last word in the receive buffer is read (i.e., buffer is empty)

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read or write the peripheral’s SFRs in
the SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: This bit can only be written when the ON bit = 0.
3: This bit is not used in the Framed SPI mode. The user should program this bit to ‘0’ for the Framed SPI
mode (FRMEN = 1).

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 PIC32MX5XX/6XX/7XX
REGISTER 18-2: SPIxSTAT: SPI STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
31:24
— — — RXBUFELM<4:0>
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
23:16
— — — TXBUFELM<4:0>
U-0 U-0 U-0 U-0 R-0 U-0 U-0 R-0
15:8
— — — — SPIBUSY — — SPITUR
R-0 R/W-0 R-0 U-0 R-1 U-0 R-0 R-0
7:0
SRMT SPIROV SPIRBE — SPITBE — SPITBF SPIRBF

Legend: C = Clearable bit HS = Set in hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-29 Unimplemented: Read as ‘0’

bit 28-24 RXBUFELM<4:0>: Receive Buffer Element Count bits (only valid when ENHBUF = 1)
bit 23-21 Unimplemented: Read as ‘0’
bit 20-16 TXBUFELM<4:0>: Transmit Buffer Element Count bits (only valid when ENHBUF = 1)
bit 15-12 Unimplemented: Read as ‘0’
bit 11 SPIBUSY: SPI Activity Status bit
1 = SPI peripheral is currently busy with some transactions
0 = SPI peripheral is currently idle
bit 10-9 Unimplemented: Read as ‘0’
bit 8 SPITUR: Transmit Under Run bit
1 = Transmit buffer has encountered an underrun condition
0 = Transmit buffer has no underrun condition
This bit is only valid in Framed Sync mode; the underrun condition must be cleared by disabling/re-enabling
the module.
bit 7 SRMT: Shift Register Empty bit (only valid when ENHBUF = 1)
1 = When SPI module shift register is empty
0 = When SPI module shift register is not empty
bit 6 SPIROV: Receive Overflow Flag bit
1 = A new data is completely received and discarded. The user software has not read the previous data in
the SPIxBUF register.
0 = No overflow has occurred
This bit is set in hardware; can only be cleared (= 0) in software.
bit 5 SPIRBE: RX FIFO Empty bit (only valid when ENHBUF = 1)
1 = RX FIFO is empty (CRPTR = SWPTR)
0 = RX FIFO is not empty (CRPTR SWPTR)
bit 4 Unimplemented: Read as ‘0’
bit 3 SPITBE: SPI Transmit Buffer Empty Status bit
1 = Transmit buffer, SPIxTXB is empty
0 = Transmit buffer, SPIxTXB is not empty
Automatically set in hardware when SPI transfers data from SPIxTXB to SPIxSR.
Automatically cleared in hardware when SPIxBUF is written to, loading SPIxTXB.
bit 2 Unimplemented: Read as ‘0’

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PIC32MX5XX/6XX/7XX
REGISTER 18-2: SPIxSTAT: SPI STATUS REGISTER
bit 1 SPITBF: SPI Transmit Buffer Full Status bit
1 = Transmit not yet started, SPITXB is full
0 = Transmit buffer is not full
Standard Buffer Mode:
Automatically set in hardware when the core writes to the SPIBUF location, loading SPITXB.
Automatically cleared in hardware when the SPI module transfers data from SPITXB to SPISR.
Enhanced Buffer Mode:
Set when CWPTR + 1 = SRPTR; cleared otherwise
bit 0 SPIRBF: SPI Receive Buffer Full Status bit
1 = Receive buffer, SPIxRXB is full
0 = Receive buffer, SPIxRXB is not full
Standard Buffer Mode:
Automatically set in hardware when the SPI module transfers data from SPIxSR to SPIxRXB.
Automatically cleared in hardware when SPIxBUF is read from, reading SPIxRXB.
Enhanced Buffer Mode:
Set when SWPTR + 1 = CRPTR; cleared otherwise

DS60001156K-page 198  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
19.0 INTER-INTEGRATED CIRCUIT The I2C module provides complete hardware support
for both Slave and Multi-Master modes of the I2C serial
(I2C) communication standard. Figure 19-1 illustrates the
Note: This data sheet summarizes the features I2C module block diagram.
of the PIC32MX5XX/6XX/7XX family of Each I2C module has a 2-pin interface: the SCLx pin is
devices. It is not intended to be a clock and the SDAx pin is data.
comprehensive reference source. To
Each I2C module offers the following key features:
complement the information in this data
sheet, refer to Section 24. “Inter- • I2C interface supporting both master and slave
Integrated Circuit (I2C)” (DS60001116) operation
in the “PIC32 Family Reference Manual”, • I2C Slave mode supports 7-bit and 10-bit addressing
which is available from the Microchip web • I2C Master mode supports 7-bit and 10-bit
site (www.microchip.com/PIC32). addressing
• I2C port allows bidirectional transfers between
master and slaves
• Serial clock synchronization for the I2C port can
be used as a handshake mechanism to suspend
and resume serial transfer (SCLREL control)
• I2C supports multi-master operation; detects bus
collision and arbitrates accordingly
• Provides support for address bit masking

 2009-2019 Microchip Technology Inc. DS60001156K-page 199

PIC32MX5XX/6XX/7XX
FIGURE 19-1: I2C BLOCK DIAGRAM

Internal
Data Bus

I2CxRCV
Read

Shift
SCLx Clock
I2CxRSR
LSB

SDAx Address Match

Match Detect Write

I2CxMSK

Write Read

I2CxADD

Read

Start and Stop

bit Detect
Write

Start and Stop

bit Generation I2CxSTAT
Control Logic

Read
Collision Write
Detect

I2CxCON
Acknowledge
Generation Read

Clock
Stretching
Write

I2CxTRN
LSB
Shift Clock Read

Reload
Control
Write

BRG Down Counter I2CxBRG

Read
PBCLK

DS60001156K-page 200  2009-2019 Microchip Technology Inc.

 19.1 Control Registers
 2009-2019 Microchip Technology Inc.

TABLE 19-1: I2C1THROUGH I2C5 REGISTER MAP

Virtual Address

Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
5000 I2C3CON
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
31:16 — — — — — — — — — — — — — — — — 0000
5010 I2C3STAT
15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5020 I2C3ADD
15:0 — — — — — — ADD<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5030 I2C3MSK
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5040 I2C3BRG
15:0 — — — — Baud Rate Generator Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5050 I2C3TRN
15:0 — — — — — — — — Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5060 I2C3RCV
15:0 — — — — — — — — Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000

PIC32MX5XX/6XX/7XX
5100 I2C4CON
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
31:16 — — — — — — — — — — — — — — — — 0000
5110 I2C4STAT
15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5120 I2C4ADD
15:0 — — — — — — ADD<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5130 I2C4MSK
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5140 I2C4BRG
15:0 — — — — Baud Rate Generator Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5150 I2C4TRN
15:0 — — — — — — — — Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5160 I2C4RCV
15:0 — — — — — — — — Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5200 I2C5CON
DS60001156K-page 201

15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
31:16 — — — — — — — — — — — — — — — — 0000
5210 I2C5STAT
15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5220 I2C5ADD
15:0 — — — — — — ADD<9:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
2: This register is not available on 64-pin devices.
DS60001156K-page 202
TABLE 19-1: I2C1THROUGH I2C5 REGISTER MAP (CONTINUED)

PIC32MX5XX/6XX/7XX
Virtual Address
Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
5230 I2C5MSK
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5240 I2C5BRG
15:0 — — — — Baud Rate Generator Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5250 I2C5TRN
15:0 — — — — — — — — Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5260 I2C5RCV
15:0 — — — — — — — — Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5300 I2C1CON
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
31:16 — — — — — — — — — — — — — — — — 0000
5310 I2C1STAT
15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
31:16 — — — — — — — — — — — — — — — — 0000
5320 I2C1ADD
15:0 — — — — — — ADD<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5330 I2C1MSK
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5340 I2C1BRG
15:0 — — — — Baud Rate Generator Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5350 I2C1TRN
15:0 — — — — — — — — Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5360 I2C1RCV
15:0 — — — — — — — — Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5400 I2C2CON(2)
15:0 ON — SIDL SCLREL STRICT A10M DISSLW SMEN GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN 1000
31:16 — — — — — — — — — — — — — — — — 0000
5410 I2C2STAT(2)
15:0 ACKSTAT TRSTAT — — — BCL GCSTAT ADD10 IWCOL I2COV D/A P S R/W RBF TBF 0000
 2009-2019 Microchip Technology Inc.

31:16 — — — — — — — — — — — — — — — — 0000
5420 I2C2ADD(2)
15:0 — — — — — — ADD<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5430 I2C2MSK(2)
15:0 — — — — — — MSK<9:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
5440 I2C2BRG(2)
15:0 — — — — Baud Rate Generator Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5450 I2C2TRN(2)
15:0 — — — — — — — — Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
5460 I2C2RCV(2)
15:0 — — — — — — — — Receive Register 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table except I2CxRCV have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
2: This register is not available on 64-pin devices.
 PIC32MX5XX/6XX/7XX
REGISTER 19-1: I2CXCON: I2C CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 R/W-1, HC R/W-0 R/W-0 R/W-0 R/W-0
15:8
ON(1) — SIDL SCLREL STRICT A10M DISSLW SMEN
R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC
7:0
GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN

Legend: HC = Cleared by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: I2C Enable bit(1)
1 = Enables the I2C module and configures the SDA and SCL pins as serial port pins
0 = Disables the I2C module; all I2C pins are controlled by PORT functions
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation when device enters Idle mode
bit 12 SCLREL: SCLx Release Control bit (when operating as I2C slave)
1 = Release SCLx clock
0 = Hold SCLx clock low (clock stretch)
If STREN = 1:
Bit is R/W (software can write ‘0’ to initiate stretch and write ‘1’ to release clock). Cleared by hardware at
the beginning of a slave transmission and at the end of slave reception.
If STREN = 0:
Bit is R/S (software can only write ‘1’ to release clock). Cleared by hardware at the beginning of slave
transmission.
bit 11 STRICT: Strict I2C Reserved Address Rule Enable bit
1 = Strict reserved addressing is enforced. Device does not respond to reserved address space or generate
addresses in reserved address space.
0 = Strict I2C reserved address rule is not enabled
bit 10 A10M: 10-bit Slave Address bit
1 = I2CxADD is a 10-bit slave address
0 = I2CxADD is a 7-bit slave address
bit 9 DISSLW: Disable Slew Rate Control bit
1 = Slew rate control is disabled
0 = Slew rate control is enabled
bit 8 SMEN: SMBus Input Levels bit
1 = Enable I/O pin thresholds compliant with SMBus specification
0 = Disable SMBus input thresholds

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

 2009-2019 Microchip Technology Inc. DS60001156K-page 203

PIC32MX5XX/6XX/7XX
REGISTER 19-1: I2CXCON: I2C CONTROL REGISTER (CONTINUED)
bit 7 GCEN: General Call Enable bit (when operating as I2C slave)
1 = Enable interrupt when a general call address is received in the I2CxRSR
(module is enabled for reception)
0 = General call address is disabled
bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave)
Used in conjunction with SCLREL bit.
1 = Enable software or receive clock stretching
0 = Disable software or receive clock stretching
bit 5 ACKDT: Acknowledge Data bit (when operating as I2C master, applicable during master receive)
Value that is transmitted when the software initiates an acknowledge sequence.
1 = Send NACK during an acknowledge
0 = Send ACK during an acknowledge
bit 4 ACKEN: Acknowledge Sequence Enable bit (when operating as I2C master, applicable during master
receive)
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit.
Hardware clear at end of master Acknowledge sequence.
0 = Acknowledge sequence not in progress
bit 3 RCEN: Receive Enable bit (when operating as I2C master)
1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte.
0 = Receive sequence is not in progress
bit 2 PEN: Stop Condition Enable bit (when operating as I2C master)
1 = Initiate Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence.
0 = Stop condition is not in progress
bit 1 RSEN: Repeated Start Condition Enable bit (when operating as I2C master)
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated
Start sequence.
0 = Repeated Start condition is not in progress
bit 0 SEN: Start Condition Enable bit (when operating as I2C master)
1 = Initiate Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence.
0 = Start condition is not in progress

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

DS60001156K-page 204  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 19-2: I2CXSTAT: I2C STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC
15:8
ACKSTAT TRSTAT — — — BCL GCSTAT ADD10
R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC
7:0
IWCOL I2COV D_A P S R_W RBF TBF

Legend: HS = Set by hardware HSC = Hardware set/cleared

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared C = Clearable bit

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ACKSTAT: Acknowledge Status bit (when operating as I2C master, applicable to master transmit operation)
This bit is set or cleared by hardware at the end of a slave Acknowledge.
1 = NACK received from slave
0 = ACK received from slave
bit 14 TRSTAT: Transmit Status bit (when operating as I2C master, applicable to master transmit operation)
This bit is set by hardware at the beginning of a master transmission, and is cleared by hardware at the end
of a slave Acknowledge.
1 = Master transmit is in progress (8 bits + ACK)
0 = Master transmit is not in progress
bit 13-11 Unimplemented: Read as ‘0’
bit 10 BCL: Master Bus Collision Detect bit
This bit is set by hardware at the detection of a bus collision.
1 = A bus collision has been detected during a master operation
0 = No collision
bit 9 GCSTAT: General Call Status bit
This bit is set by hardware when the address matches the general call address, and is cleared by hardware
clear at a Stop detection.
1 = General call address was received
0 = General call address was not received
bit 8 ADD10: 10-bit Address Status bit
This bit is set by hardware upon a match of the 2nd byte of the matched 10-bit address, and is cleared by
hardware at a Stop detection.
1 = 10-bit address was matched
0 = 10-bit address was not matched
bit 7 IWCOL: Write Collision Detect bit
This bit is set by hardware at the occurrence of a write to I2CxTRN while busy (cleared by software).
1 = An attempt to write the I2CxTRN register failed because the I2C module is busy
0 = No collision
bit 6 I2COV: Receive Overflow Flag bit
This bit is set by hardware at an attempt to transfer I2CxRSR to I2CxRCV (cleared by software).
1 = A byte was received while the I2CxRCV register is still holding the previous byte
0 = No overflow

 2009-2019 Microchip Technology Inc. DS60001156K-page 205

PIC32MX5XX/6XX/7XX
REGISTER 19-2: I2CXSTAT: I2C STATUS REGISTER (CONTINUED)
bit 5 D_A: Data/Address bit (when operating as I2C slave)
This bit is cleared by hardware upon a device address match, and is set by hardware by reception of the
slave byte.
1 = Indicates that the last byte received was data
0 = Indicates that the last byte received was device address
bit 4 P: Stop bit
This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
1 = Indicates that a Stop bit has been detected last
0 = Stop bit was not detected last
bit 3 S: Start bit
This bit is set or cleared by hardware when a Start, Repeated Start, or Stop condition is detected.
1 = Indicates that a Start (or Repeated Start) bit has been detected last
0 = Start bit was not detected last
bit 2 R_W: Read/Write Information bit (when operating as I2C slave)
This bit is set or cleared by hardware after reception of an I 2C device address byte.
1 = Read – indicates data transfer is output from slave
0 = Write – indicates data transfer is input to slave
bit 1 RBF: Receive Buffer Full Status bit
This bit is set by hardware when the I2CxRCV register is written with a received byte, and is cleared by
hardware when software reads I2CxRCV.
1 = Receive complete, I2CxRCV is full
0 = Receive not complete, I2CxRCV is empty
bit 0 TBF: Transmit Buffer Full Status bit
This bit is set by hardware when software writes to the I2CxTRN register, and is cleared by hardware upon
completion of data transmission.
1 = Transmit in progress, I2CxTRN is full
0 = Transmit complete, I2CxTRN is empty

DS60001156K-page 206  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
20.0 UNIVERSAL ASYNCHRONOUS The following are primary features of the UART
module:
RECEIVER TRANSMITTER
(UART) • Full-duplex, 8-bit or 9-bit data transmission
• Even, Odd or No Parity options (for 8-bit data)
Note: This data sheet summarizes the features • One or two Stop bits
of the PIC32MX5XX/6XX/7XX family of • Hardware auto-baud feature
devices. It is not intended to be a
• Hardware flow control option
comprehensive reference source. To
complement the information in this data • Fully integrated Baud Rate Generator (BRG) with
sheet, refer to Section 21. “Universal 16-bit prescaler
Asynchronous Receiver Transmitter • Baud rates ranging from 76 bps to 20 Mbps at
(UART)” (DS60001107) in the “PIC32 80 MHz
Family Reference Manual”, which is avail- • 8-level deep First-In-First-Out (FIFO) transmit
able from the Microchip web site data buffer
(www.microchip.com/PIC32). • 8-level deep FIFO receive data buffer
The UART module is one of the serial I/O modules • Parity, framing and buffer overrun error detection
available in the PIC32MX5XX/6XX/7XX family of • Support for interrupt-only on address detect
devices. The UART is a full-duplex, asynchronous (ninth bit = 1)
communication channel that communicates with • Separate transmit and receive interrupts
peripheral devices and personal computers through • Loopback mode for diagnostic support
protocols, such as RS-232, RS-485, LIN 1.2 and IrDA®.
The module also supports the hardware flow control • LIN 2.1 Protocol support
option, with UxCTS and UxRTS pins, and also includes • IrDA encoder and decoder with 16x baud clock
an IrDA encoder and decoder. output for external IrDA encoder/decoder support
Figure 20-1 illustrates a simplified block diagram of the
UART module.

FIGURE 20-1: UART SIMPLIFIED BLOCK DIAGRAM

Baud Rate Generator

IrDA® BCLKx

UxRTS
Hardware Flow Control
UxCTS

UARTx Receiver UxRX

UARTx Transmitter UxTX

Note: Not all pins are available for all UART modules. Refer to the device-specific pin diagram for more information
(see “Device Pin Tables”).

 2009-2019 Microchip Technology Inc. DS60001156K-page 207

PIC32MX5XX/6XX/7XX
Figure 20-2 and Figure 20-3 illustrate typical receive
and transmit timing for the UART module.

FIGURE 20-2: UART RECEPTION

Char 1 Char 2-4 Char 5-10 Char 11-13

Read to
UxRXREG

UxRX Start 1 Stop Start 2 Stop 4 Start 5 Stop 10 Start 11 Stop 13

RIDLE
Cleared by
Software
OERR
Cleared by
Software
UxRXIF
URXISEL = 00
Cleared by
Software

UxRXIF
URXISEL = 01

UxRXIF
URXISEL = 10

FIGURE 20-3: TRANSMISSION (8-BIT OR 9-BIT DATA)

8 into TxBUF

Write to
UxTXREG
TSR
BCLK/16 Pull from Buffer
(Shift Clock)

UxTX Start Bit 0 Bit 1 Stop Start Bit 1

UxTXIF
UTXISEL = 00

UxTXIF
UTXISEL = 01

UxTXIF
UTXISEL = 10

DS60001156K-page 208  2009-2019 Microchip Technology Inc.

 20.1 Control Registers
 2009-2019 Microchip Technology Inc.

TABLE 20-1: UART1 THROUGH UART6 REGISTER MAP

Virtual Address

Bits

All Resets
Bit Range
(BF80_#)

Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6000 U1MODE(1)
15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6010 U1STA(1)
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
31:16 — — — — — — — — — — — — — — — — 0000
6020 U1TXREG
15:0 — — — — — — — TX8 Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6030 U1RXREG
15:0 — — — — — — — RX8 Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6040 U1BRG(1)
15:0 BRG<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
6200 U4MODE(1)
15:0 ON — SIDL IREN — — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
(1) 31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6210 U4STA
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
31:16 — — — — — — — — — — — — — — — — 0000

PIC32MX5XX/6XX/7XX
6220 U4TXREG
15:0 — — — — — — — TX8 Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6230 U4RXREG
15:0 — — — — — — — RX8 Receive Register 0000
(1) 31:16 — — — — — — — — — — — — — — — — 0000
6240 U4BRG
15:0 BRG<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
6400 U3MODE(1)
15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6410 U3STA(1)
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
31:16 — — — — — — — — — — — — — — — — 0000
6420 U3TXREG
15:0 — — — — — — — TX8 Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6430 U3RXREG
15:0 — — — — — — — RX8 Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6440 U3BRG(1)
DS60001156K-page 209

15:0 BRG<15:0> 0000

(1) 31:16 — — — — — — — — — — — — — — — — 0000
6600 U6MODE
15:0 ON — SIDL IREN — — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6610 U6STA(1)
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DS60001156K-page 210
TABLE 20-1: UART1 THROUGH UART6 REGISTER MAP (CONTINUED)

PIC32MX5XX/6XX/7XX
Virtual Address
Bits

All Resets
Bit Range
(BF80_#)

Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
6620 U6TXREG
15:0 — — — — — — — TX8 Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6630 U6RXREG
15:0 — — — — — — — RX8 Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6640 U6BRG(1)
15:0 BRG<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
6800 U2MODE(1)
15:0 ON — SIDL IREN RTSMD — UEN<1:0> WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6810 U2STA(1)
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
31:16 — — — — — — — — — — — — — — — — 0000
6820 U2TXREG
15:0 — — — — — — — TX8 Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6830 U2RXREG
15:0 — — — — — — — RX8 Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6840 U2BRG(1)
15:0 BRG<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
6A00 U5MODE(1)
15:0 ON — SIDL IREN — — — — WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL 0000
31:16 — — — — — — — ADM_EN ADDR<7:0> 0000
6A10 U5STA(1)
15:0 UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA 0110
31:16 — — — — — — — — — — — — — — — — 0000
6A20 U5TXREG
15:0 — — — — — — — TX8 Transmit Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6A30 U5RXREG
15:0 — — — — — — — RX8 Receive Register 0000
31:16 — — — — — — — — — — — — — — — — 0000
6A40 U5BRG(1)
15:0 BRG<15:0> 0000
 2009-2019 Microchip Technology Inc.

Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
 PIC32MX5XX/6XX/7XX
REGISTER 20-1: UxMODE: UARTx MODE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0
15:8
ON(1) — SIDL IREN RTSMD — UEN<1:0>
R/W-0 R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
WAKE LPBACK ABAUD RXINV BRGH PDSEL<1:0> STSEL

Legend: HC = Cleared by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: UARTx Enable bit(1)
1 = UARTx is enabled. UARTx pins are controlled by UARTx as defined by UEN<1:0> and UTXEN
control bits.
0 = UARTx is disabled. All UARTx pins are controlled by corresponding bits in the PORTx, TRISx and LATx
registers; UARTx power consumption is minimal.
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue operation when device enters Idle mode
0 = Continue operation when device enters Idle mode
bit 12 IREN: IrDA Encoder and Decoder Enable bit
1 = IrDA is enabled
0 = IrDA is disabled
bit 11 RTSMD: Mode Selection for UxRTS Pin bit
1 = UxRTS pin is in Simplex mode
0 = UxRTS pin is in Flow Control mode
bit 10 Unimplemented: Read as ‘0’
bit 9-8 UEN<1:0>: UARTx Enable bits
11 = UxTX, UxRX and UxBCLK pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used
01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin is controlled by corresponding bits
in the PORTx register
00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/UxBCLK pins are controlled by
corresponding bits in the PORTx register
bit 7 WAKE: Enable Wake-up on Start bit Detect During Sleep Mode bit
1 = Wake-up is enabled
0 = Wake-up is disabled
bit 6 LPBACK: UARTx Loopback Mode Select bit
1 = Loopback mode is enabled
0 = Loopback mode is disabled

Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

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PIC32MX5XX/6XX/7XX
REGISTER 20-1: UxMODE: UARTx MODE REGISTER (CONTINUED)
bit 5 ABAUD: Auto-Baud Enable bit
1 = Enable baud rate measurement on the next character – requires reception of Sync character (0x55);
cleared by hardware upon completion
0 = Baud rate measurement disabled or completed
bit 4 RXINV: Receive Polarity Inversion bit
1 = UxRX Idle state is ‘0’
0 = UxRX Idle state is ‘1’
bit 3 BRGH: High Baud Rate Enable bit
1 = High-Speed mode – 4x baud clock enabled
0 = Standard Speed mode – 16x baud clock enabled
bit 2-1 PDSEL<1:0>: Parity and Data Selection bits
11 = 9-bit data, no parity
10 = 8-bit data, odd parity
01 = 8-bit data, even parity
00 = 8-bit data, no parity
bit 0 STSEL: Stop Selection bit
1 = 2 Stop bits
0 = 1 Stop bit

Note 1: When using the 1:1 PBCLK divisor, the user software should not read/write the peripheral SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.

DS60001156K-page 212  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0
31:24
— — — — — — — ADM_EN
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
ADDR<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0 R-0 R-1
15:8
UTXISEL<1:0> UTXINV URXEN UTXBRK UTXEN UTXBF TRMT
R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/W-0, HS R-0
7:0
URXISEL<1:0> ADDEN RIDLE PERR FERR OERR URXDA

Legend: HS = Set by hardware HC = Cleared by hardware

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-25 Unimplemented: Read as ‘0’

bit 24 ADM_EN: Automatic Address Detect Mode Enable bit
1 = Automatic Address Detect mode is enabled
0 = Automatic Address Detect mode is disabled
bit 23-16 ADDR<7:0>: Automatic Address Mask bits
When the ADM_EN bit is ‘1’, this value defines the address character to use for automatic address
detection.
bit 15-14 UTXISEL<1:0>: TX Interrupt Mode Selection bits
11 = Reserved, do not use
10 = Interrupt is generated and asserted while the transmit buffer is empty
01 = Interrupt is generated and asserted when all characters have been transmitted
00 = Interrupt is generated and asserted while the transmit buffer contains at least one empty space
bit 13 UTXINV: Transmit Polarity Inversion bit
If IrDA mode is disabled (i.e., IREN (UxMODE<12>) is ‘0’):
1 = UxTX Idle state is ‘0’
0 = UxTX Idle state is ‘1’

If IrDA mode is enabled (i.e., IREN (UxMODE<12>) is ‘1’):

1 = IrDA encoded UxTX Idle state is ‘1’
0 = IrDA encoded UxTX Idle state is ‘0’
bit 12 URXEN: Receiver Enable bit
1 = UARTx receiver is enabled. UxRX pin is controlled by UARTx (if ON = 1)
0 = UARTx receiver is disabled. UxRX pin is ignored by the UARTx module. UxRX pin is controlled by port.
bit 11 UTXBRK: Transmit Break bit
1 = Send Break on next transmission. Start bit followed by twelve ‘0’ bits, followed by Stop bit; cleared by
hardware upon completion.
0 = Break transmission is disabled or completed
bit 10 UTXEN: Transmit Enable bit
1 = UARTx transmitter is enabled. UxTX pin is controlled by UARTx (if ON = 1)
0 = UARTx transmitter is disabled. Any pending transmission is aborted and buffer is reset. UxTX pin is
controlled by port.
bit 9 UTXBF: Transmit Buffer Full Status bit (read-only)
1 = Transmit buffer is full
0 = Transmit buffer is not full, at least one more character can be written

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PIC32MX5XX/6XX/7XX
REGISTER 20-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED)
bit 8 TRMT: Transmit Shift Register is Empty bit (read-only)
1 = Transmit shift register is empty and transmit buffer is empty (the last transmission has completed)
0 = Transmit shift register is not empty, a transmission is in progress or queued in the transmit buffer
bit 7-6 URXISEL<1:0>: Receive Interrupt Mode Selection bit
11 = Reserved
10 = Interrupt flag bit is asserted while receive buffer is 3/4 or more full (has 6 or more data characters)
01 = Interrupt flag bit is asserted while receive buffer is 1/2 or more full (has 4 or more data characters)
00 = Interrupt flag bit is asserted while receive buffer is not empty (has at least 1 data character)
bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1)
1 = Address Detect mode is enabled. If 9-bit mode is not selected, this control bit has no effect.
0 = Address Detect mode is disabled
bit 4 RIDLE: Receiver Idle bit (read-only)
1 = Receiver is idle
0 = Data is being received
bit 3 PERR: Parity Error Status bit (read-only)
1 = Parity error has been detected for the current character
0 = Parity error has not been detected
bit 2 FERR: Framing Error Status bit (read-only)
1 = Framing error has been detected for the current character
0 = Framing error has not been detected
bit 1 OERR: Receive Buffer Overrun Error Status bit.
This bit is set in hardware and can only be cleared (= 0) in software. Clearing a previously set OERR bit
resets the receiver buffer and RSR to an empty state.
1 = Receive buffer has overflowed
0 = Receive buffer has not overflowed
bit 0 URXDA: Receive Buffer Data Available bit (read-only)
1 = Receive buffer has data, at least one more character can be read
0 = Receive buffer is empty

DS60001156K-page 214  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
21.0 PARALLEL MASTER PORT The following are key features of the PMP module:
(PMP) • 8-bit and 16-bit interface
• Up to 16 programmable address lines
Note: This data sheet summarizes the features
• Up to two Chip Select lines
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a • Programmable strobe options
comprehensive reference source. To - Individual read and write strobes, or
complement the information in this data - Read/Write strobe with enable strobe
sheet, refer to Section 13. “Parallel Mas- • Address auto-increment/auto-decrement
ter Port (PMP)” (DS60001128) in the • Programmable address/data multiplexing
“PIC32 Family Reference Manual”, which
• Programmable polarity on control signals
is available from the Microchip web site
(www.microchip.com/PIC32). • Parallel Slave Port support
- Legacy addressable
The PMP is a parallel 8-bit/16-bit input/output module - Address support
specifically designed to communicate with a wide
- 4-byte deep auto-incrementing buffer
variety of parallel devices, such as communications
peripherals, LCDs, external memory devices and • Programmable wait states
microcontrollers. Because the interface to parallel • Operates during Sleep and Idle modes
peripherals varies significantly, the PMP module is • Fast bit manipulation using CLR, SET and INV
highly configurable. Figure 21-1 shows the PMP registers
module pinout and its connections to external devices.
Note: On 64-pin devices, the PMD<15:8> data
pins are not available.

FIGURE 21-1: PMP MODULE PINOUT AND CONNECTIONS TO EXTERNAL DEVICES

Address Bus
Data Bus
Control Lines
PIC32MX5XX/6XX/7XX PMA<0>
PMALL
Parallel
Master Port
PMA<1>
PMALH
Up to 16-bit Address Flash
PMA<13:2> EEPROM
SRAM
PMA<14>
PMCS1

PMA<15>
PMCS2

PMRD
PMRD/PMWR
FIFO
PMWR Microcontroller LCD
PMENB Buffer

PMD<7:0>
PMD<15:8>(1)
16/8-bit Data (with or without multiplexed addressing)

Note 1: On 64-pin devices, data pins, PMD<15:8>, are not available in 16-bit Master modes.

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DS60001156K-page 216
21.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 21-1: PARALLEL MASTER PORT REGISTER MAP
Virtual Address Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
7000 PMCON
15:0 ON — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN CSF<1:0> ALP CS2P CS1P — WRSP RDSP 0000
31:16 — — — — — — — — — — — — — — — — 0000
7010 PMMODE
15:0 BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0> WAITB<1:0> WAITM<3:0> WAITE<1:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
7020 PMADDR
15:0 CS2EN/A15 CS1EN/A14 ADDR<13:0> 0000
31:16 0000
7030 PMDOUT DATAOUT<31:0>
15:0 0000
31:16 0000
7040 PMDIN DATAIN<31:0>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
7050 PMAEN
15:0 PTEN<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
7060 PMSTAT
15:0 IBF IBOV — — IB3F IB2F IB1F IB0F OBE OBUF — — OB3E OB2E OB1E OB0E 008F
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 21-1: PMCON: PARALLEL PORT CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
ON(1) — SIDL ADRMUX<1:0> PMPTTL PTWREN PTRDEN
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
7:0 (2) (2) (2)
CSF<1:0> ALP — CS1P — WRSP RDSP

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Parallel Master Port Enable bit(1)
1 = PMP is enabled
0 = PMP is disabled, no off-chip access performed
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation when device enters Idle mode
bit 12-11 ADRMUX<1:0>: Address/Data Multiplexing Selection bits
11 = All 16 bits of address are multiplexed on PMD<15:0> pins
10 = All 16 bits of address are multiplexed on PMD<7:0> pins
01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper bits are on PMA<15:8>
00 = Address and data appear on separate pins
bit 10 PMPTTL: PMP Module TTL Input Buffer Select bit
1 = PMP module uses TTL input buffers
0 = PMP module uses Schmitt Trigger input buffer
bit 9 PTWREN: Write Enable Strobe Port Enable bit
1 = PMWR/PMENB port is enabled
0 = PMWR/PMENB port is disabled
bit 8 PTRDEN: Read/Write Strobe Port Enable bit
1 = PMRD/PMWR port is enabled
0 = PMRD/PMWR port is disabled
bit 7-6 CSF<1:0>: Chip Select Function bits(2)
11 = Reserved
10 = PMCS2 and PMCS1 function as Chip Select
01 = PMCS2 functions as Chip Select, PMCS1 functions as address bit 14
00 = PMCS2 and PMCS1 function as address bits 15 and 14(2)

bit 5 ALP: Address Latch Polarity bit(2)

1 = Active-high (PMALL and PMALH)
0 = Active-low (PMALL and PMALH)
bit 4 Unimplemented: Read as ‘0’
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.

 2009-2019 Microchip Technology Inc. DS60001156K-page 217

PIC32MX5XX/6XX/7XX
REGISTER 21-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED)
bit 3 CS1P: Chip Select 0 Polarity bit(2)
1 = Active-high (PMCS1)
0 = Active-low (PMCS1)
bit 2 Unimplemented: Read as ‘0’
bit 1 WRSP: Write Strobe Polarity bit
For Slave Modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1 = Write strobe active-high (PMWR)
0 = Write strobe active-low (PMWR)
For Master mode 1 (PMMODE<9:8> = 11):
1 = Enable strobe active-high (PMENB)
0 = Enable strobe active-low (PMENB)
bit 0 RDSP: Read Strobe Polarity bit
For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10):
1 = Read Strobe active-high (PMRD)
0 = Read Strobe active-low (PMRD)
For Master mode 1 (PMMODE<9:8> = 11):
1 = Read/write strobe active-high (PMRD/PMWR)
0 = Read/write strobe active-low (PMRD/PMWR)

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON control bit.
2: These bits have no effect when their corresponding pins are used as address lines.

DS60001156K-page 218  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 21-2: PMMODE: PARALLEL PORT MODE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
BUSY IRQM<1:0> INCM<1:0> MODE16 MODE<1:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0 (1) (1)
WAITB<1:0> WAITM<3:0> WAITE<1:0>(1)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 BUSY: Busy bit (only Master mode)
1 = Port is busy
0 = Port is not busy
bit 14-13 IRQM<1:0>: Interrupt Request Mode bits (4)
11 = Reserved
10 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode)
or on a read or write operation when PMA<1:0> =11 (only Addressable Slave mode)
01 = Interrupt generated at the end of the read/write cycle
00 = Interrupt is not generated
bit 12-11 INCM<1:0>: Increment Mode bits
11 = Slave mode read and write buffers auto-increment (only PMMODE<1:0> = 00)
10 = Decrement ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2)
01 = Increment ADDR<10:2> and ADDR<14> by 1 every read/write cycle(2)
00 = No increment or decrement of address
bit 10 MODE16: 8/16-bit Mode bit
1 = 16-bit mode: a read or write to the data register invokes a single 16-bit transfer
0 = 8-bit mode: a read or write to the data register invokes a single 8-bit transfer
bit 9-8 MODE<1:0>: Parallel Port Mode Select bits
11 = Master mode 1 PMCSx, PMRD/PMWR, PMENB, PMA<x:0>, PMD<7:0> and PMD<8:15>(3))
10 = Master mode 2 (PMCSx, PMRD, PMWR, PMA<x:0>, PMD<7:0> and PMD<8:15>(3))
01 = Enhanced Slave mode, control signals (PMRD, PMWR, PMCS1, PMD<7:0>, and PMA<1:0>)
00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1, and PMD<7:0>)
bit 7-6 WAITB<1:0>: Data Setup to Read/Write Strobe Wait States bits(1)
11 = Data wait of 4 TPB; multiplexed address phase of 4 TPB
10 = Data wait of 3 TPB; multiplexed address phase of 3 TPB
01 = Data wait of 2 TPB; multiplexed address phase of 2 TPB
00 = Data wait of 1 TPB; multiplexed address phase of 1 TPB (default)

Note 1: Whenever WAITM<3:0> = 0000, the WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for
a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment or auto-decrement if configured as Chip Select CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).
4: These bits only control generating the Parallel Master Port (PMP) interrupt. The Parallel Master Port Error
(PMPE) is always generated.

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PIC32MX5XX/6XX/7XX
REGISTER 21-2: PMMODE: PARALLEL PORT MODE REGISTER (CONTINUED)
bit 5-2 WAITM<3:0>: Data Read/Write Strobe Wait States bits(1)
1111 = Wait of 16 TPB
•
•
•
0001 = Wait of 2 TPB
0000 = Wait of 1 TPB (default)
bit 1-0 WAITE<1:0>: Data Hold After Read/Write Strobe Wait States bits(1)
11 = Wait of 4 TPB
10 = Wait of 3 TPB
01 = Wait of 2 TPB
00 = Wait of 1 TPB (default)

For Read operations:

11 = Wait of 3 TPB
10 = Wait of 2 TPB
01 = Wait of 1 TPB
00 = Wait of 0 TPB (default)

Note 1: Whenever WAITM<3:0> = 0000, the WAITB and WAITE bits are ignored and forced to 1 TPBCLK cycle for
a write operation; WAITB = 1 TPBCLK cycle, WAITE = 0 TPBCLK cycles for a read operation.
2: Address bit A14 is not subject to auto-increment or auto-decrement if configured as Chip Select CS1.
3: These pins are active when MODE16 = 1 (16-bit mode).
4: These bits only control generating the Parallel Master Port (PMP) interrupt. The Parallel Master Port Error
(PMPE) is always generated.

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 PIC32MX5XX/6XX/7XX
REGISTER 21-3: PMADDR: PARALLEL PORT ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
(1) (3)
15:8 CS2 CS1
ADDR<13:8>
ADDR15(2) ADDR14(4)
7:0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
ADDR<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 CS2: Chip Select 2 bit(1)
1 = Chip Select 2 is active
0 = Chip Select 2 is inactive
bit 15 ADDR<15>: Destination Address bit 15(2)
bit 14 CS1: Chip Select 1 bit(3)
1 = Chip Select 1 is active
0 = Chip Select 1 is inactive
bit 14 ADDR<14>: Destination Address bit 14(4)
bit 13-0 ADDR<13:0>: Address bits

Note 1: When the CSF<1:0> bits (PMCON<7:6>) = 10 or 01.

2: When the CSF<1:0> bits (PMCON<7:6>) = 00.
3: When the CSF<1:0> bits (PMCON<7:6>) = 10.
4: When the CSF<1:0> bits (PMCON<7:6>) = 00 or 01.

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PIC32MX5XX/6XX/7XX
REGISTER 21-4: PMAEN: PARALLEL PORT PIN ENABLE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8 (1)
PTEN<15:14> — — — PTEN<10:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
PTEN<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-14 PTEN<15:14>: PMCSx Address Port Enable bits
1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1(1)
0 = PMA15 and PMA14 function as port I/O
bit 13-11 Unimplemented: Read as ‘0’
bit 10-2 PTEN<10:2>: PMP Address Port Enable bits
1 = PMA<10:2> function as PMP address lines
0 = PMA<10:2> function as port I/O
bit 1-0 PTEN<1:0>: PMALH/PMALL Strobe Enable bits
1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL(2)
0 = PMA1 and PMA0 pads function as port I/O

Note 1: The use of these pins as PMA15/PMA14 or CS2/CS1 is selected by the CSF<1:0> bits (PMCON<7:6>).
2: The use of these pins as PMA1/PMA0 or PMALH/PMALL depends on the Address/Data Multiplex mode
selected by bits ADRMUX<1:0> in the PMCON register.

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 PIC32MX5XX/6XX/7XX
REGISTER 21-5: PMSTAT: PARALLEL PORT STATUS REGISTER (ONLY SLAVE MODES)
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R-0 R/W-0, HS, SC U-0 U-0 R-0 R-0 R-0 R-0
15:8
IBF IBOV — — IB3F IB2F IB1F IB0F
R-1 R/W-0, HS, SC U-0 U-0 R-1 R-1 R-1 R-1
7:0
OBE OBUF — — OB3E OB2E OB1E OB0E

Legend: HS = Set by Hardware SC = Cleared by software

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 IBF: Input Buffer Full Status bit
1 = All writable input buffer registers are full
0 = Some or all of the writable input buffer registers are empty
bit 14 IBOV: Input Buffer Overflow Status bit
1 = A write attempt to a full input byte buffer occurred (must be cleared in software)(1)
0 = An overflow has not occurred
bit 13-12 Unimplemented: Read as ‘0’
bit 11-8 IBxF: Input Buffer ‘x’ Status Full bits
1 = Input buffer contains data that has not been read (reading buffer will clear this bit)
0 = Input buffer does not contain any unread data
bit 7 OBE: Output Buffer Empty Status bit
1 = All readable output buffer registers are empty
0 = Some or all of the readable output buffer registers are full
bit 6 OBUF: Output Buffer Underflow Status bit
1 = A read occurred from an empty output byte buffer (must be cleared in software)(1)
0 = An underflow has not occurred
bit 5-4 Unimplemented: Read as ‘0’
bit 3-0 OBxE: Output Buffer ‘x’ Status Empty bits
1 = Output buffer is empty (writing data to the buffer will clear this bit)
0 = Output buffer contains data that has not been transmitted
Note 1: This will generate a PMPE – Parallel Master Port Error interrupt.

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PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 224  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
22.0 REAL-TIME CLOCK AND Key features of the RTCC module include:
CALENDAR (RTCC) • Time: hours, minutes and seconds
• 24-hour format (military time)
Note: This data sheet summarizes the features
• Visibility of one-half second period
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a • Provides calendar: Weekday, date, month and year
comprehensive reference source. To • Alarm intervals are configurable for half of a
complement the information in this data second, one second, 10 seconds, one minute, 10
sheet, refer to Section 29. “Real-Time minutes, one hour, one day, one week, one month
Clock and Calendar (RTCC)” and one year
(DS60001125) in the “PIC32 Family Ref- • Alarm repeat with decrementing counter
erence Manual”, which is available from • Alarm with indefinite repeat: Chime
the Microchip web site (www.micro- • Year range: 2000 to 2099
chip.com/PIC32).
• Leap year correction
The PIC32 RTCC module is intended for applications • BCD format for smaller firmware overhead
in which accurate time must be maintained for • Optimized for long-term battery operation
extended periods of time with minimal or no CPU • Fractional second synchronization
intervention. Low-power optimization provides
• User calibration of the clock crystal frequency with
extended battery lifetime while keeping track of time.
auto-adjust
A simplified block diagram of the RTCC module is
illustrated in Figure 22-1. • Calibration range: 0.66 seconds error per month
• Calibrates up to 260 ppm of crystal error
• Requirements: External 32.768 kHz clock crystal
• Alarm pulse or seconds clock output on RTCC pin

FIGURE 22-1: RTCC BLOCK DIAGRAM

32.768 kHz Input

from Secondary
Oscillator (SOSC)
RTCC Prescalers
0.5s YEAR, MTH, DAY
RTCC Timer RTCVAL WKDAY
Alarm HR, MIN, SEC
Event
Comparator

MTH, DAY
Compare Registers ALRMVAL WKDAY
with Masks
HR, MIN, SEC
Repeat Counter

RTCC Interrupt
RTCC Interrupt Logic
Alarm Pulse
Seconds Pulse
RTCC Pin

RTCOE

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DS60001156K-page 226
22.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 22-1: RTCC REGISTER MAP
Virtual Address Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — CAL<9:0> 0000

0200 RTCCON
15:0 ON — SIDL — — — — — RTSECSEL RTCCLKON — — RTCWREN RTCSYNC HALFSEC RTCOE 0000
31:16 — — — — — — — — — — — — — — — — 0000
0210 RTCALRM
15:0 ALRMEN CHIME PIV ALRMSYNC AMASK<3:0> ARPT<7:0> 0000
31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
0220 RTCTIME
15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00
31:16 YEAR10<3:0> YEAR01<3:0> MONTH10<3:0> MONTH01<3:0> xxxx
0230 RTCDATE
15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx00
31:16 HR10<3:0> HR01<3:0> MIN10<3:0> MIN01<3:0> xxxx
0240 ALRMTIME
15:0 SEC10<3:0> SEC01<3:0> — — — — — — — — xx00
31:16 — — — — — — — — MONTH10<3:0> MONTH01<3:0> 00xx
0250 ALRMDATE
15:0 DAY10<3:0> DAY01<3:0> — — — — WDAY01<3:0> xx0x
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at its virtual address, plus an offset of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 22-1: RTCCON: RTC CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
31:24
— — — — — — CAL<9:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CAL<7:0>
R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
15:8
ON(1,2) — SIDL — — — — —
R/W-0 R-0 U-0 U-0 R/W-0 R-0 R-0 R/W-0
7:0
RTSECSEL(3) RTCCLKON — — RTCWREN(4) RTCSYNC HALFSEC(5) RTCOE

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-26 Unimplemented: Read as ‘0’

bit 25-16 CAL<9:0>: RTC Drift Calibration bits, which contain a signed 10-bit integer value
1111111111 = Minimum negative adjustment, subtracts 1 RTC clock pulse every one minute
•
•
•
1000000000 = Maximum negative adjustment, subtracts 512 clock pulses every one minute
0111111111 = Maximum positive adjustment, adds 511 RTC clock pulses every one minute
•
•
•
0000000001 = Minimum positive adjustment, adds 1 RTC clock pulse every one minute
0000000000 = No adjustment
bit 15 ON: RTCC On bit(1,2)
1 = RTCC module is enabled
0 = RTCC module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Disables the PBCLK to the RTCC when CPU enters in Idle mode
0 = Continue normal operation in Idle mode
bit 12-8 Unimplemented: Read as ‘0’
bit 7 RTSECSEL: RTCC Seconds Clock Output Select bit(3)
1 = RTCC Seconds Clock is selected for the RTCC pin
0 = RTCC Alarm Pulse is selected for the RTCC pin
bit 6 RTCCLKON: RTCC Clock Enable Status bit
1 = RTCC Clock is actively running
0 = RTCC Clock is not running
bit 5-4 Unimplemented: Read as ‘0’

Note 1: The ON bit is only writable when RTCWREN = 1.

2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
4: The RTCWREN bit can only be set when the write sequence is enabled.
5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).

Note: This register is only reset on a Power-on Reset (POR).

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PIC32MX5XX/6XX/7XX
REGISTER 22-1: RTCCON: RTC CONTROL REGISTER (CONTINUED)
bit 3 RTCWREN: RTC Value Registers Write Enable bit(4)
1 = RTC Value registers can be written to by the user
0 = RTC Value registers are locked out from being written to by the user
bit 2 RTCSYNC: RTCC Value Registers Read Synchronization bit
1 = RTC Value registers can change while reading, due to a rollover ripple that results in an invalid data
read. If the register is read twice and results in the same data, the data can be assumed to be valid.
0 = RTC Value registers can be read without concern about a rollover ripple
bit 1 HALFSEC: Half-Second Status bit(5)
1 = Second half period of a second
0 = First half period of a second
bit 0 RTCOE: RTCC Output Enable bit
1 = RTCC clock output is enabled (clock presented onto an I/O)
0 = RTCC clock output is disabled

Note 1: The ON bit is only writable when RTCWREN = 1.

2: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
3: Requires RTCOE = 1 (RTCCON<0>) for the output to be active.
4: The RTCWREN bit can only be set when the write sequence is enabled.
5: This bit is read-only. It is cleared to ‘0’ on a write to the seconds bit fields (RTCTIME<14:8>).

Note: This register is only reset on a Power-on Reset (POR).

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 PIC32MX5XX/6XX/7XX
REGISTER 22-2: RTCALRM: RTC ALARM CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
ALRMEN(1,2) CHIME(2) PIV (2)
ALRMSYNC(3) AMASK<3:0> (2)

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7:0
ARPT<7:0>(2)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ALRMEN: Alarm Enable bit(1,2)
1 = Alarm is enabled
0 = Alarm is disabled
bit 14 CHIME: Chime Enable bit(2)
1 = Chime is enabled – ARPT<7:0> is allowed to rollover from 0x00 to 0xFF
0 = Chime is disabled – ARPT<7:0> stops once it reaches 0x00
bit 13 PIV: Alarm Pulse Initial Value bit(3)
When ALRMEN = 0, PIV is writable and determines the initial value of the Alarm Pulse.
When ALRMEN = 1, PIV is read-only and returns the state of the Alarm Pulse.
bit 12 ALRMSYNC: Alarm Sync bit(3)
1 = ARPT<7:0> and ALRMEN may change as a result of a half second rollover during a read.
The ARPT must be read repeatedly until the same value is read twice. This must be done since multiple
bits may be changing, which are then synchronized to the PB clock domain.
0 = ARPT<7:0> and ALRMEN can be read without concerns of rollover because the prescaler is > 32 RTC
clocks away from a half-second rollover
bit 11-8 AMASK<3:0>: Alarm Mask Configuration bits(2)
1111 = Reserved
•
•
•
1010 = Reserved
1001 = Once a year (except when configured for February 29, once every four years)
1000 = Once a month
0111 = Once a week
0110 = Once a day
0101 = Every hour
0100 = Every 10 minutes
0011 = Every minute
0010 = Every 10 seconds
0001 = Every second
0000 = Every half-second

Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.

Note: This register is only reset on a Power-on Reset (POR).

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PIC32MX5XX/6XX/7XX
REGISTER 22-2: RTCALRM: RTC ALARM CONTROL REGISTER (CONTINUED)
bit 7-0 ARPT<7:0>: Alarm Repeat Counter Value bits(2)
11111111 = Alarm will trigger 256 times
•
•
•
00000000 = Alarm will trigger one time
The counter decrements on any alarm event. The counter only rolls over from 0x00 to 0xFF if CHIME = 1.

Note 1: Hardware clears the ALRMEN bit anytime the alarm event occurs, when ARPT<7:0> = 00 and
CHIME = 0.
2: This field should not be written when the RTCC ON bit = ‘1’ (RTCCON<15>) and ALRMSYNC = 1.
3: This assumes a CPU read will execute in less than 32 PBCLKs.

Note: This register is only reset on a Power-on Reset (POR).

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 PIC32MX5XX/6XX/7XX
REGISTER 22-3: RTCTIME: RTC TIME VALUE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
HR10<3:0> HR01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
MIN10<3:0> MIN01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
SEC10<3:0> SEC01<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0
— — — — — — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 HR10<3:0>: Binary-Coded Decimal Value of Hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary-Coded Decimal Value of Hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10<3:0>: Binary-Coded Decimal Value of Minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary-Coded Decimal Value of Minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10<3:0>: Binary-Coded Decimal Value of Seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8 SEC01<3:0>: Binary-Coded Decimal Value of Seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0 Unimplemented: Read as ‘0’

Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).

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PIC32MX5XX/6XX/7XX
REGISTER 22-4: RTCDATE: RTC DATE VALUE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
YEAR10<3:0> YEAR01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
MONTH10<3:0> MONTH01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
DAY10<3:0> DAY01<3:0>
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
7:0
— — — — WDAY01<3:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 YEAR10<3:0>: Binary-Coded Decimal Value of Years bits, 10 digits

bit 27-24 YEAR01<3:0>: Binary-Coded Decimal Value of Years bits, 1 digit
bit 23-20 MONTH10<3:0>: Binary-Coded Decimal Value of Months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary-Coded Decimal Value of Months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10<3:0>: Binary-Coded Decimal Value of Days bits, 10 digits; contains a value from 0 to 3
bit 11-8 DAY01<3:0>: Binary-Coded Decimal Value of Days bits, 1 digit; contains a value from 0 to 9
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 WDAY01<3:0>: Binary-Coded Decimal Value of Weekdays bits,1 digit; contains a value from 0 to 6

Note: This register is only writable when RTCWREN = 1 (RTCCON<3>).

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 PIC32MX5XX/6XX/7XX
REGISTER 22-5: ALRMTIME: ALARM TIME VALUE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
HR10<3:0> HR01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
MIN10<3:0> MIN01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
SEC10<3:0> SEC01<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0
— — — — — — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 HR10<3:0>: Binary Coded Decimal value of hours bits, 10 digits; contains a value from 0 to 2
bit 27-24 HR01<3:0>: Binary Coded Decimal value of hours bits, 1 digit; contains a value from 0 to 9
bit 23-20 MIN10<3:0>: Binary Coded Decimal value of minutes bits, 10 digits; contains a value from 0 to 5
bit 19-16 MIN01<3:0>: Binary Coded Decimal value of minutes bits, 1 digit; contains a value from 0 to 9
bit 15-12 SEC10<3:0>: Binary Coded Decimal value of seconds bits, 10 digits; contains a value from 0 to 5
bit 11-8 SEC01<3:0>: Binary Coded Decimal value of seconds bits, 1 digit; contains a value from 0 to 9
bit 7-0 Unimplemented: Read as ‘0’

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PIC32MX5XX/6XX/7XX
REGISTER 22-6: ALRMDATE: ALARM DATE VALUE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
23:16
MONTH10<3:0> MONTH01<3:0>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
DAY10<1:0> DAY01<3:0>
U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x
7:0
— — — — WDAY01<3:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-20 MONTH10<3:0>: Binary Coded Decimal value of months bits, 10 digits; contains a value from 0 to 1
bit 19-16 MONTH01<3:0>: Binary Coded Decimal value of months bits, 1 digit; contains a value from 0 to 9
bit 15-12 DAY10<3:0>: Binary Coded Decimal value of days bits, 10 digits; contains a value from 0 to 3
bit 11-8 DAY01<3:0>: Binary Coded Decimal value of days bits, 1 digit; contains a value from 0 to 9
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 WDAY01<3:0>: Binary Coded Decimal value of weekdays bits, 1 digit; contains a value from 0 to 6

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 PIC32MX5XX/6XX/7XX
23.0 10-BIT ANALOG-TO-DIGITAL • 16-word conversion result buffer
CONVERTER (ADC) • Selectable buffer fill modes
• Eight conversion result format options
Note: This data sheet summarizes the features • Operation during Sleep and Idle modes
of the PIC32MX5XX/6XX/7XX family of
A block diagram of the 10-bit ADC is illustrated in
devices. It is not intended to be a
Figure 23-1. The 10-bit ADC has up to 16 analog input
comprehensive reference source. To pins, designated AN0-AN15. In addition, there are two
complement the information in this data analog input pins for external voltage reference
sheet, refer to Section 17. “10-bit Ana- connections. These voltage reference inputs may be
log-to-Digital Converter (ADC)” shared with other analog input pins and may be
(DS60001104) in the “PIC32 Family Ref- common to other analog module references.
erence Manual”, which is available from
The analog inputs are connected through two multi-
the Microchip web site
plexers to one S&H. The analog input multiplexers can
(www.microchip.com/PIC32). be switched between two sets of analog inputs
The PIC32MX5XX/6XX/7XX 10-bit Analog-to-Digital between conversions. Unipolar differential conversions
Converter (ADC) includes the following features: are possible on all channels, other than the pin used as
the reference, using a reference input pin (see
• Successive Approximation Register (SAR) Figure 23-1).
conversion
The Analog Input Scan mode sequentially converts
• Up to 1 Msps conversion speed
user-specified channels. A control register specifies
• Up to 16 analog input pins which analog input channels will be included in the
• External voltage reference input pins scanning sequence.
• One unipolar, differential Sample and Hold (S&H) The 10-bit ADC is connected to a 16-word result buffer.
circuit Each 10-bit result is converted to one of eight 32-bit
• Automatic Channel Scan mode output formats when it is read from the result buffer.
• Selectable conversion trigger source

FIGURE 23-1: ADC1 MODULE BLOCK DIAGRAM

VREF+(1) AVDD VREF-(1) AVSS

VCFG<2:0>
AN0 ADC1BUF0
ADC1BUF1
AN15 ADC1BUF2
S&H VREFH VREFL
Channel
Scan +
CH0SA<4:0> CH0SB<4:0> SAR ADC
-

CSCNA

AN1
ADC1BUFE
VREFL
ADC1BUFF

CH0NA CH0NB

Alternate
Input Selection

Note 1: VREF+ and VREF- inputs can be multiplexed with other analog inputs.

 2009-2019 Microchip Technology Inc. DS60001156K-page 235

PIC32MX5XX/6XX/7XX
FIGURE 23-2: ADC CONVERSION CLOCK PERIOD BLOCK DIAGRAM

ADRC

FRC 2 1
TAD
ADCS<7:0> 0

ADC Conversion
Clock Multiplier
TPB
2, 4,..., 512

DS60001156K-page 236  2009-2019 Microchip Technology Inc.

 23.1 Control Registers
 2009-2019 Microchip Technology Inc.

TABLE 23-1: ADC REGISTER MAP

Virtual Address

Bits

All Resets
Bit Range
(BF80_#)

Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
9000 AD1CON1(1)
15:0 ON — SIDL — — FORM<2:0> SSRC<2:0> CLRASAM — ASAM SAMP DONE 0000
31:16 — — — — — — — — — — — — — — — — 0000
9010 AD1CON2(1)
15:0 VCFG2 VCFG1 VCFG0 OFFCAL — CSCNA — — BUFS — SMPI<3:0> BUFM ALTS 0000
31:16 — — — — — — — — — — — — — — — — 0000
9020 AD1CON3(1)
15:0 ADRC — — SAMC<4:0> ADCS<7:0> 0000
(1) 31:16 CH0NB — — — CH0SB<3:0> CH0NA — — — CH0SA<3:0> 0000
9040 AD1CHS
15:0 — — — — — — — — — — — — — — — — 0000
31:16 — — — — — — — — — — — — — — — — 0000
9060 AD1PCFG(1)
15:0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 0000
31:16 — — — — — — — — — — — — — — — — 0000
9050 AD1CSSL(1)
15:0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 0000
31:16 0000
9070 ADC1BUF0 ADC Result Word 0 (ADC1BUF0<31:0>)
15:0 0000
31:16 0000

PIC32MX5XX/6XX/7XX
9080 ADC1BUF1 ADC Result Word 1 (ADC1BUF1<31:0>)
15:0 0000
31:16 0000
9090 ADC1BUF2 ADC Result Word 2 (ADC1BUF2<31:0>)
15:0 0000
31:16 0000
90A0 ADC1BUF3 ADC Result Word 3 (ADC1BUF3<31:0>)
15:0 0000
31:16 0000
90B0 ADC1BUF4 ADC Result Word 4 (ADC1BUF4<31:0>)
15:0 0000
31:16 0000
90C0 ADC1BUF5 ADC Result Word 5 (ADC1BUF5<31:0>)
15:0 0000
31:16 0000
90D0 ADC1BUF6 ADC Result Word 6 (ADC1BUF6<31:0>)
15:0 0000
31:16 0000
90E0 ADC1BUF7 ADC Result Word 7 (ADC1BUF7<31:0>)
15:0 0000
31:16 0000
90F0 ADC1BUF8 ADC Result Word 8 (ADC1BUF8<31:0>)
DS60001156K-page 237

15:0 0000
31:16 0000
9100 ADC1BUF9 ADC Result Word 9 (ADC1BUF9<31:0>)
15:0 0000
31:16 0000
9110 ADC1BUFA ADC Result Word A (ADC1BUFA<31:0>)
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
DS60001156K-page 238
TABLE 23-1: ADC REGISTER MAP (CONTINUED)

PIC32MX5XX/6XX/7XX
Virtual Address
Bits

All Resets
Bit Range
(BF80_#)

Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 0000
9120 ADC1BUFB ADC Result Word B (ADC1BUFB<31:0>)
15:0 0000
31:16 0000
9130 ADC1BUFC ADC Result Word C (ADC1BUFC<31:0>)
15:0 0000
31:16 0000
9140 ADC1BUFD ADC Result Word D (ADC1BUFD<31:0>)
15:0 0000
31:16 0000
9150 ADC1BUFE ADC Result Word E (ADC1BUFE<31:0>)
15:0 0000
31:16 0000
9160 ADC1BUFF ADC Result Word F (ADC1BUFF<31:0>)
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: This register has corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more information.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 23-1: AD1CON1: ADC CONTROL REGISTER 1
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
ON(1) — SIDL — — FORM<2:0>
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0, HSC R/C-0, HSC
7:0 (2) (3)
SSRC<2:0> CLRASAM — ASAM SAMP DONE

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: ADC Operating Mode bit(1)
1 = ADC module is operating
0 = ADC module is not operating
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Stop in Idle Mode bit
1 = Discontinue module operation when device enters Idle mode
0 = Continue module operation in Idle mode
bit 12-11 Unimplemented: Read as ‘0’
bit 10-8 FORM<2:0>: Data Output Format bits
111 = Signed Fractional 32-bit (DOUT = sddd dddd dd00 0000 0000 0000 0000)
110 = Fractional 32-bit (DOUT = dddd dddd dd00 0000 0000 0000 0000 0000)
101 = Signed Integer 32-bit (DOUT = ssss ssss ssss ssss ssss sssd dddd dddd)
100 = Integer 32-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)
011 = Signed Fractional 16-bit (DOUT = 0000 0000 0000 0000 sddd dddd dd00 0000)
010 = Fractional 16-bit (DOUT = 0000 0000 0000 0000 dddd dddd dd00 0000)
001 = Signed Integer 16-bit (DOUT = 0000 0000 0000 0000 ssss sssd dddd dddd)
000 = Integer 16-bit (DOUT = 0000 0000 0000 0000 0000 00dd dddd dddd)

bit 7-5 SSRC<2:0>: Conversion Trigger Source Select bits

111 = Internal counter ends sampling and starts conversion (auto convert)
110 = Reserved
101 = Reserved
100 = Reserved
011 = CTMU ends sampling and starts conversion
010 = Timer 3 period match ends sampling and starts conversion
001 = Active transition on INT0 pin ends sampling and starts conversion
000 = Clearing the SAMP bit ends sampling and starts conversion
Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC<2:0> = 000, software can write a ‘0’ to end sampling and start conversion. If
SSRC<2:0> ‘000’, this bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.

 2009-2019 Microchip Technology Inc. DS60001156K-page 239

PIC32MX5XX/6XX/7XX
REGISTER 23-1: AD1CON1: ADC CONTROL REGISTER 1 (CONTINUED)
bit 4 CLRASAM: Stop Conversion Sequence bit (when the first ADC interrupt is generated)
1 = Stop conversions when the first ADC interrupt is generated. Hardware clears the ASAM bit when the
ADC interrupt is generated.
0 = Normal operation, buffer contents will be overwritten by the next conversion sequence
bit 3 Unimplemented: Read as ‘0’
bit 2 ASAM: ADC Sample Auto-Start bit
1 = Sampling begins immediately after last conversion completes; SAMP bit is automatically set
0 = Sampling begins when SAMP bit is set
bit 1 SAMP: ADC Sample Enable bit(2)
1 = The ADC S&H circuit is sampling
0 = The ADC S&H circuit is holding
When ASAM = 0, writing ‘1’ to this bit starts sampling.
When SSRC<2:0> = 000, writing ‘0’ to this bit will end sampling and start conversion.
bit 0 DONE: Analog-to-Digital Conversion Status bit(3)
Clearing this bit will not affect any operation in progress.
1 = Analog-to-digital conversion is done
0 = Analog-to-digital conversion is not done or has not started

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: If ASAM = 0, software can write a ‘1’ to start sampling. This bit is automatically set by hardware if
ASAM = 1. If SSRC<2:0> = 000, software can write a ‘0’ to end sampling and start conversion. If
SSRC<2:0> ‘000’, this bit is automatically cleared by hardware to end sampling and start conversion.
3: This bit is automatically set by hardware when analog-to-digital conversion is complete. Software can
write a ‘0’ to clear this bit (a write of ‘1’ is not allowed). Clearing this bit does not affect any operation
already in progress. This bit is automatically cleared by hardware at the start of a new conversion.

DS60001156K-page 240  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 23-2: AD1CON2: ADC CONTROL REGISTER 2
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0
15:8
VCFG<2:0> OFFCAL — CSCNA — —
R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
BUFS — SMPI<3:0> BUFM ALTS

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-13 VCFG<2:0>: Voltage Reference Configuration bits
Bit Value VREFH VREFL
1xx AVDD AVss
011 External VREF+ pin External VREF- pin
010 AVDD External VREF- pin
001 External VREF+ pin AVSS
000 AVDD AVss
bit 12 OFFCAL: Input Offset Calibration Mode Select bit
1 = Enable Offset Calibration mode
Positive and negative inputs of the S&H circuit are connected to VREFL.
0 = Disable Offset Calibration mode
The inputs to the S&H circuit are controlled by AD1CHS or AD1CSSL.
bit 11 Unimplemented: Read as ‘0’
bit 10 CSCNA: Input Scan Select bit
1 = Scan inputs
0 = Do not scan inputs
bit 9-8 Unimplemented: Read as ‘0’
bit 7 BUFS: Buffer Fill Status bit
Only valid when BUFM = 1.
1 = ADC is currently filling buffer 0x8-0xF, user should access data in 0x0-0x7
0 = ADC is currently filling buffer 0x0-0x7, user should access data in 0x8-0xF
bit 6 Unimplemented: Read as ‘0’
bit 5-2 SMPI<3:0>: Sample/Convert Sequences Per Interrupt Selection bits
1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence
1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence
•
•
•
0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence
0000 = Interrupts at the completion of conversion for each sample/convert sequence
bit 1 BUFM: ADC Result Buffer Mode Select bit
1 = Buffer configured as two 8-word buffers, ADC1BUF7-ADC1BUF0, ADC1BUFF-ADCBUF8
0 = Buffer configured as one 16-word buffer ADC1BUFF-ADC1BUF0
bit 0 ALTS: Alternate Input Sample Mode Select bit
1 = Uses Sample A input multiplexer settings for first sample, and then alternates between Sample B and
Sample A input multiplexer settings for all subsequent samples
0 = Always use Sample A input multiplexer settings

 2009-2019 Microchip Technology Inc. DS60001156K-page 241

PIC32MX5XX/6XX/7XX
REGISTER 23-3: AD1CON3: ADC CONTROL REGISTER 3
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
ADRC — — SAMC<4:0>(1)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W R/W-0
7:0
ADCS<7:0>(2)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ADRC: ADC Conversion Clock Source bit
1 = Clock derived from FRC
0 = Clock derived from Peripheral Bus Clock (PBCLK)
bit 14-13 Unimplemented: Read as ‘0’
bit 12-8 SAMC<4:0>: Auto-Sample Time bits(1)
11111 = 31 TAD
•
•
•
00001 = 1 TAD
00000 = 0 TAD (Not allowed)
bit 7-0 ADCS<7:0>: ADC Conversion Clock Select bits(2)
11111111 =TPB • 2 • (ADCS<7:0> + 1) = 512 • TPB = TAD
•
•
•
00000001 =TPB • 2 • (ADCS<7:0> + 1) = 4 • TPB = TAD
00000000 =TPB • 2 • (ADCS<7:0> + 1) = 2 • TPB = TAD

Note 1: This bit is only used if the SSRC<2:0> bits (AD1CON1<7:5>) = 111.
2: This bit is not used if the ADRC bit (AD1CON3<15>) = 1.

DS60001156K-page 242  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 23-4: AD1CHS: ADC INPUT SELECT REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
CH0NB — — — CH0SB<3:0>
R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CH0NA — — — CH0SA<3:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0
— — — — — — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 CH0NB: Negative Input Select bit for Sample B

1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VREFL
bit 30-28 Unimplemented: Read as ‘0’
bit 27-24 CH0SB<3:0>: Positive Input Select bits for Sample B
1111 = Channel 0 positive input is AN15
•
•
•
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 23 CH0NA: Negative Input Select bit for Sample A Multiplexer Setting
1 = Channel 0 negative input is AN1
0 = Channel 0 negative input is VREFL
bit 22-20 Unimplemented: Read as ‘0’
bit 19-16 CH0SA<3:0>: Positive Input Select bits for Sample A Multiplexer Setting
1111 = Channel 0 positive input is AN15
•
•
•
0001 = Channel 0 positive input is AN1
0000 = Channel 0 positive input is AN0
bit 15-0 Unimplemented: Read as ‘0’

 2009-2019 Microchip Technology Inc. DS60001156K-page 243

PIC32MX5XX/6XX/7XX
REGISTER 23-5: AD1CSSL: ADC INPUT SCAN SELECT REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 CSSL<15:0>: ADC Input Pin Scan Selection bits(1)
1 = Select ANx for input scan
0 = Skip ANx for input scan

Note 1: CSSL = ANx, where ‘x’ = 0-15.

DS60001156K-page 244  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
24.0 CONTROLLER AREA - FIFO can be a transmit message FIFO or a
receive message FIFO
NETWORK (CAN)
- User-defined priority levels for message
Note: This data sheet summarizes the features FIFOs used for transmission
of the PIC32MX5XX/6XX/7XX family of - 32 acceptance filters for message filtering
devices. It is not intended to be a - Four acceptance filter mask registers for
comprehensive reference source. To message filtering
complement the information in this data
- Automatic response to remote transmit request
sheet, refer to Section 34. “Controller
Area Network (CAN)” (DS60001154) in - DeviceNet™ addressing support
the “PIC32 Family Reference Manual”, • Additional Features:
which is available from the Microchip web - Loopback, Listen All Messages, and Listen
site (www.microchip.com/PIC32). Only modes for self-test, system diagnostics
and bus monitoring
The Controller Area Network (CAN) module supports
- Low-power operating modes
the following key features:
- CAN module is a bus master on the PIC32
• Standards Compliance: system bus
- Full CAN 2.0B compliance - Use of DMA is not required
- Programmable bit rate up to 1 Mbps - Dedicated time-stamp timer
• Message Reception and Transmission: - Dedicated DMA channels
- 32 message FIFOs - Data-only Message Reception mode
- Each FIFO can have up to 32 messages for a
Figure 24-1 illustrates the general structure of the CAN
total of 1024 messages
module.

FIGURE 24-1: PIC32 CAN MODULE BLOCK DIAGRAM

CxTX

32 Filters
4 Masks

CxRX CPU
CAN Module

System Bus

Message
Buffer Size
System RAM 2 or 4 Words
Up to 32 Message Buffers

Message Buffer 31 Message Buffer 31 Message Buffer 31

Message Buffer 1 Message Buffer 1 Message Buffer 1

Message Buffer 0 Message Buffer 0 Message Buffer 0
FIFO0 FIFO1 FIFO31

CAN Message FIFO (up to 32 FIFOs)

 2009-2019 Microchip Technology Inc. DS60001156K-page 245

DS60001156K-page 246
24.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 24-1: CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — ABAT REQOP<2:0> OPMOD<2:0> CANCAP — — — — 0480

B000 C1CON
15:0 ON — SIDLE — CANBUSY — — — — — — DNCNT<4:0> 0000
31:16 — — — — — — — — — WAKFIL — — — SEG2PH<2:0> 0000
B010 C1CFG
15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000
31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — — — — — MODIE CTMRIE RBIE TBIE 0000
B020 C1INT
15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF — — — — — — — MODIF CTMRIF RBIF TBIF 0000
31:16 — — — — — — — — — — — — — — — — 0000
B030 C1VEC
15:0 — — — FILHIT<4:0> — ICODE<6:0> 0040
31:16 — — — — — — — — — — TXBO TXBP RXBP TXWARN RXWARN EWARN 0000
B040 C1TREC
15:0 TERRCNT<7:0> RERRCNT<7:0> 0000
31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
B050 C1FSTAT
15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
B060 C1RXOVF
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
31:16 CANTS<15:0> 0000
B070 C1TMR
15:0 CANTSPRE<15:0> 0000
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
B080 C1RXM0
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
B090 C1RXM1
15:0 EID<15:0> xxxx
 2009-2019 Microchip Technology Inc.

31:16 SID<10:0> -— MIDE — EID<17:16> xxxx

B0A0 C1RXM2
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
B0B0 C1RXM3
15:0 EID<15:0> xxxx
31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000
B0C0 C1FLTCON0
15:0 FLTEN1 MSEL1<1:0> FSEL1<4:0> FLTEN0 MSEL0<1:0> FSEL0<4:0> 0000
31:16 FLTEN7 MSEL7<1:0> FSEL7<4:0> FLTEN6 MSEL6<1:0> FSEL6<4:0> 0000
B0D0 C1FLTCON1
15:0 FLTEN5 MSEL5<1:0> FSEL5<4:0> FLTEN4 MSEL4<1:0> FSEL4<4:0> 0000
31:16 FLTEN11 MSEL11<1:0> FSEL11<4:0> FLTEN10 MSEL10<1:0> FSEL10<4:0> 0000
B0E0 C1FLTCON2
15:0 FLTEN9 MSEL9<1:0> FSEL9<4:0> FLTEN8 MSEL8<1:0> FSEL8<4:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 TABLE 24-1: CAN1 REGISTER SUMMARY FOR PIC32MX534F064H, PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H,
 2009-2019 Microchip Technology Inc.

PIC32MX575F512H, PIC32MX764F128H, PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX534F064L,

PIC32MX564F064L, PIC32MX564F128L, PIC32MX575F256L, PIC32MX575F512L, PIC32MX764F128L, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000

B0F0 C1FLTCON3
15:0 FLTEN13 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 0000
31:16 FLTEN19 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000
B100 C1FLTCON4
15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0> 0000
31:16 FLTEN23 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000
B110 C1FLTCON5
15:0 FLTEN21 MSEL21<1:0> FSEL21<4:0> FLTEN20 MSEL20<1:0> FSEL20<4:0> 0000
31:16 FLTEN27 MSEL27<1:0> FSEL27<4:0> FLTEN26 MSEL26<1:0> FSEL26<4:0> 0000
B120 C1FLTCON6
15:0 FLTEN25 MSEL25<1:0> FSEL25<4:0> FLTEN24 MSEL24<1:0> FSEL24<4:0> 0000
31:16 FLTEN31 MSEL31<1:0> FSEL31<4:0> FLTEN30 MSEL30<1:0> FSEL30<4:0> 0000
B130 C1FLTCON7
15:0 FLTEN29 MSEL29<1:0> FSEL29<4:0> FLTEN28 MSEL28<1:0> FSEL28<4:0> 0000
C1RXFn 31:16 SID<10:0> -— EXID — EID<17:16> xxxx
B140
(n = 0-31) 15:0 EID<15:0> xxxx
31:16 0000
B340 C1FIFOBA C1FIFOBA<31:0>
15:0

PIC32MX5XX/6XX/7XX
0000
C1FIFOCONn 31:16 — — — — — — — — — — — FSIZE<4:0> 0000
B350
(n = 0-31) 15:0 — FRESET UINC DONLY — — — — TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
RXN
31:16 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE — — — — RXOVFLIE RXFULLIE RXHALFIE 0000
C1FIFOINTn EMPTYIE
B360
(n = 0-31) RXN
15:0 — — — — — TXNFULLIF TXHALFIF TXEMPTYIF — — — — RXOVFLIF RXFULLIF RXHALFIF 0000
EMPTYIF
C1FIFOUAn 31:16 0000
B370 C1FIFOUA<31:0>
(n = 0-31) 15:0 0000
C1FIFOCIn 31:16 — — — — — — — — — — — — — — — — 0000
B380
(n = 0-31) 15:0 — — — — — — — — — — — C1FIFOCI<4:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DS60001156K-page 247
DS60001156K-page 248

PIC32MX5XX/6XX/7XX
TABLE 24-2: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — ABAT REQOP<2:0> OPMOD<2:0> CANCAP — — — — 0480

C000 C2CON
15:0 ON — SIDLE — CANBUSY — — — — — — DNCNT<4:0> 0000
31:16 — — — — — — — — — WAKFIL — — — SEG2PH<2:0> 0000
C010 C2CFG
15:0 SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0> SJW<1:0> BRP<5:0> 0000
31:16 IVRIE WAKIE CERRIE SERRIE RBOVIE — — — — — — — MODIE CTMRIE RBIE TBIE 0000
C020 C2INT
15:0 IVRIF WAKIF CERRIF SERRIF RBOVIF — — — — — — — MODIF CTMRIF RBIF TBIF 0000
31:16 — — — — — — — — — — — — — — — — 0000
C030 C2VEC
15:0 — — — FILHIT<4:0> — ICODE<6:0> 0040
31:16 — — — — — — — — — — TXBO TXBP RXBP TXWARN RXWARN EWARN 0000
C040 C2TREC
15:0 TERRCNT<7:0> RERRCNT<7:0> 0000
31:16 FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24 FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16 0000
C050 C2FSTAT
15:0 FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8 FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0 0000
31:16 RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24 RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16 0000
C060 C2RXOVF
15:0 RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8 RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0 0000
31:16 CANTS<15:0> 0000
C070 C2TMR
15:0 CANTSPRE<15:0> 0000
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
C080 C2RXM0
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
C0A0 C2RXM1
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
C0B0 C2RXM2
15:0 EID<15:0> xxxx
31:16 SID<10:0> -— MIDE — EID<17:16> xxxx
C0B0 C2RXM3
 2009-2019 Microchip Technology Inc.

15:0 EID<15:0> xxxx

31:16 FLTEN3 MSEL3<1:0> FSEL3<4:0> FLTEN2 MSEL2<1:0> FSEL2<4:0> 0000
C0C0 C2FLTCON0
15:0 FLTEN1 MSEL1<1:0> FSEL1<4:0> FLTEN0 MSEL0<1:0> FSEL0<4:0> 0000
31:16 FLTEN7 MSEL7<1:0> FSEL7<4:0> FLTEN6 MSEL6<1:0> FSEL6<4:0> 0000
C0D0 C2FLTCON1
15:0 FLTEN5 MSEL5<1:0> FSEL5<4:0> FLTEN4 MSEL4<1:0> FSEL4<4:0> 0000
31:16 FLTEN11 MSEL11<1:0> FSEL11<4:0> FLTEN10 MSEL10<1:0> FSEL10<4:0> 0000
C0E0 C2FLTCON2
15:0 FLTEN9 MSEL9<1:0> FSEL9<4:0> FLTEN8 MSEL8<1:0> FSEL8<4:0> 0000
31:16 FLTEN15 MSEL15<1:0> FSEL15<4:0> FLTEN14 MSEL14<1:0> FSEL14<4:0> 0000
C0F0 C2FLTCON3
15:0 FLTEN13 MSEL13<1:0> FSEL13<4:0> FLTEN12 MSEL12<1:0> FSEL12<4:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
 TABLE 24-2: CAN2 REGISTER SUMMARY FOR PIC32MX775F256H, PIC32MX775F512H, PIC32MX795F512H, PIC32MX775F256L,
 2009-2019 Microchip Technology Inc.

Virtual Address
PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 FLTEN19 MSEL19<1:0> FSEL19<4:0> FLTEN18 MSEL18<1:0> FSEL18<4:0> 0000

C100 C2FLTCON4
15:0 FLTEN17 MSEL17<1:0> FSEL17<4:0> FLTEN16 MSEL16<1:0> FSEL16<4:0: 0000
31:16 FLTEN23 MSEL23<1:0> FSEL23<4:0> FLTEN22 MSEL22<1:0> FSEL22<4:0> 0000
C110 C2FLTCON5
15:0 FLTEN21 MSEL21<1:0> FSEL21<4:0> FLTEN20 MSEL20<1:0> FSEL20<4:0> 0000
31:16 FLTEN27 MSEL27<1:0> FSEL27<4:0> FLTEN26 MSEL26<1:0> FSEL26<4:0> 0000
C120 C2FLTCON6
15:0 FLTEN25 MSEL25<1:0> FSEL25<4:0> FLTEN24 MSEL24<1:0> FSEL24<4:0> 0000
31:16 FLTEN31 MSEL31<1:0> FSEL31<4:0> FLTEN30 MSEL30<1:0> FSEL30<4:0> 0000
C130 C2FLTCON7
15:0 FLTEN29 MSEL29<1:0> FSEL29<4:0> FLTEN28 MSEL28<1:0> FSEL28<4:0> 0000
C2RXFn 31:16 SID<10:0> -— EXID — EID<17:16> xxxx
C140
(n = 0-31) 15:0 EID<15:0> xxxx
31:16 0000
C340 C2FIFOBA C2FIFOBA<31:0>
15:0 0000
C2FIFOCONn 31:16 — — — — — — — — — — — FSIZE<4:0> 0000
C350
(n = 0-31) 15:0 — FRESET UINC DONLY — — — — TXEN TXABAT TXLARB TXERR TXREQ RTREN TXPRI<1:0> 0000
RXN 0000

PIC32MX5XX/6XX/7XX
31:16 — — — — — TXNFULLIE TXHALFIE TXEMPTYIE — — — — RXOVFLIE RXFULLIE RXHALFIE
C2FIFOINTn EMPTYIE
C360
(n = 0-31) RXN 0000
15:0 — — — — — TXNFULLIF TXHALFIF TXEMPTYIF — — — — RXOVFLIF RXFULLIF RXHALFIF
EMPTYIF
C2FIFOUAn 31:16 0000
C370 C2FIFOUA<31:0>
(n = 0-31) 15:0 0000
C2FIFOCIn 31:16 — — — — — — — — — — — — — — — — 0000
C380
(n = 0-31) 15:0 — — — — — — — — — — — C2FIFOCI<4:0> 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers” for more
information.
DS60001156K-page 249
PIC32MX5XX/6XX/7XX
REGISTER 24-1: CiCON: CAN MODULE CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 S/HC-0 R/W-1 R/W-0 R/W-0
31:24
— — — — ABAT REQOP<2:0>
R-1 R-0 R-0 R/W-0 U-0 U-0 U-0 U-0
23:16
OPMOD<2:0> CANCAP — — — —
R/W-0 U-0 R/W-0 U-0 R-0 U-0 U-0 U-0
15:8
ON(1) — SIDLE — CANBUSY — — —
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — DNCNT<4:0>

Legend: HC = Hardware Clear S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 Unimplemented: Read as ‘0’

bit 27 ABAT: Abort All Pending Transmissions bit
1 = Signal all transmit buffers to abort transmission
0 = Module will clear this bit when all transmissions aborted
bit 26-24 REQOP<2:0>: Request Operation Mode bits
111 = Set Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Set Configuration mode
011 = Set Listen Only mode
010 = Set Loopback mode
001 = Set Disable mode
000 = Set Normal Operation mode
bit 23-21 OPMOD<2:0>: Operation Mode Status bits
111 = Module is in Listen All Messages mode
110 = Reserved
101 = Reserved
100 = Module is in Configuration mode
011 = Module is in Listen Only mode
010 = Module is in Loopback mode
001 = Module is in Disable mode
000 = Module is in Normal Operation mode
bit 20 CANCAP: CAN Message Receive Time Stamp Timer Capture Enable bit
1 = CANTMR value is stored on valid message reception and is stored with the message
0 = Disable CAN message receive time stamp timer capture and stop CANTMR to conserve power
bit 19-16 Unimplemented: Read as ‘0’
bit 15 ON: CAN On bit(1)
1 = CAN module is enabled
0 = CAN module is disabled
bit 14 Unimplemented: Read as ‘0’

Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.

DS60001156K-page 250  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-1: CiCON: CAN MODULE CONTROL REGISTER (CONTINUED)
bit 13 SIDLE: CAN Stop in Idle bit
1 = CAN Stops operation when system enters Idle mode
0 = CAN continues operation when system enters Idle mode
bit 12 Unimplemented: Read as ‘0’
bit 11 CANBUSY: CAN Module is Busy bit
1 = The CAN module is active
0 = The CAN module is completely disabled
bit 10-5 Unimplemented: Read as ‘0’
bit 4-0 DNCNT<4:0>: Device Net Filter Bit Number bits
10011-11111 = Invalid Selection (compare up to 18-bits of data with EID)
10010 = Compare up to data byte 2 bit 6 with EID17 (CiRXFn<17>)
•
•
•
00001 = Compare up to data byte 0 bit 7 with EID0 (CiRXFn<0>)
00000 = Do not compare data bytes

Note 1: If the user application clears this bit, it may take a number of cycles before the CAN module completes the
current transaction and responds to this request. The user application should poll the CANBUSY bit to
verify that the request has been honored.

 2009-2019 Microchip Technology Inc. DS60001156K-page 251

PIC32MX5XX/6XX/7XX
REGISTER 24-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
23:16
— WAKFIL — — — SEG2PH<2:0>(1,4)
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8 (1) (2)
SEG2PHTS SAM SEG1PH<2:0> PRSEG<2:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0 (3)
SJW<1:0> BRP<5:0>

Legend: HC = Hardware Clear S = Settable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-23 Unimplemented: Read as ‘0’

bit 22 WAKFIL: CAN Bus Line Filter Enable bit
1 = Use CAN bus line filter for wake-up
0 = CAN bus line filter is not used for wake-up
bit 21-19 Unimplemented: Read as ‘0’
bit 18-16 SEG2PH<2:0>: Phase Buffer Segment 2 bits(1,4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 15 SEG2PHTS: Phase Segment 2 Time Select bit(1)
1 = Freely programmable
0 = Maximum of SEG1PH or Information Processing Time, whichever is greater
bit 14 SAM: Sample of the CAN Bus Line bit(2)
1 = Bus line is sampled three times at the sample point
0 = Bus line is sampled once at the sample point
bit 13-11 SEG1PH<2:0>: Phase Buffer Segment 1 bits(4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ

Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.

2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW  SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).

DS60001156K-page 252  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-2: CiCFG: CAN BAUD RATE CONFIGURATION REGISTER (CONTINUED)
bit 10-8 PRSEG<2:0>: Propagation Time Segment bits(4)
111 = Length is 8 x TQ
•
•
•
000 = Length is 1 x TQ
bit 7-6 SJW<1:0>: Synchronization Jump Width bits(3)
11 = Length is 4 x TQ
10 = Length is 3 x TQ
01 = Length is 2 x TQ
00 = Length is 1 x TQ
bit 5-0 BRP<5:0>: Baud Rate Prescaler bits
111111 = TQ = (2 x 64)/FSYS
111110 = TQ = (2 x 63)/FSYS
•
•
•
000001 = TQ = (2 x 2)/FSYS
000000 = TQ = (2 x 1)/FSYS

Note 1: SEG2PH SEG1PH. If SEG2PHTS is clear, SEG2PH will be set automatically.

2: 3 Time bit sampling is not allowed for BRP < 2.
3: SJW  SEG2PH.
4: The Time Quanta per bit must be greater than 7 (that is, TQBIT > 7).

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).

 2009-2019 Microchip Technology Inc. DS60001156K-page 253

PIC32MX5XX/6XX/7XX
REGISTER 24-3: CiINT: CAN INTERRUPT REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
31:24
IVRIE WAKIE CERRIE SERRIE RBOVIE — — —
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
— — — — MODIE CTMRIE RBIE TBIE
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0
15:8 (1)
IVRIF WAKIF CERRIF SERRIF RBOVIF — — —
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — — MODIF CTMRIF RBIF TBIF

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 IVRIE: Invalid Message Received Interrupt Enable bit

1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 30 WAKIE: CAN Bus Activity Wake-up Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 29 CERRIE: CAN Bus Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 28 SERRIE: System Error Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 27 RBOVIE: Receive Buffer Overflow Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 26-20 Unimplemented: Read as ‘0’
bit 19 MODIE: Mode Change Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 18 CTMRIE: CAN Timestamp Timer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 17 RBIE: Receive Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 16 TBIE: Transmit Buffer Interrupt Enable bit
1 = Interrupt request is enabled
0 = Interrupt request is not enabled
bit 15 IVRIF: Invalid Message Received Interrupt Flag bit
1 = An invalid messages interrupt has occurred
0 = An invalid message interrupt has not occurred

Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON<15>).

DS60001156K-page 254  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-3: CiINT: CAN INTERRUPT REGISTER (CONTINUED)
bit 14 WAKIF: CAN Bus Activity Wake-up Interrupt Flag bit
1 = A bus wake-up activity interrupt has occurred
0 = A bus wake-up activity interrupt has not occurred
bit 13 CERRIF: CAN Bus Error Interrupt Flag bit
1 = A CAN bus error has occurred
0 = A CAN bus error has not occurred
bit 12 SERRIF: System Error Interrupt Flag bit
1 = A system error occurred (typically an illegal address was presented to the system bus)
0 = A system error has not occurred
bit 11 RBOVIF: Receive Buffer Overflow Interrupt Flag bit
1 = A receive buffer overflow has occurred
0 = A receive buffer overflow has not occurred
bit 10-4 Unimplemented: Read as ‘0’
bit 3 MODIF: CAN Mode Change Interrupt Flag bit
1 = A CAN module mode change has occurred (OPMOD<2:0> has changed to reflect REQOP)
0 = A CAN module mode change has not occurred
bit 2 CTMRIF: CAN Timer Overflow Interrupt Flag bit
1 = A CAN timer (CANTMR) overflow has occurred
0 = A CAN timer (CANTMR) overflow has not occurred
bit 1 RBIF: Receive Buffer Interrupt Flag bit
1 = A receive buffer interrupt is pending
0 = A receive buffer interrupt is not pending
bit 0 TBIF: Transmit Buffer Interrupt Flag bit
1 = A transmit buffer interrupt is pending
0 = A transmit buffer interrupt is not pending

Note 1: This bit can only be cleared by turning the CAN module Off and On by clearing or setting the ON bit
(CiCON<15>).

 2009-2019 Microchip Technology Inc. DS60001156K-page 255

PIC32MX5XX/6XX/7XX
REGISTER 24-4: CiVEC: CAN INTERRUPT CODE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
15:8
— — — FILHIT<4:0>
U-0 R-1 R-0 R-0 R-0 R-0 R-0 R-0
7:0 (1)
— ICODE<6:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as ‘0’

bit 12-8 FILHIT<4:0>: Filter Hit Number bit
11111 = Filter 31
11110 = Filter 30
•
•
•
00001 = Filter 1
00000 = Filter 0
bit 7 Unimplemented: Read as ‘0’
bit 6-0 ICODE<6:0>: Interrupt Flag Code bits(1)
1111111 = Reserved
•
•
•
1001001 = Reserved
1001000 = Invalid message received (IVRIF)
1000111 = CAN module mode change (MODIF)
1000110 = CAN timestamp timer (CTMRIF)
1000101 = Bus bandwidth error (SERRIF)
1000100 = Address error interrupt (SERRIF)
1000011 = Receive FIFO overflow interrupt (RBOVIF)
1000010 = Wake-up interrupt (WAKIF)
1000001 = Error Interrupt (CERRIF)
1000000 = No interrupt
0111111 = Reserved
•
•
•
0100000 = Reserved
0011111 = FIFO31 Interrupt (CiFSTAT<31> set)
0011110 = FIFO30 Interrupt (CiFSTAT<30> set)
•
•
•
0000001 = FIFO1 Interrupt (CiFSTAT<1> set)
0000000 = FIFO0 Interrupt (CiFSTAT<0> set)

Note 1: These bits are only updated for enabled interrupts.

DS60001156K-page 256  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-5: CiTREC: CAN TRANSMIT/RECEIVE ERROR COUNT REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
— — TXBO TXBP RXBP TXWARN RXWARN EWARN
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
TERRCNT<7:0>
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
RERRCNT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-22 Unimplemented: Read as ‘0’

bit 21 TXBO: Transmitter in Error State Bus OFF (TERRCNT  256)
bit 20 TXBP: Transmitter in Error State Bus Passive (TERRCNT  128)
bit 19 RXBP: Receiver in Error State Bus Passive (RERRCNT  128)
bit 18 TXWARN: Transmitter in Error State Warning (128 > TERRCNT  96)
bit 17 RXWARN: Receiver in Error State Warning (128 > RERRCNT  96)
bit 16 EWARN: Transmitter or Receiver is in Error State Warning
bit 15-8 TERRCNT<7:0>: Transmit Error Counter
bit 7-0 RERRCNT<7:0>: Receive Error Counter

REGISTER 24-6: CiFSTAT: CAN FIFO STATUS REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
FIFOIP31 FIFOIP30 FIFOIP29 FIFOIP28 FIFOIP27 FIFOIP26 FIFOIP25 FIFOIP24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
FIFOIP23 FIFOIP22 FIFOIP21 FIFOIP20 FIFOIP19 FIFOIP18 FIFOIP17 FIFOIP16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
FIFOIP15 FIFOIP14 FIFOIP13 FIFOIP12 FIFOIP11 FIFOIP10 FIFOIP9 FIFOIP8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
FIFOIP7 FIFOIP6 FIFOIP5 FIFOIP4 FIFOIP3 FIFOIP2 FIFOIP1 FIFOIP0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 FIFOIP<31:0>: FIFOn Interrupt Pending bits

1 = One or more enabled FIFO interrupts are pending
0 = No FIFO interrupts are pending

 2009-2019 Microchip Technology Inc. DS60001156K-page 257

PIC32MX5XX/6XX/7XX
REGISTER 24-7: CiRXOVF: CAN RECEIVE FIFO OVERFLOW STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
31:24
RXOVF31 RXOVF30 RXOVF29 RXOVF28 RXOVF27 RXOVF26 RXOVF25 RXOVF24
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
23:16
RXOVF23 RXOVF22 RXOVF21 RXOVF20 RXOVF19 RXOVF18 RXOVF17 RXOVF16
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
15:8
RXOVF15 RXOVF14 RXOVF13 RXOVF12 RXOVF11 RXOVF10 RXOVF9 RXOVF8
R-0 R-0 R-0 R-0 R-0 R-0 R-0 R-0
7:0
RXOVF7 RXOVF6 RXOVF5 RXOVF4 RXOVF3 RXOVF2 RXOVF1 RXOVF0

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 RXOVF<31:0>: FIFOn Receive Overflow Interrupt Pending bit

1 = FIFO has overflowed
0 = FIFO has not overflowed

REGISTER 24-8: CiTMR: CAN TIMER REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
CANTS<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CANTS<7:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CANTSPRE<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CANTSPRE<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CANTS<15:0>: CAN Time Stamp Timer bits

This is a free-running timer that increments every CANTSPRE system clocks when the CANCAP bit
(CiCON<20>) is set.
bit 15-0 CANTSPRE<15:0>: CAN Time Stamp Timer Prescaler bits
1111 1111 1111 1111 = CAN time stamp timer (CANTS) increments every 65,535 system clocks
•
•
•
0000 0000 0000 0000 = CAN time stamp timer (CANTS) increments every system clock

Note 1: CiTMR will be paused when CANCAP = 0.

2: The CiTMR prescaler count will be reset on any write to CiTMR (CANTSPRE will be unaffected).

DS60001156K-page 258  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-9: CiRXMn: CAN ACCEPTANCE FILTER MASK ‘n’ REGISTER (n = 0, 1, 2 OR 3)
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
SID<10:3>
R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 R/W-0 R/W-0
23:16
SID<2:0> — MIDE — EID<17:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
EID<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
EID<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 SID<10:0>: Standard Identifier bits

1 = Include the SIDx bit in filter comparison
0 = The SIDx bit is a ‘don’t care’ in filter operation
bit 20 Unimplemented: Read as ‘0’
bit 19 MIDE: Identifier Receive Mode bit
1 = Match only message types (standard/extended address) that correspond to the EXID bit in filter
0 = Match either standard or extended address message if filters match (that is, if (Filter SID) = (Message
SID) or if (FILTER SID/EID) = (Message SID/EID))
bit 18 Unimplemented: Read as ‘0’
bit 17-0 EID<17:0>: Extended Identifier bits
1 = Include the EIDx bit in filter comparison
0 = The EIDx bit is a ‘don’t care’ in filter operation

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).

 2009-2019 Microchip Technology Inc. DS60001156K-page 259

PIC32MX5XX/6XX/7XX
REGISTER 24-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0
Bit Bit Bit Bit Bit Bit Bit Bit
Bit Range
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FLTEN3 MSEL3<1:0> FSEL3<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FLTEN2 MSEL2<1:0> FSEL2<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FLTEN1 MSEL1<1:0> FSEL1<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FLTEN0 MSEL0<1:0> FSEL0<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN3: Filter 3 Enable bit

1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL3<1:0>: Filter 3 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL3<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN2: Filter 2 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL2<1:0>: Filter 2 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL2<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

DS60001156K-page 260  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-10: CiFLTCON0: CAN FILTER CONTROL REGISTER 0 (CONTINUED)
bit 15 FLTEN1: Filter 1 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL1<1:0>: Filter 1 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL1<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN0: Filter 0 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL0<1:0>: Filter 0 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL0<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2009-2019 Microchip Technology Inc. DS60001156K-page 261

PIC32MX5XX/6XX/7XX
REGISTER 24-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FLTEN7 MSEL7<1:0> FSEL7<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FLTEN6 MSEL6<1:0> FSEL6<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FLTEN5 MSEL5<1:0> FSEL5<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FLTEN4 MSEL4<1:0> FSEL4<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN7: Filter 7 Enable bit

1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL7<1:0>: Filter 7 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL7<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN6: Filter 6 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL6<1:0>: Filter 6 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL6<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

DS60001156K-page 262  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-11: CiFLTCON1: CAN FILTER CONTROL REGISTER 1 (CONTINUED)
bit 15 FLTEN5: Filter 17 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL5<1:0>: Filter 5 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL5<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN4: Filter 4 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL4<1:0>: Filter 4 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL4<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2009-2019 Microchip Technology Inc. DS60001156K-page 263

PIC32MX5XX/6XX/7XX
REGISTER 24-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FLTEN11 MSEL11<1:0> FSEL11<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FLTEN10 MSEL10<1:0> FSEL10<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FLTEN9 MSEL9<1:0> FSEL9<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FLTEN8 MSEL8<1:0> FSEL8<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN11: Filter 11 Enable bit

1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL11<1:0>: Filter 11 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL11<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN10: Filter 10 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL10<1:0>: Filter 10 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL10<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

DS60001156K-page 264  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-12: CiFLTCON2: CAN FILTER CONTROL REGISTER 2 (CONTINUED)
bit 15 FLTEN9: Filter 9 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL9<1:0>: Filter 9 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL9<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN8: Filter 8 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL8<1:0>: Filter 8 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL8<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2009-2019 Microchip Technology Inc. DS60001156K-page 265

PIC32MX5XX/6XX/7XX
REGISTER 24-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FLTEN15 MSEL15<1:0> FSEL15<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FLTEN14 MSEL14<1:0> FSEL14<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FLTEN13 MSEL13<1:0> FSEL13<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FLTEN12 MSEL12<1:0> FSEL12<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN15: Filter 15 Enable bit

1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL15<1:0>: Filter 15 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL15<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN14: Filter 14 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL14<1:0>: Filter 14 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL14<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

DS60001156K-page 266  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-13: CiFLTCON3: CAN FILTER CONTROL REGISTER 3 (CONTINUED)
bit 15 FLTEN13: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL13<1:0>: Filter 13 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL13<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN12: Filter 12 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL12<1:0>: Filter 12 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL12<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2009-2019 Microchip Technology Inc. DS60001156K-page 267

PIC32MX5XX/6XX/7XX
,4

REGISTER 24-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FLTEN19 MSEL19<1:0> FSEL19<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FLTEN18 MSEL18<1:0> FSEL18<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FLTEN17 MSEL17<1:0> FSEL17<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FLTEN16 MSEL16<1:0> FSEL16<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN19: Filter 19 Enable bit

1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL19<1:0>: Filter 19 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL19<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN18: Filter 18 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL18<1:0>: Filter 18 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL18<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

DS60001156K-page 268  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-14: CiFLTCON4: CAN FILTER CONTROL REGISTER 4 (CONTINUED)
bit 15 FLTEN17: Filter 13 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL17<1:0>: Filter 17 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL17<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN16: Filter 16 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL16<1:0>: Filter 16 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL16<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2009-2019 Microchip Technology Inc. DS60001156K-page 269

PIC32MX5XX/6XX/7XX
REGISTER 24-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FLTEN23 MSEL23<1:0> FSEL23<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FLTEN22 MSEL22<1:0> FSEL22<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FLTEN21 MSEL21<1:0> FSEL21<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FLTEN20 MSEL20<1:0> FSEL20<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN23: Filter 23 Enable bit

1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL23<1:0>: Filter 23 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL23<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN22: Filter 22 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL22<1:0>: Filter 22 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL22<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

DS60001156K-page 270  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-15: CiFLTCON5: CAN FILTER CONTROL REGISTER 5 (CONTINUED)
bit 15 FLTEN21: Filter 21 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL21<1:0>: Filter 21 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL21<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN20: Filter 20 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL20<1:0>: Filter 20 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL20<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2009-2019 Microchip Technology Inc. DS60001156K-page 271

PIC32MX5XX/6XX/7XX
REGISTER 24-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FLTEN27 MSEL27<1:0> FSEL27<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FLTEN26 MSEL26<1:0> FSEL26<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FLTEN25 MSEL25<1:0> FSEL25<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FLTEN24 MSEL24<1:0> FSEL24<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN27: Filter 27 Enable bit

1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL27<1:0>: Filter 27 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL27<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN26: Filter 26 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL26<1:0>: Filter 26 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL26<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

DS60001156K-page 272  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-16: CiFLTCON6: CAN FILTER CONTROL REGISTER 6 (CONTINUED)
bit 15 FLTEN25: Filter 25 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL25<1:0>: Filter 25 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL25<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN24: Filter 24 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL24<1:0>: Filter 24 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL24<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2009-2019 Microchip Technology Inc. DS60001156K-page 273

PIC32MX5XX/6XX/7XX
REGISTER 24-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
FLTEN31 MSEL31<1:0> FSEL31<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
FLTEN30 MSEL30<1:0> FSEL30<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FLTEN29 MSEL29<1:0> FSEL29<4:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FLTEN28 MSEL28<1:0> FSEL28<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FLTEN31: Filter 31 Enable bit

1 = Filter is enabled
0 = Filter is disabled
bit 30-29 MSEL31<1:0>: Filter 31 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 28-24 FSEL31<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 23 FLTEN30: Filter 30Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 22-21 MSEL30<1:0>: Filter 30Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 20-16 FSEL30<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

DS60001156K-page 274  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-17: CiFLTCON7: CAN FILTER CONTROL REGISTER 7 (CONTINUED)
bit 15 FLTEN29: Filter 29 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 14-13 MSEL29<1:0>: Filter 29 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 12-8 FSEL29<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0
bit 7 FLTEN28: Filter 28 Enable bit
1 = Filter is enabled
0 = Filter is disabled
bit 6-5 MSEL28<1:0>: Filter 28 Mask Select bits
11 = Acceptance Mask 3 selected
10 = Acceptance Mask 2 selected
01 = Acceptance Mask 1 selected
00 = Acceptance Mask 0 selected
bit 4-0 FSEL28<4:0>: FIFO Selection bits
11111 = Message matching filter is stored in FIFO buffer 31
11110 = Message matching filter is stored in FIFO buffer 30
•
•
•
00001 = Message matching filter is stored in FIFO buffer 1
00000 = Message matching filter is stored in FIFO buffer 0

Note: The bits in this register can only be modified if the corresponding filter enable (FLTENn) bit is ‘0’.

 2009-2019 Microchip Technology Inc. DS60001156K-page 275

PIC32MX5XX/6XX/7XX
REGISTER 24-18: CiRXFn: CAN ACCEPTANCE FILTER ‘n’ REGISTER 7 (n = 0 THROUGH 31)
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
31:24
SID<10:3>
R/W-x R/W-x R/W-x U-0 R/W-0 U-0 R/W-x R/W-x
23:16
SID<2:0> — EXID — EID<17:16>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
15:8
EID<15:8>
R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x
7:0
EID<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 SID<10:0>: Standard Identifier bits

1 = Message address bit SIDx must be ‘1’ to match filter
0 = Message address bit SIDx must be ‘0’ to match filter
bit 20 Unimplemented: Read as ‘0’
bit 19 EXID: Extended Identifier Enable bits
1 = Match only messages with extended identifier addresses
0 = Match only messages with standard identifier addresses
bit 18 Unimplemented: Read as ‘0’
bit 17-0 EID<17:0>: Extended Identifier bits
1 = Message address bit EIDx must be ‘1’ to match filter
0 = Message address bit EIDx must be ‘0’ to match filter

Note: This register can only be modified when the filter is disabled (FLTENn = 0).

DS60001156K-page 276  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-19: CiFIFOBA: CAN MESSAGE BUFFER BASE ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
CiFIFOBA<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
CiFIFOBA<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
CiFIFOBA<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0(1) R-0(1)
7:0
CiFIFOBA<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CiFIFOBA<31:0>: CAN FIFO Base Address bits

These bits define the base address of all message buffers. Individual message buffers are located based
on the size of the previous message buffers. This address is a physical address. Bits <1:0> are read-only
and read as ‘0’, forcing the messages to be 32-bit word-aligned in device RAM.

Note 1: This bit is unimplemented and will always read ‘0’, which forces word-alignment of messages.

Note: This register can only be modified when the CAN module is in Configuration mode (OPMOD<2:0>
(CiCON<23:21>) = 100).

 2009-2019 Microchip Technology Inc. DS60001156K-page 277

PIC32MX5XX/6XX/7XX
REGISTER 24-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31)
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
— — — FSIZE<4:0>(1)
U-0 S/HC-0 S/HC-0 R/W-0 U-0 U-0 U-0 U-0
15:8 (1)
— FRESET UINC DONLY — — — —
R/W-0 R-0 R-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
TXEN TXABAT(2) TXLARB(3) TXERR(3) TXREQ RTREN TXPR<1:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-21 Unimplemented: Read as ‘0’

bit 20-16 FSIZE<4:0>: FIFO Size bits(1)
11111 = FIFO is 32 messages deep
•
•
•
00010 = FIFO is 3 messages deep
00001 = FIFO is 2 messages deep
00000 = FIFO is 1 message deep
bit 15 Unimplemented: Read as ‘0’
bit 14 FRESET: FIFO Reset bits
1 = FIFO will be reset when bit is set, cleared by hardware when FIFO is reset. After setting, the user should
poll whether this bit is clear before taking any action.
0 = No effect
bit 13 UINC: Increment Head/Tail bit
TXEN = 1: (FIFO configured as a Transmit FIFO)
When this bit is set the FIFO head will increment by a single message
TXEN = 0: (FIFO configured as a Receive FIFO)
When this bit is set the FIFO tail will increment by a single message
bit 12 DONLY: Store Message Data Only bit(1)
TXEN = 1: (FIFO configured as a Transmit FIFO)
This bit is not used and has no effect.
TXEN = 0: (FIFO configured as a Receive FIFO)
1 = Only data bytes will be stored in the FIFO
0 = Full message is stored, including identifier
bit 11-8 Unimplemented: Read as ‘0’
bit 7 TXEN: TX/RX Buffer Selection bit
1 = FIFO is a Transmit FIFO
0 = FIFO is a Receive FIFO

Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the FIFO is reset.

DS60001156K-page 278  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-20: CiFIFOCONn: CAN FIFO CONTROL REGISTER ‘n’ (n = 0 THROUGH 31)
bit 6 TXABAT: Message Aborted bit(2)
1 = Message was aborted
0 = Message completed successfully
bit 5 TXLARB: Message Lost Arbitration bit(3)
1 = Message lost arbitration while being sent
0 = Message did not lose arbitration while being sent
bit 4 TXERR: Error Detected During Transmission bit(3)
1 = A bus error occured while the message was being sent
0 = A bus error did not occur while the message was being sent
bit 3 TXREQ: Message Send Request
TXEN = 1: (FIFO configured as a Transmit FIFO)
Setting this bit to ‘1’ requests sending a message.
The bit will automatically clear when all the messages queued in the FIFO are successfully sent.
Clearing the bit to ‘0’ while set (‘1’) will request a message abort.
TXEN = 0: (FIFO configured as a receive FIFO)
This bit has no effect.
bit 2 RTREN: Auto RTR Enable bit
1 = When a remote transmit is received, TXREQ will be set
0 = When a remote transmit is received, TXREQ will be unaffected
bit 1-0 TXPR<1:0>: Message Transmit Priority bits
11 = Highest message priority
10 = High intermediate message priority
01 = Low intermediate message priority
00 = Lowest message priority

Note 1: These bits can only be modified when the CAN module is in Configuration mode (OPMOD<2:0> bits
(CiCON<23:21>) = 100).
2: This bit is updated when a message completes (or aborts) or when the FIFO is reset.
3: This bit is reset on any read of this register or when the FIFO is reset.

 2009-2019 Microchip Technology Inc. DS60001156K-page 279

PIC32MX5XX/6XX/7XX
REGISTER 24-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31)
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
31:24
— — — — — TXNFULLIE TXHALFIE TXEMPTYIE
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
— — — — RXOVFLIE RXFULLIE RXHALFIE RXNEMPTYIE
U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0
15:8
— — — — — TXNFULLIF(1) TXHALFIF TXEMPTYIF(1)
U-0 U-0 U-0 U-0 R/W-0 R-0 R-0 R-0
7:0 (1) (1)
— — — — RXOVFLIF RXFULLIF RXHALFIF RXNEMPTYIF(1)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-27 Unimplemented: Read as ‘0’

bit 26 TXNFULLIE: Transmit FIFO Not Full Interrupt Enable bit
1 = Interrupt enabled for FIFO not full
0 = Interrupt disabled for FIFO not full
bit 25 TXHALFIE: Transmit FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 24 TXEMPTYIE: Transmit FIFO Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO empty
0 = Interrupt disabled for FIFO empty
bit 23-20 Unimplemented: Read as ‘0’
bit 19 RXOVFLIE: Overflow Interrupt Enable bit
1 = Interrupt enabled for overflow event
0 = Interrupt disabled for overflow event
bit 18 RXFULLIE: Full Interrupt Enable bit
1 = Interrupt enabled for FIFO full
0 = Interrupt disabled for FIFO full
bit 17 RXHALFIE: FIFO Half Full Interrupt Enable bit
1 = Interrupt enabled for FIFO half full
0 = Interrupt disabled for FIFO half full
bit 16 RXNEMPTYIE: Empty Interrupt Enable bit
1 = Interrupt enabled for FIFO not empty
0 = Interrupt disabled for FIFO not empty
bit 15-11 Unimplemented: Read as ‘0’
bit 10 TXNFULLIF: Transmit FIFO Not Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is not full
0 = FIFO is full
TXEN = 0: (FIFO configured as a receive buffer)
Unused, reads ‘0’

Note 1: This bit is read-only and reflects the status of the FIFO.

DS60001156K-page 280  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 24-21: CiFIFOINTn: CAN FIFO INTERRUPT REGISTER ‘n’ (n = 0 THROUGH 31)
bit 9 TXHALFIF: FIFO Transmit FIFO Half Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is  half full
0 = FIFO is > half full
TXEN = 0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
bit 8 TXEMPTYIF: Transmit FIFO Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
1 = FIFO is empty
0 = FIFO is not empty, at least 1 message queued to be transmitted
TXEN = 0: (FIFO configured as a receive buffer)
Unused, reads ‘0’
bit 7-4 Unimplemented: Read as ‘0’
bit 3 RXOVFLIF: Receive FIFO Overflow Interrupt Flag bit
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = Overflow event has occurred
0 = No overflow event occured
bit 2 RXFULLIF: Receive FIFO Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = FIFO is full
0 = FIFO is not full
bit 1 RXHALFIF: Receive FIFO Half Full Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = FIFO is half full
0 = FIFO is < half full
bit 0 RXNEMPTYIF: Receive Buffer Not Empty Interrupt Flag bit(1)
TXEN = 1: (FIFO configured as a transmit buffer)
Unused, reads ‘0’
TXEN = 0: (FIFO configured as a receive buffer)
1 = FIFO is not empty, has at least 1 message
0 = FIFO is empty

Note 1: This bit is read-only and reflects the status of the FIFO.

 2009-2019 Microchip Technology Inc. DS60001156K-page 281

PIC32MX5XX/6XX/7XX
REGISTER 24-22: CiFIFOUAn: CAN FIFO USER ADDRESS REGISTER ‘n’ (n = 0 THROUGH 31)
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R-x R-x R-x R-x R-x R-x R-x R-x
31:24
CiFIFOUAn<31:24>
R-x R-x R-x R-x R-x R-x R-x R-x
23:16
CiFIFOUAn<23:16>
R-x R-x R-x R-x R-x R-x R-x R-x
15:8
CiFIFOUAn<15:8>
R-x R-x R-x R-x R-x R-x R-0(1) R-0(1)
7:0
CiFIFOUAn<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 CiFIFOUAn<31:0>: CAN FIFO User Address bits

TXEN = 1: (FIFO configured as a transmit buffer)
A read of this register will return the address where the next message is to be written (FIFO head).
TXEN = 0: (FIFO configured as a receive buffer)
A read of this register will return the address where the next message is to be read (FIFO tail).

Note 1: This bit will always read ‘0’, which forces byte-alignment of messages.

Note: This register is not guaranteed to read correctly in Configuration mode, and should only be accessed when
the module is not in Configuration mode.

REGISTER 24-23: CiFIFOCIN: CAN MODULE MESSAGE INDEX REGISTER ‘n’ (n = 0 THROUGH 31)
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 R-0 R-0 R-0 R-0 R-0
7:0
— — — CiFIFOCI<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-5 Unimplemented: Read as ‘0’

bit 4-0 CiFIFOCIn<4:0>: CAN Side FIFO Message Index bits
TXEN = 1: (FIFO configured as a transmit buffer)
A read of this register will return an index to the message that the FIFO will next attempt to transmit.
TXEN = 0: (FIFO configured as a receive buffer)
A read of this register will return an index to the message that the FIFO will use to save the next message.

DS60001156K-page 282  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
25.0 ETHERNET CONTROLLER Key features of the Ethernet Controller include:
• Supports 10/100 Mbps data transfer rates
Note: This data sheet summarizes the features
• Supports full-duplex and half-duplex operation
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a • Supports RMII and MII PHY interface
comprehensive reference source. To • Supports MIIM PHY management interface
complement the information in this data • Supports both manual and automatic Flow Control
sheet, refer to Section 35. “Ethernet • RAM descriptor-based DMA operation for both
Controller” (DS60001155) in the “PIC32 receive and transmit path
Family Reference Manual”, which is avail-
• Fully configurable interrupts
able from the Microchip web site
(www.microchip.com/PIC32). • Configurable receive packet filtering
- CRC check
The Ethernet controller is a bus master module that - 64-byte pattern match
interfaces with an off-chip Physical Layer (PHY) to
- Broadcast, multicast and unicast packets
implement a complete Ethernet node in a system.
- Magic Packet™
- 64-bit hash table
- Runt packet
• Supports packet payload checksum calculation
• Supports various hardware statistics counters
Figure 25-1 illustrates a block diagram of the Ethernet
controller.

FIGURE 25-1: ETHERNET CONTROLLER BLOCK DIAGRAM

FIFO
TX

TX DMA TX BM

TX Bus TX Function
Master

TX Flow Control
System Bus

MII/RMII
IF
RX Flow
Control
FIFO
RX

RX DMA RX BM

MAC External
PHY
RX Bus RX Filter RX Function
Master

Checksum MIIM
IF

MAC Control
Fast Peripheral

DMA
Control and
Registers Configuration
Ethernet DMA
Bus

Registers

Host IF

Ethernet Controller

 2009-2019 Microchip Technology Inc. DS60001156K-page 283

PIC32MX5XX/6XX/7XX
Table 25-1, Table 25-2, Table 25-3 and Table 25-4 TABLE 25-3: MII MODE ALTERNATE
show four interfaces and the associated pins that can INTERFACE SIGNALS
be used with the Ethernet Controller.
(FMIIEN = 1, FETHIO = 0)

TABLE 25-1: MII MODE DEFAULT Pin Name Description

INTERFACE SIGNALS AEMDC Management Clock
(FMIIEN = 1, FETHIO = 1) AEMDIO Management I/O
Pin Name Description AETXCLK Transmit Clock
EMDC Management Clock AETXEN Transmit Enable
EMDIO Management I/O AETXD0 Transmit Data
ETXCLK Transmit Clock AETXD1 Transmit Data
ETXEN Transmit Enable AETXD2 Transmit Data
ETXD0 Transmit Data AETXD3 Transmit Data
ETXD1 Transmit Data AETXERR Transmit Error
ETXD2 Transmit Data AERXCLK Receive Clock
ETXD3 Transmit Data AERXDV Receive Data Valid
ETXERR Transmit Error AERXD0 Receive Data
ERXCLK Receive Clock AERXD1 Receive Data
ERXDV Receive Data Valid AERXD2 Receive Data
ERXD0 Receive Data AERXD3 Receive Data
ERXD1 Receive Data AERXERR Receive Error
ERXD2 Receive Data AECRS Carrier Sense
ERXD3 Receive Data AECOL Collision Indication
ERXERR Receive Error
Note: The MII mode Alternate Interface is not
ECRS Carrier Sense available on 64-pin devices.
ECOL Collision Indication

TABLE 25-4: RMII MODE ALTERNATE

TABLE 25-2: RMII MODE DEFAULT
INTERFACE SIGNALS
INTERFACE SIGNALS
(FMIIEN = 0, FETHIO = 0)
(FMIIEN = 0, FETHIO = 1)
Pin Name Description
Pin Name Description
AEMDC Management Clock
EMDC Management Clock
AEMDIO Management I/O
EMDIO Management I/O
AETXEN Transmit Enable
ETXEN Transmit Enable
AETXD0 Transmit Data
ETXD0 Transmit Data
AETXD1 Transmit Data
ETXD1 Transmit Data
AEREFCLK Reference Clock
EREFCLK Reference Clock
AECRSDV Carrier Sense – Receive Data Valid
ECRSDV Carrier Sense – Receive Data Valid
AERXD0 Receive Data
ERXD0 Receive Data
AERXD1 Receive Data
ERXD1 Receive Data
AERXERR Receive Error
ERXERR Receive Error

Note: Ethernet controller pins that are not used

by selected interface can be used by
other peripherals.

DS60001156K-page 284  2009-2019 Microchip Technology Inc.

 25.1 Control Registers
 2009-2019 Microchip Technology Inc.

TABLE 25-5: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 PTV<15:0> 0000

9000 ETHCON1
15:0 ON — SIDL — — — TXRTS RXEN AUTOFC — — MANFC — — — BUFCDEC 0000
31:16 — — — — — — — — — — — — — — — — 0000
9010 ETHCON2
15:0 — — — — — RXBUFSZ<6:0> — — — — 0000
31:16 TXSTADDR<31:16> 0000
9020 ETHTXST
15:0 TXSTADDR<15:2> — — 0000
31:16 RXSTADDR<31:16> 0000
9030 ETHRXST
15:0 RXSTADDR<15:2> — — 0000
31:16 0000
9040 ETHHT0 HT<31:0>
15:0 0000
31:16 0000
9050 ETHHT1 HT<63:32>

PIC32MX5XX/6XX/7XX
15:0 0000
31:16 0000
9060 ETHPMM0 PMM<31:0>
15:0 0000
31:16 0000
9070 ETHPMM1 PMM<63:32>
15:0 0000
31:16 — — — — — — — — — — — — — — — — 0000
9080 ETHPMCS
15:0 PMCS<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
9090 ETHPMO
15:0 PMO<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
90A0 ETHRXFC CRC CRC RUNT NOT
15:0 HTEN MPEN — NOTPM PMMODE<3:0> RUNTEN UCEN MCEN BCEN 0000
ERREN OKEN ERREN MEEN
31:16 — — — — — — — — RXFWM<7:0> 0000
90B0 ETHRXWM
15:0 — — — — — — — — RXEWM<7:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
DS60001156K-page 285

90C0 ETHIEN TX RX EW FW RX PK RX TX TX RX RX
15:0 — — — — — 0000
BUSEIE BUSEIE MARKIE MARKIE DONEIE TPENDIE ACTIE DONEIE ABORTIE BUFNAIE OVFLWIE
31:16 — — — — — — — — — — — — — — — — 0000
90D0 ETHIRQ
15:0 — TXBUSE RXBUSE — — — EWMARK FWMARK RXDONE PKTPEND RXACT — TXDONE TXABORT RXBUFNA RXOVFLW 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
2: Reset values default to the factory programmed value.
DS60001156K-page 286
TABLE 25-5: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,

PIC32MX5XX/6XX/7XX
PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,
PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
Virtual Address PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — BUFCNT<7:0> 0000

90E0 ETHSTAT
15:0 — — — — — — — — BUSY TXBUSY RXBUSY — — — — — 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9100
RXOVFLOW 15:0 RXOVFLWCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9110
FRMTXOK 15:0 FRMTXOKCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9120
SCOLFRM 15:0 SCOLFRMCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9130
MCOLFRM 15:0 MCOLFRMCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9140
FRMRXOK 15:0 FRMRXOKCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9150
FCSERR 15:0 FCSERRCNT<15:0> 0000
ETH 31:16 — — — — — — — — — — — — — — — — 0000
9160
ALGNERR 15:0 ALGNERRCNT<15:0> 0000
31:16 — — — — — — — — — — — — — — — — 0000
EMAC1
9200 SOFT SIM RESET RESET RESET RESET
CFG1 15:0 — — — — — LOOPBACK TXPAUSE RXPAUSE PASSALL RXENABLE 800D
RESET RESET RMCS RFUN TMCS TFUN
31:16 — — — — — — — — — — — — — — — — 0000
EMAC1
9210 EXCESS BP PAD CRC
CFG2 15:0 — NOBKOFF — — LONGPRE PUREPRE AUTOPAD VLANPAD DELAYCRC HUGEFRM LENGTHCK FULLDPLX 4082
DFR NOBKOFF ENABLE ENABLE
EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
9220
 2009-2019 Microchip Technology Inc.

IPGT 15:0 — — — — — — — — — B2BIPKTGP<6:0> 0012

EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
9230
IPGR 15:0 — NB2BIPKTGP1<6:0> — NB2BIPKTGP2<6:0> 0C12
EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
9240
CLRT 15:0 — — CWINDOW<5:0> — — — — RETX<3:0> 370F
EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
9250
MAXF 15:0 MACMAXF<15:0> 05EE
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
2: Reset values default to the factory programmed value.
 TABLE 25-5: ETHERNET CONTROLLER REGISTER SUMMARY FOR PIC32MX664F064H, PIC32MX664F128H, PIC32MX664F064L,
 2009-2019 Microchip Technology Inc.

PIC32MX664F128L, PIC32MX675F256H, PIC32MX675F512H, PIC32MX695F512H, PIC32MX775F256H, PIC32MX775F512H,

PIC32MX795F512H, PIC32MX695F512L, PIC32MX675F256L, PIC32MX675F512L, PIC32MX764F128H, PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L AND PIC32MX795F512L DEVICES (CONTINUED)
Virtual Address

Bits

All Resets
Bit Range
(BF88_#)

Register
Name(1)

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
EMAC1
9260 RESET SPEED
SUPP 15:0 — — — — — — — — — — — — — — 1000
RMII RMII
EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
9270
TEST 15:0 — — — — — — — — — — — — — TESTBP TESTPAUSE SHRTQNTA 0000
31:16 — — — — — — — — — — — — — — — — 0000
EMAC1
9280 RESET
MCFG 15:0 — — — — — — — — — CLKSEL<3:0> NOPRE SCANINC 0020
MGMT
EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
9290
MCMD 15:0 — — — — — — — — — — — — — — SCAN READ 0000
EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
92A0
MADR 15:0 — — — PHYADDR<4:0> — — — REGADDR<4:0> 0100
EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
92B0
MWTD 15:0 MWTD<15:0> 0000

PIC32MX5XX/6XX/7XX
EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
92C0
MRDD 15:0 MRDD<15:0> 0000
EMAC1 31:16 — — — — — — — — — — — — — — — — 0000
92D0
MIND 15:0 — — — — — — — — — — — — LINKFAIL NOTVALID SCAN MIIMBUSY 0000
EMAC1 31:16 — — — — — — — — — — — — — — — — xxxx
9300
SA0(2) 15:0 STNADDR6<7:0> STNADDR5<7:0> xxxx
EMAC1 31:16 — — — — — — — — — — — — — — — — xxxx
9310
SA1(2) 15:0 STNADDR4<7:0> STNADDR3<7:0> xxxx
EMAC1 31:16 — — — — — — — — — — — — — — — — xxxx
9320
SA2(2) 15:0 STNADDR2<7:0> STNADDR1<7:0> xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table (with the exception of ETHSTAT) have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and
INV Registers” for more information.
2: Reset values default to the factory programmed value.
DS60001156K-page 287
PIC32MX5XX/6XX/7XX
REGISTER 25-1: ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1
Bit Range Bit Bit Bit Bit Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
PTV<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
PTV<7:0>
R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
ON — SIDL — — — TXRTS RXEN(1)
R/W-0 U-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0
7:0
AUTOFC — — MANFC — — — BUFCDEC

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 PTV<15:0>: PAUSE Timer Value bits

PAUSE Timer Value used for Flow Control.
This register should only be written when RXEN (ETHCON1<8>) is not set.
These bits are only used for Flow Control operations.
bit 15 ON: Ethernet ON bit
1 = Ethernet module is enabled
0 = Ethernet module is disabled
bit 14 Unimplemented: Read as ‘0’
bit 13 SIDL: Ethernet Stop in Idle Mode bit
1 = Ethernet module transfers are paused during Idle mode
0 = Ethernet module transfers continue during Idle mode
bit 12-10 Unimplemented: Read as ‘0’
bit 9 TXRTS: Transmit Request to Send bit
1 = Activate the TX logic and send the packet(s) defined in the TX EDT
0 = Stop transmit (when cleared by software) or transmit done (when cleared by hardware)
After the bit is written with a ‘1’, it will clear to a ‘0’ whenever the transmit logic has finished transmitting
the requested packets in the Ethernet Descriptor Table (EDT). If a ‘0’ is written by the CPU, the transmit
logic finishes the current packet’s transmission and then stops any further.
This bit only affects TX operations.
bit 8 RXEN: Receive Enable bit(1)
1 = Enable RX logic, packets are received and stored in the RX buffer as controlled by the filter
configuration
0 = Disable RX logic, no packets are received in the RX buffer
This bit only affects RX operations.

Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.

DS60001156K-page 288  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 25-1: ETHCON1: ETHERNET CONTROLLER CONTROL REGISTER 1 (CONTINUED)
bit 7 AUTOFC: Automatic Flow Control bit
1 = Automatic Flow Control is enabled
0 = Automatic Flow Control is disabled
Setting this bit will enable automatic Flow Control. If set, the full and empty watermarks are used to
automatically enable and disable the Flow Control, respectively. When the number of received buffers
BUFCNT (ETHSTAT<16:23>) rises to the full watermark, Flow Control is automatically enabled. When
the BUFCNT falls to the empty watermark, Flow Control is automatically disabled.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 6-5 Unimplemented: Read as ‘0’
bit 4 MANFC: Manual Flow Control bit
1 = Manual Flow Control is enabled
0 = Manual Flow Control is disabled
Setting this bit will enable manual Flow Control. If set, the Flow Control logic will send a PAUSE frame
using the PAUSE timer value in the PTV register. It will then resend a PAUSE frame every 128 *
PTV<15:0>/2 TX clock cycles until the bit is cleared.
Note: For 10 Mbps operation, TX clock runs at 2.5 MHz. For 100 Mbps operation, TX clock runs at
25 MHz.
When this bit is cleared, the Flow Control logic will automatically send a PAUSE frame with a 0x0000
PAUSE timer value to disable Flow Control.
This bit is only used for Flow Control operations and affects both TX and RX operations.
bit 3-1 Unimplemented: Read as ‘0’
bit 0 BUFCDEC: Descriptor Buffer Count Decrement bit
The BUFCDEC bit is a write-1 bit that reads as ‘0’. When written with a ‘1’, the Descriptor Buffer Counter,
BUFCNT, will decrement by one. If BUFCNT is incremented by the RX logic at the same time that this bit
is written, the BUFCNT value will remain unchanged. Writing a ‘0’ will have no effect.
This bit is only used for RX operations.

Note 1: It is not recommended to clear the RXEN bit and then make changes to any RX related field/register. The
Ethernet Controller must be reinitialized (ON cleared to ‘0’), and then the RX changes applied.

 2009-2019 Microchip Technology Inc. DS60001156K-page 289

PIC32MX5XX/6XX/7XX
REGISTER 25-2: ETHCON2: ETHERNET CONTROLLER CONTROL REGISTER 2
Bit Range Bit Bit Bit Bit Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
15:8
— — — — — RXBUFSZ<6:4>
R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0
7:0
RXBUFSZ<3:0> — — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-11 Unimplemented: Read as ‘0’

bit 10-4 RXBUFSZ<6:0>: RX Data Buffer Size for All RX Descriptors (in 16-byte increments) bits
1111111 = RX data Buffer size for descriptors is 2032 bytes
•
•
•
1100000 = RX data Buffer size for descriptors is 1536 bytes
•
•
•
0000011 = RX data Buffer size for descriptors is 48 bytes
0000010 = RX data Buffer size for descriptors is 32 bytes
0000001 = RX data Buffer size for descriptors is 16 bytes
0000000 = Reserved
bit 3-0 Unimplemented: Read as ‘0’

Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.

DS60001156K-page 290  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 25-3: ETHTXST: ETHERNET CONTROLLER TX PACKET DESCRIPTOR START
ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
TXSTADDR<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
TXSTADDR<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
TXSTADDR<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
7:0
TXSTADDR<7:2> — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-2 TXSTADDR<31:2>: Starting Address of First Transmit Descriptor bits

This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’

Note 1: This register is only used for TX operations.

2: This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.

REGISTER 25-4: ETHRXST: ETHERNET CONTROLLER RX PACKET DESCRIPTOR START

ADDRESS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
RXSTADDR<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
RXSTADDR<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
RXSTADDR<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0
7:0
RXSTADDR<7:2> — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-2 RXSTADDR<31:2>: Starting Address of First Receive Descriptor bits

This register should not be written while any transmit, receive or DMA operations are in progress.
This address must be 4-byte aligned (bits 1-0 must be ‘00’).
bit 1-0 Unimplemented: Read as ‘0’

Note 1: This register is only used for RX operations.

2: This register will be updated by hardware with the last descriptor used by the last successfully transmitted
packet.

 2009-2019 Microchip Technology Inc. DS60001156K-page 291

PIC32MX5XX/6XX/7XX
REGISTER 25-5: ETHHT0: ETHERNET CONTROLLER HASH TABLE 0 REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
HT<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
HT<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
HT<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
HT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 HT<31:0>: Hash Table Bytes 0-3 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit
(ETHRXFC<15>) = 0.

REGISTER 25-6: ETHHT1: ETHERNET CONTROLLER HASH TABLE 1 REGISTER

Bit Range Bit Bit Bit Bit Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
HT<63:56>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
HT<55:48>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
HT<47:40>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
HT<39:32>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-0 HT<63:32>: Hash Table Bytes 4-7 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the HTEN bit
(ETHRXFC<15>) = 0.

DS60001156K-page 292  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 25-7: ETHPMM0: ETHERNET CONTROLLER PATTERN MATCH MASK 0 REGISTER
Bit Range Bit Bit Bit Bit Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
31:24
PMM<31:24>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
PMM<23:16>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
PMM<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
PMM<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 PMM<31:24>: Pattern Match Mask 3 bits

bit 23-16 PMM<23:16>: Pattern Match Mask 2 bits
bit 15-8 PMM<15:8>: Pattern Match Mask 1 bits
bit 7-0 PMM<7:0>: Pattern Match Mask 0 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit
(ETHRXFC<11:8>) = 0.

REGISTER 25-8: ETHPMM1: ETHERNET CONTROLLER PATTERN MATCH MASK 1 REGISTER

Bit Range Bit
Bit Bit Bit Bit Bit Bit Bit
24/16/8/0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

31:24
PMM<63:56>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
PMM<55:48>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
PMM<47:40>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
PMM<39:32>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 PMM<63:56>: Pattern Match Mask 7 bits

bit 23-16 PMM<55:48>: Pattern Match Mask 6 bits
bit 15-8 PMM<47:40>: Pattern Match Mask 5 bits
bit 7-0 PMM<39:32>: Pattern Match Mask 4 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit
(ETHRXFC<11:8>) = 0.

 2009-2019 Microchip Technology Inc. DS60001156K-page 293

PIC32MX5XX/6XX/7XX
REGISTER 25-9: ETHPMCS: ETHERNET CONTROLLER PATTERN MATCH CHECKSUM
REGISTER
Bit Range Bit
Bit Bit Bit Bit Bit Bit Bit
24/16/8/0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
PMCS<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
PMCS<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-8 PMCS<15:8>: Pattern Match Checksum 1 bits
bit 7-0 PMCS<7:0>: Pattern Match Checksum 0 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit
(ETHRXFC<11:8>) = 0.

REGISTER 25-10: ETHPMO: ETHERNET CONTROLLER PATTERN MATCH OFFSET REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
PMO<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
PMO<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 PMO<15:0>: Pattern Match Offset 1 bits

Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0 or the PMMODE bit
(ETHRXFC<11:8>) = 0.

DS60001156K-page 294  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 25-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION
REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
HTEN MPEN — NOTPM PMMODE<3:0>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
CRCERREN CRCOKEN RUNTERREN RUNTEN UCEN NOTMEEN MCEN BCEN

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 HTEN: Enable Hash Table Filtering bit
1 = Enable Hash Table Filtering
0 = Disable Hash Table Filtering
bit 14 MPEN: Magic Packet™ Enable bit
1 = Enable Magic Packet Filtering
0 = Disable Magic Packet Filtering
bit 13 Unimplemented: Read as ‘0’
bit 12 NOTPM: Pattern Match Inversion bit
1 = The Pattern Match Checksum must not match for a successful Pattern Match to occur
0 = The Pattern Match Checksum must match for a successful Pattern Match to occur
This bit determines whether Pattern Match Checksum must match in order for a successful Pattern Match
to occur.
bit 11-8 PMMODE<3:0>: Pattern Match Mode bits
1001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Packet = Magic Packet)(1,3)
1000 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Hash Table Filter match)(1,2)
0111 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Broadcast Address)(1)
0110 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Broadcast Address)(1)
0101 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Unicast Address)(1)
0100 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Unicast Address)(1)
0011 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Station Address)(1)
0010 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches) AND
(Destination Address = Station Address)(1)
0001 = Pattern match is successful if (NOTPM = 1 XOR Pattern Match Checksum matches)(1)
0000 = Pattern Match is disabled; pattern match is always unsuccessful

Note 1: XOR = True when either one or the other conditions are true, but not both.
2: This Hash Table Filter match is active regardless of the value of the HTEN bit.
3: This Magic Packet Filter match is active regardless of the value of the MPEN bit.

Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.

 2009-2019 Microchip Technology Inc. DS60001156K-page 295

PIC32MX5XX/6XX/7XX
REGISTER 25-11: ETHRXFC: ETHERNET CONTROLLER RECEIVE FILTER CONFIGURATION
REGISTER (CONTINUED)
bit 7 CRCERREN: CRC Error Collection Enable bit
1 = The received packet CRC must be invalid for the packet to be accepted
0 = Disable CRC Error Collection filtering
This bit allows the user to collect all packets that have an invalid CRC.
bit 6 CRCOKEN: CRC OK Enable bit
1 = The received packet CRC must be valid for the packet to be accepted
0 = Disable CRC filtering
This bit allows the user to reject all packets that have an invalid CRC.
bit 5 RUNTERREN: Runt Error Collection Enable bit
1 = The received packet must be a runt packet for the packet to be accepted
0 = Disable Runt Error Collection filtering
This bit allows the user to collect all packets that are runt packets. For this filter, a runt packet is defined as
any packet with a size of less than 64 bytes (when CRCOKEN = 0) or any packet with a size of less than
64 bytes that has a valid CRC (when CRCOKEN = 1).
bit 4 RUNTEN: Runt Enable bit
1 = The received packet must not be a runt packet for the packet to be accepted
0 = Disable Runt filtering
This bit allows the user to reject all runt packets. For this filter, a runt packet is defined as any packet with a
size of less than 64 bytes.
bit 3 UCEN: Unicast Enable bit
1 = Enable Unicast Filtering
0 = Disable Unicast Filtering
This bit allows the user to accept all unicast packets whose Destination Address matches the Station
Address.
bit 2 NOTMEEN: Not Me Unicast Enable bit
1 = Enable Not Me Unicast Filtering
0 = Disable Not Me Unicast Filtering
This bit allows the user to accept all unicast packets whose Destination Address does not match the Station
Address.
bit 1 MCEN: Multicast Enable bit
1 = Enable Multicast Filtering
0 = Disable Multicast Filtering
This bit allows the user to accept all Multicast Address packets.
bit 0 BCEN: Broadcast Enable bit
1 = Enable Broadcast Filtering
0 = Disable Broadcast Filtering
This bit allows the user to accept all Broadcast Address packets.

Note 1: XOR = True when either one or the other conditions are true, but not both.
2: This Hash Table Filter match is active regardless of the value of the HTEN bit.
3: This Magic Packet Filter match is active regardless of the value of the MPEN bit.

Note 1: This register is only used for RX operations.

2: The bits in this register may only be changed while the RXEN bit (ETHCON1<8>) = 0.

DS60001156K-page 296  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 25-12: ETHRXWM: ETHERNET CONTROLLER RECEIVE WATERMARKS REGISTER
Bit Range Bit Bit Bit Bit Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
RXFWM<7:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RXEWM<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-16 RXFWM<7:0>: Receive Full Watermark bits
The software controlled RX Buffer Full Watermark Pointer is compared against the RX BUFCNT to
determine the full watermark condition for the FWMARK interrupt and for enabling Flow Control when
automatic Flow Control is enabled. The Full Watermark Pointer should always be greater than the Empty
Watermark Pointer.
bit 15-8 Unimplemented: Read as ‘0’
bit 7-0 RXEWM<7:0>: Receive Empty Watermark bits
The software controlled RX Buffer Empty Watermark Pointer is compared against the RX BUFCNT to
determine the empty watermark condition for the EWMARK interrupt and for disabling Flow Control when
automatic Flow Control is enabled. The Empty Watermark Pointer should always be less than the Full
Watermark Pointer.

Note: This register is only used for RX operations.

 2009-2019 Microchip Technology Inc. DS60001156K-page 297

PIC32MX5XX/6XX/7XX
REGISTER 25-13: ETHIEN: ETHERNET CONTROLLER INTERRUPT ENABLE REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
— TXBUSEIE(1) RXBUSEIE(2) — — — EWMARKIE(2) FWMARKIE(2)
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RXDONEIE(2) PKTPENDIE(2) RXACTIE(2) — TXDONEIE(1) TXABORTIE(1) RXBUFNAIE(2) RXOVFLWIE(2)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as ‘0’

bit 14 TXBUSEIE: Transmit BVCI Bus Error Interrupt Enable bit(1)
1 = Enable TXBUS Error Interrupt
0 = Disable TXBUS Error Interrupt
bit 13 RXBUSEIE: Receive BVCI Bus Error Interrupt Enable bit(2)
1 = Enable RXBUS Error Interrupt
0 = Disable RXBUS Error Interrupt
bit 12-10 Unimplemented: Read as ‘0’
bit 9 EWMARKIE: Empty Watermark Interrupt Enable bit(2)
1 = Enable EWMARK Interrupt
0 = Disable EWMARK Interrupt
bit 8 FWMARKIE: Full Watermark Interrupt Enable bit(2)
1 = Enable FWMARK Interrupt
0 = Disable FWMARK Interrupt
bit 7 RXDONEIE: Receiver Done Interrupt Enable bit(2)
1 = Enable RXDONE Interrupt
0 = Disable RXDONE Interrupt
bit 6 PKTPENDIE: Packet Pending Interrupt Enable bit(2)
1 = Enable PKTPEND Interrupt
0 = Disable PKTPEND Interrupt
bit 5 RXACTIE: RX Activity Interrupt Enable bit
1 = Enable RXACT Interrupt
0 = Disable RXACT Interrupt
bit 4 Unimplemented: Read as ‘0’
bit 3 TXDONEIE: Transmitter Done Interrupt Enable bit(1)
1 = Enable TXDONE Interrupt
0 = Disable TXDONE Interrupt
bit 2 TXABORTIE: Transmitter Abort Interrupt Enable bit(1)
1 = Enable TXABORT Interrupt
0 = Disable TXABORT Interrupt
bit 1 RXBUFNAIE: Receive Buffer Not Available Interrupt Enable bit(2)
1 = Enable RXBUFNA Interrupt
0 = Disable RXBUFNA Interrupt
bit 0 RXOVFLWIE: Receive FIFO Overflow Interrupt Enable bit(2)
1 = Enable RXOVFLW Interrupt
0 = Disable RXOVFLW Interrupt

Note 1: This bit is only used for TX operations.

2: This bit is only used for RX operations.

DS60001156K-page 298  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 25-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
Bit Range Bit Bit Bit Bit Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0
15:8
— TXBUSE RXBUSE — — — EWMARK FWMARK
R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RXDONE PKTPEND RXACT — TXDONE TXABORT RXBUFNA RXOVFLW

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as ‘0’

bit 14 TXBUSE: Transmit BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the TX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 13 RXBUSE: Receive BVCI Bus Error Interrupt bit
1 = BVCI Bus Error has occurred
0 = BVCI Bus Error has not occurred
This bit is set when the RX DMA encounters a BVCI Bus error during a memory access. It is cleared by
either a Reset or CPU write of a ‘1’ to the CLR register.
bit 12-10 Unimplemented: Read as ‘0’
bit 9 EWMARK: Empty Watermark Interrupt bit
1 = Empty Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is less than or equal to the value in the
RXEWM bit (ETHRXWM<0:7>) value. It is cleared by BUFCNT bit (ETHSTAT<16:23>)
being incremented by hardware. Writing a ‘0’ or a ‘1’ has no effect.
bit 8 FWMARK: Full Watermark Interrupt bit
1 = Full Watermark pointer reached
0 = No interrupt pending
This bit is set when the RX Descriptor Buffer Count is greater than or equal to the value in the RXFWM
bit (ETHRXWM<16:23>) field. It is cleared by writing the BUFCDEC (ETHCON1<0>) bit to decrement
the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 7 RXDONE: Receive Done Interrupt bit
1 = RX packet was successfully received
0 = No interrupt pending
This bit is set whenever an RX packet is successfully received. It is cleared by either a Reset or CPU
write of a ‘1’ to the CLR register.

Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.

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PIC32MX5XX/6XX/7XX
REGISTER 25-14: ETHIRQ: ETHERNET CONTROLLER INTERRUPT REQUEST REGISTER
bit 6 PKTPEND: Packet Pending Interrupt bit
1 = RX packet pending in memory
0 = RX packet is not pending in memory
This bit is set when the BUFCNT counter has a value other than ‘0’. It is cleared by either a Reset or by
writing the BUFCDEC bit to decrement the BUFCNT counter. Writing a ‘0’ or a ‘1’ has no effect.
bit 5 RXACT: Receive Activity Interrupt bit
1 = RX packet data was successfully received
0 = No interrupt pending
This bit is set whenever RX packet data is stored in the RXBM FIFO. It is cleared by either a Reset or
CPU write of a ‘1’ to the CLR register.
bit 4 Unimplemented: Read as ‘0’
bit 3 TXDONE: Transmit Done Interrupt bit
1 = TX packet was successfully sent
0 = No interrupt pending
This bit is set when the currently transmitted TX packet completes transmission, and the Transmit Status
Vector is loaded into the first descriptor used for the packet. It is cleared by either a Reset or CPU write
of a ‘1’ to the CLR register.
bit 2 TXABORT: Transmit Abort Condition Interrupt bit
1 = TX abort condition occurred on the last TX packet
0 = No interrupt pending
This bit is set when the MAC aborts the transmission of a TX packet for one of the following reasons:
• Jumbo TX packet abort
• Underrun abort
• Excessive defer abort
• Late collision abort
• Excessive collisions abort
This bit is cleared by either a Reset or CPU write of a ‘1’ to the CLR register.
bit 1 RXBUFNA: Receive Buffer Not Available Interrupt bit
1 = RX Buffer Descriptor Not Available condition has occurred
0 = No interrupt pending
This bit is set by a RX Buffer Descriptor Overrun condition. It is cleared by either a Reset or a CPU write
of a ‘1’ to the CLR register.
bit 0 RXOVFLW: Receive FIFO Over Flow Error bit
1 = RX FIFO Overflow Error condition has occurred
0 = No interrupt pending
RXOVFLW is set by the RXBM Logic for an RX FIFO Overflow condition. It is cleared by either a Reset
or CPU write of a ‘1’ to the CLR register.

Note: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.

DS60001156K-page 300  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 25-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
23:16
BUFCNT<7:0>
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0
7:0
ETHBUSY(1) TXBUSY(2) RXBUSY(2) — — — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Unimplemented: Read as ‘0’

bit 23-16 BUFCNT<7:0>: Packet Buffer Count bits
Number of packet buffers received in memory. Once a packet has been successfully received, this register
is incremented by hardware based on the number of descriptors used by the packet. Software decrements
the counter (by writing to the BUFCDEC bit (ETHCON1<0>) for each descriptor used) after a packet has
been read out of the buffer. The register does not roll over (0xFF to 0x00) when hardware tries to increment
the register and the register is already at 0xFF. Conversely, the register does not roll under (0x00 to 0xFF)
when software tries to decrement the register and the register is already at 0x0000. When software attempts
to decrement the counter at the same time that the hardware attempts to increment the counter, the counter
value will remain unchanged.
When this register value reaches 0xFF, the RX logic will halt (only if automatic Flow Control is enabled)
awaiting software to write the BUFCDEC bit in order to decrement the register below 0xFF.
If automatic Flow Control is disabled, the RXDMA will continue processing and the BUFCNT will saturate at
a value of 0xFF.
When this register is non-zero, the PKTPEND status bit will be set and an interrupt may be generated,
depending on the value of the ETHIEN bit <PKTPENDIE> register.
When the ETHRXST register is written, the BUFCNT counter is automatically cleared to 0x00.
Note: BUFCNT will not be cleared when ON is set to ‘0’. This enables software to continue to utilize
and decrement this count.
bit 15-8 Unimplemented: Read as ‘0’
bit 7 ETHBUSY: Ethernet Module busy bit(1)
1 = Ethernet logic has been turned on (ON (ETHCON1<15>) = 1) or is completing a transaction
0 = Ethernet logic is idle
This bit indicates that the module has been turned on or is completing a transaction after being turned off.
bit 6 TXBUSY: Transmit Busy bit(2)
1 = TX logic is receiving data
0 = TX logic is idle
This bit indicates that a packet is currently being transmitted. A change in this status bit is not necessarily
reflected by the TXDONE interrupt, as TX packets may be aborted or rejected by the MAC.

Note 1: This bit will be set when the ON bit (ETHCON1<15>) = 1.

2: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.

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PIC32MX5XX/6XX/7XX
REGISTER 25-15: ETHSTAT: ETHERNET CONTROLLER STATUS REGISTER (CONTINUED)
bit 5 RXBUSY: Receive Busy bit(2)
1 = RX logic is receiving data
0 = RX logic is idle
This bit indicates that a packet is currently being received. A change in this status bit is not necessarily
reflected by the RXDONE interrupt, as RX packets may be aborted or rejected by the RX filter.
bit 4-0 Unimplemented: Read as ‘0’

Note 1: This bit will be set when the ON bit (ETHCON1<15>) = 1.

2: This bit will be cleared when the ON bit (ETHCON1<15>) = 0.

DS60001156K-page 302  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
REGISTER 25-16: ETHRXOVFLOW: ETHERNET CONTROLLER RECEIVE OVERFLOW STATISTICS
REGISTER
Bit Range Bit Bit Bit Bit Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
RXOVFLWCNT<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
RXOVFLWCNT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 RXOVFLWCNT<15:0>: Dropped Receive Frames Count bits
Increment counter for frames accepted by the RX filter and subsequently dropped due to internal receive
error (RXFIFO overrun). This event also sets the RXOVFLW bit (ETHIRQ<0>) interrupt flag.

Note 1: This register is only used for RX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.

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PIC32MX5XX/6XX/7XX
REGISTER 25-17: ETHFRMTXOK: ETHERNET CONTROLLER FRAMES TRANSMITTED OK
STATISTICS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FRMTXOKCNT<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FRMTXOKCNT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 FRMTXOKCNT<15:0>: Frame Transmitted OK Count bits
Increment counter for frames successfully transmitted.

Note 1: This register is only used for TX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-18: ETHSCOLFRM: ETHERNET CONTROLLER SINGLE COLLISION FRAMES
STATISTICS REGISTER
Bit Range Bit Bit Bit Bit Bit Bit Bit Bit
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
SCOLFRMCNT<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
SCOLFRMCNT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 SCOLFRMCNT<15:0>: Single Collision Frame Count bits
Increment count for frames that were successfully transmitted on the second try.

Note 1: This register is only used for TX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.

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PIC32MX5XX/6XX/7XX
REGISTER 25-19: ETHMCOLFRM: ETHERNET CONTROLLER MULTIPLE COLLISION FRAMES
STATISTICS REGISTER
Bit Bit
Range Bit Bit Bit Bit Bit Bit Bit
24/16/8/0
31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1

U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0

31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
MCOLFRMCNT<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
MCOLFRMCNT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 MCOLFRMCNT<15:0>: Multiple Collision Frame Count bits
Increment count for frames that were successfully transmitted after there was more than one collision.

Note 1: This register is only used for TX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-20: ETHFRMRXOK: ETHERNET CONTROLLER FRAMES RECEIVED OK
STATISTICS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FRMRXOKCNT<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FRMRXOKCNT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 FRMRXOKCNT<15:0>: Frames Received OK Count bits
Increment count for frames received successfully by the RX Filter. This count will not be incremented if
there is a Frame Check Sequence (FCS) or Alignment error.

Note 1: This register is only used for RX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for
bytes 0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should only be done for debug/test purposes.

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PIC32MX5XX/6XX/7XX
REGISTER 25-21: ETHFCSERR: ETHERNET CONTROLLER FRAME CHECK SEQUENCE ERROR
STATISTICS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
FCSERRCNT<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
FCSERRCNT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 FCSERRCNT<15:0>: FCS Error Count bits
Increment count for frames received with FCS error and the frame length in bits is an integral multiple of
8 bits.

Note 1: This register is only used for RX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-22: ETHALGNERR: ETHERNET CONTROLLER ALIGNMENT ERRORS STATISTICS
REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
ALGNERRCNT<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
ALGNERRCNT<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 ALGNERRCNT<15:0>: Alignment Error Count bits
Increment count for frames with alignment errors. Note that an alignment error is a frame that has an FCS
error and the frame length in bits is not an integral multiple of 8 bits (a.k.a., dribble nibble)

Note 1: This register is only used for RX operations.

2: This register is automatically cleared by hardware after a read operation, unless the byte enables for bytes
0/1 are ‘0’.
3: It is recommended to use the SET, CLR, or INV registers to set or clear any bit in this register. Setting or
clearing any bits in this register should be only done for debug/test purposes.

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PIC32MX5XX/6XX/7XX

REGISTER 25-23: EMAC1CFG1: ETHERNET CONTROLLER MAC CONFIGURATION 1 REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-1 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8 SOFT SIM RESET RESET RESET RESET
— —
RESET RESET RMCS RFUN TMCS TFUN
U-0 U-0 U-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-1
7:0 TX RX RX
— — — LOOPBACK PASSALL
PAUSE PAUSE ENABLE

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 SOFTRESET: Soft Reset bit
Setting this bit will put the MACMII in reset. Its default value is ‘1’.
bit 14 SIMRESET: Simulation Reset bit
Setting this bit will cause a reset to the random number generator within the Transmit Function.
bit 13-12 Unimplemented: Read as ‘0’
bit 11 RESETRMCS: Reset MCS/RX bit
Setting this bit will put the MAC Control Sub-layer/Receive domain logic in reset.
bit 10 RESETRFUN: Reset RX Function bit
Setting this bit will put the MAC Receive function logic in reset.
bit 9 RESETTMCS: Reset MCS/TX bit
Setting this bit will put the MAC Control Sub-layer/TX domain logic in reset.
bit 8 RESETTFUN: Reset TX Function bit
Setting this bit will put the MAC Transmit function logic in reset.
bit 7-5 Unimplemented: Read as ‘0’
bit 4 LOOPBACK: MAC Loopback mode bit
1 = MAC Transmit interface is loop backed to the MAC Receive interface
0 = MAC normal operation
bit 3 TXPAUSE: MAC TX Flow Control bit
1 = PAUSE Flow Control frames are allowed to be transmitted
0 = PAUSE Flow Control frames are blocked
bit 2 RXPAUSE: MAC RX Flow Control bit
1 = The MAC acts upon received PAUSE Flow Control frames
0 = Received PAUSE Flow Control frames are ignored
bit 1 PASSALL: MAC Pass all Receive Frames bit
1 = The MAC will accept all frames regardless of type (Normal vs. Control)
0 = The received Control frames are ignored
bit 0 RXENABLE: MAC Receive Enable bit
1 = Enable the MAC receiving of frames
0 = Disable the MAC receiving of frames

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 25/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0
15:8 EXCESS BPNOBK NOBK
— — — LONGPRE PUREPRE
DFR OFF OFF
R/W-1 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
7:0 AUTO VLAN PAD CRC
DELAYCRC HUGEFRM LENGTHCK FULLDPLX
PAD(1,2) PAD(1,2) ENABLE(1,3) ENABLE

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as ‘0’

bit 14 EXCESSDER: Excess Defer bit
1 = The MAC will defer to carrier indefinitely as per the Standard
0 = The MAC will abort when the excessive deferral limit is reached
bit 13 BPNOBKOFF: Backpressure/No Backoff bit
1 = The MAC after incidentally causing a collision during backpressure will immediately retransmit without
backoff reducing the chance of further collisions and ensuring transmit packets get sent
0 = The MAC will not remove the backoff
bit 12 NOBKOFF: No Backoff bit
1 = Following a collision, the MAC will immediately retransmit rather than using the Binary Exponential Back-
off algorithm as specified in the Standard
0 = Following a collision, the MAC will use the Binary Exponential Backoff algorithm
bit 11-10 Unimplemented: Read as ‘0’
bit 9 LONGPRE: Long Preamble Enforcement bit
1 = The MAC only allows receive packets which contain preamble fields less than 12 bytes in length
0 = The MAC allows any length preamble as per the Standard
bit 8 PUREPRE: Pure Preamble Enforcement bit
1 = The MAC will verify the content of the preamble to ensure it contains 0x55 and is error-free. A packet with
errors in its preamble is discarded
0 = The MAC does not perform any preamble checking
bit 7 AUTOPAD: Automatic Detect Pad Enable bit(1,2)
1 = The MAC will automatically detect the type of frame, either tagged or untagged, by comparing the two
octets following the source address with 0x8100 (VLAN Protocol ID) and pad accordingly
0 = The MAC does not perform automatic detection

Note 1: Table 25-6 provides a description of the pad function based on the configuration of this register.
2: This bit is ignored if the PADENABLE bit is cleared.
3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware

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PIC32MX5XX/6XX/7XX
REGISTER 25-24: EMAC1CFG2: ETHERNET CONTROLLER MAC CONFIGURATION 2 REGISTER
bit 6 VLANPAD: VLAN Pad Enable bit(1,2)
1 = The MAC will pad all short frames to 64 bytes and append a valid CRC
0 = The MAC does not perform padding of short frames
bit 5 PADENABLE: Pad/CRC Enable bit(1,3)
1 = The MAC will pad all short frames
0 = The frames presented to the MAC have a valid length
bit 4 CRCENABLE: CRC Enable1 bit
1 = The MAC will append a CRC to every frame whether padding was required or not. Must be set if the
PADENABLE bit is set.
0 = The frames presented to the MAC have a valid CRC
bit 3 DELAYCRC: Delayed CRC bit
This bit determines the number of bytes, if any, of proprietary header information that exist on the front of the
IEEE 802.3 frames.
1 = Four bytes of header (ignored by the CRC function)
0 = No proprietary header
bit 2 HUGEFRM: Huge Frame enable bit
1 = Frames of any length are transmitted and received
0 = Huge frames are not allowed for receive or transmit
bit 1 LENGTHCK: Frame Length checking bit
1 = Both transmit and receive frame lengths are compared to the Length/Type field. If the Length/Type field
represents a length then the check is performed. Mismatches are reported on the transmit/receive
statistics vector.
0 = Length/Type field check is not performed
bit 0 FULLDPLX: Full-Duplex Operation bit
1 = The MAC operates in Full-Duplex mode
0 = The MAC operates in Half-Duplex mode

Note 1: Table 25-6 provides a description of the pad function based on the configuration of this register.
2: This bit is ignored if the PADENABLE bit is cleared.
3: This bit is used in conjunction with the AUTOPAD and VLANPAD bits.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware

TABLE 25-6: PAD OPERATION

Type AUTOPAD VLANPAD PADENABLE Action
Any x x 0 No pad, check CRC
Any 0 0 1 Pad to 60 Bytes, append CRC
Any x 1 1 Pad to 64 Bytes, append CRC
Any 1 0 1 If untagged: Pad to 60 Bytes, append CRC
If VLAN tagged: Pad to 64 Bytes, append CRC

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 PIC32MX5XX/6XX/7XX
REGISTER 25-25: EMAC1IPGT: ETHERNET CONTROLLER MAC BACK-TO-BACK INTERPACKET
GAP REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
7:0
— B2BIPKTGP<6:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-7 Unimplemented: Read as ‘0’

bit 6-0 B2BIPKTGP<6:0>: Back-to-Back Interpacket Gap bits
This is a programmable field representing the nibble time offset of the minimum possible period between
the end of any transmitted packet, to the beginning of the next. In Full-Duplex mode, the register value
should be the desired period in nibble times minus 3. In Half-Duplex mode, the register value should be the
desired period in nibble times minus 6. In Full-Duplex the recommended setting is 0x15 (21d), which rep-
resents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps). In Half-Duplex mode, the rec-
ommended setting is 0x12 (18d), which also represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6
µs (in 10 Mbps).

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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PIC32MX5XX/6XX/7XX
REGISTER 25-26: EMAC1IPGR: ETHERNET CONTROLLER MAC NON-BACK-TO-BACK
INTERPACKET GAP REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-1 R/W-0 R/W-0
15:8
— NB2BIPKTGP1<6:0>
U-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-0 R/W-1 R/W-0
7:0
— NB2BIPKTGP2<6:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-15 Unimplemented: Read as ‘0’

bit 14-8 NB2BIPKTGP1<6:0>: Non-Back-to-Back Interpacket Gap Part 1 bits
This is a programmable field representing the optional carrierSense window referenced in section
4.2.3.2.1 “Deference” of the IEEE 80.23 Specification. If the carrier is detected during the timing of IPGR1,
the MAC defers to the carrier. If, however, the carrier comes after IPGR1, the MAC continues timing IPGR2
and transmits, knowingly causing a collision, thus ensuring fair access to the medium. Its range of values
is 0x0 to IPGR2. Its recommend value is 0xC (12d).
bit 7 Unimplemented: Read as ‘0’
bit 6-0 NB2BIPKTGP2<6:0>: Non-Back-to-Back Interpacket Gap Part 2 bits
This is a programmable field representing the non-back-to-back Inter-Packet-Gap. Its recommended value
is 0x12 (18d), which represents the minimum IPG of 0.96 µs (in 100 Mbps) or 9.6 µs (in 10 Mbps).

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-27: EMAC1CLRT: ETHERNET CONTROLLER MAC COLLISION WINDOW/RETRY
LIMIT REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1
15:8
— — CWINDOW<5:0>
U-0 U-0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1
7:0
— — — — RETX<3:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-14 Unimplemented: Read as ‘0’

bit 13-8 CWINDOW<5:0>: Collision Window bits
This is a programmable field representing the slot time or collision window during which collisions occur in
properly configured networks. Since the collision window starts at the beginning of transmission, the pre-
amble and SFD is included. Its default of 0x37 (55d) corresponds to the count of frame bytes at the end of
the window.
bit 7-4 Unimplemented: Read as ‘0’
bit 3-0 RETX<3:0>: Retransmission Maximum bits
This is a programmable field specifying the number of retransmission attempts following a collision before
aborting the packet due to excessive collisions. The Standard specifies the maximum number of attempts
(attemptLimit) to be 0xF (15d). Its default is ‘0xF’.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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PIC32MX5XX/6XX/7XX
REGISTER 25-28: EMAC1MAXF: ETHERNET CONTROLLER MAC MAXIMUM FRAME LENGTH
REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 R/W-0 R/W-1
15:8
MACMAXF<15:8>(1)
R/W-1 R/W-1 R/W-1 R/W-0 R/W-1 R/W-1 R/W-1 R/W-0
7:0
MACMAXF<7:0>(1)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 MACMAXF<15:0>: Maximum Frame Length bits(1)
These bits reset to 0x05EE, which represents a maximum receive frame of 1518 octets. An untagged
maximum size Ethernet frame is 1518 octets. A tagged frame adds four octets for a total of 1522 octets. If
a shorter/longer maximum length restriction is desired, program this 16-bit field.

Note 1: If a proprietary header is allowed, this bit should be adjusted accordingly. For example, if 4-byte headers
are prepended to frames, MACMAXF could be set to 1527 octets. This would allow the maximum VLAN
tagged frame plus the 4-byte header.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-29: EMAC1SUPP: ETHERNET CONTROLLER MAC PHY SUPPORT REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 R/W-0 U-0 U-0 R/W-0
15:8
— — — — RESETRMII(1) — — SPEEDRMII(1)
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
7:0
— — — — — — — —

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-12 Unimplemented: Read as ‘0’

bit 11 RESETRMII: Reset RMII Logic bit(1)
1 = Reset the MAC RMII module
0 = Normal operation.
bit 10-9 Unimplemented: Read as ‘0’
bit 8 SPEEDRMII: RMII Speed bit(1)
This bit configures the Reduced MII logic for the current operating speed.
1 = RMII is running at 100 Mbps
0 = RMII is running at 10 Mbps
bit 7-0 Unimplemented: Read as ‘0’

Note 1: This bit is only used for the RMII module.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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PIC32MX5XX/6XX/7XX
REGISTER 25-30: EMAC1TEST: ETHERNET CONTROLLER MAC TEST REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0
7:0
— — — — — TESTBP TESTPAUSE(1) SHRTQNTA(1)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-3 Unimplemented: Read as ‘0’

bit 2 TESTBP: Test Backpressure bit
1 = The MAC will assert backpressure on the link. Backpressure causes preamble to be transmitted, raising
carrier sense. A transmit packet from the system will be sent during backpressure.
0 = Normal operation
bit 1 TESTPAUSE: Test PAUSE bit(1)
1 = The MAC Control sub-layer will inhibit transmissions, just as if a PAUSE Receive Control frame with a
non-zero pause time parameter was received
0 = Normal operation
bit 0 SHRTQNTA: Shortcut PAUSE Quanta bit(1)
1 = The MAC reduces the effective PAUSE Quanta from 64 byte-times to 1 byte-time
0 = Normal operation

Note 1: This bit is only for testing purposes.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-31: EMAC1MCFG: ETHERNET CONTROLLER MAC MII MANAGEMENT
CONFIGURATION REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
RESETMGMT — — — — — — —
U-0 U-0 R/W-1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — CLKSEL<3:0>(1) NOPRE SCANINC

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 RESETMGMT: Test Reset MII Management bit
1 = Reset the MII Management module
0 = Normal Operation
bit 14-6 Unimplemented: Read as ‘0’
bit 5-2 CLKSEL<3:0>: MII Management Clock Select 1 bits(1)
These bits are used by the clock divide logic in creating the MII Management Clock (MDC), which the IEEE
802.3 Specification defines to be no faster than 2.5 MHz. Some PHYs support clock rates up to 12.5 MHz.
bit 1 NOPRE: Suppress Preamble bit
1 = The MII Management will perform read/write cycles without the 32-bit preamble field. Some PHYs
support suppressed preamble
0 = Normal read/write cycles are performed
bit 0 SCANINC: Scan Increment bit
1 = The MII Management module will perform read cycles across a range of PHYs. The read cycles will start
from address 1 through the value set in EMAC1MADR<PHYADDR>
0 = Continuous reads of the same PHY

Note 1: Table 25-7 provides a description of the clock divider encoding.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

TABLE 25-7: MIIM CLOCK SELECTION

MIIM Clock Select EMAC1MCFG<5:2>
SYSCLK divided by 4 000x
SYSCLK divided by 6 0010
SYSCLK divided by 8 0011
SYSCLK divided by 10 0100
SYSCLK divided by 14 0101
SYSCLK divided by 20 0110
SYSCLK divided by 28 0111
SYSCLK divided by 40 1000
Undefined Any other combination

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PIC32MX5XX/6XX/7XX
REGISTER 25-32: EMAC1MCMD: ETHERNET CONTROLLER MAC MII MANAGEMENT COMMAND
REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0
7:0
— — — — — — SCAN READ

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-2 Unimplemented: Read as ‘0’

bit 1 SCAN: MII Management Scan Mode bit
1 = The MII Management module will perform read cycles continuously (for example, useful for monitoring
the Link Fail)
0 = Normal Operation
bit 0 READ: MII Management Read Command bit
1 = The MII Management module will perform a single read cycle. The read data is returned in the
EMAC1MRDD register
0 = The MII Management module will perform a write cycle. The write data is taken from the EMAC1MWTD
register

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-33: EMAC1MADR: ETHERNET CONTROLLER MAC MII MANAGEMENT ADDRESS
REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1
15:8
— — — PHYADDR<4:0>
U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — REGADDR<4:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-13 Unimplemented: Read as ’0’

bit 12-8 PHYADDR<4:0>: MII Management PHY Address bits
This field represents the 5-bit PHY Address field of Management cycles. Up to 31 PHYs can be addressed
(0 is reserved).
bit 7-5 Unimplemented: Read as ’0’
bit 4-0 REGADDR<4:0>: MII Management Register Address bits
This field represents the 5-bit Register Address field of Management cycles. Up to 32 registers can be
accessed.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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PIC32MX5XX/6XX/7XX
REGISTER 25-34: EMAC1MWTD: ETHERNET CONTROLLER MAC MII MANAGEMENT WRITE
DATA REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
MWTD<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
MWTD<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ’0’

bit 15-0 MWTD<15:0>: MII Management Write Data bits
When written, a MII Management write cycle is performed using the 16-bit data and the pre-configured PHY
and Register addresses from the EMAC1MADR register.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

REGISTER 25-35: EMAC1MRDD: ETHERNET CONTROLLER MAC MII MANAGEMENT READ DATA
REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
15:8
MRDD<15:8>
R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
MRDD<7:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-0 MRDD<15:0>: MII Management Read Data bits
Following a MII Management Read Cycle, the 16-bit data can be read from this location.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-36: EMAC1MIND: ETHERNET CONTROLLER MAC MII MANAGEMENT INDICATORS
REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0
7:0
— — — — LINKFAIL NOTVALID SCAN MIIMBUSY

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3 LINKFAIL: Link Fail bit
When ‘1’ is returned - indicates link fail has occurred. This bit reflects the value last read from the PHY status
register.
bit 2 NOTVALID: MII Management Read Data Not Valid bit
When ‘1’ is returned - indicates an MII management read cycle has not completed and the Read Data is not
yet valid.
bit 1 SCAN: MII Management Scanning bit
When ‘1’ is returned - indicates a scan operation (continuous MII Management Read cycles) is in progress.
bit 0 MIIMBUSY: MII Management Busy bit
When ‘1’ is returned - indicates MII Management module is currently performing an MII Management Read
or Write cycle.

Note: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.

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PIC32MX5XX/6XX/7XX
REGISTER 25-37: EMAC1SA0: ETHERNET CONTROLLER MAC STATION ADDRESS 0 REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
15:8
STNADDR6<7:0>
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
7:0
STNADDR5<7:0>

Legend: P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-8 STNADDR6<7:0>: Station Address Octet 6 bits
These bits hold the sixth transmitted octet of the station address.
bit 7-0 STNADDR5<7:0>: Station Address Octet 5 bits
These bits hold the fifth transmitted octet of the station address.

Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2: This register is loaded at reset from the factory preprogrammed station address.

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 PIC32MX5XX/6XX/7XX
REGISTER 25-38: EMAC1SA1: ETHERNET CONTROLLER MAC STATION ADDRESS 1 REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
15:8
STNADDR4<7:0>
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
7:0
STNADDR3<7:0>

Legend: P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15-8 STNADDR4<7:0>: Station Address Octet 4 bits
These bits hold the fourth transmitted octet of the station address.
bit 7-0 STNADDR3<7:0>: Station Address Octet 3 bits
These bits hold the third transmitted octet of the station address.

Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2: This register is loaded at reset from the factory preprogrammed station address.

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PIC32MX5XX/6XX/7XX
REGISTER 25-39: EMAC1SA2: ETHERNET CONTROLLER MAC STATION ADDRESS 2 REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
15:8
STNADDR2<7:0>
R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P R/W-P
7:0
STNADDR1<7:0>

Legend: P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Reserved: Maintain as ‘0’; ignore read

bit 15-8 STNADDR2<7:0>: Station Address Octet 2 bits
These bits hold the second transmitted octet of the station address.
bit 7-0 STNADDR1<7:0>: Station Address Octet 1 bits
These bits hold the most significant (first transmitted) octet of the station address.

Note 1: Both 16-bit and 32-bit accesses are allowed to these registers (including the SET, CLR and INV registers).
8-bit accesses are not allowed and are ignored by the hardware.
2: This register is loaded at reset from the factory preprogrammed station address.

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 PIC32MX5XX/6XX/7XX
26.0 COMPARATOR The Comparator module contains two comparators that
can be configured in a variety of ways.
Note: This data sheet summarizes the features Key features of the Comparator module include:
of the PIC32MX5XX/6XX/7XX family of
devices. It is not intended to be a • Selectable inputs available include:
comprehensive reference source. To - Analog inputs multiplexed with I/O pins
complement the information in this data - On-chip internal absolute voltage reference (IVREF)
sheet, refer to Section 19. - Comparator voltage reference (CVREF)
“Comparator” (DS60001110) in the
• Outputs can be inverted
“PIC32 Family Reference Manual”, which
is available from the Microchip web site • Selectable interrupt generation
(www.microchip.com/PIC32). A block diagram of the Comparator module is
illustrated in Figure 26-1.

FIGURE 26-1: COMPARATOR MODULE BLOCK DIAGRAM

Comparator 1

CREF COUT (CM1CON<8>)

ON C1OUT (CMSTAT<0>)
CPOL
C1IN+(1)
CVREF(2)
C1OUT

CCH<1:0> C1
C1IN-
COE
C1IN+
C2IN+
IVREF(2)

Comparator 2
CREF COUT (CM2CON<8>)
ON C2OUT (CMSTAT<1>)
CPOL
C2IN+
CVREF(2)
C2OUT

CCH<1:0> C2
C2IN-
COE
C2IN+
C1IN+
IVREF(2)

Note 1: On devices with a USB module, and when the module is enabled, this pin is controlled by the USB module,
and therefore, is not available as a comparator input.
2: Internally connected. See Section 27.0 “Comparator Voltage Reference (CVREF)”.

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26.1 Control Registers

PIC32MX5XX/6XX/7XX
TABLE 26-1: COMPARATOR REGISTER MAP
Virtual Address Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1)
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
A000 CM1CON
15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3
31:16 — — — — — — — — — — — — — — — — 0000
A010 CM2CON
15:0 ON COE CPOL — — — — COUT EVPOL<1:0> — CREF — — CCH<1:0> 00C3
31:16 — — — — — — — — — — — — — — — — 0000
A060 CMSTAT
15:0 — — SIDL — — — — — — — — — — — C2OUT C1OUT 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 26-1: CMxCON: COMPARATOR ‘x’ CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 U-0 R-0
15:8 (1) (2)
ON COE CPOL — — — — COUT
R/W-1 R/W-1 U-0 R/W-0 U-0 U-0 R/W-1 R/W-1
7:0
EVPOL<1:0> — CREF — — CCH<1:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Comparator ON bit(1)
Clearing this bit does not affect the other bits in this register.
1 = Module is enabled. Setting this bit does not affect the other bits in this register
0 = Module is disabled and does not consume current.
bit 14 COE: Comparator Output Enable bit
1 = Comparator output is driven on the output CxOUT pin
0 = Comparator output is not driven on the output CxOUT pin
bit 13 CPOL: Comparator Output Inversion bit(2)
1 = Output is inverted
0 = Output is not inverted
bit 12-9 Unimplemented: Read as ‘0’
bit 8 COUT: Comparator Output bit
1 = Output of the Comparator is a ‘1’
0 = Output of the Comparator is a ‘0’
bit 7-6 EVPOL<1:0>: Interrupt Event Polarity Select bits
11 = Comparator interrupt is generated on a low-to-high or high-to-low transition of the comparator output
10 = Comparator interrupt is generated on a high-to-low transition of the comparator output
01 = Comparator interrupt is generated on a low-to-high transition of the comparator output
00 = Comparator interrupt generation is disabled
bit 5 Unimplemented: Read as ‘0’
bit 4 CREF: Comparator Positive Input Configure bit
1 = Comparator non-inverting input is connected to the internal CVREF
0 = Comparator non-inverting input is connected to the CXIN+ pin
bit 3-2 Unimplemented: Read as ‘0’
bit 1-0 CCH<1:0>: Comparator Negative Input Select bits for Comparator
11 = Comparator inverting input is connected to the IVREF
10 = Comparator inverting input is connected to the C2IN+ pin for C1 and C1IN+ pin for C2
01 = Comparator inverting input is connected to the C1IN+ pin for C1 and C2IN+ pin for C2
00 = Comparator inverting input is connected to the C1IN- pin for C1 and C2IN- pin for C2

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: Setting this bit will invert the signal to the comparator interrupt generator as well. This will result in an
interrupt being generated on the opposite edge from the one selected by EVPOL<1:0>.

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PIC32MX5XX/6XX/7XX
REGISTER 26-2: CMSTAT: COMPARATOR STATUS REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0
15:8
— — SIDL — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 R-0 R-0
7:0
— — — — — — C2OUT C1OUT

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-14 Unimplemented: Read as ‘0’

bit 13 SIDL: Stop in Idle Control bit
1 = All Comparator modules are disabled while in Idle mode
0 = All Comparator modules continue to operate while in Idle mode
bit 12-2 Unimplemented: Read as ‘0’
bit 1 C2OUT: Comparator Output bit
1 = Output of Comparator 2 is a ‘1’
0 = Output of Comparator 2 is a ‘0’
bit 0 C1OUT: Comparator Output bit
1 = Output of Comparator 1 is a ‘1’
0 = Output of Comparator 1 is a ‘0’

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 PIC32MX5XX/6XX/7XX
27.0 COMPARATOR VOLTAGE A block diagram of the module is illustrated in
Figure 27-1. The resistor ladder is segmented to
REFERENCE (CVREF) provide two ranges of voltage reference values and has
Note: This data sheet summarizes the features a power-down function to conserve power when the
of the PIC32MX5XX/6XX/7XX family of reference is not being used. The module’s supply refer-
devices. It is not intended to be a ence can be provided from either device VDD/VSS or an
comprehensive reference source. To com- external voltage reference. The CVREF output is avail-
plement the information in this data sheet, able for the comparators and typically available for pin
refer to Section 20. “Comparator Voltage output.
Reference (CVREF)” (DS60001109) in the Key features of the CVREF module include:
“PIC32 Family Reference Manual”, which
• High and low range selection
is available from the Microchip web site
• Sixteen output levels available for each range
(www.microchip.com/PIC32).
• Internally connected to comparators to conserve
The CVREF module is a 16-tap, resistor ladder network device pins
that provides a selectable reference voltage. Although • Output can be connected to a pin
its primary purpose is to provide a reference for the
analog comparators, it also may be used independently
of them.

FIGURE 27-1: COMPARATOR VOLTAGE REFERENCE MODULE BLOCK DIAGRAM

BGSEL<1:0>(1)

1.2V

0.6V IVREF

VREFSEL(1)

CVRSS = 1
VREF+ CVRSRC
CVREF
AVDD
CVRSS = 0 8R
CVR<3:0>

CVREN R

R
16-to-1 MUX

16 Steps
CVREFOUT

CVROE (CVRCON<6>)
R

R
R

CVRR 8R
CVRSS = 1
VREF-

AVSS
CVRSS = 0
Note 1: This bit is not available on PIC32MX575/675/695/775/795 devices. On these devices CVREF is generated by the
Register network and IVREF is connected to 0.6V.

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27.1 Control Register

PIC32MX5XX/6XX/7XX
TABLE 27-1:
Virtual Address
COMPARATOR VOLTAGE REFERENCE REGISTER MAP
Bits

All Resets
Bit Range
(BF80_#)

Register
Name(1) 31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
9800 CVRCON
15:0 ON — — — — VREFSEL(2) BGSEL<1:0>(2) — CVROE CVRR CVRSS CVR<3:0> 0100
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: All registers in this table have corresponding CLR, SET and INV registers at their virtual addresses, plus offsets of 0x4, 0x8 and 0xC, respectively. See Section 12.1.1 “CLR, SET and INV Registers”
for more information.
2: These bits are not available on PIC32MX575/675/695/775/795 devices. On these devices, reset value for CVRCON is ‘0000’.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 27-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
R/W-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-1
15:8 (1)
ON — — — — VREFSEL(2) BGSEL<1:0> (2)

U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0

7:0
— CVROE CVRR CVRSS CVR<3:0>

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-16 Unimplemented: Read as ‘0’

bit 15 ON: Comparator Voltage Reference On bit(1)
Setting or clearing this bit does not affect the other bits in this register.
1 = Module is enabled
0 = Module is disabled and does not consume current
bit 14-11 Unimplemented: Read as ‘0’
bit 10 VREFSEL: Voltage Reference Select bit(2)
1 = CVREF = VREF+
0 = CVREF is generated by the resistor network
bit 9-8 BGSEL<1:0>: Band Gap Reference Source bits(2)
11 = IVREF = VREF+
10 = Reserved
01 = IVREF = 0.6V (nominal, default)
00 = IVREF = 1.2V (nominal)
bit 7 Unimplemented: Read as ‘0’
bit 6 CVROE: CVREFOUT Enable bit
1 = Voltage level is output on CVREFOUT pin
0 = Voltage level is disconnected from CVREFOUT pin
bit 5 CVRR: CVREF Range Selection bit
1 = 0 to 0.625 CVRSRC, with CVRSRC/24 step size
0 = 0.25 CVRSRC to 0.719 CVRSRC, with CVRSRC/32 step size
bit 4 CVRSS: CVREF Source Selection bit
1 = Comparator voltage reference source, CVRSRC = (VREF+) – (VREF-)
0 = Comparator voltage reference source, CVRSRC = AVDD – AVSS
bit 3-0 CVR<3:0>: CVREF Value Selection 0  CVR<3:0>  15 bits
When CVRR = 1:
CVREF = (CVR<3:0>/24)  (CVRSRC)
When CVRR = 0:
CVREF = 1/4  (CVRSRC) + (CVR<3:0>/32)  (CVRSRC)

Note 1: When using the 1:1 PBCLK divisor, the user’s software should not read/write the peripheral’s SFRs in the
SYSCLK cycle immediately following the instruction that clears the module’s ON bit.
2: These bits are not available on PIC32MX575/675/775/795 devices. On these devices, the reset value for
CVRON is ‘0000’.

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PIC32MX5XX/6XX/7XX
NOTES:

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 PIC32MX5XX/6XX/7XX
28.0 POWER-SAVING FEATURES • SOSC Idle mode: the system clock is derived from
the SOSC. Peripherals continue to operate, but
Note: This data sheet summarizes the features can optionally be individually disabled.
of the PIC32MX5XX/6XX/7XX family of
• LPRC Idle mode: the system clock is derived
devices. It is not intended to be a
from the LPRC. Peripherals continue to operate,
comprehensive reference source. To com-
but can optionally be individually disabled. This is
plement the information in this data the lowest power mode for the device with a clock
sheet, refer to Section 10. “Power-Sav- running.
ing Features” (DS60001130) in the
• Sleep mode: the CPU, the system clock source
“PIC32 Family Reference Manual”, which
and any peripherals that operate from the system
is available from the Microchip web site
clock source are Halted. Some peripherals can
(www.microchip.com/PIC32).
operate in Sleep using specific clock sources.
This section describes power-saving features for the This is the lowest power mode for the device.
PIC32MX5XX/6XX/7XX family of devices. These
devices offer a total of nine methods and modes, 28.3 Power-Saving Operation
organized into two categories, that allow the user to Peripherals and the CPU can be halted or disabled to
balance power consumption with device performance. further reduce power consumption.
In all of the methods and modes described in this
section, power-saving is controlled by software. 28.3.1 SLEEP MODE
Sleep mode has the lowest power consumption of the
28.1 Power-Saving with CPU Running device power-saving operating modes. The CPU and
When the CPU is running, power consumption can be most peripherals are halted. Select peripherals can
controlled by reducing the CPU clock frequency, continue to operate in Sleep mode and can be used to
lowering the Peripheral Bus Clock (PBCLK) and by wake the device from Sleep. See the individual
individually disabling modules. These methods are peripheral module sections for descriptions of
grouped into the following categories: behavior in Sleep.
• FRC Run mode: the CPU is clocked from the FRC Sleep mode includes the following characteristics:
clock source with or without postscalers. • The CPU is halted
• LPRC Run mode: the CPU is clocked from the • The system clock source is typically shutdown.
LPRC clock source. See Section 28.3.3 “Peripheral Bus Scaling
• SOSC Run mode: the CPU is clocked from the Method” for specific information.
SOSC clock source. • There can be a wake-up delay based on the
In addition, the Peripheral Bus Scaling mode is available oscillator selection
where peripherals are clocked at the programmable • The Fail-Safe Clock Monitor (FSCM) does not
fraction of the CPU clock (SYSCLK). operate during Sleep mode
• The BOR circuit, if enabled, remains operative
28.2 CPU Halted Methods during Sleep mode
• The WDT, if enabled, is not automatically cleared
The device supports two power-saving modes, Sleep prior to entering Sleep mode
and Idle, both of which Halt the clock to the CPU. These
• Some peripherals can continue to operate at
modes operate with all clock sources, as listed below:
limited functionality in Sleep mode. These
• POSC Idle mode: the system clock is derived from peripherals include I/O pins that detect a change
the POSC. The system clock source continues to in the input signal, WDT, ADC, UART and
operate. Peripherals continue to operate, but can peripherals that use an external clock input or the
optionally be individually disabled. internal LPRC oscillator (e.g., RTCC, Timer1 and
• FRC Idle mode: the system clock is derived from Input Capture).
the FRC with or without postscalers. Peripherals • I/O pins continue to sink or source current in the
continue to operate, but can optionally be same manner as they do when the device is not in
individually disabled. Sleep
• Modules can be individually disabled by software
prior to entering Sleep in order to further reduce
consumption

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PIC32MX5XX/6XX/7XX
The processor will exit, or ‘wake-up’, from Sleep mode The device enters Idle mode when the SLPEN bit
on one of the following events: (OSCCON<4>) is clear and a WAIT instruction is
• On any interrupt from an enabled source that is executed.
operating in Sleep mode. The interrupt priority The processor will wake or exit from Idle mode on the
must be greater than the current CPU priority. following events:
• On any form of device Reset
• On any interrupt event for which the interrupt
• On a WDT time-out source is enabled. The priority of the interrupt
If the interrupt priority is lower than or equal to the event must be greater than the current priority of
current priority, the CPU will remain Halted, but the the CPU. If the priority of the interrupt event is
PBCLK will start running and the device will enter into lower than or equal to current priority of the CPU,
Idle mode. the CPU will remain Halted and the device will
remain in Idle mode.
28.3.2 IDLE MODE • On any form of device Reset
In Idle mode, the CPU is Halted but the System Clock • On a WDT time-out interrupt
(SYSCLK) source is still enabled. This allows peripher-
als to continue operation when the CPU is Halted. 28.3.3 PERIPHERAL BUS SCALING
Peripherals can be individually configured to Halt when METHOD
entering Idle by setting their respective SIDL bit.
Most of the peripherals on the device are clocked using
Latency, when exiting Idle mode, is very low due to the
the PBCLK. The Peripheral Bus (PB) can be scaled rel-
CPU oscillator source remaining active.
ative to the SYSCLK to minimize the dynamic power
Note 1: Changing the PBCLK divider ratio consumed by the peripherals. The PBCLK divisor is con-
requires recalculation of peripheral tim- trolled by PBDIV<1:0> (OSCCON<20:19>), allowing
ing. For example, assume the UART is SYSCLK to PBCLK ratios of 1:1, 1:2, 1:4 and 1:8. All
configured for 9600 baud with a PB clock peripherals using PBCLK are affected when the divisor
ratio of 1:1 and a POSC of 8 MHz. When is changed. Peripherals such as USB, interrupt control-
the PB clock divisor of 1:2 is used, the ler, DMA, bus matrix and prefetch cache are clocked
input frequency to the baud clock is cut in directly from SYSCLK. As a result, they are not affected
half; therefore, the baud rate is reduced by PBCLK divisor changes.
to 1/2 its former value. Due to numeric Changing the PBCLK divisor affects:
truncation in calculations (such as the
baud rate divisor), the actual baud rate • The CPU to peripheral access latency. The CPU
may be a tiny percentage different than has to wait for next PBCLK edge for a read to
expected. For this reason, any timing cal- complete. In 1:8 mode, this results in a latency of
culation required for a peripheral should one to seven SYSCLKs.
be performed with the new PB clock fre- • The power consumption of the peripherals. Power
quency instead of scaling the previous consumption is directly proportional to the fre-
value based on a change in the PB divisor quency at which the peripherals are clocked. The
ratio. greater the divisor, the lower the power consumed
by the peripherals.
2: Oscillator start-up and PLL lock delays
are applied when switching to a clock To minimize dynamic power, the PB divisor should be
source that was disabled and that uses a chosen to run the peripherals at the lowest frequency
crystal and/or the PLL. For example, that provides acceptable system performance. When
assume the clock source is switched from selecting a PBCLK divider, peripheral clock require-
POSC to LPRC just prior to entering Sleep ments, such as baud rate accuracy, should be taken
in order to save power. No oscillator start- into account. For example, the UART peripheral may
up delay would be applied when exiting not be able to achieve all baud rate values at some
Idle. However, when switching back to PBCLK divider depending on the SYSCLK value.
POSC, the appropriate PLL and/or
oscillator start-up/lock delays would be
applied.

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 PIC32MX5XX/6XX/7XX
29.0 SPECIAL FEATURES
Note: This data sheet summarizes the features
of the PIC32MX5XX/6XX/7XX family of
devices. However, it is not intended to be
a comprehensive reference source. To
complement the information in this data
sheet, refer to Section 33. “Programming
and Diagnostics” (DS60001129) in the
“PIC32 Family Reference Manual”, which
are available from the Microchip web site
(www.microchip.com/PIC32).

The PIC32MX5XX/6XX/7XX family of devices include

several features intended to maximize application
flexibility and reliability and minimize cost through
elimination of external components. Key features
include:
• Flexible device configuration
• Watchdog Timer (WDT)
• Joint Test Action Group (JTAG) interface
• In-Circuit Serial Programming™ (ICSP™)

29.1 Configuration Bits

The Configuration bits can be programmed using the
following registers to select various device
configurations.
• DEVCFG0: Device Configuration Word 0
• DEVCFG1: Device Configuration Word 1
• DEVCFG2: Device Configuration Word 2
• DEVCFG3: Device Configuration Word 3
• DEVID: Device and Revision ID Register

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DS60001156K-page 338

PIC32MX5XX/6XX/7XX
TABLE 29-1: DEVCFG: DEVICE CONFIGURATION WORD SUMMARY

Virtual Address
Bits

All Resets
Bit Range
(BFC0_#)

Register
Name
31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 FVBUSONIO FUSBIDIO — — — FCANIO FETHIO FMIIEN — — — — — FSRSSEL<2:0> xxxx

2FF0 DEVCFG3
15:0 USERID<15:0> xxxx
31:16 — — — — — — — — — — — — — FPLLODIV<2:0> xxxx
2FF4 DEVCFG2
15:0 UPLLEN — — — — UPLLIDIV<2:0> — FPLLMUL<2:0> — FPLLIDIV<2:0> xxxx
31:16 — — — — — — — — FWDTEN — — WDTPS<4:0> xxxx
2FF8 DEVCFG1
15:0 FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0> IESO — FSOSCEN — — FNOSC<2:0> xxxx
31:16 — — — CP — — — BWP — — — — PWP<7:4> xxxx
2FFC DEVCFG0
15:0 PWP<3:0> — — — — — — — — ICESEL — DEBUG<1:0> xxxx
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.

TABLE 29-2: DEVICE ID, REVISION, AND CONFIGURATION SUMMARY

Virtual Address

Bits

All Resets(1)
Bit Range
(BF80_#)

Register
Name

31/15 30/14 29/13 28/12 27/11 26/10 25/9 24/8 23/7 22/6 21/5 20/4 19/3 18/2 17/1 16/0

31:16 — — — — — — — — — — — — — — — — 0000
F200 DDPCON
15:0 — — — — — — — — — — — — JTAGEN TROEN — TDOEN 0008
31:16 VER<3:0> DEVID<27:16> xxxx
F220 DEVID
15:0 DEVID<15:0> xxxx
31:16 0000
F230 SYSKEY SYSKEY<31:0>
15:0 0000
Legend: x = unknown value on Reset; — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Note 1: Reset values are dependent on the device variant. Refer to “PIC32MX5XX/6XX/7XX Family Silicon Errata and Data Sheet Clarification” (DS80000480) for more information.
 2009-2019 Microchip Technology Inc.
 PIC32MX5XX/6XX/7XX
REGISTER 29-1: DEVCFG0: DEVICE CONFIGURATION WORD 0
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-0 r-1 r-1 R/P r-1 r-1 r-1 R/P
31:24
— — — CP — — — BWP
r-1 r-1 r-1 r-1 R/P R/P R/P R/P
23:16
— — — — PWP<7:4>
R/P R/P R/P R/P r-1 r-1 r-1 r-1
15:8
PWP<3:0> — — — —
r-1 r-1 r-1 r-1 R/P r-1 R/P R/P
7:0
— — — — ICESEL — DEBUG<1:0>

Legend: r = Reserved bit P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 Reserved: Write ‘0’

bit 30-29 Reserved: Write ‘1’
bit 28 CP: Code-Protect bit
Prevents boot and program Flash memory from being read or modified by an external programming device.
1 = Protection is disabled
0 = Protection is enabled
bit 27-25 Reserved: Write ‘1’
bit 24 BWP: Boot Flash Write-Protect bit
Prevents boot Flash memory from being modified during code execution.
1 = Boot Flash is writable
0 = Boot Flash is not writable
bit 23-20 Reserved: Write ‘1’
bit 19-12 PWP<7:0>: Program Flash Write-Protect bits
Prevents selected program Flash memory pages from being modified during code execution. The PWP bits
represent the 1’s complement of the number of write-protected program Flash memory pages.
11111111 = Disabled
11111110 = 0xBD00_0FFF
11111101 = 0xBD00_1FFF
11111100 = 0xBD00_2FFF
11111011 = 0xBD00_3FFF
11111010 = 0xBD00_4FFF
11111001 = 0xBD00_5FFF
11111000 = 0xBD00_6FFF
11110111 = 0xBD00_7FFF
11110110 = 0xBD00_8FFF
11110101 = 0xBD00_9FFF
11110100 = 0xBD00_AFFF
11110011 = 0xBD00_BFFF
11110010 = 0xBD00_CFFF
11110001 = 0xBD00_DFFF
11110000 = 0xBD00_EFFF
11101111 = 0xBD00_FFFF
•
•
•
01111111 = 0xBD07_FFFF
bit 11-4 Reserved: Write ‘1’

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PIC32MX5XX/6XX/7XX
REGISTER 29-1: DEVCFG0: DEVICE CONFIGURATION WORD 0 (CONTINUED)
bit 3 ICESEL: In-Circuit Emulator/Debugger Communication Channel Select bit
1 = PGEC2/PGED2 pair is used
0 = PGEC1/PGED1 pair is used
bit 2 Reserved: Write ‘1’
bit 1-0 DEBUG<1:0>: Background Debugger Enable bits (forced to ‘11’ if code-protect is enabled)
11 = Debugger is disabled
10 = Debugger is enabled
01 = Reserved (same as ‘11’ setting)
00 = Reserved (same as ‘11’ setting)

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 PIC32MX5XX/6XX/7XX
REGISTER 29-2: DEVCFG1: DEVICE CONFIGURATION WORD 1
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
31:24
— — — — — — — —
R/P r-1 r-1 R/P R/P R/P R/P R/P
23:16
FWDTEN — — WDTPS<4:0>
R/P R/P R/P R/P r-1 R/P R/P R/P
15:8
FCKSM<1:0> FPBDIV<1:0> — OSCIOFNC POSCMOD<1:0>
R/P r-1 R/P r-1 r-1 R/P R/P R/P
7:0
IESO — FSOSCEN — — FNOSC<2:0>

Legend: r = Reserved bit P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-24 Reserved: Write ‘1’

bit 23 FWDTEN: Watchdog Timer Enable bit
1 = The WDT is enabled and cannot be disabled by software
0 = The WDT is not enabled; it can be enabled in software
bit 22-21 Reserved: Write ‘1’
bit 20-16 WDTPS<4:0>: Watchdog Timer Postscale Select bits
10100 = 1:1048576
10011 = 1:524288
10010 = 1:262144
10001 = 1:131072
10000 = 1:65536
01111 = 1:32768
01110 = 1:16384
01101 = 1:8192
01100 = 1:4096
01011 = 1:2048
01010 = 1:1024
01001 = 1:512
01000 = 1:256
00111 = 1:128
00110 = 1:64
00101 = 1:32
00100 = 1:16
00011 = 1:8
00010 = 1:4
00001 = 1:2
00000 = 1:1
All other combinations not shown result in operation = 10100
bit 15-14 FCKSM<1:0>: Clock Switching and Monitor Selection Configuration bits
1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled
01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled
00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source.

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PIC32MX5XX/6XX/7XX
REGISTER 29-2: DEVCFG1: DEVICE CONFIGURATION WORD 1 (CONTINUED)
bit 13-12 FPBDIV<1:0>: Peripheral Bus Clock Divisor Default Value bits
11 = PBCLK is SYSCLK divided by 8
10 = PBCLK is SYSCLK divided by 4
01 = PBCLK is SYSCLK divided by 2
00 = PBCLK is SYSCLK divided by 1
bit 11 Reserved: Write ‘1’
bit 10 OSCIOFNC: CLKO Enable Configuration bit
1 = CLKO output is disabled
0 = CLKO output signal is active on the OSCO pin; the Primary Oscillator must be disabled or configured
for External Clock mode (EC) for the CLKO to be active (POSCMOD<1:0> = 11 or 00)
bit 9-8 POSCMOD<1:0>: Primary Oscillator Configuration bits
11 = Primary Oscillator is disabled
10 = HS Oscillator mode is selected
01 = XT Oscillator mode is selected
00 = External Clock mode is selected
bit 7 IESO: Internal External Switchover bit
1 = Internal External Switchover mode is enabled (Two-Speed Start-up is enabled)
0 = Internal External Switchover mode is disabled (Two-Speed Start-up is disabled)
bit 6 Reserved: Write ‘1’
bit 5 FSOSCEN: Secondary Oscillator Enable bit
1 = Enable the Secondary Oscillator
0 = Disable the Secondary Oscillator
bit 4-3 Reserved: Write ‘1’
bit 2-0 FNOSC<2:0>: Oscillator Selection bits
111 = Fast RC Oscillator with divide-by-N (FRCDIV)
110 = FRCDIV16 Fast RC Oscillator with fixed divide-by-16 postscaler
101 = Low-Power RC Oscillator (LPRC)
100 = Secondary Oscillator (SOSC)
011 = Primary Oscillator (POSC) with PLL module (XT+PLL, HS+PLL, EC+PLL)
010 = Primary Oscillator (XT, HS, EC)(1)
001 = Fast RC Oscillator with divide-by-N with PLL module (FRCDIV+PLL)
000 = Fast RC Oscillator (FRC)

Note 1: Do not disable the POSC (POSCMOD = 11) when using this oscillator source.

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 PIC32MX5XX/6XX/7XX
REGISTER 29-3: DEVCFG2: DEVICE CONFIGURATION WORD 2
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
r-1 r-1 r-1 r-1 r-1 r-1 r-1 r-1
31:24
— — — — — — — —
r-1 r-1 r-1 r-1 r-1 R/P R/P R/P
23:16
— — — — — FPLLODIV<2:0>
R/P r-1 r-1 r-1 r-1 R/P R/P R/P
15:8
UPLLEN — — — — UPLLIDIV<2:0>
r-1 R/P-1 R/P R/P-1 r-1 R/P R/P R/P
7:0
— FPLLMUL<2:0> — FPLLIDIV<2:0>

Legend: r = Reserved bit P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-19 Reserved: Write ‘1’

bit 18-16 FPLLODIV<2:0>: PLL Output Divider bits
111 = PLL output divided by 256
110 = PLL output divided by 64
101 = PLL output divided by 32
100 = PLL output divided by 16
011 = PLL output divided by 8
010 = PLL output divided by 4
001 = PLL output divided by 2
000 = PLL output divided by 1
bit 15 UPLLEN: USB PLL Enable bit
1 = Disable and bypass USB PLL
0 = Enable USB PLL
bit 14-11 Reserved: Write ‘1’
bit 10-8 UPLLIDIV<2:0>: USB PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider
bit 7 Reserved: Write ‘1’
bit 6-4 FPLLMUL<2:0>: PLL Multiplier bits
111 = 24x multiplier
110 = 21x multiplier
101 = 20x multiplier
100 = 19x multiplier
011 = 18x multiplier
010 = 17x multiplier
001 = 16x multiplier
000 = 15x multiplier
bit 3 Reserved: Write ‘1’

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PIC32MX5XX/6XX/7XX
REGISTER 29-3: DEVCFG2: DEVICE CONFIGURATION WORD 2 (CONTINUED)
bit 2-0 FPLLIDIV<2:0>: PLL Input Divider bits
111 = 12x divider
110 = 10x divider
101 = 6x divider
100 = 5x divider
011 = 4x divider
010 = 3x divider
001 = 2x divider
000 = 1x divider

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 PIC32MX5XX/6XX/7XX
REGISTER 29-4: DEVCFG3: DEVICE CONFIGURATION WORD 3
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R/P R/P r-1 r-1 r-1 R/P R/P R/P
31:24
FVBUSONIO FUSBIDIO — — — FCANIO(1) FETHIO(2) FMIIEN(2)
r-1 r-1 r-1 r-1 r-1 R/P R/P R/P
23:16
— — — — — FSRSSEL<2:0>
R/P R/P R/P R/P R/P R/P R/P R/P
15:8
USERID<15:8>
R/P R/P R/P R/P R/P R/P R/P R/P
7:0
USERID<7:0>

Legend: r = Reserved bit P = Programmable bit

R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31 FVBUSONIO: USB VBUSON Selection bit

1 = VBUSON pin is controlled by the USB module
0 = VBUSON pin is controlled by the port function
bit 30 FUSBIDIO: USB USBID Selection bit
1 = USBID pin is controlled by the USB module
0 = USBID pin is controlled by the port function
bit 29-27 Reserved: Write ‘1’
bit 26 FCANIO: CAN I/O Pin Selection bit(1)
1 = Default CAN I/O Pins
0 = Alternate CAN I/O Pins
bit 25 FETHIO: Ethernet I/O Pin Selection bit(2)
1 = Default Ethernet I/O Pins
0 = Alternate Ethernet I/O Pins
bit 24 FMIIEN: Ethernet MII Enable bit(2)
1 = MII is enabled
0 = RMII is enabled
bit 23-19 Reserved: Write ‘1’
bit 18-16 FSRSSEL<2:0>: SRS Select bits
111 = Assign Interrupt Priority 7 to a shadow register set
110 = Assign Interrupt Priority 6 to a shadow register set
•
•
•
001 = Assign Interrupt Priority 1 to a shadow register set
000 = All interrupt priorities are assigned to a shadow register set
bit 15-0 USERID<15:0>: User ID bits
This is a 16-bit value that is user-defined and is readable via ICSP™ and JTAG.

Note 1: This bit is Reserved and reads ‘1’ on PIC32MX664/675/695 devices.

2: This bit is Reserved and reads ‘1’ on PIC32MX534/564/575 devices.

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PIC32MX5XX/6XX/7XX
REGISTER 29-5: DEVID: DEVICE AND REVISION ID REGISTER
Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
R R R R R R R R
31:24 (1) (1)
VER<3:0> DEVID<27:24>
R R R R R R R R
23:16 (1)
DEVID<23:16>
R R R R R R R R
15:8 (1)
DEVID<15:8>
R R R R R R R R
7:0
DEVID<7:0>(1)

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-28 VER<3:0>: Revision Identifier bits(1)

bit 27-0 DEVID<27:0>: Device ID bits(1)

Note 1: See the “PIC32 Flash Programming Specification” (DS60001145) for a list of Revision and Device ID values.

REGISTER 29-6: DDPCON: DEBUG DATA PORT CONTROL REGISTER

Bit Bit Bit Bit Bit Bit Bit Bit Bit
Range 31/23/15/7 30/22/14/6 29/21/13/5 28/20/12/4 27/19/11/3 26/18/10/2 25/17/9/1 24/16/8/0
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
31:24
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
23:16
— — — — — — — —
U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0
15:8
— — — — — — — —
U-0 U-0 U-0 U-0 R/W-1 R/W-0 U-0 R/W-0
7:0
— — — — JTAGEN TROEN — TDOEN

Legend:
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown

bit 31-4 Unimplemented: Read as ‘0’

bit 3 JTAGEN: JTAG Port Enable bit
1 = Enable the JTAG port
0 = Disable the JTAG port
bit 2 TROEN: Trace Output Enable bit
1 = Enable the trace port
0 = Disable the trace port
bit 1 Unimplemented: Read as ‘0’
bit 0 TDOEN: TDO Enable for 2-Wire JTAG
1 = 2-wire JTAG protocol uses TDO
0 = 2-wire JTAG protocol does not use TDO

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 PIC32MX5XX/6XX/7XX
29.2 On-Chip Voltage Regulator 29.3 Programming and Diagnostics
All PIC32MX5XX/6XX/7XX devices’ core and digital PIC32MX5XX/6XX/7XX devices provide a complete
logic are designed to operate at a nominal 1.8V. To range of programming and diagnostic features that can
simplify system designs, most devices in the PIC32MX- increase the flexibility of any application using them.
5XX/6XX/7XX family incorporate an on-chip regulator These features allow system designers to include:
providing the required core logic voltage from VDD. • Simplified field programmability using two-wire
A low-ESR capacitor (such as tantalum) must be In-Circuit Serial Programming™ (ICSP™)
connected to the VCAP pin (see Figure 29-1). This interfaces
helps to maintain the stability of the regulator. The • Debugging using ICSP
recommended value for the filter capacitor is provided • Programming and debugging capabilities using
in Section 32.1 “DC Characteristics”. the EJTAG extension of JTAG
Note: It is important that the low-ESR capacitor • JTAG boundary scan testing for device and board
is placed as close as possible to the VCAP diagnostics
pin. PIC32 devices incorporate two programming and diag-
nostic modules, and a trace controller, that provide a
29.2.1 ON-CHIP REGULATOR AND POR range of functions to the application developer.
It takes a fixed delay for the on-chip regulator to generate
an output. During this time, designated as TPU, code FIGURE 29-2: PROGRAMMING,
execution is disabled. TPU is applied every time the
DEBUGGING, AND TRACE
device resumes operation after any power-down,
PORTS BLOCK DIAGRAM
including Sleep mode.

29.2.2 ON-CHIP REGULATOR AND BOR PGEC1

PIC32MX5XX/6XX/7XX devices also have a simple PGED1
brown-out capability. If the voltage supplied to the ICSP™
regulator is inadequate to maintain a regulated level, Controller
the regulator Reset circuitry will generate a Brown-out PGEC2
Reset (BOR). This event is captured by the BOR flag PGED2
bit (RCON<1>). The brown-out voltage levels are
specified in Section 32.1 “DC Characteristics”.
ICESEL

FIGURE 29-1: CONNECTIONS FOR THE TDI

ON-CHIP REGULATOR TDO JTAG Core
TCK Controller
3.3V(1)
TMS
PIC32
VDD
JTAGEN DEBUG<1:0>

VCAP TRCLK
CEFC(2) TRD0
VSS
(10 F typical) Instruction Trace
TRD1
Controller
TRD2 (see Note 1)

Note 1: These are typical operating voltages. Refer to TRD3

Section 32.1 “DC Characteristics” for the full
operating ranges of VDD. DEBUG<1:0>
2: It is important that the low-ESR capacitor is
placed as close as possible to the VCAP pin. Note 1: Trace is not available on 64-pin devices.

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PIC32MX5XX/6XX/7XX
NOTES:

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 PIC32MX5XX/6XX/7XX
30.0 INSTRUCTION SET
The PIC32MX5XX/6XX/7XX family instruction set
complies with the MIPS32 Release 2 instruction set
architecture. The PIC32 device family does not support
the following features:
• Core Extend instructions
• Coprocessor 1 instructions
• Coprocessor 2 instructions

Note: Refer to “MIPS32® Architecture for

Programmers Volume II: The MIPS32®
Instruction Set” at www.imgtec.com for
more information.

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PIC32MX5XX/6XX/7XX
NOTES:

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 PIC32MX5XX/6XX/7XX
31.0 DEVELOPMENT SUPPORT 31.1 MPLAB X Integrated Development
® ® Environment Software
The PIC microcontrollers (MCU) and dsPIC digital
signal controllers (DSC) are supported with a full range The MPLAB X IDE is a single, unified graphical user
of software and hardware development tools: interface for Microchip and third-party software, and
• Integrated Development Environment hardware development tool that runs on Windows®,
Linux and Mac OS® X. Based on the NetBeans IDE,
- MPLAB® X IDE Software
MPLAB X IDE is an entirely new IDE with a host of free
• Compilers/Assemblers/Linkers software components and plug-ins for high-
- MPLAB XC Compiler performance application development and debugging.
- MPASMTM Assembler Moving between tools and upgrading from software
- MPLINKTM Object Linker/ simulators to hardware debugging and programming
MPLIBTM Object Librarian tools is simple with the seamless user interface.
- MPLAB Assembler/Linker/Librarian for With complete project management, visual call graphs,
Various Device Families a configurable watch window and a feature-rich editor
• Simulators that includes code completion and context menus,
- MPLAB X SIM Software Simulator MPLAB X IDE is flexible and friendly enough for new
users. With the ability to support multiple tools on
• Emulators
multiple projects with simultaneous debugging, MPLAB
- MPLAB REAL ICE™ In-Circuit Emulator X IDE is also suitable for the needs of experienced
• In-Circuit Debuggers/Programmers users.
- MPLAB ICD 3 Feature-Rich Editor:
- PICkit™ 3
• Color syntax highlighting
• Device Programmers
• Smart code completion makes suggestions and
- MPLAB PM3 Device Programmer provides hints as you type
• Low-Cost Demonstration/Development Boards, • Automatic code formatting based on user-defined
Evaluation Kits and Starter Kits rules
• Third-party development tools • Live parsing
User-Friendly, Customizable Interface:
• Fully customizable interface: toolbars, toolbar
buttons, windows, window placement, etc.
• Call graph window
Project-Based Workspaces:
• Multiple projects
• Multiple tools
• Multiple configurations
• Simultaneous debugging sessions
File History and Bug Tracking:
• Local file history feature
• Built-in support for Bugzilla issue tracker

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PIC32MX5XX/6XX/7XX
31.2 MPLAB XC Compilers 31.4 MPLINK Object Linker/
The MPLAB XC Compilers are complete ANSI C
MPLIB Object Librarian
compilers for all of Microchip’s 8, 16, and 32-bit MCU The MPLINK Object Linker combines relocatable
and DSC devices. These compilers provide powerful objects created by the MPASM Assembler. It can link
integration capabilities, superior code optimization and relocatable objects from precompiled libraries, using
ease of use. MPLAB XC Compilers run on Windows, directives from a linker script.
Linux or MAC OS X.
The MPLIB Object Librarian manages the creation and
For easy source level debugging, the compilers provide modification of library files of precompiled code. When
debug information that is optimized to the MPLAB X a routine from a library is called from a source file, only
IDE. the modules that contain that routine will be linked in
The free MPLAB XC Compiler editions support all with the application. This allows large libraries to be
devices and commands, with no time or memory used efficiently in many different applications.
restrictions, and offer sufficient code optimization for The object linker/library features include:
most applications.
• Efficient linking of single libraries instead of many
MPLAB XC Compilers include an assembler, linker and smaller files
utilities. The assembler generates relocatable object • Enhanced code maintainability by grouping
files that can then be archived or linked with other relo- related modules together
catable object files and archives to create an execut-
• Flexible creation of libraries with easy module
able file. MPLAB XC Compiler uses the assembler to
listing, replacement, deletion and extraction
produce its object file. Notable features of the assem-
bler include:
31.5 MPLAB Assembler, Linker and
• Support for the entire device instruction set
Librarian for Various Device
• Support for fixed-point and floating-point data
Families
• Command-line interface
• Rich directive set MPLAB Assembler produces relocatable machine
• Flexible macro language code from symbolic assembly language for PIC24,
PIC32 and dsPIC DSC devices. MPLAB XC Compiler
• MPLAB X IDE compatibility
uses the assembler to produce its object file. The
assembler generates relocatable object files that can
31.3 MPASM Assembler then be archived or linked with other relocatable object
The MPASM Assembler is a full-featured, universal files and archives to create an executable file. Notable
macro assembler for PIC10/12/16/18 MCUs. features of the assembler include:

The MPASM Assembler generates relocatable object • Support for the entire device instruction set
files for the MPLINK Object Linker, Intel® standard HEX • Support for fixed-point and floating-point data
files, MAP files to detail memory usage and symbol • Command-line interface
reference, absolute LST files that contain source lines • Rich directive set
and generated machine code, and COFF files for • Flexible macro language
debugging.
• MPLAB X IDE compatibility
The MPASM Assembler features include:
• Integration into MPLAB X IDE projects
• User-defined macros to streamline
assembly code
• Conditional assembly for multipurpose
source files
• Directives that allow complete control over the
assembly process

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 PIC32MX5XX/6XX/7XX
31.6 MPLAB X SIM Software Simulator 31.8 MPLAB ICD 3 In-Circuit Debugger
The MPLAB X SIM Software Simulator allows code
System
development in a PC-hosted environment by simulat- The MPLAB ICD 3 In-Circuit Debugger System is
ing the PIC MCUs and dsPIC DSCs on an instruction Microchip’s most cost-effective, high-speed hardware
level. On any given instruction, the data areas can be debugger/programmer for Microchip Flash DSC and
examined or modified and stimuli can be applied from MCU devices. It debugs and programs PIC Flash
a comprehensive stimulus controller. Registers can be microcontrollers and dsPIC DSCs with the powerful,
logged to files for further run-time analysis. The trace yet easy-to-use graphical user interface of the MPLAB
buffer and logic analyzer display extend the power of IDE.
the simulator to record and track program execution,
The MPLAB ICD 3 In-Circuit Debugger probe is
actions on I/O, most peripherals and internal registers.
connected to the design engineer’s PC using a high-
The MPLAB X SIM Software Simulator fully supports speed USB 2.0 interface and is connected to the target
symbolic debugging using the MPLAB XC Compilers, with a connector compatible with the MPLAB ICD 2 or
and the MPASM and MPLAB Assemblers. The soft- MPLAB REAL ICE systems (RJ-11). MPLAB ICD 3
ware simulator offers the flexibility to develop and supports all MPLAB ICD 2 headers.
debug code outside of the hardware laboratory envi-
ronment, making it an excellent, economical software 31.9 PICkit 3 In-Circuit Debugger/
development tool.
Programmer
31.7 MPLAB REAL ICE In-Circuit The MPLAB PICkit 3 allows debugging and program-
Emulator System ming of PIC and dsPIC Flash microcontrollers at a most
affordable price point using the powerful graphical user
The MPLAB REAL ICE In-Circuit Emulator System is interface of the MPLAB IDE. The MPLAB PICkit 3 is
Microchip’s next generation high-speed emulator for connected to the design engineer’s PC using a full-
Microchip Flash DSC and MCU devices. It debugs and speed USB interface and can be connected to the tar-
programs all 8, 16 and 32-bit MCU, and DSC devices get via a Microchip debug (RJ-11) connector (compati-
with the easy-to-use, powerful graphical user interface of ble with MPLAB ICD 3 and MPLAB REAL ICE). The
the MPLAB X IDE. connector uses two device I/O pins and the Reset line
The emulator is connected to the design engineer’s to implement in-circuit debugging and In-Circuit Serial
PC using a high-speed USB 2.0 interface and is Programming™ (ICSP™).
connected to the target with either a connector
compatible with in-circuit debugger systems (RJ-11) 31.10 MPLAB PM3 Device Programmer
or with the new high-speed, noise tolerant, Low-
Voltage Differential Signal (LVDS) interconnection The MPLAB PM3 Device Programmer is a universal,
(CAT5). CE compliant device programmer with programmable
voltage verification at VDDMIN and VDDMAX for
The emulator is field upgradable through future firmware maximum reliability. It features a large LCD display
downloads in MPLAB X IDE. MPLAB REAL ICE offers (128 x 64) for menus and error messages, and a mod-
significant advantages over competitive emulators ular, detachable socket assembly to support various
including full-speed emulation, run-time variable package types. The ICSP cable assembly is included
watches, trace analysis, complex breakpoints, logic as a standard item. In Stand-Alone mode, the MPLAB
probes, a ruggedized probe interface and long (up to PM3 Device Programmer can read, verify and program
three meters) interconnection cables. PIC devices without a PC connection. It can also set
code protection in this mode. The MPLAB PM3
connects to the host PC via an RS-232 or USB cable.
The MPLAB PM3 has high-speed communications and
optimized algorithms for quick programming of large
memory devices, and incorporates an MMC card for file
storage and data applications.

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PIC32MX5XX/6XX/7XX
31.11 Demonstration/Development 31.12 Third-Party Development Tools
Boards, Evaluation Kits, and Microchip also offers a great collection of tools from
Starter Kits third-party vendors. These tools are carefully selected
A wide variety of demonstration, development and to offer good value and unique functionality.
evaluation boards for various PIC MCUs and dsPIC • Device Programmers and Gang Programmers
DSCs allows quick application development on fully from companies, such as SoftLog and CCS
functional systems. Most boards include prototyping • Software Tools from companies, such as Gimpel
areas for adding custom circuitry and provide applica- and Trace Systems
tion firmware and source code for examination and • Protocol Analyzers from companies, such as
modification. Saleae and Total Phase
The boards support a variety of features, including LEDs, • Demonstration Boards from companies, such as
temperature sensors, switches, speakers, RS-232 MikroElektronika, Digilent® and Olimex
interfaces, LCD displays, potentiometers and additional • Embedded Ethernet Solutions from companies,
EEPROM memory. such as EZ Web Lynx, WIZnet and IPLogika®
The demonstration and development boards can be
used in teaching environments, for prototyping custom
circuits and for learning about various microcontroller
applications.
In addition to the PICDEM™ and dsPICDEM™
demonstration/development board series of circuits,
Microchip has a line of evaluation kits and demonstra-
tion software for analog filter design, KEELOQ® security
ICs, CAN, IrDA®, PowerSmart battery management,
SEEVAL® evaluation system, Sigma-Delta ADC, flow
rate sensing, plus many more.
Also available are starter kits that contain everything
needed to experience the specified device. This usually
includes a single application and debug capability, all
on one board.
Check the Microchip web page (www.microchip.com)
for the complete list of demonstration, development
and evaluation kits.

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 PIC32MX5XX/6XX/7XX
32.0 ELECTRICAL CHARACTERISTICS
This section provides an overview of the PIC32MX5XX/6XX/7XX electrical characteristics. Additional information will be
provided in future revisions of this document as it becomes available.
Absolute maximum ratings for the PIC32MX5XX/6XX/7XX devices are listed below. Exposure to these maximum rating
conditions for extended periods may affect device reliability. Functional operation of the device at these or any other
conditions, above the parameters indicated in the operation listings of this specification, is not implied.

Absolute Maximum Ratings

(See Note 1)
Ambient temperature under bias............................................................................................................ .-40°C to +105°C
Storage temperature .............................................................................................................................. -65°C to +150°C
Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V
Voltage on any pin that is not 5V tolerant, with respect to VSS (Note 3)......................................... -0.3V to (VDD + 0.3V)
Voltage on any 5V tolerant pin with respect to VSS when VDD  2.3V (Note 3)........................................ -0.3V to +5.5V
Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V (Note 3)........................................ -0.3V to +3.6V
Voltage on VBUS with respect to VSS ....................................................................................................... -0.3V to +5.5V
Maximum current out of VSS pin(s) .......................................................................................................................300 mA
Maximum current into VDD pin(s) (Note 2)............................................................................................................300 mA
Maximum output current sunk by any I/O pin..........................................................................................................25 mA
Maximum output current sourced by any I/O pin ....................................................................................................25 mA
Maximum current sunk by all ports .......................................................................................................................200 mA
Maximum current sourced by all ports (Note 2)....................................................................................................200 mA

Note 1: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of the device at those or any other conditions,
above those indicated in the operation listings of this specification, is not implied. Exposure to maximum
rating conditions for extended periods may affect device reliability.
2: Maximum allowable current is a function of device maximum power dissipation (see Table 32-2).
3: See the “Device Pin Tables” section for the 5V tolerant pins.

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PIC32MX5XX/6XX/7XX
32.1 DC Characteristics

TABLE 32-1: OPERATING MIPS VS. VOLTAGE

VDD Range Temp. Range Max. Frequency
Characteristic
(in Volts)(1) (in °C) PIC32MX5XX/6XX/7XX
DC5 2.3-3.6V -40°C to +85°C 80 MHz
DC5b 2.3-3.6V -40°C to +105°C 80 MHz
Note 1: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
parameter BO10 in Table 32-10 for BOR values.

TABLE 32-2: THERMAL OPERATING CONDITIONS

Rating Symbol Min. Typical Max. Unit
Industrial Temperature Devices
Operating Junction Temperature Range TJ -40 — +125 °C
Operating Ambient Temperature Range TA -40 — +85 °C
V-Temp Temperature Devices
Operating Junction Temperature Range TJ -40 — +140 °C
Operating Ambient Temperature Range TA -40 — +105 °C
Power Dissipation:
Internal Chip Power Dissipation:
PINT = VDD x (IDD – S IOH) PD PINT + PI/O W
I/O Pin Power Dissipation:
I/O = S (({VDD – VOH} x IOH) + S (VOL x IOL))
Maximum Allowed Power Dissipation PDMAX (TJ – TA)/JA W

TABLE 32-3: THERMAL PACKAGING CHARACTERISTICS

See
Characteristics Symbol Typical Max. Unit
Note
Package Thermal Resistance, 121-Pin TFBGA (10x10x1.1 mm) JA 40 — °C/W 1
Package Thermal Resistance, 100-Pin TQFP (14x14x1 mm) JA 43 — °C/W 1
Package Thermal Resistance, 100-Pin TQFP (12x12x1 mm) JA 43 — °C/W 1
Package Thermal Resistance, 64-Pin TQFP (10x10x1 mm) JA 47 — °C/W 1
Package Thermal Resistance, 64-Pin QFN (9x9x0.9 mm) JA 28 — °C/W 1
Package Thermal Resistance, 124-Pin VTLA (9x9x0.9 mm) JA 21 — °C/W 1
Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations.

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 PIC32MX5XX/6XX/7XX
TABLE 32-4: DC TEMPERATURE AND VOLTAGE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical Max. Units Conditions
No.
Operating Voltage
DC10 VDD Supply Voltage 2.3 — 3.6 V —
DC12 VDR RAM Data Retention Voltage(1) 1.75 — — V —
DC16 VPOR VDD Start Voltage to Ensure 1.75 — 2.1 V —
Internal Power-on Reset Signal
DC17 SVDD VDD Rise Rate to Ensure 0.00005 — 0.115 V/s —
Internal Power-on Reset Signal
Note 1: This is the limit to which VDD can be lowered without losing RAM data.
2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN. Refer to
parameter BO10 in Table 32-10 for BOR values.

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PIC32MX5XX/6XX/7XX
TABLE 32-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Typical(3) Max. Units Conditions
No.
Operating Current (IDD)(1,2,4) for PIC32MX575/675/695/775/795 Family Devices
-40ºC,
DC20 6 9 +25ºC,
Code executing from Flash +85ºC
mA — 4 MHz
DC20b 7 10 +105ºC
DC20a 4 — Code executing from SRAM —
DC21 37 40 Code executing from Flash
mA — — 25 MHz
DC21a 25 — Code executing from SRAM
DC22 64 70 Code executing from Flash
mA — — 60 MHz
DC22a 61 — Code executing from SRAM
-40ºC,
DC23 85 98 +25ºC,
Code executing from Flash +85ºC
mA — 80 MHz
DC23b 90 120 +105ºC
DC23a 85 — Code executing from SRAM —
DC25a 125 150 µA — +25°C 3.3V LPRC (31 kHz)
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.

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 PIC32MX5XX/6XX/7XX
TABLE 32-5: DC CHARACTERISTICS: OPERATING CURRENT (IDD) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Typical(3) Max. Units Conditions
No.
Operating Current (IDD)(1,2) for PIC32MX534/564/664/764 Family Devices
-40ºC,
DC20c 6 9 +25ºC,
Code executing from Flash +85ºC
mA — 4 MHz
DC20d 7 10 +105ºC
DC20e 2 — Code executing from SRAM —
DC21b 19 32 Code executing from Flash 25 MHz
mA — —
DC21c 14 — Code executing from SRAM (Note 4)
DC22b 31 50 Code executing from Flash 60 MHz
mA — —
DC22c 29 — Code executing from SRAM (Note 4)
-40ºC,
DC23c 39 65 +25ºC,
Code executing from Flash +85ºC
mA — 80 MHz
DC23d 49 70 +105ºC
DC23e 39 — Code executing from SRAM —
LPRC (31 kHz)
DC25b 100 150 µA — +25°C 3.3V
(Note 4)
Note 1: A device’s IDD supply current is mainly a function of the operating voltage and frequency. Other factors,
such as PBCLK (Peripheral Bus Clock) frequency, number of peripheral modules enabled, internal code
execution pattern, execution from Program Flash memory vs. SRAM, I/O pin loading and switching rate,
oscillator type, as well as temperature, can have an impact on the current consumption.
2: The test conditions for IDD measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU, program Flash, and SRAM data memory are operational, program Flash memory Wait
states = 111, Program Cache and Prefetch are disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• CPU executing while(1) statement from Flash
• RTCC and JTAG are disabled
3: Data in “Typical” column is at 3.3V, 25°C at specified operating frequency unless otherwise stated.
Parameters are for design guidance only and are not tested.
4: All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.

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PIC32MX5XX/6XX/7XX
TABLE 32-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Parameter
Typical(2) Max. Units Conditions
No.
Idle Current (IIDLE)(1,3) for PIC32MX575/675/695/775/795 Family Devices
DC30 4.5 6.5 -40ºC, +25ºC, +85ºC
mA — 4 MHz
DC30b 5 7 +105°C
DC31 13 15 mA -40ºC, +25ºC, +85ºC — 25 MHz
DC32 28 30 mA -40ºC, +25ºC, +85ºC — 60 MHz
DC33 36 42 mA -40ºC, +25ºC, +85ºC
— 80 MHz
DC33b 39 45 mA +105°C
DC34 40 -40°C
DC34a 75 +25°C
— µA 2.3V
DC34b 800 +85°C
DC34c 1000 +105°C
DC35 35 -40°C
DC35a 65 +25°C
— µA 3.3V LPRC (31 kHz)
DC35b 600 +85°C
DC35c 800 +105°C
DC36 43 -40°C
DC36a 106 +25°C
— µA 3.6V
DC36b 800 +85°C
DC36c 1000 +105°C
Note 1: The test conditions for IIDLE current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode, program Flash memory Wait states = 111, Program Cache and Prefetch are dis-
abled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: This parameter is characterized, but not tested in manufacturing.
4: All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.

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 PIC32MX5XX/6XX/7XX
TABLE 32-6: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Parameter
Typical(2) Max. Units Conditions
No.
Idle Current (IIDLE)(1) for PIC32MX534/564/664/764 Family Devices
DC30a 1.5 5 -40ºC, +25ºC, +85ºC
— 4 MHz
DC30c 3.5 6 mA +105ºC
DC31a 7 11 -40ºC, +25ºC, +85ºC — 25 MHz (Note 3)
DC32a 13 20 mA -40ºC, +25ºC, +85ºC — 60 MHz (Note 3)
DC33a 17 25 -40ºC, +25ºC, +85ºC
mA — 80 MHz
DC33c 20 27 +105ºC
DC34c 40 -40°C
DC34d 75 +25°C
— µA 2.3V
DC34e 800 +85°C
DC34f 1000 +105ºC
DC35c 30 -40°C
DC35d 55 +25°C LPRC (31 kHz)
— µA 3.3V
DC35e 230 +85°C (Note 3)
DC35f 800 +105ºC
DC36c 43 -40°C
DC36d 106 +25°C
— µA 3.6V
DC36e 800 +85°C
DC36f 1000 +105ºC
Note 1: The test conditions for IIDLE current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Idle mode, program Flash memory Wait states = 111, Program Cache and Prefetch are dis-
abled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: This parameter is characterized, but not tested in manufacturing.
4: All parameters are characterized, but only those parameters listed for 4 MHz and 80 MHz are tested at
3.3V in manufacturing.

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PIC32MX5XX/6XX/7XX
TABLE 32-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Typical(2) Max. Units Conditions
No.
Power-Down Current (IPD)(1) for PIC32MX575/675/695/775/795 Family Devices
DC40 10 40 -40°C
DC40a 36 100 +25°C
2.3V Base Power-Down Current (Note 6)
DC40b 400 720 +85°C
DC40h 900 1800 +105°C
DC40c 41 120 +25°C 3.3V Base Power-Down Current
A
DC40d 22 80 -40°C
DC40e 42 120 +25°C
DC40g 315 400(5) +70°C 3.6V Base Power-Down Current (Note 6)
DC40f 410 800 +85°C
DC40i 1000 2000 +105°C
Module Differential Current for PIC32MX575/675/695/775/795 Family Devices
DC41 — 10 2.3V Watchdog Timer Current: IWDT (Notes 3,6)
DC41a 5 — A — 3.3V Watchdog Timer Current: IWDT (Note 3)
DC41b — 20 3.6V Watchdog Timer Current: IWDT (Note 3,6)
DC42 — 40 2.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3,6)
DC42a 23 — A — 3.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
DC42b — 50 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3,6)
DC43 — 1300 2.5V ADC: IADC (Notes 3,4,6)
DC43a 1100 — A — 3.3V ADC: IADC (Notes 3,4)
DC43b — 1300 3.6V ADC: IADC (Notes 3,4,6)
Note 1: The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are
disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.
6: This parameter is characterized, but not tested in manufacturing.

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 PIC32MX5XX/6XX/7XX
TABLE 32-7: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Typical(2) Max. Units Conditions
No.
Power-Down Current (IPD)(1) for PIC32MX534/564/664/764 Family Devices
DC40g 12 40 -40°C
DC40h 20 120 +25°C
2.3V Base Power-Down Current (Note 6)
DC40i 210 600 +85°C
DC40o 400 1000 +105°C
DC40j 20 120 +25°C 3.3V Base Power-Down Current
A
DC40k 15 80 -40°C
DC40l 20 120 +25°C
DC40m 113 350(5) +70°C 3.6V Base Power-Down Current
DC40n 220 650 +85°C
DC40p 500 1000 +105°C
Module Differential Current for PIC32MX534/564/664/764 Family Devices
DC41c — 10 2.5V Watchdog Timer Current: IWDT (Notes 3,6)
DC41d 5 — A — 3.3V Watchdog Timer Current: IWDT (Note 3)
DC41e — 20 3.6V Watchdog Timer Current: IWDT (Note 3)
DC42c — 40 2.5V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Notes 3,6)
DC42d 23 — A — 3.3V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
DC42e — 50 3.6V RTCC + Timer1 w/32 kHz Crystal: IRTCC (Note 3)
DC43c — 1300 2.5V ADC: IADC (Notes 3,4,6)
DC43d 1100 — A — 3.3V ADC: IADC (Notes 3,4)
DC43e — 1300 3.6V ADC: IADC (Notes 3,4)
Note 1: The test conditions for IPD current measurements are as follows:
• Oscillator mode is EC (for 8 MHz and below) and EC+PLL (for above 8 MHz) with OSC1 driven by
external square wave from rail-to-rail, (OSC1 input clock input over/undershoot < 100 mV required)
• OSC2/CLKO is configured as an I/O input pin
• USB PLL oscillator is disabled if the USB module is implemented, PBCLK divisor = 1:8
• CPU is in Sleep mode, program Flash memory Wait states = 111, Program Cache and Prefetch are
disabled and SRAM data memory Wait states = 1
• No peripheral modules are operating, (ON bit = 0)
• WDT, Clock Switching, Fail-Safe Clock Monitor, and Secondary Oscillator are disabled
• All I/O pins are configured as inputs and pulled to VSS
• MCLR = VDD
• RTCC and JTAG are disabled
2: Data in the “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: The  current is the additional current consumed when the module is enabled. This current should be
added to the base IPD current.
4: Test conditions for ADC module differential current are as follows: Internal ADC RC oscillator enabled.
5: Data is characterized at +70°C and not tested. Parameter is for design guidance only.
6: This parameter is characterized, but not tested in manufacturing.

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PIC32MX5XX/6XX/7XX
TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
No.
VIL Input Low Voltage
DI10 I/O Pins:
with TTL Buffer VSS — 0.15 VDD V
with Schmitt Trigger Buffer VSS — 0.2 VDD V
DI15 MCLR(2) VSS — 0.2 VDD V
DI16 OSC1 (XT mode) VSS — 0.2 VDD V (Note 4)
DI17 OSC1 (HS mode) VSS — 0.2 VDD V (Note 4)
DI18 SDAx, SCLx VSS — 0.3 VDD V SMBus disabled
(Note 4)
DI19 SDAx, SCLx VSS — 0.8 V SMBus enabled
(Note 4)
VIH Input High Voltage
DI20 I/O Pins not 5V-tolerant(5) 0.65 VDD — VDD V (Note 4,6)
I/O Pins 5V-tolerant with 0.25 VDD + 0.8V — 5.5 V (Note 4,6)
PMP(5)
I/O Pins 5V-tolerant(5) 0.65 VDD — 5.5 V
DI28 SDAx, SCLx 0.65 VDD — 5.5 V SMBus disabled
(Note 4,6)
DI29 SDAx, SCLx 2.1 — 5.5 V SMBus enabled,
2.3V  VPIN  5.5
(Note 4,6)
DI30 ICNPU Change Notification — — -50 A VDD = 3.3V, VPIN = VSS
Pull-up Current (Note 3,6)
DI31 ICNPD Change Notification — 50 — µA VDD = 3.3V, VPIN = VDD
Pull-down Current(4)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Device Pin Tables” section for the 5V-tolerant pins.
6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-select-
able pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pull-
ups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the
external load does not exceed the maximum value of ICNPU.
7: VIL source < (VSS - 0.3). Characterized but not tested.
8: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD +
0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the speci-
fied limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS).
RS = Resistance between input source voltage and device pin. If (VSS - 0.3)  VSOURCE  (VDD + 0.3), injec-
tion current = 0.

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 PIC32MX5XX/6XX/7XX
TABLE 32-8: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
No.
(3)
IIL Input Leakage Current
DI50 I/O Ports — — +1 A VSS  VPIN  VDD,
Pin at high-impedance
DI51 Analog Input Pins — — +1 A VSS  VPIN  VDD,
Pin at high-impedance
DI55 MCLR(2) — — +1 A VSS VPIN VDD
DI56 OSC1 — — +1 A VSS VPIN VDD,
XT and HS modes
This parameter applies
to all pins, with the
Input Low Injection (7,10) exception of RB10.
DI60a IICL 0 — -5 mA
Current Maximum IICH current
for this exception is
0 mA.
This parameter applies
to all pins, with the
exception of all 5V toler-
Input High Injection
DI60b IICH 0 — +5(8,9,10) mA ant pins, SOSCI, and
Current
RB10. Maximum IICH
current for these
exceptions is 0 mA.
DI60c IICT Total Input Injection -20(11) — +20(11) mA Absolute instantaneous
Current (sum of all I/O sum of all ± input
and control pins) injection currents from
all I/O pins
( | IICL + | IICH | )  IICT
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
2: The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified
levels represent normal operating conditions. Higher leakage current may be measured at different input
voltages.
3: Negative current is defined as current sourced by the pin.
4: This parameter is characterized, but not tested in manufacturing.
5: See the “Device Pin Tables” section for the 5V-tolerant pins.
6: The VIH specification is only in relation to externally applied inputs and not with respect to the user-select-
able pull-ups. Externally applied high impedance or open drain input signals utilizing the PIC32 internal pull-
ups are guaranteed to be recognized as a logic “high” internally to the PIC32 device, provided that the
external load does not exceed the maximum value of ICNPU.
7: VIL source < (VSS - 0.3). Characterized but not tested.
8: VIH source > (VDD + 0.3) for non-5V tolerant pins only.
9: Digital 5V tolerant pins do not have an internal high side diode to VDD, and therefore, cannot tolerate any
“positive” input injection current.
10: Injection currents > | 0 | can affect the ADC results by approximately 4 to 6 counts (i.e., VIH Source > (VDD +
0.3) or VIL source < (VSS - 0.3)).
11: Any number and/or combination of I/O pins not excluded under IICL or IICH conditions are permitted pro-
vided the “absolute instantaneous” sum of the input injection currents from all pins do not exceed the speci-
fied limit. If Note 7, IICL = (((Vss - 0.3) - VIL source) / Rs). If Note 8, IICH = ((IICH source - (VDD + 0.3)) / RS).
RS = Resistance between input source voltage and device pin. If (VSS - 0.3)  VSOURCE  (VDD + 0.3), injec-
tion current = 0.

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PIC32MX5XX/6XX/7XX
TABLE 32-9: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-temp
Param. Symbol Characteristic Min. Typ. Max. Units Conditions
Output Low Voltage
I/O Pins:
4x Sink Driver Pins - All I/O — — 0.4 V IOL  10 mA, VDD = 3.3V
output pins not defined as 8x
DO10 VOL Sink Driver pins
Output Low Voltage
I/O Pins: — — 0.4 V IOL  15 mA, VDD = 3.3V
8x Sink Driver Pins - RC15
Output High Voltage
I/O Pins:
4x Source Driver Pins - All I/O 2.4 — — V IOH  -10 mA, VDD = 3.3V
output pins not defined as 8x
DO20 VOH
Source Driver pins
Output High Voltage
I/O Pins: 2.4 — — V IOH  -15 mA, VDD = 3.3V
8x Source Driver Pins - RC15
Output High Voltage 1.5(1) — — IOH  -14 mA, VDD = 3.3V
I/O Pins:
4x Source Driver Pins - All I/O 2.0(1) — — V IOH  -12 mA, VDD = 3.3V
output pins not defined as 8x
Sink Driver pins 3.0(1) — — IOH  -7 mA, VDD = 3.3V
DO20A VOH1
Output High Voltage 1.5(1) — — IOH  -22 mA, VDD = 3.3V
I/O Pins:
8x Source Driver Pins - RC15 2.0(1) — — V IOH  -18 mA, VDD = 3.3V

3.0(1) — — IOH  -10 mA, VDD = 3.3V

Note 1: Parameters are characterized, but not tested.
2: This driver pin only applies to devices with less than 64 pins.
3: This driver pin only applies to devices with 64 pins.

TABLE 32-10: ELECTRICAL CHARACTERISTICS: BOR

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min.(1) Typical Max. Units Conditions
No.
BO10 VBOR BOR Event on VDD transition 2.0 — 2.3 V —
high-to-low (Note 2)
Note 1: Parameters are for design guidance only and are not tested in manufacturing.
2: Overall functional device operation at VBORMIN < VDD < VDDMIN is tested, but not characterized. All device
Analog modules, such as ADC, etc., will function, but with degraded performance below VDDMIN.

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 PIC32MX5XX/6XX/7XX

TABLE 32-11: DC CHARACTERISTICS: PROGRAM MEMORY(3)

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typ.(1) Max. Units Conditions
No.
D130 EP Cell Endurance 1000 — — E/W —
D130a EP Cell Endurance 20,000 — — E/W See Note 5
D131 VPR VDD for Read 2.3 — 3.6 V —
D132 VPEW VDD for Erase or Write 3.0 — 3.6 V —
D132a VPEW VDD for Erase or Write 2.3 — 3.6 V See Note 5
D134 TRETD Characteristic Retention 20 — — Year Provided no other specifications
are violated
D135 IDDP Supply Current during — 10 — mA —
Programming
D138 TWW Word Write Cycle Time(4) — 411 — FRC Cycles —
D136 TRW Row Write Cycle Time(2,4) — 26067 — FRC Cycles —
D137 TPE Page Erase Cycle Time(4) — 201060 — FRC Cycles —
D139 TCE Chip Erase Cycle Time(4) — 804652 — FRC Cycles —
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: The minimum SYSCLK for row programming is 4 MHz. Care should be taken to minimize bus activities
during row programming, such as suspending any memory-to-memory DMA operations. If heavy bus loads
are expected, selecting Bus Matrix Arbitration mode 2 (rotating priority) may be necessary. The default
Arbitration mode is mode 1 (CPU has lowest priority).
3: Refer to “PIC32 Flash Programming Specification” (DS60001145) for operating conditions during
programming and erase cycles.
4: Translating this value to seconds depends on the FRC accuracy (see Table 32-19) and the FRC tuning val-
ues (see Register 8-2).
5: This parameter only applies to PIC32MX534/564/664/764 devices.

TABLE 32-12: PROGRAM FLASH MEMORY WAIT STATE CHARACTERISTICS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Required Flash Wait States SYSCLK Units Comments
0 Wait State 0 to 30 MHz —
1 Wait State 31 to 60
2 Wait States 61 to 80

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PIC32MX5XX/6XX/7XX
TABLE 32-13: COMPARATOR SPECIFICATIONS
Standard Operating Conditions (see Note 3): 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical Max. Units Comments
No.
D300 VIOFF Input Offset Voltage — ±7.5 ±25 mV AVDD = VDD,
AVSS = VSS
D301 VICM Input Common Mode Voltage 0 — VDD V AVDD = VDD,
AVSS = VSS
(Note 2)
D302 CMRR Common Mode Rejection Ratio 55 — — dB Max VICM = (VDD - 1)V
(Note 2)
D303 TRESP Response Time — 150 400 ns AVDD = VDD,
AVSS = VSS
(Notes 1, 2)
D304 ON2OV Comparator Enabled to Output — — 10 s Comparator module is
Valid configured before setting
the comparator ON bit
(Note 2)
D305 IVREF Internal Voltage Reference 0.57 0.6 0.63 V For devices without
BGSEL<1:0>
1.14 1.2 1.26 V BGSEL<1:0> = 00
0.57 0.6 0.63 V BGSEL<1:0> = 01
Note 1: Response time measured with one comparator input at (VDD – 1.5)/2, while the other input transitions
from VSS to VDD.
2: These parameters are characterized but not tested.
3: The Comparator module is functional at VBORMIN < VDD < VDDMIN, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.

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 PIC32MX5XX/6XX/7XX
TABLE 32-14: VOLTAGE REFERENCE SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical Max. Units Comments
No.
D312 TSET Internal 4-bit DAC — — 10 µs See Note 1
Comparator Reference
Settling time.
D313 DACREFH CVREF Input Voltage AVSS — AVDD V CVRSRC with CVRSS = 0
Reference Range VREF- — VREF+ V CVRSRC with CVRSS = 1
D314 DVREF CVREF Programmable 0 — 0.625 x V 0 to 0.625 DACREFH with
Output Range DACREFH DACREFH/24 step size
0.25 x — 0.719 x V 0.25 x DACREFH to 0.719
DACREFH DACREFH DACREFH with DACREFH/32
step size
D315 DACRES Resolution — — DACREFH/ CVRCON<CVRR> = 1
24
— — DACREFH/ CVRCON<CVRR> = 0
32
D316 DACACC Absolute Accuracy(2) — — 1/4 LSB DACREFH/24,
CVRCON<CVRR> = 1
— — 1/2 LSB DACREFH/32,
CVRCON<CVRR> = 0
Note 1: Settling time measured while CVRR = 1 and CVR<3:0> transitions from ‘0000’ to ‘1111’. This parameter
is characterized, but not tested in manufacturing.
2: These parameters are characterized but not tested.

TABLE 32-15: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
DC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical Max. Units Comments
No.
D321 CEFC External Filter Capacitor Value 8 10 — F Capacitor must be low series
resistance (1 ohm)
D322 TPWRT Power-up Timer Period — 64 — ms —

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PIC32MX5XX/6XX/7XX
32.2 AC Characteristics and Timing
Parameters
The information contained in this section defines
PIC32MX5XX/6XX/7XX AC characteristics and timing
parameters.

FIGURE 32-1: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS

Load Condition 1 – for all pins except OSC2 Load Condition 2 – for OSC2

VDD/2

RL Pin CL

VSS
CL
Pin RL = 464
CL = 50 pF for all pins
VSS 50 pF for OSC2 pin (EC mode)

TABLE 32-16: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
No.
DO50 Cosco OSC2 pin — — 15 pF In XT and HS modes when an
external crystal is used to drive
OSC1
DO56 CIO All I/O pins and OSC2 — — 50 pF In EC mode
DO58 CB SCLx, SDAx — — 400 pF In I2C mode
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.

FIGURE 32-2: EXTERNAL CLOCK TIMING

OS20 OS30 OS31

OSC1

OS30 OS31

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 PIC32MX5XX/6XX/7XX
TABLE 32-17: EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
No.
OS10 FOSC External CLKI Frequency DC — 50 MHz EC (Note 4)
(External clocks only allowed 4 — 50 MHz ECPLL (Note 3)
in EC and ECPLL modes)
OS11 Oscillator Crystal Frequency 3 — 10 MHz XT (Note 4)
OS12 4 — 10 MHz XTPLL
(Notes 3,4)
OS13 10 — 25 MHz HS (Note 4)
OS14 10 — 25 MHz HSPLL
(Notes 3,4)
OS15 32 32.768 100 kHz SOSC (Note 4)
OS20 TOSC TOSC = 1/FOSC = TCY(2) — — — — See parameter
OS10 for FOSC
value
OS30 TOSL, External Clock In (OSC1) 0.45 x TOSC — — ns EC (Note 4)
TOSH High or Low Time
OS31 TOSR, External Clock In (OSC1) — — 0.05 x TOSC ns EC (Note 4)
TOSF Rise or Fall Time
OS40 TOST Oscillator Start-up Timer Period — 1024 — TOSC (Note 4)
(Only applies to HS, HSPLL,
XT, XTPLL and SOSC Clock
Oscillator modes)
OS41 TFSCM Primary Clock Fail Safe — 2 — ms (Note 4)
Time-out Period
OS42 GM External Oscillator — 12 — mA/V VDD = 3.3V,
Transconductance (Primary TA = +25°C
Oscillator only) (Note 4)
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are characterized but are not
tested.
2: Instruction cycle period (TCY) equals the input oscillator time base period. All specified values are based on
characterization data for that particular oscillator type under standard operating conditions with the device
executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or
higher than expected current consumption. All devices are tested to operate at “min.” values with an
external clock applied to the OSC1/CLKI pin.
3: PLL input requirements: 4 MHZ  FPLLIN  5 MHZ (use PLL prescaler to reduce FOSC). This parameter is
characterized, but is only tested at 10 MHz at manufacturing.
4: This parameter is characterized, but not tested in manufacturing.

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PIC32MX5XX/6XX/7XX
TABLE 32-18: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.3V TO 3.6V)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
No.
OS50 FPLLI PLL Voltage Controlled 3.92 — 5 MHz ECPLL, HSPLL, XTPLL,
Oscillator (VCO) Input FRCPLL modes
Frequency Range
OS51 FSYS On-Chip VCO System 60 — 120 MHz —
Frequency
OS52 TLOCK PLL Start-up Time (Lock Time) — — 2 ms —
OS53 DCLK CLKO Stability(2) -0.25 — +0.25 % Measured over 100 ms
(Period Jitter or Cumulative) period
Note 1: These parameters are characterized, but not tested in manufacturing.
2: This jitter specification is based on clock-cycle by clock-cycle measurements. To get the effective jitter for
individual time-bases on communication clocks, use the following formula:
D CLK
EffectiveJitter = --------------------------------------------------------------
SYSCLK
----------------------------------------------------------
CommunicationClock

For example, if SYSCLK = 80 MHz and SPI bit rate = 20 MHz, the effective jitter is as follows:
D CLK D CLK
EffectiveJitter = -------------- = --------------
80 2
------
20

TABLE 32-19: INTERNAL FRC ACCURACY

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Characteristics Min. Typical Max. Units Conditions
No.
Internal FRC Accuracy @ 8.00 MHz(1) for PIC32MX575/675/695/775/795 Family Devices
F20a FRC -2 — +2 % —
Internal FRC Accuracy @ 8.00 MHz(1) for PIC32MX534/564/664/764 Family Devices
F20b FRC -0.9 — +0.9 % —
Note 1: Frequency calibrated at 25°C and 3.3V. The TUN bits can be used to compensate for temperature drift.

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 PIC32MX5XX/6XX/7XX
TABLE 32-20: INTERNAL RC ACCURACY
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Characteristics Min. Typical Max. Units Conditions
No.
LPRC @ 31.25 kHz(1)
F21 LPRC -15 — +15 % —
Note 1: Change of LPRC frequency as VDD changes.

FIGURE 32-3: I/O TIMING CHARACTERISTICS

I/O Pin
(Input)

DI35
DI40

I/O Pin
(Output)
DO31
DO32
Note: Refer to Figure 32-1 for load conditions.

TABLE 32-21: I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(2) Min. Typical(1) Max. Units Conditions
No.
DO31 TIOR Port Output Rise Time — 5 15 ns VDD < 2.5V
— 5 10 ns VDD > 2.5V
DO32 TIOF Port Output Fall Time — 5 15 ns VDD < 2.5V
— 5 10 ns VDD > 2.5V
DI35 TINP INTx Pin High or Low Time 10 — — ns —
DI40 TRBP CNx High or Low Time (input) 2 — — TSYSCLK —
Note 1: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated.
2: This parameter is characterized, but not tested in manufacturing.

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PIC32MX5XX/6XX/7XX
FIGURE 32-4: POWER-ON RESET TIMING CHARACTERISTICS

Internal Voltage Regulator Enabled

Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)

VDD

VPOR
(TSYSDLY)
SY02

Power-up Sequence
(Note 2)

CPU Starts Fetching Code

SY00
(TPU)
(Note 1)

Internal Voltage Regulator Enabled

Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC)
VDD

VPOR (TSYSDLY)
SY02

Power-up Sequence
(Note 2)

CPU Starts Fetching Code

SY00 OS40
(TPU) (TOST)
(Note 1)

Note 1: The power-up period will be extended if the power-up sequence completes before the device exits from BOR
(VDD < VDDMIN).
2: Includes interval voltage regulator stabilization delay.

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 PIC32MX5XX/6XX/7XX
FIGURE 32-5: EXTERNAL RESET TIMING CHARACTERISTICS
Clock Sources = (FRC, FRCDIV, FRCDIV16, FRCPLL, EC, ECPLL and LPRC)

MCLR

TMCLR
(SY20)

BOR

TBOR (TSYSDLY)
(SY30) SY02
Reset Sequence

CPU Starts Fetching Code

Clock Sources = (HS, HSPLL, XT, XTPLL and SOSC) (TSYSDLY)

SY02
Reset Sequence

CPU Starts Fetching Code

TOST
(OS40)

TABLE 32-22: RESETS TIMING

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions
No.
SY00 TPU Power-up Period — 400 600 s -40°C to +85°C
Internal Voltage Regulator Enabled
SY02 TSYSDLY System Delay Period: — 1 µs + — — -40°C to +85°C
Time Required to Reload Device 8 SYSCLK
Configuration Fuses plus SYSCLK cycles
Delay before First instruction is
Fetched.
SY20 TMCLR MCLR Pulse Width (low) — 2 — s -40°C to +85°C
SY30 TBOR BOR Pulse Width (low) — 1 — s -40°C to +85°C
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Characterized by design but not tested.

 2009-2019 Microchip Technology Inc. DS60001156K-page 375

PIC32MX5XX/6XX/7XX
FIGURE 32-6: TIMER1, 2, 3, 4, 5 EXTERNAL CLOCK TIMING CHARACTERISTICS

TxCK

Tx10 Tx11

Tx15 Tx20
OS60
TMRx

Note: Refer to Figure 32-1 for load conditions.

TABLE 32-23: TIMER1 EXTERNAL CLOCK TIMING REQUIREMENTS(1)

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(2) Min. Typical Max. Units Conditions
No.
TA10 TTXH TxCK Synchronous, [(12.5 ns or 1 TPB)/N] — — ns Must also meet
High Time with prescaler + 25 ns parameter TA15
Asynchronous, 10 — — ns —
with prescaler
TA11 TTXL TxCK Synchronous, [(12.5 ns or 1 TPB)/N] — — ns Must also meet
Low Time with prescaler + 25 ns parameter TA15
Asynchronous, 10 — — ns —
with prescaler
TA15 TTXP TxCK Synchronous, [(Greater of 25 ns or — — ns VDD > 2.7V
Input Period with prescaler 2 TPB)/N] + 30 ns
[(Greater of 25 ns or — — ns VDD < 2.7V
2 TPB)/N] + 50 ns
Asynchronous, 20 — — ns VDD > 2.7V
with prescaler (Note 3)
50 — — ns VDD < 2.7V
(Note 3)
OS60 FT1 SOSC1/T1CK Oscillator 32 — 100 kHz —
Input Frequency Range
(oscillator enabled by setting
TCS bit (T1CON<1>))
TA20 TCKEXTMRL Delay from External TxCK — — 1 TPB —
Clock Edge to Timer
Increment
Note 1: Timer1 is a Type A.
2: This parameter is characterized, but not tested in manufacturing.
3: N = Prescale Value (1, 8, 64, 256).

DS60001156K-page 376  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 32-24: TIMER2, 3, 4, 5 EXTERNAL CLOCK TIMING REQUIREMENTS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
TB10 TTXH TxCK Synchronous, with [(12.5 ns or 1 TPB)/N] — ns Must also meet N = prescale
High Time prescaler + 25 ns parameter value
TB15 (1, 2, 4, 8,
TB11 TTXL TxCK Synchronous, with [(12.5 ns or 1 TPB)/N] — ns Must also meet 16, 32, 64,
Low Time prescaler + 25 ns parameter 256)
TB15
TB15 TTXP TxCK Synchronous, with [(Greater of [(25 ns or — ns VDD > 2.7V
Input prescaler 2 TPB)/N] + 30 ns
Period [(Greater of [(25 ns or — ns VDD < 2.7V
2 TPB)/N] + 50 ns
TB20 TCKEXTMRL Delay from External TxCK — 1 TPB —
Clock Edge to Timer Increment
Note 1: These parameters are characterized, but not tested in manufacturing.

 2009-2019 Microchip Technology Inc. DS60001156K-page 377

PIC32MX5XX/6XX/7XX
FIGURE 32-7: INPUT CAPTURE (CAPx) TIMING CHARACTERISTICS
ICx

IC10 IC11

IC15

Note: Refer to Figure 32-1 for load conditions.

TABLE 32-25: INPUT CAPTURE MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Max. Units Conditions
No.
IC10 TCCL ICx Input Low Time [(12.5 ns or 1 TPB)/N] — ns Must also N = prescale
+ 25 ns meet value (1, 4, 16)
parameter
IC15.
IC11 TCCH ICx Input High Time [(12.5 ns or 1 TPB)/N] — ns Must also
+ 25 ns meet
parameter
IC15.
IC15 TCCP ICx Input Period [(25 ns or 2 TPB)/N] — ns —
+ 50 ns
Note 1: These parameters are characterized, but not tested in manufacturing.

FIGURE 32-8: OUTPUT COMPARE MODULE (OCx) TIMING CHARACTERISTICS

OCx
(Output Compare
or PWM mode) OC11 OC10

Note: Refer to Figure 32-1 for load conditions.

TABLE 32-26: OUTPUT COMPARE MODULE TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions
No.
OC10 TCCF OCx Output Fall Time — — — ns See parameter DO32
OC11 TCCR OCx Output Rise Time — — — ns See parameter DO31
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.

DS60001156K-page 378  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 32-9: OCx/PWM MODULE TIMING CHARACTERISTICS

OC20

OCFA/OCFB

OC15

OCx OCx is tri-stated

Note: Refer to Figure 32-1 for load conditions.

TABLE 32-27: SIMPLE OCx/PWM MODE TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param
Symbol Characteristics(1) Min Typical(2) Max Units Conditions
No.
OC15 TFD Fault Input to PWM I/O Change — — 50 ns —
OC20 TFLT Fault Input Pulse Width 50 — — ns —
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.

 2009-2019 Microchip Technology Inc. DS60001156K-page 379

PIC32MX5XX/6XX/7XX
FIGURE 32-10: SPIx MODULE MASTER MODE (CKE = 0) TIMING CHARACTERISTICS
SCKx
(CKP = 0)

SP11 SP10 SP21 SP20

SCKx
(CKP = 1)

SP35 SP20 SP21

SDOx MSb Bit 14 - - - - - -1 LSb

SP31 SP30

SDIx MSb In Bit 14 - - - -1 LSb In

SP40 SP41

Note: Refer to Figure 32-1 for load conditions.

TABLE 32-28: SPIx MASTER MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions
No.
SP10 TSCL SCKx Output Low Time(3) TSCK/2 — — ns —
SP11 TSCH SCKx Output High Time(3) TSCK/2 — — ns —
SP20 TSCF SCKx Output Fall Time(4) — — — ns See parameter DO32
SP21 TSCR SCKx Output Rise Time(4) — — — ns See parameter DO31
SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See parameter DO32
SP31 TDOR SDOx Data Output Rise — — — ns See parameter DO31
Time(4)
SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V
TSCL2DOV SCKx Edge — — ns VDD < 2.7V
20
SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns —
TDIV2SCL to SCKx Edge
SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns —
TSCL2DIL to SCKx Edge
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance
only and are not tested.
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.

DS60001156K-page 380  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 32-11: SPIx MODULE MASTER MODE (CKE = 1) TIMING CHARACTERISTICS
SP36
SCKX
(CKP = 0)

SP11 SP10 SP21 SP20

SCKX
(CKP = 1)
SP35
SP20 SP21

SDOX MSb Bit 14 - - - - - -1 LSb

SP30,SP31

SDIX MSb In Bit 14 - - - -1 LSb In

SP40 SP41

Note: Refer to Figure 32-1 for load conditions.

TABLE 32-29: SPIx MODULE MASTER MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions
No.
SP10 TSCL SCKx Output Low Time(3) TSCK/2 — — ns —
SP11 TSCH SCKx Output High Time(3) TSCK/2 — — ns —
SP20 TSCF SCKx Output Fall Time(4) — — — ns See parameter DO32
SP21 TSCR SCKx Output Rise Time(4) — — — ns See parameter DO31
SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See parameter DO32
SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See parameter DO31
SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V
TSCL2DOV SCKx Edge — — 20 ns VDD < 2.7V
SP36 TDOV2SC, SDOx Data Output Setup to 15 — — ns —
TDOV2SCL First SCKx Edge
SP40 TDIV2SCH, Setup Time of SDIx Data Input to 15 — — ns VDD > 2.7V
TDIV2SCL SCKx Edge 20 — — ns VDD < 2.7V
SP41 TSCH2DIL, Hold Time of SDIx Data Input 15 — — ns VDD > 2.7V
TSCL2DIL to SCKx Edge 20 — — ns VDD < 2.7V
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns. Therefore, the clock generated in Master mode must not
violate this specification.
4: Assumes 50 pF load on all SPIx pins.

 2009-2019 Microchip Technology Inc. DS60001156K-page 381

PIC32MX5XX/6XX/7XX
FIGURE 32-12: SPIx MODULE SLAVE MODE (CKE = 0) TIMING CHARACTERISTICS

SSX

SP50 SP52
SCKX
(CKP = 0)

SP71 SP70
SP73 SP72

SCKX
(CKP = 1)

SP35 SP72 SP73

SDOX MSb Bit 14 - - - - - -1 LSb

SP30,SP31 SP51

SDIX MSb In Bit 14 - - - -1 LSb In

SP40 SP41
Note: Refer to Figure 32-1 for load conditions.

TABLE 32-30: SPIx MODULE SLAVE MODE (CKE = 0) TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typ.(2) Max. Units Conditions
No.
SP70 TSCL SCKx Input Low Time(3) TSCK/2 — — ns —
SP71 TSCH SCKx Input High Time(3) TSCK/2 — — ns —
SP72 TSCF SCKx Input Fall Time — — — ns See parameter DO32
SP73 TSCR SCKx Input Rise Time — — — ns See parameter DO31
SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See parameter DO32
SP31 TDOR SDOx Data Output Rise Time(4) — — — ns See parameter DO31
SP35 TSCH2DOV, SDOx Data Output Valid after — — 15 ns VDD > 2.7V
TSCL2DOV SCKx Edge — — 20 ns VDD < 2.7V
SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns —
TDIV2SCL to SCKx Edge
SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns —
TSCL2DIL to SCKx Edge
SP50 TSSL2SCH, SSx  to SCKx  or SCKx Input 175 — — ns —
TSSL2SCL
SP51 TSSH2DOZ SSx  to SDOx Output 5 — 25 ns —
High-Impedance(3)
SP52 TSCH2SSH SSx after SCKx Edge TSCK + 20 — — ns —
TSCL2SSH
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.

DS60001156K-page 382  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 32-13: SPIx MODULE SLAVE MODE (CKE = 1) TIMING CHARACTERISTICS
SP60
SSx

SP50 SP52
SCKx
(CKP = 0)

SP71 SP70 SP73 SP72

SCKx
(CKP = 1)
SP35
SP72 SP73

SDOx MSb Bit 14 - - - - - -1 LSb

SP30,SP31 SP51

SDIx
SDI
MSb In Bit 14 - - - -1 LSb In
SP40 SP41

Note: Refer to Figure 32-1 for load conditions.

TABLE 32-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions
No.
SP70 TSCL SCKx Input Low Time(3) TSCK/2 — — ns —
SP71 TSCH SCKx Input High Time(3) TSCK/2 — — ns —
SP72 TSCF SCKx Input Fall Time — 5 10 ns —
SP73 TSCR SCKx Input Rise Time — 5 10 ns —
SP30 TDOF SDOx Data Output Fall Time(4) — — — ns See parameter DO32
SP31 TDOR (4)
SDOx Data Output Rise Time — — — ns See parameter DO31
SP35 TSCH2DOV, SDOx Data Output Valid after — — 20 ns VDD > 2.7V
TSCL2DOV SCKx Edge — — 30 ns VDD < 2.7V
SP40 TDIV2SCH, Setup Time of SDIx Data Input 10 — — ns —
TDIV2SCL to SCKx Edge
SP41 TSCH2DIL, Hold Time of SDIx Data Input 10 — — ns —
TSCL2DIL to SCKx Edge
SP50 TSSL2SCH, SSx  to SCKx  or SCKx  Input 175 — — ns —
TSSL2SCL
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.

 2009-2019 Microchip Technology Inc. DS60001156K-page 383

PIC32MX5XX/6XX/7XX
TABLE 32-31: SPIx MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical(2) Max. Units Conditions
No.
SP51 TSSH2DOZ SSx  to SDOX Output 5 — 25 ns —
High-Impedance(4)
SP52 TSCH2SSH SSx  after SCKx Edge TSCK + — — ns —
TSCL2SSH 20
SP60 TSSL2DOV SDOx Data Output Valid after — — 25 ns —
SSx Edge
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Data in “Typical” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.
3: The minimum clock period for SCKx is 40 ns.
4: Assumes 50 pF load on all SPIx pins.

DS60001156K-page 384  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 32-14: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE)

SCLx
IM31 IM34
IM30 IM33

SDAx

Start Stop
Condition Condition

Note: Refer to Figure 32-1 for load conditions.

FIGURE 32-15: I2Cx BUS DATA TIMING CHARACTERISTICS (MASTER MODE)

IM20 IM11 IM21

IM10
SCLx
IM11 IM26
IM10 IM25 IM33
SDAx
In
IM40 IM40 IM45

SDAx
Out

Note: Refer to Figure 32-1 for load conditions.

 2009-2019 Microchip Technology Inc. DS60001156K-page 385

PIC32MX5XX/6XX/7XX
TABLE 32-32: I2Cx BUS DATA TIMING REQUIREMENTS (MASTER MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min.(1) Max. Units Conditions
No.
IM10 TLO:SCL Clock Low Time 100 kHz mode TPB * (BRG + 2) — s —
400 kHz mode TPB * (BRG + 2) — s —
1 MHz mode(2) TPB * (BRG + 2) — s —
IM11 THI:SCL Clock High Time 100 kHz mode TPB * (BRG + 2) — s —
400 kHz mode TPB * (BRG + 2) — s —
(2)
1 MHz mode TPB * (BRG + 2) — s —
IM20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(2) — 100 ns
IM21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns from 10 to 400 pF
1 MHz mode(2) — 300 ns
IM25 TSU:DAT Data Input 100 kHz mode 250 — ns —
Setup Time 400 kHz mode 100 — ns
1 MHz mode(2) 100 — ns
IM26 THD:DAT Data Input 100 kHz mode 0 — s —
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode(2) 0 0.3 s
IM30 TSU:STA Start Condition 100 kHz mode TPB * (BRG + 2) — ns Only relevant for
Setup Time 400 kHz mode TPB * (BRG + 2) — ns Repeated Start
condition
1 MHz mode(2) TPB * (BRG + 2) — ns
IM31 THD:STA Start Condition 100 kHz mode TPB * (BRG + 2) — ns After this period, the
Hold Time 400 kHz mode TPB * (BRG + 2) — ns first clock pulse is
generated
1 MHz mode(2) TPB * (BRG + 2) — ns
IM33 TSU:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — ns —
Setup Time 400 kHz mode TPB * (BRG + 2) — ns
1 MHz mode(2) TPB * (BRG + 2) — ns
IM34 THD:STO Stop Condition 100 kHz mode TPB * (BRG + 2) — ns —
Hold Time 400 kHz mode TPB * (BRG + 2) — ns
1 MHz mode(2) TPB * (BRG + 2) — ns
IM40 TAA:SCL Output Valid from 100 kHz mode — 3500 ns —
Clock 400 kHz mode — 1000 ns —
(2)
1 MHz mode — 350 ns —
IM45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s The amount of time the
400 kHz mode 1.3 — s bus must be free before
a new
1 MHz mode(2) 0.5 — s
transmission can start
IM50 CB Bus Capacitive Loading — 400 pF —
(3)
IM51 TPGD Pulse Gobbler Delay 52 312 ns —
Note 1: BRG is the value of the I2C Baud Rate Generator.
2: Maximum pin capacitance = 10 pF for all I2Cx pins (only for 1 MHz mode).
3: The typical value for this parameter is 104 ns.

DS60001156K-page 386  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 32-16: I2Cx BUS START/STOP BITS TIMING CHARACTERISTICS (SLAVE MODE)

SCLx
IS31 IS34
IS30 IS33

SDAx

Start Stop
Condition Condition

Note: Refer to Figure 32-1 for load conditions.

FIGURE 32-17: I2Cx BUS DATA TIMING CHARACTERISTICS (SLAVE MODE)

IS20 IS11 IS21

IS10
SCLx
IS30 IS26
IS31 IS25 IS33
SDAx
In
IS40 IS40 IS45

SDAx
Out

Note: Refer to Figure 32-1 for load conditions.

 2009-2019 Microchip Technology Inc. DS60001156K-page 387

PIC32MX5XX/6XX/7XX
TABLE 32-33: I2Cx BUS DATA TIMING REQUIREMENTS (SLAVE MODE)
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Max. Units Conditions
No.
IS10 TLO:SCL Clock Low Time 100 kHz mode 4.7 — s PBCLK must operate at a
minimum of 800 kHz
400 kHz mode 1.3 — s PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode(1) 0.5 — s —
IS11 THI:SCL Clock High Time 100 kHz mode 4.0 — s PBCLK must operate at a
minimum of 800 kHz
400 kHz mode 0.6 — s PBCLK must operate at a
minimum of 3.2 MHz
1 MHz mode(1) 0.5 — s —
IS20 TF:SCL SDAx and SCLx 100 kHz mode — 300 ns CB is specified to be from
Fall Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode(1) — 100 ns
IS21 TR:SCL SDAx and SCLx 100 kHz mode — 1000 ns CB is specified to be from
Rise Time 400 kHz mode 20 + 0.1 CB 300 ns 10 to 400 pF
1 MHz mode(1) — 300 ns
IS25 TSU:DAT Data Input 100 kHz mode 250 — ns —
Setup Time 400 kHz mode 100 — ns
1 MHz mode(1) 100 — ns
IS26 THD:DAT Data Input 100 kHz mode 0 — ns —
Hold Time 400 kHz mode 0 0.9 s
1 MHz mode(1) 0 0.3 s
IS30 TSU:STA Start Condition 100 kHz mode 4700 — ns Only relevant for Repeated
Setup Time 400 kHz mode 600 — ns Start condition
1 MHz mode(1) 250 — ns
IS31 THD:STA Start Condition 100 kHz mode 4000 — ns After this period, the first
Hold Time 400 kHz mode 600 — ns clock pulse is generated
1 MHz mode(1) 250 — ns
IS33 TSU:STO Stop Condition 100 kHz mode 4000 — ns —
Setup Time 400 kHz mode 600 — ns
1 MHz mode(1) 600 — ns
IS34 THD:STO Stop Condition 100 kHz mode 4000 — ns —
Hold Time 400 kHz mode 600 — ns
1 MHz mode(1) 250 ns
IS40 TAA:SCL Output Valid from 100 kHz mode 0 3500 ns —
Clock 400 kHz mode 0 1000 ns
1 MHz mode(1) 0 350 ns
IS45 TBF:SDA Bus Free Time 100 kHz mode 4.7 — s The amount of time the bus
400 kHz mode 1.3 — s must be free before a new
transmission can start
1 MHz mode(1) 0.5 — s
IS50 CB Bus Capacitive Loading — 400 pF —
Note 1: Maximum pin capacitance = 10 pF for all I2Cx pins (only for 1 MHz mode).

DS60001156K-page 388  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 32-18: CAN MODULE I/O TIMING CHARACTERISTICS

CiTx Pin
Old Value New Value
(output)

CA10 CA11
CiRx Pin
(input)

CA20

TABLE 32-34: CAN MODULE I/O TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param
Symbol Characteristic(1) Min Typ(2) Max Units Conditions
No.
CA10 TioF Port Output Fall Time — — — ns See parameter DO32
CA11 TioR Port Output Rise Time — — — ns See parameter DO31
CA20 Tcwf Pulse Width to Trigger 700 — — ns —
CAN Wake-up Filter
Note 1: These parameters are characterized but not tested in manufacturing.
2: Data in “Typ” column is at 3.3V, 25°C unless otherwise stated. Parameters are for design guidance only
and are not tested.

 2009-2019 Microchip Technology Inc. DS60001156K-page 389

PIC32MX5XX/6XX/7XX
TABLE 32-35: ETHERNET MODULE SPECIFICATIONS
Standard Operating Conditions (see Note 1): 2.9V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Characteristic Min. Typical Max. Units Conditions
No.
MIIM Timing Requirements
ET1 MDC Duty Cycle 40 — 60 % —
ET2 MDC Period 400 — — ns —
ET3 MDIO Output Setup and Hold 10 — 10 ns See Figure 32-19
ET4 MDIO Input Setup and Hold 0 — 300 ns See Figure 32-20
MII Timing Requirements
ET5 TX Clock Frequency — 25 — MHz —
ET6 TX Clock Duty Cycle 35 — 65 % —
ET7 ETXDx, ETEN, ETXERR Output Delay 0 — 25 ns See Figure 32-21
ET8 RX Clock Frequency — 25 — MHz —
ET9 RX Clock Duty Cycle 35 — 65 % —
ET10 ERXDx, ERXDV, ERXERR Setup and Hold 10 — 30 ns See Figure 32-22
RMII Timing Requirements
ET11 Reference Clock Frequency — 50 — MHz —
ET12 Reference Clock Duty Cycle 35 — 65 % —
ET13 ETXDx, ETEN, Setup and Hold 2 — 4 ns —
ET14 ERXDx, ERXDV, ERXERR Setup and Hold 2 — 4 ns —
Note 1: The Ethernet module is functional at VBORMIN < VDD < 2.9V, but with degraded performance. Unless other-
wise stated, module functionality is tested, but not characterized.

FIGURE 32-19: MDIO SOURCED BY THE PIC32 DEVICE

VIHMIN
MDC
VILMAX

VIHMIN
MDIO
VILMAX
ET3 (Hold)
(Setup) ET3

FIGURE 32-20: MDIO SOURCED BY THE PHY

VIHMIN
MDC
VILMAX

VIHMIN
MDIO
VILMAX

ET4

DS60001156K-page 390  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 32-21: TRANSMIT SIGNAL TIMING RELATIONSHIPS AT THE MII

VIHMIN
VILMAX
TX Clock

VIHMIN
ETXD<3:0>, VILMAX
ETEN,
ETXERR
ET7

FIGURE 32-22: RECEIVE SIGNAL TIMING RELATIONSHIPS AT THE MII

VIHMIN
RX Clock VILMAX

VIHMIN

ERXD<3:0>, VILMAX
ERXDV,
ERXERR
(Setup) ET10

ET10 (Hold)

 2009-2019 Microchip Technology Inc. DS60001156K-page 391

PIC32MX5XX/6XX/7XX
TABLE 32-36: ADC MODULE SPECIFICATIONS
Standard Operating Conditions (see Note 5): 2.5V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical Max. Units Conditions
No.
Device Supply
AD01 AVDD Module VDD Supply Greater of — Lesser of V
VDD – 0.3 VDD + 0.3 —
or 2.5 or 3.6
AD02 AVSS Module VSS Supply VSS — VSS + 0.3 V —
Reference Inputs
AD05 VREFH Reference Voltage High AVSS + 2.0 — AVDD V (Note 1)
AD05a 2.5 — 3.6 V VREFH = AVDD (Note 3)
AD06 VREFL Reference Voltage Low AVSS — VREFH – 2.0 V (Note 1)
AD07 VREF Absolute Reference 2.0 — AVDD V (Note 3)
Voltage (VREFH – VREFL)
AD08 IREF Current Drain — 250 400 A ADC operating
AD08a — — 3 A ADC off
Analog Input
AD12 VINH-VINL Full-Scale Input Span VREFL — VREFH V —
AD13 VINL Absolute VINL Input AVSS – 0.3 — AVDD/2 V —
Voltage
AD14 VIN Absolute Input Voltage AVSS – 0.3 — AVDD + 0.3 V —
AD15 Leakage Current — ±0.001 ±0.610 A VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
Source Impedance = 10 k
AD17 RIN Recommended — — 5K  (Note 1)
Impedance of Analog
Voltage Source
ADC Accuracy – Measurements with External VREF+/VREF-
AD20c Nr Resolution 10 data bits bits —
AD21c INL Integral Nonlinearity > -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD22c DNL Differential Nonlinearity > -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
(Note 2)
AD23c GERR Gain Error > -1 — <1 LSb VINL = AVSS = VREFL = 0V,
AVDD = VREFH = 3.3V
AD24c EOFF Offset Error > -1 — <1 LSb VINL = AVSS = 0V,
AVDD = 3.3V
AD25c — Monotonicity — — — — Guaranteed
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with a 1 kHz sine wave.
5: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise
stated, module functionality is tested, but not characterized.

DS60001156K-page 392  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 32-36: ADC MODULE SPECIFICATIONS (CONTINUED)
Standard Operating Conditions (see Note 5): 2.5V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical Max. Units Conditions
No.
ADC Accuracy – Measurements with Internal VREF+/VREF-
AD20d Nr Resolution 10 data bits bits (Note 3)
AD21d INL Integral Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD22d DNL Differential Nonlinearity > -1 — <1 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Notes 2,3)
AD23d GERR Gain Error > -4 — <4 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD24d EOFF Offset Error > -2 — <2 LSb VINL = AVSS = 0V,
AVDD = 2.5V to 3.6V
(Note 3)
AD25d — Monotonicity — — — — Guaranteed
Dynamic Performance
AD31b SINAD Signal to Noise and 55 58.5 — dB (Notes 3,4)
Distortion
AD34b ENOB Effective Number of Bits 9.0 9.5 — bits (Notes 3,4)
Note 1: These parameters are not characterized or tested in manufacturing.
2: With no missing codes.
3: These parameters are characterized, but not tested in manufacturing.
4: Characterized with a 1 kHz sine wave.
5: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise
stated, module functionality is tested, but not characterized.

 2009-2019 Microchip Technology Inc. DS60001156K-page 393

PIC32MX5XX/6XX/7XX
TABLE 32-37: 10-BIT ADC CONVERSION RATE PARAMETERS
Standard Operating Conditions (see Note 3): 2.5V to 3.6V
(unless otherwise stated)
Operating temperature -40°C  TA  +85°C for Industrial
-40°C TA  +105°C for V-Temp
Sampling
TAD RS
ADC Speed(2) Time VDD ADC Channels Configuration
Minimum Maximum
Minimum
1 Msps to 65 ns 132 ns 500 3.0V to 3.6V
400 ksps(1) VREF- VREF+

CHX
ANx
S&H ADC

Up to 400 ksps 200 ns 200 ns 5.0 k 2.5V to 3.6V

VREF- VREF+
or or
AVSS AVDD

ANx CHX
S&H ADC

ANx or VREF-

Note 1: External VREF- and VREF+ pins must be used for correct operation.
2: These parameters are characterized, but not tested in manufacturing.
3: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless
otherwise stated, module functionality is tested, but not characterized.

DS60001156K-page 394  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 32-38: ANALOG-TO-DIGITAL CONVERSION TIMING REQUIREMENTS
Standard Operating Conditions (see Note 4): 2.5V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics Min. Typical(1) Max. Units Conditions
No.
Clock Parameters
AD50 TAD Analog-to-Digital Clock Period(2) 65 — — ns See Table 32-37
Conversion Rate
AD55 TCONV Conversion Time — 12 TAD — — —
AD56 FCNV Throughput Rate — — 1000 ksps AVDD = 3.0V to 3.6V
(Sampling Speed) — — 400 ksps AVDD = 2.5V to 3.6V
AD57 TSAMP Sample Time 1 TAD — — — TSAMP must be  132 ns
Timing Parameters
AD60 TPCS Conversion Start from Sample — 1.0 TAD — — Auto-Convert Trigger
Trigger(3) (SSRC<2:0> = 111)
not selected
AD61 TPSS Sample Start from Setting 0.5 TAD — 1.5 TAD — —
Sample (SAMP) bit
AD62 TCSS Conversion Completion to — 0.5 TAD — — —
Sample Start (ASAM = 1)(3)
AD63 TDPU Time to Stabilize Analog Stage — — 2 s —
from Analog-to-Digital Off to
Analog-to-Digital On(3)
Note 1: These parameters are characterized, but not tested in manufacturing.
2: Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity
performance, especially at elevated temperatures.
3: Characterized by design but not tested.
4: The ADC module is functional at VBORMIN < VDD < 2.5V, but with degraded performance. Unless otherwise
stated, module functionality is tested, but not characterized.

 2009-2019 Microchip Technology Inc. DS60001156K-page 395

PIC32MX5XX/6XX/7XX
FIGURE 32-23: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING
CHARACTERISTICS (ASAM = 0, SSRC<2:0> = 000)

AD50

ADCLK
Instruction
Execution Set SAMP Clear SAMP

SAMP

ch0_dischrg

ch0_samp

eoc

AD61
AD60

TSAMP AD55 AD55

CONV

ADxIF

Buffer(0)

Buffer(1)

1 2 3 4 5 6 7 8 5 6 7 8

1 – Software sets ADxCON. SAMP to start sampling.

2 – Sampling starts after discharge period. TSAMP is described in Section 17. “10-bit A/D Converter” (DS60001104) of the
“PIC32 Family Reference Manual”.
3 – Software clears ADxCON. SAMP to start conversion.
4 – Sampling ends, conversion sequence starts.
5 – Convert bit 9.
6 – Convert bit 8.
7 – Convert bit 0.
8 – One TAD for end of conversion.

DS60001156K-page 396  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 32-24: ANALOG-TO-DIGITAL CONVERSION (10-BIT MODE) TIMING CHARACTERISTICS
(ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001)

AD50

ADCLK
Instruction
Execution Set ADON

SAMP

ch0_dischrg

ch0_samp

eoc

TSAMP TSAMP
AD55 AD55 TCONV

CONV

ADxIF

Buffer(0)

Buffer(1)

1 2 3 4 5 6 7 3 4 5 6 8 3 4

1 – Software sets ADxCON. ADON to start AD operation. 5 – Convert bit 0.

2 – Sampling starts after discharge period. 6 – One TAD for end of conversion.
TSAMP is described in Section 17. “10-bit A/D Converter”
(DS60001104) of the “PIC32 Family Reference Manual. 7 – Begin conversion of next channel.

3 – Convert bit 9. 8 – Sample for time specified by SAMC<4:0>.

4 – Convert bit 8.

 2009-2019 Microchip Technology Inc. DS60001156K-page 397

PIC32MX5XX/6XX/7XX
FIGURE 32-25: PARALLEL SLAVE PORT TIMING

CS

PS5

RD

PS6
WR

PS4 PS7

PMD<7:0>

PS1
PS3

PS2

TABLE 32-39: PARALLEL SLAVE PORT REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
No.
PS1 TdtV2wrH Data In Valid before WR or CS 20 — — ns —
Inactive (setup time)
PS2 TwrH2dtI WR or CS Inactive to Data-In 40 — — ns —
Invalid (hold time)
PS3 TrdL2dtV RD and CS Active to Data-Out — — 60 ns —
Valid
PS4 TrdH2dtI RD Activeor CS Inactive to 0 — 10 ns —
Data-Out Invalid
PS5 Tcs CS Active Time TPB + 40 — — ns —
PS6 TWR WR Active Time TPB + 25 — — ns —
PS7 TRD RD Active Time TPB + 25 — — ns —
Note 1: These parameters are characterized, but not tested in manufacturing.

DS60001156K-page 398  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
FIGURE 32-26: PARALLEL MASTER PORT READ TIMING DIAGRAM

TPB TPB TPB TPB TPB TPB TPB TPB

PB Clock

PM4

PMA<13:18> Address

PM6

PMD<7:0> Address<7:0>
Address<7:0> Data
Data

PM2
PM7
PM3
PMRD
PM5

PMWR
PM1
PMALL/PMALH

PMCS<2:1>

TABLE 32-40: PARALLEL MASTER PORT READ TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
No.
PM1 TLAT PMALL/PMALH Pulse Width — 1 TPB — — —
PM2 TADSU Address Out Valid to PMALL/ — 2 TPB — — —
PMALH Invalid (address setup
time)
PM3 TADHOLD PMALL/PMALH Invalid to Address — 1 TPB — — —
Out Invalid (address hold time)
PM4 TAHOLD PMRD Inactive to Address Out 5 — — ns —
Invalid
(address hold time)
PM5 TRD PMRD Pulse Width — 1 TPB — — —
PM6 TDSU PMRD or PMENB Active to Data In 15 — — ns —
Valid (data setup time)
PM7 TDHOLD PMRD or PMENB Inactive to Data 1 TPBCLK — — ns PMP PBCLK
In Invalid (data hold time)
Note 1: These parameters are characterized, but not tested in manufacturing.

 2009-2019 Microchip Technology Inc. DS60001156K-page 399

PIC32MX5XX/6XX/7XX
FIGURE 32-27: PARALLEL MASTER PORT WRITE TIMING DIAGRAM

TPB TPB TPB TPB TPB TPB TPB TPB

PB Clock

PMA<13:18> Address

PM2 + PM3

PMD<7:0> Address<7:0> Data

PM12
PM13
PMRD
PM11
PMWR

PM1
PMALL/PMALH

PMCS<2:1>

TABLE 32-41: PARALLEL MASTER PORT WRITE TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
No.
PM11 TWR PMWR Pulse Width — 1 TPB — — —
PM12 TDVSU Data Out Valid before PMWR or — 2 TPB — — —
PMENB goes Inactive (data setup
time)
PM13 TDVHOLD PMWR or PMEMB Invalid to Data — 1 TPB — — —
Out Invalid (data hold time)
Note 1: These parameters are characterized, but not tested in manufacturing.

DS60001156K-page 400  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
TABLE 32-42: USB OTG ELECTRICAL SPECIFICATIONS
Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Characteristics(1) Min. Typical Max. Units Conditions
No.
USB313 VUSB3V3 USB Voltage 3.0 — 3.6 V Voltage on VUSB3V3
must be in this range for
proper USB operation
USB315 VILUSB Input Low Voltage for USB Buffer — — 0.8 V —
USB316 VIHUSB Input High Voltage for USB Buffer 2.0 — — V —
USB318 VDIFS Differential Input Sensitivity — — 0.2 V The difference between
D+ and D- must exceed
this value while VCM is
met
USB319 VCM Differential Common Mode Range 0.8 — 2.5 V —
USB320 ZOUT Driver Output Impedance 28.0 — 44.0  —
USB321 VOL Voltage Output Low 0.0 — 0.3 V 1.425 k load
connected to VUSB3V3
USB322 VOH Voltage Output High 2.8 — 3.6 V 14.25 k load
connected to ground
Note 1: These parameters are characterized, but not tested in manufacturing.

 2009-2019 Microchip Technology Inc. DS60001156K-page 401

PIC32MX5XX/6XX/7XX
FIGURE 32-28: EJTAG TIMING CHARACTERISTICS

TTCKcyc
TTCKhigh TTCKlow
Trf

TCK
Trf

TMS

TDI

TTsetup TThold Trf

Trf

TDO

TTRST*low
TTDOout TTDOzstate

TRST*

Defined Undefined
Trf

TABLE 32-43: EJTAG TIMING REQUIREMENTS

Standard Operating Conditions: 2.3V to 3.6V
(unless otherwise stated)
AC CHARACTERISTICS
Operating temperature -40°C  TA  +85°C for Industrial
-40°C  TA  +105°C for V-Temp
Param.
Symbol Description(1) Min. Max. Units Conditions
No.
EJ1 TTCKCYC TCK Cycle Time 25 — ns —
EJ2 TTCKHIGH TCK High Time 10 — ns —
EJ3 TTCKLOW TCK Low Time 10 — ns —
EJ4 TTSETUP TAP Signals Setup Time Before 5 — ns —
Rising TCK
EJ5 TTHOLD TAP Signals Hold Time After 3 — ns —
Rising TCK
EJ6 TTDOOUT TDO Output Delay Time from — 5 ns —
Falling TCK
EJ7 TTDOZSTATE TDO 3-State Delay Time from — 5 ns —
Falling TCK
EJ8 TTRSTLOW TRST Low Time 25 — ns —
EJ9 TRF TAP Signals Rise/Fall Time, All — — ns —
Input and Output
Note 1: These parameters are characterized, but not tested in manufacturing.

DS60001156K-page 402  2009-2019 Microchip Technology Inc.

 33.0 DC AND AC DEVICE CHARACTERISTICS GRAPHS
 2009-2019 Microchip Technology Inc.

Note: The graphs provided following this note are a statistical summary based on a limited number of samples and are provided for design guidance purposes
only. The performance characteristics listed herein are not tested or guaranteed. In some graphs, the data presented may be outside the specified operating
range (e.g., outside specified power supply range) and therefore, outside the warranted range.

FIGURE 33-1: VOH – 4x DRIVER PINS FIGURE 33-3: VOL – 4x DRIVER PINS

VOH (V)
-0.050 VOL(V)
0.050
-0.045 3.6V
0.045 3.6V
-0.040
3.3V 0.040 3.3V
-0.035
0.035 3V
-0.030 3V
0.030
IOH(A)

IOH(A)
-0.025 0.025
-0.020 0.020
-0.015 Absolute Maximum 0.015 Absolute Maximum
-0.010 0.010
-0.005 0.005
0.000 0.000

PIC32MX5XX/6XX/7XX
0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00

FIGURE 33-2: VOH – 8x DRIVER PINS FIGURE 33-4: VOL – 8x DRIVER PINS
8X
VOH(V) VOL(V)
-0.080 0.080 3.6V
3.6V
-0.070 0.070 3.3V
3.3V
-0.060 0.060 3V
-0.050 3V 0.050
IOH(A)

IOH(A)
-0.040 0.040
DS60001156K-page 403

0 030
-0.030 0.030
Absolute Maximum Absolute Maximum
-0.020 0 020
0.020

-0.010 0.010

0.000 0.000

0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00
PIC32MX5XX/6XX/7XX
NOTES:

DS60001156K-page 404  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
34.0 PACKAGING INFORMATION
34.1 Package Marking Information

64-Lead TQFP (10x10x1 mm) Example

XXXXXXXXXX PIC32MX575F
XXXXXXXXXX 512H-80I/PT
XXXXXXXXXX e3
YYWWNNN 0510017

100-Lead TQFP (14x14x1 mm) Example

XXXXXXXXXXXX PIC32MX575F
XXXXXXXXXXXX 512L-80I/PF e3
YYWWNNN 0510017

100-Lead TQFP (12x12x1 mm) Example

XXXXXXXXXXXX PIC32MX575F
XXXXXXXXXXXX 512L-80I/PT e3
YYWWNNN 0510017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e) 3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

 2009-2019 Microchip Technology Inc. DS60001156K-page 405

PIC32MX5XX/6XX/7XX
34.1 Package Marking Information (Continued)

64-Lead QFN (9x9x0.9 mm) Example

XXXXXXXXXX PIC32MX575F
XXXXXXXXXX 512H-80I/MR
XXXXXXXXXX e3
YYWWNNN 0510017

121-Lead TFBGA (10x10x1.1 mm) Example

XXXXXXXXXX PIC32MX575F
XXXXXXXXXX 512H-80I/BG
XXXXXXXXXX e3
YYWWNNN 0510017

124-Lead VTLA (9x9x0.9 mm) Example

XXXXXXXXXX PIC32MX795F
XXXXXXXXXX 512L-80I/TL
XXXXXXXXXX e3
YYWWNNN 0510017

Legend: XX...X Customer-specific information

Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
* This package is Pb-free. The Pb-free JEDEC designator ( e) 3
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.

DS60001156K-page 406  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
34.2 Package Details
The following sections give the technical details of the packages.
64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D
D1

D1/2
D

NOTE 2

E1/2
A B

E1 E
A A
SEE DETAIL 1
N

4X N/4 TIPS
0.20 C A-B D 1 3
2
4X
NOTE 1
0.20 H A-B D

TOP VIEW

A2
A
C 0.05
SEATING
PLANE
A1
64 X b
0.08 C 0.08 C A-B D
e

SIDE VIEW

Microchip Technology Drawing C04-085C Sheet 1 of 2

 2009-2019 Microchip Technology Inc. DS60001156K-page 407

PIC32MX5XX/6XX/7XX

64-Lead Plastic Thin Quad Flatpack (PT)-10x10x1 mm Body, 2.00 mm Footprint [TQFP]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

E
L T
(L1) X=A—B OR D

SECTION A-A X

e/2

DETAIL 1

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Leads N 64
Lead Pitch e 0.50 BSC
Overall Height A - - 1.20
Molded Package Thickness A2 0.95 1.00 1.05
Standoff A1 0.05 - 0.15
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle I 0° 3.5° 7°
Overall Width E 12.00 BSC
Overall Length D 12.00 BSC
Molded Package Width E1 10.00 BSC
Molded Package Length D1 10.00 BSC
Lead Thickness c 0.09 - 0.20
Lead Width b 0.17 0.22 0.27
Mold Draft Angle Top D 11° 12° 13°
Notes: Mold Draft Angle Bottom E 11° 12° 13°

1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Chamfers at corners are optional; size may vary.
3. Dimensions D1 and E1 do not include mold flash or protrusions. Mold flash or
protrusions shall not exceed 0.25mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
Microchip Technology Drawing C04-085C Sheet 2 of 2

DS60001156K-page 408  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2019 Microchip Technology Inc. DS60001156K-page 409

PIC32MX5XX/6XX/7XX

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D1

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DS60001156K-page 410  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2019 Microchip Technology Inc. DS60001156K-page 411

PIC32MX5XX/6XX/7XX
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DS60001156K-page 412  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2019 Microchip Technology Inc. DS60001156K-page 413

PIC32MX5XX/6XX/7XX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

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 PIC32MX5XX/6XX/7XX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

 2009-2019 Microchip Technology Inc. DS60001156K-page 415

PIC32MX5XX/6XX/7XX

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

DS60001156K-page 416  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX

121-Ball Plastic Thin Profile Fine Pitch Ball Grid Array (BG) -
10x10x1.10 mm Body [TFBGA]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

D A B

NOTE 1

E
(DATUM B)
(DATUM A)
2X
0.10 C

2X
0.10 C TOP VIEW

DETAIL A
A1
SIDE VIEW

D1
e

L
K
J
H
G
F E1
E
D
C
B
DETAIL B A

BOTTOM VIEW

Microchip Technology Drawing C04-148 Rev F Sheet 1 of 2

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PIC32MX5XX/6XX/7XX

121-Ball Plastic Thin Profile Fine Pitch Ball Grid Array (BG) -
10x10x1.10 mm Body [TFBGA]
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

0.10 C
DETAIL A

NX Øb
0.15 C A B
0.08 C

DETAIL B

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Contacts N 121
Contact Pitch e 0.80 BSC
Overall Height A 1.00 1.10 1.20
Ball Height A1 0.25 0.30 0.35
Overall Width E 10.00 BSC
Array Width E1 8.00 BSC
Overall Length D 10.00 BSC
Array Length D1 8.00 BSC
Contact Diameter b 0.35 0.40 0.45

Notes:
1. Ball A1 visual index feature may vary, but must be located within the hatched area.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Reference Dimension, usually without tolerance, for information purposes only.
3. The outer rows and colums of balls are located with respect to datums A and B.
4. Ball interface to package body: 0.37mm nominal diameter.

Microchip Technology Drawing C04-148 Rev F Sheet 2 of 2

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 PIC32MX5XX/6XX/7XX

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PIC32MX5XX/6XX/7XX

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 PIC32MX5XX/6XX/7XX

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PIC32MX5XX/6XX/7XX

124-Very Thin Leadless Array Package (TL) – 9x9x0.9 mm Body [VTLA]

Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging

E
E/2
X1 G4

X2
G3
E

T2 C2

G1

G5
X4
G2
SILK SCREEN
W3
W2
C1

RECOMMENDED LAND PATTERN

Units MILLIMETERS
Dimension Limits MIN NOM MAX
Contact Pitch E 0.50 BSC
Pad Clearance G1 0.20
Pad Clearance G2 0.20
Pad Clearance G3 0.20
Pad Clearance G4 0.20
Contact to Center Pad Clearance (X4) G5 0.30
Optional Center Pad Width T2 6.60
Optional Center Pad Length W2 6.60
Optional Center Pad Chamfer (X4) W3 0.10
Contact Pad Spacing C1 8.50
Contact Pad Spacing C2 8.50
Contact Pad Width (X124) X1 0.30
Contact Pad Length (X124) X2 0.30
Notes:
1. Dimensioning and tolerancing per ASME Y14.5M
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Microchip Technology Drawing No. C04-2193A

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 PIC32MX5XX/6XX/7XX
APPENDIX A: MIGRATING FROM PIC32MX3XX/4XX TO PIC32MX5XX/6XX/7XX
DEVICES
This appendix provides an overview of considerations For example, to clear a UART receive interrupt, the
for migrating from PIC32MX3XX/4XX devices to the user application must first read the UART Receive
PIC32MX5XX/6XX/7XX family of devices. The code register to clear the interrupt condition and then clear
developed for the PIC32MX3XX/4XX devices can be the associated UxIF flag to clear the pending UART
ported to the PIC32MX5XX/6XX/7XX devices after interrupt. In other words, the UxIF flag cannot be
making the appropriate changes outlined below. cleared by software until the UART Receive register is
read.
A.1 DMA Table A-1 outlines the peripherals and associated
interrupts that are implemented differently on
PIC32MX5XX/6XX/7XX devices do not support
PIC32MX5XX/6XX/7XX versus PIC32MX3XX/4XX
stopping DMA transfers in Idle mode.
devices.

A.2 Interrupts In addition, on the SPI module, the IRQ numbers for the
receive done interrupts were changed from 25 to 24
PIC32MX5XX/6XX/7XX devices have persistent and the transfer done interrupts were changed from 24
interrupts for some of the peripheral modules. This to 25.
means that the interrupt condition for these peripherals
must be cleared before the interrupt flag can be
cleared.

TABLE A-1: PIC32MX3XX/4XX VERSUS PIC32MX5XX/6XX/7XX INTERRUPT IMPLEMENTATION

DIFFERENCES
Module Interrupt Implementation
Input Capture To clear an interrupt source, read the Buffer Result (ICxBUF) register to obtain the number of
capture results in the buffer that are below the interrupt threshold (specified by ICI<1:0> bits).
SPI Receive and transmit interrupts are controlled by the SRXISEL<1:0> and STXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be written to, or read from, the SPIxBUF
register to obtain the number of data to receive/transmit below the level specified by the
SRXISEL<1:0> and STXISEL<1:0> bits.
UART TX interrupt will be generated as soon as the UART module is enabled.
Receive and transmit interrupts are controlled by the URXISEL<1:0> and UTXISEL<1:0> bits,
respectively. To clear an interrupt source, data must be read from, or written to, the UxRXREG or
UxTXREG registers to obtain the number of data to receive/transmit below the level specified by
the URXISEL<1:0> and UTXISEL<1:0> bits.
ADC All samples must be read from the result registers (ADC1BUFx) to clear the interrupt source.
PMP To clear an interrupt source, read the Parallel Master Port Data Input/Output (PMDIN/PMDOUT)
register.

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PIC32MX5XX/6XX/7XX
APPENDIX B: REVISION HISTORY

Revision A (August 2009)

This is the initial released version of this document.

Revision B (November 2009)

The revision includes the following global update:
Added Note 2 to the shaded table that appears
at the beginning of each chapter. This new note
provides information regarding the availability of
registers and their associated bits.
Other major changes are referenced by their respective
chapter/section in Table B-1.

TABLE B-1: MAJOR SECTION UPDATES

Section Name Update Description
“High-Performance, USB, CAN and Added the following devices:
Ethernet 32-bit Flash - PIC32MX575F256L
Microcontrollers”
- PIC32MX695F512L
- PIC32MX695F512H
The 100-pin TQFP pin diagrams have been updated to reflect the current pin
name locations (see the “Pin Diagrams” section).
Added the 121-pin Ball Grid Array (XBGA) pin diagram.
Updated Table 1: “PIC32 USB and CAN – Features”
Added the following tables:
- Table 4: “Pin Names: PIC32MX534F064L, PIC32MX564F064L,
PIC32MX564F128L, PIC32MX575F256L and PIC32MX575F512L
Devices”
- Table 5: “Pin Names: PIC32MX664F064L, PIC32MX664F128L,
PIC32MX675F256L, PIC32MX675F512L and PIC32MX695F512L
Devices”
- Table 6: “Pin Names: PIC32MX775F256L, PIC32MX775F512L and
PIC32MX795F512L Devices”
Updated the following pins as 5V tolerant:
- 64-pin QFN: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 64-pin TQFP: Pin 36 (D-/RG3) and Pin 37 (D+/RG2)
- 100-pin TQFP: Pin 56 (D-/RG3) and Pin 57 (D+/RG2)
1.0 “Guidelines for Getting Started Removed the last sentence of 1.3.1 “Internal Regulator Mode”.
with 32-bit Microcontrollers” Removed Section 2.3.2 “External Regulator Mode”

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 PIC32MX5XX/6XX/7XX
TABLE B-1: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
4.0 “Memory Organization” Updated all register tables to include the Virtual Address and All Resets
columns.
Updated the title of Figure 4-4 to include the PIC32MX575F256L device.
Updated the title of Figure 4-6 to include the PIC32MX695F512L and
PIC32MX695F512H devices. Also changed PIC32MX795F512L to
PIC32MX795F512H.
Updated the title of Table 4-3 to include the PIC32MX695F512H device.
Updated the title of Table 4-5 to include the PIC32MX575F5256L device.
Updated the title of Table 4-6 to include the PIC32MX695F512L device.
Reversed the order of Table 4-11 and Table 4-12.
Reversed the order of Table 4-14 and Table 4-15.
Updated the title of Table 4-15 to include the PIC32MX575F256L and
PIC32MX695F512L devices.
Updated the title of Table 4-45 to include the PIC32MX575F256L device.
Updated the title of Table 4-47 to include the PIC32MX695F512H and
PIC32MX695F512L devices.
1.0 “I/O Ports” Updated the second paragraph of 1.1.2 “Digital Inputs” and removed Table
12-1.
22.0 “10-bit Analog-to-Digital Updated the ADC Conversion Clock Period Block Diagram (see Figure 22-2).
Converter (ADC)”
1.0 “Special Features” Removed references to the ENVREG pin in 1.3 “On-Chip Voltage
Regulator”.
Updated the first sentence of 1.3.1 “On-Chip Regulator and POR” and
1.3.2 “On-Chip Regulator and BOR”.
Updated the Connections for the On-Chip Regulator (see Figure 1-2).
1.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings and added Note 3.
Added Thermal Packaging Characteristics for the 121-pin XBGA package
(see Table 1-3).
Updated the Operating Current (IDD) DC Characteristics (see Table 1-5).
Updated the Idle Current (IIDLE) DC Characteristics (see Table 1-6).
Updated the Power-Down Current (IPD) DC Characteristics (see Table 1-7).
Removed Note 1 from the Program Flash Memory Wait State Characteristics
(see Table 1-12).
Updated the SPIx Module Slave Mode (CKE = 1) Timing Characteristics,
changing SP52 to SP35 between the MSb and Bit 14 on SDOx (see Figure 1-
13).
1.0 “Packaging Information” Added the 121-pin XBGA package marking information and package details.
“Product Identification System” Added the definition for BG (121-lead 10x10x1.1 mm, XBGA).
Added the definition for Speed.

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PIC32MX5XX/6XX/7XX
Revision C (February 2010)
The revision includes the following updates, as
described in Table B-2:

TABLE B-2: MAJOR SECTION UPDATES

Section Name Update Description
“High-Performance, USB, CAN Added the following devices:
and Ethernet 32-bit Flash • PIC32MX675F256H
Microcontrollers” • PIC32MX775F256H
• PIC32MX775F512H
• PIC32MX675F256L
• PIC32MX775F256L
• PIC32MX775F512L
Added the following pins:
• EREFCLK
• ECRSDV
• AEREFCLK
• AECRSDV
Added the EREFCLK and ECRSDV pins to Table 5 and Table 6.
1.0 “Device Overview” Updated the pin number pinout I/O descriptions for the following pin names in
Table 1-1:
• SCL3 • SCL5 • RTCC • C1OUT
• SDA3 • SDA5 • CVREF- • C2IN-
• SCL2 • TMS • CVREF+ • C2IN+
• SDA2 • TCK • CVREFOUT • C2OUT
• SCL4 • TDI • C1IN- • PMA0
• SDA4 • TDO • C1IN+ • PMA1

Added the following pins to the Pinout I/O Descriptions table (Table 1-1):
• EREFCLK
• ECRSDV
• AEREFCLK
• AECRSDV
4.0 “Memory Organization” Added new devices and updated the virtual and physical memory map values in
Figure 4-4.
Added new devices to Figure 4-5.
Added new devices to the following register maps:
• Table 4-3, Table 4-4, Table 4-6 and Table 4-7 (Interrupt Register Maps)
• Table 4-12 (I2C2 Register Map)
• Table 4-15 (SPI1 Register Map)
• Table 4-24 through Table 4-35 (PORTA-PORTG Register Maps)
• Table 4-36 and Table 4-37 (Change Notice and Pull-up Register Maps)
• Table 4-45 (CAN1 Register Map)
• Table 4-46 (CAN2 Register Map)
• Table 4-47 (Ethernet Controller Register Map)
Changed the bits named POSCMD to POSCMOD in Table 4-42 (Device
Configuration Word Summary).
1.0 “Special Features” Changed all references of POSCMD to POSCMOD in the Device Configuration
Word 1 register (see Register 1-2).
Appendix A: “Migrating from Added the new section Appendix .
PIC32MX3XX/4XX to
PIC32MX5XX/6XX/7XX
Devices”

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 PIC32MX5XX/6XX/7XX
Revision D (May 2010)
The revision includes the following updates, as
described in Table B-3:

TABLE B-3: MAJOR SECTION UPDATES

Section Name Update Description
“High-Performance, USB, CAN Updated the initial Flash memory range to 64K.
and Ethernet 32-bit Flash Updated the initial SRAM memory range to 16K.
Microcontrollers”
Added the following devices (see Table 1, Table 2, Table 3 and the Pin
Diagrams):
• PIC32MX534F064H
• PIC32MX564F064H
• PIC32MX664F064H
• PIC32MX564F128H
• PIC32MX664F128H
• PIC32MX764F128H
• PIC32MX534F064L
• PIC32MX564F064L
• PIC32MX664F064L
• PIC32MX564F128L
• PIC32MX664F128L
• PIC32MX764F128L
4.0 “Memory Organization” Added new Memory Maps (Figure 4-1, Figure 4-2 and Figure 4-3).
The bit named I2CSIF was changed to I2C1SIF and the bit named I2CBIF was
changed to I2C1BIF in the Interrupt Register Map tables (Table 4-2, Table 4-3,
Table 4-4, Table 4-5, Table 4-6 and Table 4-7)
Added the following devices to the Interrupt Register Map (Table 4-2):
• PIC32MX534F064H
• PIC32MX564F064H
• PIC32MX564F128H
Added the following devices to the Interrupt Register Map (Table 4-3):
• PIC32MX664F064H
• PIC32MX664F128H
Added the following device to the Interrupt Register Map (Table 4-4):
• PIC32MX764F128H
Added the following devices to the Interrupt Register Map (Table 4-5):
• PIC32MX534F064L
• PIC32MX564F064L
• PIC32MX564F128L
Added the following devices to the Interrupt Register Map (Table 4-6):
• PIC32MX664F064L
• PIC32MX664F128L
Added the following device to the Interrupt Register Map (Table 4-7):
• PIC32MX764F128L

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PIC32MX5XX/6XX/7XX
TABLE B-3: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
4.0 “Memory Organization” Made the following bit name changes in the I2C1, I2C3, I2C4 and I2C5 Register
(Continued) Map (Table 4-11):
• I2C3BRG SFR: I2C1BRG was changed to I2C3BRG
• I2C4BRG SFR: I2C1BRG was changed to I2C4BRG
• I2C5BRG SFR: I2C1BRG was changed to I2C5BRG
• I2C4TRN SFR: I2CT1DATA was changed to I2CT2ADATA
• I2C4RCV SFR: I2CR2DATA was changed to I2CR2ADATA
• I2C5TRN SFR: I2CT1DATA was changed to I2CT3ADATA
• I2C5RCV SFR: I2CR1DATA was changed to I2CR3ADATA
Added the RTSMD bit and UEN<1:0> bits to the UART1A, UART1B, UART2A,
UART2B, UART3A and UART3B Register Map (Table 4-13)
Added the SIDL bit to the DMA Global Register Map (Table 4-17).
Changed the CM bit to CMR in the System Control Register Map (Table 4-23).
Added the following devices to the I2C2, SPI1, PORTA, PORTC, PORTD,
PORTE, PORTF, PORTG, Change Notice and Pull-up Register Maps (Table 4-12,
Table 4-14, Table 4-24, Table 4-27, Table 4-29, Table 4-31, Table 4-33, Table 4-35
and Table 4-36):
• PIC32MX534F064L
• PIC32MX564F064L
• PIC32MX564F128L
• PIC32MX664F064L
• PIC32MX664F128L
• PIC32MX764F128L
Added the following devices to the PORTC, PORTD, PORTE, PORTF, PORTG,
Change Notice and Pull-up Register Maps (Table 4-26, Table 4-28, Table 4-30,
Table 4-32, Table 4-34 and Table 4-37):
• PIC32MX534F064H
• PIC32MX564F064H
• PIC32MX564F128H
• PIC32MX664F064H
• PIC32MX664F128H
• PIC32MX764F128H
Added the following devices to the CAN1 Register Map (Table 4-45):
• PIC32MX534F064H
• PIC32MX564F064H
• PIC32MX564F128H
• PIC32MX764F128H
• PIC32MX534F064L
• PIC32MX564F064L
• PIC32MX564F128L
• PIC32MX764F128L
Added the following devices to the Ethernet Controller Register Map (Table 4-47):
• PIC32MX664F064H
• PIC32MX664F128H
• PIC32MX764F128H
• PIC32MX664F064L
• PIC32MX664F128L
• PIC32MX764F128L

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 PIC32MX5XX/6XX/7XX
TABLE B-3: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
1.0 “Electrical Characteristics” Updated the Typical and Maximum DC Characteristics: Operating Current (IDD) in
Table 1-5.
Updated the Typical and Maximum DC Characteristics: Idle Current (IIDLE) in
Table 1-6.
Updated the Typical and Maximum DC Characteristics: Power-Down Current (IPD)
in Table 1-7.
Added DC Characteristics: Program Memory parameters D130a and D132a in
Table 1-11.
Added the Internal Voltage Reference parameter (D305) to the Comparator
Specifications in Table 1-13.

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PIC32MX5XX/6XX/7XX
Revision E (July 2010) Revision F (December 2010)
Minor corrections were incorporated throughout the The revision includes the following global update:
document. VCAP/VDDCORE has been changed to: VCAP/VCORE
Other major changes are referenced by their respective
chapter/section in Table B-4:

TABLE B-4: SECTION UPDATES

Section Name Update Description
High-Performance, USB, CAN and Removed the following Analog Feature: FV tolerant input pins
Ethernet 32-bit Flash Microcontrollers (digital pins only)
Updated the term LIN 1.2 support as LIN support for the peripheral
feature: Six UART modules with: RS-232, RS-485, and LIN support
1.0 “Device Overview” Updated the value of 64-pin QFN/TQFP pin number for the following pin
names: PMA0, PMA1 and ECRSDV
4.0 “Memory Organization” The following register map tables were updated:
• Table 4-2:
- Changed bits 24/8 to I2C5BIF in IFS1
- Changed bits 24/8-24/10 to SRIPL<2:0> in INTSTAT
- Changed bits 25/9/-24/8 to U5IS<1:0> in IPC12
- Added note 2
• Table 4-3 through Table 4-7:
- Changed bits 24/8-24/10 to SRIPL<2:0> in INTSTAT
- Changed bits 25/9-24/8 to U5IS<1:0> in IPC12
• Table 4-3:
- Changed bits 24/8 to I2C5BIF in IFS1
- Added note 2
• Table 4-4:
- Changed bits 24/8 to I2C5BIF in IFS1
- Changed bits 24/8 to I2C5BIE in IEC1
- Added note 2 references
• Table 4-5:
- Changed bits 24/8 to I2C5BIF in IFS1
- Changed bits 24/8 to I2C5BIE in IEC1
- Added note 2 references
• Table 4-6:
- Changed bit 24/8 to I2C5BIF in IFS1
- Updated the bit value of bit 24/8 as I2C5BIE for the IEC1 register.
- Added note 2
• Table 4-7:
- Changed bit 25/9 to I2C5SIF in IFS1
- Changed bit 24/8 as I2C5BIF in IFS1
- Changed bit 25/9 as I2C5SIE in IEC1
- Changed bit 24/8 as I2C5BIE in IEC1
- Added note 2 references
• Added note 2 to Table 4-8
• Updated the All Resets values for the following registers in Table 4-11:
I2C3CON, I2C4CON, I2C5CON and I2C1CON.
• Updated the All Resets values for the I2C2CON register in Table 4-12

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 PIC32MX5XX/6XX/7XX
TABLE B-4: SECTION UPDATES (CONTINUED)
Section Name Update Description
4.0 “Memory Organization” • Table 4-13:
(Continued) - Changed register U4RG to U1BRG
- Changed register U5RG to U3BRG
- Changed register U6RG to U2BRG
• Table 4-14:
- Updated the All Resets values for the following registers: SPI3STAT,
SPI2STAT and SPI4STAT
• Table 4-15: Updated the All Resets values for the SPI1STAT register
• Table 4-17: Added note 2
• Table 4-19: Added note 2
• Table 4-20: Updated the All Resets values for the CM1CON and
CM2CON registers
• Table 4-21:
- Updated the All Resets values as 0000 for the CVRCON register
- Updated note 2
• Table 4-38: Updated the All Resets values for the PMSTAT register
• Table 4-40: Updated the All Resets values for the CHECON and
CHETAG registers
• Table 4-42: Updated the bit value of bit 29/13 as ‘—’ for the DEVCFG3
register
• Table 4-44:
- Updated the note references in the entire table
- Changed existing note 1 to note 4
- Added notes 1, 2 and 3
- Changed bits 23/7 in U1PWRC to UACTPND
- Changed register U1DDR to U1ADDR
- Changed register U4DTP1 to U1BDTP1
- Changed register U4DTP2 to U1BDTP2
- Changed register U4DTP3 to U1BDTP3
• Table 4-45:
- Updated the All Resets values for the C1CON and C1VEC registers
- Changed bits 30/14 in C1CON to FRZ
- Changed bits 27/11 in C1CON to CANBUSY
- Changed bits 22/6-16/0 in C1VEC to ICODE<6:0>
- Changed bits 22/6-16/0 in C1TREC to RERRCNT<7:0>
- Changed bits 31/15-24/8 in C1TREC to TERRCNT<7:0>
• Table 4-46:
- Updated the All Resets values for the C2CON and C2VEC registers
- Changed bits 30/14 in C1CON to FRZ
- Changed bits 27/11 in C1CON to CANBUSY
- Changed bits 22/6-16/0 in C1VEC register to ICODE<6:0>
- Changed bits 22/6-16/0 in C1TREC register to RERRCNT<7:0>
- Changed bits 31/15-24/8 in C1TREC to TERRCNT<7:0>

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PIC32MX5XX/6XX/7XX
TABLE B-4: SECTION UPDATES (CONTINUED)
Section Name Update Description
7.0 “Interrupt Controller” • Updated the following Interrupt Sources in Table 7-1:
- Changed IC2AM – I2C4 Master Event to: IC4M – I2C4 Master Event
- Changed IC3AM – I2C5 Master Event to: IC5M – I2C4 Master Event
- Changed U1E – UART1A Error to: U1E – UART1 Error
- Changed U4E – UART1B Error to: U4E – UART4 Error
- Changed U1RX – UART1A Receiver to: U1RX – UART1 Receiver
- Changed U4RX – UART1B Receiver to: U4RX – UART4 Receiver
- Changed U1TX – UART1A Transmitter to: U1TX – UART1 Transmitter
- Changed U4TX – UART1B Transmitter to: U4TX – UART4 Transmitter
- Changed U6E – UART2B Error to: U6E – UART6 Error
- Changed U6RX – UART2B Receiver to: U6RX – UART6 Receiver
- Changed U6TX – UART2B Transmitter to: U6TX – UART6 Transmitter
- Changed U5E – UART3B Error to: U5E – UART5 Error
- Changed U5RX – UART3B Receiver to: U5RX – UART5 Receiver
- Changed U5TX – UART3B Transmitter to: U5TX – UART5 Transmitter
1.0 “Oscillator Configuration” Updated Figure 1-1
1.0 “Output Compare” Updated Figure 1-1
1.0 “Ethernet Controller” Added a note on using the Ethernet controller pins (see note above
Table 1-3)
1.0 “Comparator Voltage Reference Updated the note in Figure 1-1
(CVREF)”
1.0 “Special Features” Updated the bit description for bit 10 in Register 1-2
Added notes 1 and 2 to Register 1-4
1.0 “Electrical Characteristics” Updated the Absolute Maximum Ratings:
• Voltage on any 5V tolerant pin with respect to VSS when VDD < 2.3V -
0.3V to +3.6V was updated
• Voltage on VBUS with respect to VSS - 0.3V to +5.5V was added
Updated the maximum value of DC16 as 2.1 in Table 1-4
Updated the Typical values for the following parameters: DC20b, DC20c,
DC21c, DC22c and DC23c (see Table 1-5)
Updated Table 1-11:
• Removed the following DC Characteristics: Programming temperature
0°C  TA  +70°C (25°C recommended)
• Updated the Minimum value for the Parameter number D131 as 2.3
• Removed the Conditions for the following Parameter numbers: D130,
D131, D132, D135, D136 and D137
• Updated the condition for the parameter number D130a and D132a
Updated the Minimum, Typical and Maximum values for parameter D305
in Table 1-13
Added note 2 to Table 1-18
Updated the Minimum and Maximum values for parameter F20b (see
Table 1-19)
Updated the following figures:
• Figure 1-4
• Figure 1-9
• Figure 1-22
• Figure 1-23
Appendix A: “Migrating from Removed the A.3 Pin Assignments sub-section.
PIC32MX3XX/4XX to PIC32MX5XX/
6XX/7XX Devices”

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 PIC32MX5XX/6XX/7XX
Revision G (May 2011) This revision also includes minor typographical and
formatting changes throughout the data sheet text.
The revision includes the following global updates: Major updates are referenced by their respective
• All references to VDDCORE/VCAP have been section in Table B-5.
changed to: VCORE/VCAP
• Added references to the new V-Temp temperature
range: -40ºC to +105ºC

TABLE B-5: MAJOR SECTION UPDATES

Section Name Update Description
High-Performance, USB, CAN and Removed the shading for all D- and D+ pins in all pin diagrams.
Ethernet 32-bit Flash Microcontrollers
1.0 “Device Overview” Updated the VBUS description in Table 1-1.
1.0 “Guidelines for Getting Started with Added “Alternatively, inputs can be reserved by connecting the pin
32-bit Microcontrollers” to Vss through a 1k to 10k resistor and configuring the pin as an
input.”.
4.0 “Memory Organization” Added Note 3 to the Interrupt Register Map tables (see Table 4-2 through
Table 4-7.
22.0 “10-bit Analog-to-Digital Converter Updated the ADC Conversion Clock Period Block Diagram (see
(ADC)” Figure 22-2).
1.0 “Comparator Voltage Reference Updated the Comparator Voltage Reference Block Diagram (see
(CVREF)” Figure 1-1).
1.0 “Special Features” Removed the second paragraph from 1.3.1 “On-Chip Regulator and
POR”.
1.0 “Electrical Characteristics” Added the new V-Temp temperature range (-40ºC to +105ºC) to the
heading of all specification tables.

Updated the Ambient temperature under bias, updated the Voltage on

any 5V tolerant pin with respect to VSS when VDD < 2.3V, and added
Voltage on VBUS with respect to Vss in Absolute Maximum Ratings.

Added the characteristic, DC5a to Operating MIPS vs. Voltage (see

Table 1-1).

Updated or added the following parameters to the Operating Current

(IDD) DC Characteristics: DC20, DC20b, DC23, and DC23b (see Table 1-
5).

Added the following parameters to the Idle Current (IIDLE) DC

Characteristics: DC30b, DC33b, DC34c, DC35c, and DC36c (see
Table 1-6).

Added the following parameters to the Power-down Current (IPD) DC

Characteristics: DC40g, DC40h, DC40i, and DC41g, (see Table 1-7).

Added parameter IM51 and Note 3 to the I2Cx Bus Data Timing
Requirements (Master Mode) (see Table 1-32).

Updated the 10-bit ADC Conversion Rate Parameters (see Table 1-37).

Updated parameter AD57 (TSAMP) in the Analog-to-Digital Conversion

Timing Requirements (see Table 1-38).
1.0 “Packaging Information” Updated the 64-Lead Plastic Quad Flat, No Lead Package (MR) –
9x9x0.9 mm Body [QFN] packing diagram.
Product Identification System Added the new V-Temp (V) temperature information.

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PIC32MX5XX/6XX/7XX
Revision H (March 2013) • All occurrences of VUSB have been updated to:
VUSB3V3
This revision includes the following global updates:
This revision also includes minor typographical and
• Where applicable, control register tables have formatting changes throughout the data sheet text.
been added to the document
All other significant changes are referenced by their
• All references to VCORE were removed
respective section in Table B-6.
• All occurrences of XBGA have been updated to:
TFBGA

TABLE B-6: MAJOR SECTION UPDATES

Section Name Update Description
“32-bit Microcontrollers Updated Core features.
(up to 512 KB Flash and 128 Added the VTLA to the Packages table.
KB SRAM) with Graphics Added Note 5 to the Feature tables (see Table 1, Table 2, and Table 3).
Interface, USB, CAN, and
Ethernet”
Section 2.0 “Guidelines for The Recommended Minimum Connection was updated (see Figure 2-1).
Getting Started with 32-bit
MCUs”
Section 5.0 “Flash Program A note regarding Flash page size and row size was added.
Memory”
Section 8.0 “Oscillator The RP resistor was added and Note 1 was updated in the Oscillator Diagram (see
Configuration” Figure 8-1).
Section 31.0 “Electrical Added Note 1 to Operating MIPS vs. Voltage (see Table 31-1).
Characteristics” Added the VTLA package to Thermal Packaging Characteristics (see Table 31-3).
Added Note 2 to DC Temperature and Voltage Specifications (see Table 31-4).
Updated Note 2 in the Operating Current DC Characteristics (see Table 31-5).
Updated Note 1 in the Idle Current DC Characteristics (see Table 31-6).
Updated Note 1 in the Power-Down Current DC Characteristics (see Table 31-7).
Updated the I/O Pin Output Specifications (see Table 31-9).
Added Note 2 to the BOR Electrical Characteristics (see Table 31-10).
Added Note 3 to the Comparator Specifications (see Table 31-13).
Parameter D320 (VCORE) was removed (see Table 31-15).
Updated the Minimum value for parameter OS50 (see Table 31-18).
Parameter SY01 (TPWRT) was removed (see Table 31-22).
Note 1 was added and the conditions for parameters ET3, ET4, ET7, and ET9 were
updated in the Ethernet Module Specifications (see Table 31-35).
Added Note 6 to the ADC Module Specifications (see Table 31-36).
Added Note 3 to the 10-bit ADC Conversion Rate Parameter (see Table 31-37).
Added Note 4 to the Analog-to-Digital Conversion Timing Requirements (see
Table 31-38).
The following figures were added:
Figure 31-19: “MDIO Sourced by the PIC32 Device”
Figure 31-21: “Transmit Signal Timing Relationships at the MII”
Figure 31-22: “Receive Signal Timing Relationships at the MII”
Section 32.0 “DC and AC This new chapter was added.
Device Characteristics
Graphs”
Section 33.0 “Packaging Added the 124-lead VTLA package information (see Section 33.1 “Package
Information” Marking Information” and Section 33.2 “Package Details”).
“Product Identification Added the TL definition for VTLA packages.
System”

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 PIC32MX5XX/6XX/7XX
Revision J (September 2016)
This revision includes typographical and formatting
updates throughout the data sheet text. In addition, all
SFR Register maps were moved from the Memory
chapter to their respective peripheral chapters.
All other major updates are referenced by their
respective section in Table B-7.

TABLE B-7: MAJOR SECTION UPDATES

Section Name Update Description
“32-bit Microcontrollers (up to 512 Updated Communication Interfaces for LIN support to 2.1.
KB Flash and 128 KB SRAM) with Updated Qualification and Class B Support to AEC-Q100 REVH.
Graphics Interface, USB, CAN, and
Ethernet”
2.0 “Guidelines for Getting Started The Recommended Minimum Connection diagram was updated (see
with 32-bit MCUs” Figure 2-1).
The Example of MCLR Pin Connections diagram was updated (see Figure 2-
2).
2.12 “EMI/EMC/EFT (IEC 61000-4-4 and IEC 61000-4-2) Suppression
Considerations” was added.
4.0 “Memory Organization” The SFR Memory Map was added (see Table 4-1).
7.0 “Interrupt Controller” The UART interrupt sources were updated in the Interrupt IRQ, Vector, and
Bit location table (see Table 7-1).
8.0 “Oscillator Configuration” Updated the bit value definitions for the TUN<5:0> bits in the OCSTUN
register (see Register 8-2).
15.0 “Watchdog Timer (WDT)” The content in this chapter was relocated from the Special Features chapter
to its own chapter.
18.0 “Serial Peripheral Interface The register map tables were combined (see Table 18-1).
(SPI)”
19.0 “Inter-Integrated Circuit (I2C)” The register map tables were combined (see Table 19-1).
The PMADDR register was updated (see Register 21-3).
21.0 “Parallel Master Port (PMP)” The bit value definitions for the ADRMUX<1:0> and CSF<1:0> bits in the
PMCON register were updated (see Register 21-1).
29.0 “Special Features” Removed the duplicate bit value definition for ‘010’ in the DEVCFG2 register
(see Register 29-3).
Note 1 was added to the Programming, Debugging, and Trace Ports block
diagram (see Figure 29-2).
The DDPCON register was relocated (see Register 29-6).
The Device ID, Revision, and Configuration Summary was updated (see
Table 29-2).

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PIC32MX5XX/6XX/7XX
TABLE B-7: MAJOR SECTION UPDATES (CONTINUED)
Section Name Update Description
32.0 “Electrical Characteristics” Note 4 in the Operating Current specification was updated (see Table 32-5).
Note 3 in the Idle Current specification was updated (see Table 32-6).
Note 6 references in the Power-Down Current specification were updated
(see Table 32-7).
The Program Memory parameters, D135, D136, and D137, and Note 4 were
updated (see Table 32-11).
The Voltage Reference Specifications were updated (see Table 32-14).
Parameter DO50 (Cosco) was added to the Capacitive Loading
Requirements on Output Pins (see Table 32-16).
The EJTAG Timing Characteristics were updated (see Figure 32-28).
The maximum value for parameters ET13 and ET14 were updated in the
Ethernet Module Specifications (see Table 32-35).
Parameter PM7 (TDHOLD) was updated (see Table 32-40).
34.0 “Packaging Information” Packaging diagrams were updated.
Product Identification System The Speed and Program Memory Size were updated and Note 1 was added.

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 PIC32MX5XX/6XX/7XX
Revision K (September 2019)
This revision includes typographical and formatting
updates throughout the data sheet text. In addition, all
SFR Register maps were moved from the Memory
chapter to their respective peripheral chapters.
All other major updates are referenced by their
respective section in Table B-8.

TABLE B-8: MAJOR SECTION UPDATES

Section Name Update Description
7.0 “Interrupt Controller” Updated the U3 and U2 bit names in the following Register Maps:
• TABLE 7-2: “Interrupt Register Map for PIC32MX534F064H,
PIC32MX564F064H, PIC32MX564F128H, PIC32MX575F256H and
PIC32MX575F512H Devices”
• TABLE 7-3: “Interrupt Register Map for PIC32MX664F064H,
PIC32MX664F128H, PIC32MX675F256H, PIC32MX675F512H and
PIC32MX695F512H Devices”
• TABLE 7-4: “Interrupt Register Map for PIC32MX764F128H,
PIC32MX775F256H, PIC32MX775F512H and PIC32MX795F512H
Devices”
• TABLE 7-5: “Interrupt Register Map for PIC32MX534F064L,
PIC32MX564F064L, PIC32MX564F128L PIC32MX575F512L and
PIC32MX575F256L Devices”
• TABLE 7-6: “Interrupt Register Map for PIC32MX664F064L,
PIC32MX664F128L, PIC32MX675F256L, PIC32MX675F512L and
PIC32MX695F512L Devices”
• TABLE 7-7: “Interrupt Register Map for PIC32MX764F128L,
PIC32MX775F256L, PIC32MX775F512L and PIC32MX795F512L
Devices”
18.0 “Serial Peripheral Interface Updated the FRMPOL bit description in Register 18-1: “SPIx CON: SPI
(SPI)” Control Register”
20.0 “Universal Asynchronous Updated FIGURE 20-3: “Transmission (8-bit or 9-bit Data)”
Receiver Transmitter (UART)”
21.0 “Parallel Master Port (PMP)” Updated bit 10 for Register 21-2: “PMMODE: Parallel Port Mode Register”

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PIC32MX5XX/6XX/7XX
NOTES:

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 PIC32MX5XX/6XX/7XX
INDEX
A Graphs and Tables ................................................... 403
DC Characteristics............................................................ 356
AC Characteristics ............................................................ 370
I/O Pin Input Specifications ...................................... 364
10-bit Conversion Rate Parameters.......................... 394
I/O Pin Output Specifications.................................... 366
ADC Specifications ................................................... 392
Idle Current (IIDLE) .................................................... 360
Analog-to-Digital Conversion Requirements............. 395
Power-Down Current (IPD)........................................ 362
EJTAG Timing Requirements ................................... 402
Program Memory...................................................... 367
Ethernet .................................................................... 390
Temperature and Voltage Specifications.................. 357
Internal FRC Accuracy.............................................. 372
Development Support ....................................................... 351
Internal RC Accuracy ................................................ 373
Direct Memory Access (DMA) Controller.......................... 115
OTG Electrical Specifications ................................... 401
Parallel Master Port Read Requirements ................. 399 E
Parallel Master Port Write ......................................... 400
Electrical Characteristics .................................................. 355
Parallel Master Port Write Requirements.................. 400
AC............................................................................. 370
Parallel Slave Port Requirements ............................. 398
Errata .................................................................................. 23
PLL Clock Timing...................................................... 372
Ethernet Controller............................................................ 283
Analog-to-Digital Converter (ADC).................................... 235
ETHPMM0 (Ethernet Controller Pattern Match Mask 0)... 293
B ETHPMM1 (Ethernet Controller Pattern Match Mask 1)... 293
Block Diagrams External Clock
ADC1 Module............................................................ 235 Timer1 Timing Requirements ................................... 376
Timer2, 3, 4, 5 Timing Requirements ....................... 377
Comparator I/O Operating Modes............................. 327
Comparator Voltage Reference ................................ 331 Timing Requirements ............................................... 371
Connections for On-Chip Voltage Regulator............. 347 F
Core and Peripheral Modules ..................................... 25
Flash Program Memory ...................................................... 67
DMA .......................................................................... 115
RTSP Operation ......................................................... 67
Ethernet Controller.................................................... 283
I2C Circuit ................................................................. 200 I
Input Capture ............................................................ 185 I/O Ports ........................................................................... 161
Interrupt Controller ...................................................... 77
Parallel I/O (PIO) ...................................................... 162
JTAG Programming, Debugging and Trace Ports .... 347 Input Capture .................................................................... 185
MCU............................................................................ 45 Instruction Set................................................................... 349
Output Compare Module........................................... 189
Inter-Integrated Circuit (I2C) ............................................. 199
PIC32 CAN Module................................................... 245 Internal Voltage Reference Specifications........................ 369
PMP Pinout and Connections to External Devices ... 215 Internet Address ............................................................... 443
Prefetch Module........................................................ 105
Interrupt Controller.............................................................. 77
Reset System.............................................................. 73 IRG, Vector and Bit Location ...................................... 78
RTCC ........................................................................ 225
SPI Module ............................................................... 193 M
Timer1....................................................................... 171 MCU
Timer2/3/4/5 (16-Bit) ................................................. 175 Architecture Overview ................................................ 46
Typical Multiplexed Port Structure ............................ 161 Coprocessor 0 Registers ............................................ 47
UART ........................................................................ 207 Core Exception Types ................................................ 48
WDT and Power-up Timer ........................................ 181 EJTAG Debug Support............................................... 49
Brown-out Reset (BOR) Power Management ................................................... 49
and On-Chip Voltage Regulator................................ 347 MCU Module....................................................................... 45
C Memory Map....................................................................... 56
Memory Maps ............................................. 52, 53, 54, 55, 57
C Compilers
Memory Organization ......................................................... 51
MPLAB XC................................................................ 352
Layout......................................................................... 51
Clock Diagram .................................................................... 99
Microchip Internet Web Site.............................................. 443
Comparator
Migration
Specifications............................................................ 368
PIC32MX3XX/4XX to PIC32MX5XX/6XX/7XX......... 423
Comparator Module .......................................................... 327
MPASM Assembler........................................................... 352
Comparator Voltage Reference (CVref ............................. 331
MPLAB Assembler, Linker, and Librarian......................... 352
Configuration Bits.............................................................. 337
MPLAB ICD 3 In-Circuit Debugger System ...................... 353
Controller Area Network (CAN)......................................... 245
MPLAB PM3 Device Programmer .................................... 353
CPU Module........................................................................ 37
MPLAB REAL ICE In-Circuit Emulator System ................ 353
Customer Change Notification Service ............................. 443
MPLAB X Integrated Development Environment Software ....
Customer Notification Service........................................... 443
351
Customer Support ............................................................. 443
MPLINK Object Linker/MPLIB Object Librarian ................ 352
D O
DC and AC Characteristics
Open-Drain Configuration................................................. 162

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PIC32MX5XX/6XX/7XX
Oscillator Configuration....................................................... 99 CiFLTCON4 (CAN Filter Control 4) .......................... 268
Output Compare................................................................ 189 CiFLTCON5 (CAN Filter Control 5) .......................... 270
CiFLTCON6 (CAN Filter Control 6) .......................... 272
P CiFLTCON7 (CAN Filter Control 7) .......................... 274
Packaging ......................................................................... 405 CiFSTAT (CAN FIFO Status).................................... 257
Details ....................................................................... 407 CiINT (CAN Interrupt) ............................................... 254
Marking ..................................................................... 405 CiRXFn (CAN Acceptance Filter ‘n’)......................... 276
Parallel Master Port (PMP) ............................................... 215 CiRXMn (CAN Acceptance Filter Mask ‘n’) .............. 259
PIC32 Family USB Interface Diagram............................... 138 CiRXOVF (CAN Receive FIFO Overflow Status) ..... 258
PICkit 3 In-Circuit Debugger/Programmer ........................ 353 CiTMR (CAN Timer) ................................................. 258
Pinout I/O Descriptions (table) ............................................ 26 CiTREC (CAN Transmit/Receive Error Count) ......... 257
Power-on Reset (POR) CiVEC (CAN Interrupt Code) .................................... 256
and On-Chip Voltage Regulator ................................ 347 CMSTAT (Comparator Control Register).................. 330
Power-Saving Features..................................................... 335 CMxCON (Comparator ’x’ Control) ........................... 329
CPU Halted Methods ................................................ 335 CNCON (Change Notice Control)............................. 170
Operation .................................................................. 335 CVRCON (Comparator Voltage Reference Control) 333
with CPU Running..................................................... 335 DCHxCON (DMA Channel ’x’ Control) ..................... 128
Prefetch Cache ................................................................. 105 DCHxCPTR (DMA Channel ’x’ Cell Pointer)............. 135
Program Flash Memory DCHxCSIZ (DMA Channel ’x’ Cell-Size) .................. 135
Wait State Characteristics......................................... 367 DCHxDAT (DMA Channel ’x’ Pattern Data).............. 136
DCHxDPTR (Channel ’x’ Destination Pointer).......... 134
R DCHxDSA (DMA Channel ’x’ Destination
Real-Time Clock and Calendar (RTCC)............................ 225 Start Address)................................................... 132
Register Maps ............................................................. 59–287 DCHxDSIZ (DMA Channel ’x’ Destination Size)....... 133
Registers DCHxECON (DMA Channel ’x’ Event Control)......... 129
AD1CHS (ADC Input Select) .................................... 243 DCHxINT (DMA Channel ’x’ Interrupt Control) ......... 130
AD1CON1 (ADC Control 1) ...................................... 239 DCHxSPTR (DMA Channel ’x’ Source Pointer)........ 134
AD1CON2 (ADC Control 2) ...................................... 241 DCHxSSA (DMA Channel ’x’ Source Start Address) 132
AD1CON3 (ADC Control 3) ...................................... 242 DCHxSSIZ (DMA Channel ’x’ Source Size).............. 133
AD1CSSL (ADC Input Scan Select) ......................... 244 DCRCCON (DMA CRC Control)............................... 125
ALRMDATE (Alarm Date Value) ............................... 234 DCRCDATA (DMA CRC Data) ................................. 127
ALRMTIME (Alarm Time Value) ............................... 233 DCRCXOR (DMA CRCXOR Enable) ....................... 127
BMXBOOTSZ (Boot Flash (IFM) Size) ....................... 65 DDPCON (Debug Data Port Control) ....................... 346
BMXCON (Bus Matrix Configuration) ......................... 60 DEVCFG0 (Device Configuration Word 0................. 339
BMXDKPBA (Data RAM Kernel Program DEVCFG1 (Device Configuration Word 1................. 341
Base Address) .................................................... 61 DEVCFG2 (Device Configuration Word 2................. 343
BMXDRMSZ (Data RAM Size) ................................... 64 DEVCFG3 (Device Configuration Word 3................. 345
BMXDUDBA (Data RAM User Data Base Address) ... 62 DEVID (Device and Revision ID) .............................. 346
BMXDUPBA (Data RAM User Program DMAADDR (DMA Address) ...................................... 124
Base Address) .................................................... 63 DMACON (DMA Controller Control) ......................... 123
BMXPFMSZ (Program Flash (PFM) Size) .................. 65 DMASTAT (DMA Status) .......................................... 124
BMXPUPBA (Program Flash (PFM) User Program EMAC1CFG1 (Ethernet Controller MAC Configuration 1)
Base Address) .................................................... 64 310
CHEACC (Cache Access) ........................................ 108 EMAC1CFG2 (Ethernet Controller MAC Configuration 2)
CHECON (Cache Control) ........................................ 107 311
CHEHIT (Cache Hit Statistics) .................................. 113 EMAC1CLRT (Ethernet Controller MAC Collision Win-
CHELRU (Cache LRU) ............................................. 112 dow/Retry Limit)................................................ 315
CHEMIS (Cache Miss Statistics) .............................. 113 EMAC1IPGR (Ethernet Controller MAC Non-Back-to-
CHEMSK (Cache TAG Mask) ................................... 110 Back Interpacket Gap)...................................... 314
CHETAG (Cache TAG) ............................................. 109 EMAC1IPGT (Ethernet Controller MAC Back-to-Back In-
CHEW0 (Cache Word 0)........................................... 110 terpacket Gap).................................................. 313
CHEW1 (Cache Word 1)........................................... 111 EMAC1MADR (Ethernet Controller MAC MII Manage-
CHEW2 (Cache Word 2)........................................... 111 ment Address) .................................................. 321
CHEW3 (Cache Word 3)........................................... 112 EMAC1MAXF (Ethernet Controller MAC Maximum
CiCFG (CAN Baud Rate Configuration).................... 252 Frame Length) .................................................. 316
CiCON (CAN Module Control) .................................. 250 EMAC1MCFG (Ethernet Controller MAC MII Manage-
CiFIFOBA (CAN Message Buffer Base Address) ..... 277 ment Configuration) .......................................... 319
CiFIFOCINn (CAN Module Message Index Register ‘n’) EMAC1MCMD (Ethernet Controller MAC MII Manage-
282 ment Command)............................................... 320
CiFIFOCONn (CAN FIFO Control Register ‘n’)......... 278 EMAC1MIND (Ethernet Controller MAC MII Manage-
CiFIFOINTn (CAN FIFO Interrupt Register ‘n’) ......... 280 ment Indicators)................................................ 323
CiFIFOUAn (CAN FIFO User Address Register ‘n’).. 282 EMAC1MRDD (Ethernet Controller MAC MII Manage-
CiFLTCON0 (CAN Filter Control 0)........................... 260 ment Read Data) .............................................. 322
CiFLTCON1 (CAN Filter Control 1)........................... 262 EMAC1MWTD (Ethernet Controller MAC MII Manage-
CiFLTCON2 (CAN Filter Control 2)........................... 264 ment Write Data) .............................................. 322
CiFLTCON3 (CAN Filter Control 3)........................... 266

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 PIC32MX5XX/6XX/7XX
EMAC1SA0 (Ethernet Controller MAC Station Address RTCCON (RTC Control)........................................... 227
0)....................................................................... 324 RTCDATE (RTC Date Value) ................................... 232
EMAC1SA1 (Ethernet Controller MAC Station Address RTCTIME (RTC Time Value).................................... 231
1)....................................................................... 325 SPIxCON (SPI Control) ............................................ 195
EMAC1SA2 (Ethernet Controller MAC Station Address SPIxSTAT (SPI Status) ............................................ 197
2)....................................................................... 326 T1CON (Type A Timer Control)................................ 173
EMAC1SUPP (Ethernet Controller MAC PHY Support) . TPTMR (Temporal Proximity Timer)........................... 94
317 TxCON (Type B Timer Control) ................................ 178
EMAC1TEST (Ethernet Controller MAC Test) .......... 318 U1ADDR (USB Address).......................................... 154
ETHALGNERR (Ethernet Controller Alignment Errors U1BDTP1 (USB BDT Page 1) .................................. 156
Statistics) .......................................................... 309 U1BDTP2 (USB BDT Page 2) .................................. 157
ETHCON1 (Ethernet Controller Control 1)................ 288 U1BDTP3 (USB BDT Page 3) .................................. 157
ETHCON2 (Ethernet Controller Control 2)................ 290 U1CNFG1 (USB Configuration 1)............................. 158
ETHFCSERR (Ethernet Controller Frame Check Se- U1CON (USB Control).............................................. 152
quence Error Statistics) .................................... 308 U1EIE (USB Error Interrupt Enable)......................... 150
ETHFRMRXOK (Ethernet Controller Frames Received U1EIR (USB Error Interrupt Status).......................... 149
OK Statistics) .................................................... 307 U1EP0-U1EP15 (USB Endpoint Control) ................. 159
ETHFRMTXOK (Ethernet Controller Frames Transmit- U1FRMH (USB Frame Number High) ...................... 155
ted OK Statistics) .............................................. 304 U1FRML (USB Frame Number Low)........................ 154
ETHHT0 (Ethernet Controller Hash Table 0) ............ 292 U1IE (USB Interrupt Enable) .................................... 148
ETHHT1 (Ethernet Controller Hash Table 1) ............ 292 U1IR (USB Interrupt) ................................................ 147
ETHIEN (Ethernet Controller Interrupt Enable)......... 298 U1OTGCON (USB OTG Control) ............................. 145
ETHIRQ (Ethernet Controller Interrupt Request) ...... 299 U1OTGIE (USB OTG Interrupt Enable).................... 143
ETHMCOLFRM (Ethernet Controller Multiple Collision U1OTGIR (USB OTG Interrupt Status) .................... 142
Frames Statistics) ............................................. 306 U1OTGSTAT (USB OTG Status) ............................. 144
ETHPM0 (Ethernet Controller Pattern Match Offset) 294 U1PWRC (USB Power Control) ............................... 146
ETHPMCS (Ethernet Controller Pattern Match Check- U1SOF (USB SOF Threshold) ................................. 156
sum) .................................................................. 294 U1STAT (USB Status).............................................. 151
ETHRXFC (Ethernet Controller Receive Filter Configura- U1TOK (USB Token)................................................ 155
tion) ................................................................... 295 UxMODE (UARTx Mode) ......................................... 211
ETHRXOVFLOW (Ethernet Controller Receive Overflow UxSTA (UARTx Status and Control) ........................ 213
Statistics) .......................................................... 303 WDTCON (Watchdog Timer Control) ....................... 183
ETHRXST (Ethernet Controller RX Packet Descriptor Resets ................................................................................ 73
Start Address) ................................................... 291 Revision History................................................................ 424
ETHRXWM (Ethernet Controller Receive Watermarks) . RTCALRM (RTC ALARM Control).................................... 229
297
ETHSCOLFRM (Ethernet Controller Single Collision S
Frames Statistics) ............................................. 305 Serial Peripheral Interface (SPI) ....................................... 193
ETHSTAT (Ethernet Controller Status)..................... 301 Software Simulator (MPLAB X SIM) ................................. 353
ETHTXST (Ethernet Controller TX Packet Descriptor Special Features............................................................... 337
Start Address) ................................................... 291
I2CxCON (I2C Control) ............................................. 203
T
I2CxSTAT (I2C Status) ............................................. 205 Timer1 Module.................................................................. 171
ICxCON (Input Capture ’x’ Control) .......................... 187 Timer2/3, Timer4/5 Modules............................................. 175
IECx (Interrupt Enable Control)................................... 95 Timing Diagrams
IFSx (Interrupt Flag Status)......................................... 95 10-bit Analog-to-Digital Conversion (ASAM = 0, SS-
INTCON (Interrupt Control)......................................... 93 RC<2:0> = 000)................................................ 396
INTSTAT (Interrupt Status) ......................................... 94 10-bit Analog-to-Digital Conversion (ASAM = 1, SS-
IPCx (Interrupt Priority Control)................................... 96 RC<2:0> = 111, SAMC<4:0> = 00001) ............ 397
NVMADDR (Flash Address) ....................................... 70 CAN I/O .................................................................... 389
NVMCON (Programming Control) .............................. 69 EJTAG ...................................................................... 402
NVMDATA (Flash Program Data) ............................... 71 External Clock .......................................................... 370
NVMKEY (Programming Unlock)................................ 70 I/O Characteristics .................................................... 373
NVMSRCADDR (Source Data Address)..................... 71 I2Cx Bus Data (Master Mode) .................................. 385
OCxCON (Output Compare ’x’ Control).................... 191 I2Cx Bus Data (Slave Mode) .................................... 387
OSCCON (Oscillator Control) ................................... 101 I2Cx Bus Start/Stop Bits (Master Mode)................... 385
OSCTUN (FRC Tuning) ............................................ 104 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 387
PFABT (Prefetch Cache Abort Statistics) ................. 114 Input Capture (CAPx) ............................................... 378
PMADDR (Parallel Port Address) ............................. 221 OCx/PWM................................................................. 379
PMAEN (Parallel Port Pin Enable)............................ 222 Output Compare (OCx) ............................................ 378
PMCON (Parallel Port Control) ................................. 217 Parallel Master Port Read ........................................ 399
PMMODE (Parallel Port Mode) ................................. 219 Parallel Master Port Write......................................... 400
PMSTAT (Parallel Port Status (Slave Modes only)... 223 Parallel Slave Port .................................................... 398
RCON (Reset Control) ................................................ 75 SPIx Master Mode (CKE = 0) ................................... 380
RSWRST (Software Reset) ........................................ 76 SPIx Master Mode (CKE = 1) ................................... 381
SPIx Slave Mode (CKE = 0) ..................................... 382

 2009-2019 Microchip Technology Inc. DS60001156K-page 441

PIC32MX5XX/6XX/7XX
SPIx Slave Mode (CKE = 1)...................................... 383
Timer1, 2, 3, 4, 5 External Clock............................... 376
UART Reception ....................................................... 208
UART Transmission (8-bit or 9-bit Data)................... 208
Timing Requirements
CLKO and I/O ........................................................... 373
Timing Specifications
CAN I/O Requirements ............................................. 389
I2Cx Bus Data Requirements (Master Mode) ........... 386
I2Cx Bus Data Requirements (Slave Mode) ............. 388
Input Capture Requirements ..................................... 378
Output Compare Requirements ................................ 378
Simple OCx/PWM Mode Requirements.................... 379
SPIx Master Mode (CKE = 0) Requirements ............ 380
SPIx Master Mode (CKE = 1) Requirements ............ 381
SPIx Slave Mode (CKE = 1) Requirements .............. 383
SPIx Slave Mode Requirements (CKE = 0) .............. 382

U
UART ................................................................................ 207
USB On-The-Go (OTG) .................................................... 137

V
VCAP pin ............................................................................ 347
Voltage Reference Specifications ..................................... 369
Voltage Regulator (On-Chip)............................................. 347

W
Watchdog Timer (WDT) .................................................... 181
WWW Address.................................................................. 443
WWW, On-Line Support...................................................... 23

DS60001156K-page 442  2009-2019 Microchip Technology Inc.

 PIC32MX5XX/6XX/7XX
THE MICROCHIP WEB SITE CUSTOMER SUPPORT
Microchip provides online support via our WWW site at Users of Microchip products can receive assistance
www.microchip.com. This web site is used as a means through several channels:
to make files and information easily available to • Distributor or Representative
customers. Accessible by using your favorite Internet
• Local Sales Office
browser, the web site contains the following
information: • Field Application Engineer (FAE)
• Technical Support
• Product Support – Data sheets and errata,
application notes and sample programs, design Customers should contact their distributor,
resources, user’s guides and hardware support representative or Field Application Engineer (FAE) for
documents, latest software releases and archived support. Local sales offices are also available to help
software customers. A listing of sales offices and locations is
• General Technical Support – Frequently Asked included in the back of this document.
Questions (FAQ), technical support requests, Technical support is available through the web site
online discussion groups, Microchip consultant at: http://microchip.com/support
program member listing
• Business of Microchip – Product selector and
ordering guides, latest Microchip press releases,
listing of seminars and events, listings of
Microchip sales offices, distributors and factory
representatives

CUSTOMER CHANGE NOTIFICATION

SERVICE
Microchip’s customer notification service helps keep
customers current on Microchip products. Subscribers
will receive e-mail notification whenever there are
changes, updates, revisions or errata related to a
specified product family or development tool of interest.
To register, access the Microchip web site at
www.microchip.com. Under “Support”, click on
“Customer Change Notification” and follow the
registration instructions.

 2009-2019 Microchip Technology Inc. DS60001156K-page 443

 PIC32MX5XX/6XX/7XX
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.

PIC32 MX 5XX F 512 H T - 80 I / PT - XXX Example:

PIC32MX575F256H-80I/PT:
Microchip Brand General purpose PIC32,
Architecture 32-bit RISC MCU,
256 KB program memory,
Product Groups 64-pin, Industrial temperature,
TQFP package.
Flash Memory Family
Program Memory Size (KB)
Pin Count
Tape and Reel Flag (if applicable)
Speed (see Note 1)
Temperature Range
Package
Pattern

Flash Memory Family

Architecture MX = 32-bit RISC MCU core

Product Groups 5XX = General purpose microcontroller family

6XX = General purpose microcontroller family
7XX = General purpose microcontroller family

Flash Memory Family F = Flash program memory

Program Memory Size 64 = 64K

128 = 128K
256 = 256K
512 = 512K

Pin Count H = 64-pin

L = 100-pin, 121-pin, 124-pin

Speed (see Note 1) Blank or 80 = 80 MHz

Temperature Range I = -40°C to +85°C (Industrial)

V = -40°C to +105°C (V-Temp)

Package PT = 64-Lead (10x10x1 mm) TQFP (Thin Quad Flatpack)

PT = 100-Lead (12x12x1 mm) TQFP (Thin Quad Flatpack)
PF = 100-Lead (14x14x1 mm) TQFP (Thin Quad Flatpack)
MR = 64-Lead (9x9x0.9 mm) QFN (Plastic Quad Flat)
BG = 121-Lead (10x10x1.1 mm) TFBGA (Plastic Thin Profile Ball Grid Array)
TL = 124-Lead (9x9x0.9 mm) VTLA (Very Thin Leadless Array)

Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise)

ES = Engineering Sample

Note 1: This option is not available for PIC32MX534/564/664/764 devices.

 2009-2019 Microchip Technology Inc. DS60001156K-page 444

Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.

• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”

Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our
products. Attempts to break Microchip’s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Information contained in this publication regarding device Trademarks

applications and the like is provided only for your convenience The Microchip name and logo, the Microchip logo, Adaptec,
and may be superseded by updates. It is your responsibility to AnyRate, AVR, AVR logo, AVR Freaks, BesTime, BitCloud, chipKIT,
ensure that your application meets with your specifications. chipKIT logo, CryptoMemory, CryptoRF, dsPIC, FlashFlex,
flexPWR, HELDO, IGLOO, JukeBlox, KeeLoq, Kleer, LANCheck,
MICROCHIP MAKES NO REPRESENTATIONS OR LinkMD, maXStylus, maXTouch, MediaLB, megaAVR, Microsemi,
WARRANTIES OF ANY KIND WHETHER EXPRESS OR Microsemi logo, MOST, MOST logo, MPLAB, OptoLyzer,
IMPLIED, WRITTEN OR ORAL, STATUTORY OR PackeTime, PIC, picoPower, PICSTART, PIC32 logo, PolarFire,
OTHERWISE, RELATED TO THE INFORMATION, Prochip Designer, QTouch, SAM-BA, SenGenuity, SpyNIC, SST,
INCLUDING BUT NOT LIMITED TO ITS CONDITION, SST Logo, SuperFlash, Symmetricom, SyncServer, Tachyon,
TempTrackr, TimeSource, tinyAVR, UNI/O, Vectron, and XMEGA
QUALITY, PERFORMANCE, MERCHANTABILITY OR are registered trademarks of Microchip Technology Incorporated in
FITNESS FOR PURPOSE. Microchip disclaims all liability the U.S.A. and other countries.
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at APT, ClockWorks, The Embedded Control Solutions Company,
the buyer’s risk, and the buyer agrees to defend, indemnify and EtherSynch, FlashTec, Hyper Speed Control, HyperLight Load,
IntelliMOS, Libero, motorBench, mTouch, Powermite 3, Precision
hold harmless Microchip from any and all damages, claims, Edge, ProASIC, ProASIC Plus, ProASIC Plus logo, Quiet-Wire,
suits, or expenses resulting from such use. No licenses are SmartFusion, SyncWorld, Temux, TimeCesium, TimeHub,
conveyed, implicitly or otherwise, under any Microchip TimePictra, TimeProvider, Vite, WinPath, and ZL are registered
intellectual property rights unless otherwise stated. trademarks of Microchip Technology Incorporated in the U.S.A.

Adjacent Key Suppression, AKS, Analog-for-the-Digital Age, Any

Capacitor, AnyIn, AnyOut, BlueSky, BodyCom, CodeGuard,
CryptoAuthentication, CryptoAutomotive, CryptoCompanion,
CryptoController, dsPICDEM, dsPICDEM.net, Dynamic Average
Matching, DAM, ECAN, EtherGREEN, In-Circuit Serial
Programming, ICSP, INICnet, Inter-Chip Connectivity, JitterBlocker,
KleerNet, KleerNet logo, memBrain, Mindi, MiWi, MPASM, MPF,
MPLAB Certified logo, MPLIB, MPLINK, MultiTRAK, NetDetach,
Omniscient Code Generation, PICDEM, PICDEM.net, PICkit,
PICtail, PowerSmart, PureSilicon, QMatrix, REAL ICE, Ripple
Blocker, SAM-ICE, Serial Quad I/O, SMART-I.S., SQI,
SuperSwitcher, SuperSwitcher II, Total Endurance, TSHARC,
USBCheck, VariSense, ViewSpan, WiperLock, Wireless DNA, and
ZENA are trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.

SQTP is a service mark of Microchip Technology Incorporated in

the U.S.A.
The Adaptec logo, Frequency on Demand, Silicon Storage
Technology, and Symmcom are registered trademarks of Microchip
Technology Inc. in other countries.
GestIC is a registered trademark of Microchip Technology Germany
II GmbH & Co. KG, a subsidiary of Microchip Technology Inc., in
other countries.
All other trademarks mentioned herein are property of their
respective companies.

© 2009-2019, Microchip Technology Incorporated, All Rights

Reserved.
For information regarding Microchip’s Quality Management Systems,
please visit www.microchip.com/quality. ISBN: 978-1-5224-4828-0

 2009-2019 Microchip Technology Inc. 60001156K-page 445

 Worldwide Sales and Service
AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE
Corporate Office Australia - Sydney India - Bangalore Austria - Wels
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Tel: 480-792-7200 Tel: 86-10-8569-7000 Tel: 91-11-4160-8631 Denmark - Copenhagen
Fax: 480-792-7277 Tel: 45-4450-2828
China - Chengdu India - Pune
Technical Support: Fax: 45-4485-2829
Tel: 86-28-8665-5511 Tel: 91-20-4121-0141
http://www.microchip.com/
China - Chongqing Japan - Osaka Finland - Espoo
support Tel: 358-9-4520-820
Tel: 86-23-8980-9588 Tel: 81-6-6152-7160
Web Address:
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Tel: 905-695-1980
Fax: 905-695-2078

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05/14/19