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LIFO 16x8 RAM

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100 views6 pages

LIFO 16x8 RAM

Uploaded by

Cregan
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Download as PDF, TXT or read online on Scribd
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Gopu Krishnan G

BPRN 12

Q. Write a RTL and a task-based test bench for the 16x8


last-in-first-out RAM memory
1 module LIFO_16x8(
2 input clock, resetn,
3 input write_enb, read_enb,
4 input [7:0] data_in,
5 output full, empty,
6 output reg [7:0] data_out
7 );
8 reg [4:0] wr_ptr, rd_ptr;
9 reg [7:0] lifo [15:0];
10 integer i;
11
12 always @(posedge clock)
13 begin
14 if (!resetn) begin
15 for(i = 0; i < 16; i = i + 1) begin
16 lifo[i] <= 8'd0;
17 end
18 wr_ptr <= 5'd0;
19 end
20 else if (write_enb && !full) begin
21 lifo[wr_ptr] <= data_in;
22 wr_ptr <= (wr_ptr + 1'b1);
23 end
24 end
25
26 always @(posedge clock)
27 begin
28 if (!resetn) begin
29 data_out <= 8'd0;
30 rd_ptr <= 5'd15;
31 end
32 else if (read_enb && !empty) begin
33 data_out <= lifo[rd_ptr];
34 rd_ptr <= (rd_ptr - 1'b1);
35 end
36 end
37
38 assign full = (wr_ptr == ~rd_ptr) ? 1'b1 : 1'b0;
39 //assign full = (wr_ptr == 5'b10000 && rd_ptr == 5'b01111) ? 1'b1 : 1'b0;
40
41 assign empty = (wr_ptr == {rd_ptr[4], ~rd_ptr[3:0]}) ? 1'b1 : 1'b0;
42 //assign empty = (wr_ptr == 5'b00000 && rd_ptr == 5'b01111)||(wr_ptr == 5'b10000 && rd_ptr == 5'b11111) ? 1'b1:1'b0;
43
44 endmodule
1 module LIFO_16x8_tb;
2 reg clk, resetn, write_enb, read_enb;
3 reg [7:0] data_in;
4 wire full, empty;
5 wire [7:0] data_out;
6 integer i;
7
8 LIFO_16x8 DUT (
9 .clock(clk),
10 .resetn(resetn),
11 .write_enb(write_enb),
12 .read_enb(read_enb),
13 .data_in(data_in),
14 .full(full),
15 .empty(empty),
16 .data_out(data_out)
17 );
18
19 initial begin
20 clk = 1'b0;
21 forever #5 clk = ~clk;
22 end
23
24 task reset();
25 begin
26 @(negedge clk);
27 resetn = 1'b0;
28 @(negedge clk);
29 resetn = 1'b1;
30 end
31 endtask
32
33 task initialize();
34 begin
35 write_enb = 1'b0;
36 read_enb = 1'b0;
37 resetn = 1'b1;
38 data_in = 8'd0;
39 end
40 endtask
41
42 task write(input [7:0]data);
43 begin
44 @(negedge clk);
45 write_enb = 1'b1;
46 read_enb = 1'b0;
47 data_in = data;
48 end
49 endtask
50
51 task delay();
52 begin
53 #10;
54 end
55 endtask
56
57 task read();
58 begin
59 @(negedge clk);
60 write_enb = 1'b0;
61 read_enb = 1'b1;
62 end
63 endtask
64
65 initial begin
66 initialize;
67 reset;
68 delay;
69 for(i = 0; i < 16; i = i + 1)
70 begin
71 write({$random} % 256);
72 end
73 read;
74 @(negedge clk);
75 wait(empty);
76 delay;
77 $finish;
78 end
79
80 initial begin
81 $monitor("data_out = %0h, full = %b, empty = %b, write_enb = %b, read_enb = %b, wr_ptr = %d, rd_ptr = %d",
82 data_out, full, empty, write_enb, read_enb, DUT.wr_ptr, DUT.rd_ptr);
83 end
84 endmodule

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