CH6- Centeral Processing Unit
CH6- Centeral Processing Unit
• Introduction
• Stack Organization
• Instruction Formats
• Addressing Modes
• Program Control
• Transfer Components
Bus
• Control Components
Control Unit Register
File ALU
Control Unit
REGISTERS
SELD
OPR ALU
Output
Control
ALU CONTROL
Encoding of ALU operations OPR
Select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 ADD A + B ADD
00101 Subtract A - B SUB
00110 Decrement A DECA
01000 AND A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift right A SHRA
11000 Shift left A SHLA
FULL EMPTY
Stack pointer 4
SP C 3
6 bits B 2
A 1
Push, Pop operations 0
DR
/* Initially, SP = 0, EMPTY = 1, FULL = 0 */
PUSH POP
SP SP + 1 DR M[SP]
M[SP] DR SP SP − 1
If (SP = 0) then (FULL 1) If (SP = 0) then (EMPTY 1)
EMPTY 0 FULL 0
Stack Organization
SP 3000
stack
3997
3998
3999
4000
4001
- A portion of memory is used as a stack with a Stack grows
processor register as a stack pointer In this direction
- PUSH: SP SP - 1
M[SP] DR
- POP: DR M[SP]
SP SP + 1
- Most computers do not provide hardware to check stack overflow (full
stack) or underflow (empty stack) → must be done in software
Stack Organization
(3 * 4) + (5 * 6) 34*56*+
6
4 5 5 30
3 3 12 12 12 12 42
3 4 * 5 6 * +
PROCESSOR ORGANIZATION
In general, most processors are organized in one of 3 ways
Stack organization
All operations are done using the hardware stack
For example, an OR instruction will pop the two top elements from the stack,
do a logical OR on them, and push the result on the stack
Instruction Format
INSTRUCTION FORMAT
• Instruction Fields
OP-code field - specifies the operation to be performed
Address field - designates memory address(es) or a processor register(s)
Mode field - determines how the address field is to be interpreted (to
get effective address or the operand)
• Two-Address Instructions
Program to evaluate X = (A + B) * (C + D) :
ADDRESSING MODES
• Addressing Modes
• Implied Mode
Address of the operands are specified implicitly
in the definition of the instruction
- No need to specify address in the instruction
- EA = AC, or EA = Stack[SP]
- Examples from Basic Computer
CLA, CME, INP
• Immediate Mode
Instead of specifying the address of the operand, operand itself
is specified
- No need to specify address in the instruction
- However, operand itself needs to be specified
- Sometimes, require more bits than the address
- Fast to acquire an operand
Addressing Modes
399 450
XR = 100
400 700
AC
500 800
600 900
In Basic Computer, the processor had several (status) flags – 1 bit value that indicated
various information about the processor’s state – E, FGI, FGO, I, IEN, R
In some processors, flags like these are often combined into a register – the processor
status register (PSR); sometimes called a processor status word (PSW)
Common flags in PSW are
C (Carry): Set to 1 if the carry out of the ALU is 1
S (Sign): The MSB bit of the ALU’s output
Z (Zero): Set to 1 if the ALU’s output is all 0’s
Status Flag Circuit
V (Overflow): Set to 1 if there is an overflow
A B
8 8
c7
c8 8-bit ALU
F7 - F0
V Z S C
F7
Check for 8
zero output
F
Program Control
PROGRAM INTERRUPT
Types of Interrupts
External interrupts
External Interrupts initiated from the outside of CPU and Memory
- I/O Device → Data transfer request or Data transfer complete
- Timing Device → Timeout
- Power Failure
- Operator
Software Interrupts
Both External and Internal Interrupts are initiated by the computer HW.
Software Interrupts are initiated by the executing an instruction.
- Supervisor Call → Switching from a user mode to the supervisor mode
→ Allows to execute a certain class of operations
which are not allowed in the user mode
Program Control
INTERRUPT PROCEDURE
Interrupt Procedure and Subroutine Call
- The interrupt is usually initiated by an internal or
an external signal rather than from the execution of
an instruction (except for the software interrupt)
Also, multiple operand instructions could specify different addressing modes for each
operand
For example,
Operand 1 could be a directly addressed register,
Operand 2 could be an indirectly addressed memory location,
Operand 3 (the destination) could be an indirectly addressed register.
All of this led to the need to have different length instructions in different situations,
depending on the opcode and operands used
VARIABLE LENGTH INSTRUCTIONS
For example, an instruction that only specifies register operands may only be two
bytes in length
One byte to specify the instruction and addressing mode
One byte to specify the source and destination registers.
An instruction that specifies memory addresses for operands may need five bytes
One byte to specify the instruction and addressing mode
Two bytes to specify each memory address
Maybe more if there’s a large amount of memory.
Variable length instructions greatly complicate the fetch and decode problem for a
processor
The circuitry to recognize the various instructions and to properly fetch the required
number of bytes for operands is very complex
COMPLEX INSTRUCTION SET COMPUTER
Another characteristic of CISC computers is that they have instructions
that act directly on memory addresses
For example,
ADD L1, L2, L3
that takes the contents of M[L1] adds it to the contents of M[L2] and
stores the result in location M[L3]
An instruction like this takes three memory access cycles to execute
❑ Complex Instruction
✓ Micro program control storage takes substantial portion of CPU chip area
✓ General purpose instruction set includes all the features required by individually
different applications when any one application is running, all the features
required by the other applications are extra burden to the application
REDUCED INSTRUCTION SET COMPUTERS (RISC)
In the late ‘70s and early ‘80s there was a reaction to the shortcomings
of the CISC style of processors
Reduced Instruction Set Computers (RISC) were proposed as an
alternative
The underlying idea behind RISC processors is to simplify the
instruction set and reduce instruction execution time
RISC processors often feature:
Few instructions
Few addressing modes
Only load and store instructions access memory
All other operations are done using on-processor registers
Fixed length instructions
Single cycle execution of instructions
The control unit is hardwired, not microprogrammed
REDUCED INSTRUCTION SET COMPUTERS
Since all but the load and store instructions use only registers for
operands, only a few addressing modes are needed
By having all instructions the same length, reading them in is easy and
fast
The fetch and decode stages are simple, looking much more like Mano’s
Basic Computer than a CISC machine
The instruction and address formats are designed to be easy to decode
Unlike the variable length CISC instructions, the opcode and register
fields of RISC instructions can be decoded simultaneously
The control logic of a RISC processor is designed to be simple and fast
The control logic is simple because of the small number of instructions
and the simple addressing modes
The control logic is hardwired, rather than microprogrammed, because
hardwired control is faster
REGISTERS
CHARACTERISTICS OF RISC
• RISC Characteristics
- Relatively few instructions
- Relatively few addressing modes
- Memory access limited to load and store instructions
- All operations done within the registers of the CPU
- Fixed-length, easily decoded instruction format
- Single-cycle instruction format
- Hardwired rather than microprogrammed control
• Advantages of RISC
- VLSI Realization
- Computing Speed
- Design Costs and Reliability
- High Level Language Support
RISC
ADVANTAGES OF RISC
• VLSI Realization Example:
RISC I: 6%
Control area is considerably reduced RISC II: 10%
MC68020: 68%
general CISCs: ~50%
• Computing Speed
- Simpler, smaller control unit faster
- Simpler instruction set; addressing modes; instruction format
faster decoding
- Register operation faster than memory operation
- Register window enhances the overall speed of execution
- Identical instruction length, One cycle instruction execution
suitable for pipelining faster
RISC
ADVANTAGES OF RISC
• Design Costs and Reliability
- Shorter time to design
reduction in the overall design cost and
reduces the problem that the end product will
be obsolete by the time the design is completed
- Simpler, smaller control unit
higher reliability
- Simple instruction format (of fixed length)
ease of virtual memory management
? QUESTION
End!!