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Project Report Format for DLD

DLD project report format

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janmejayd2021
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10 views

Project Report Format for DLD

DLD project report format

Uploaded by

janmejayd2021
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as DOCX, PDF, TXT or read online on Scribd
You are on page 1/ 12

External Project Report

on Digital Logic Design


(EET1211)

[Topic Name-to
be filled up by
students]

Submitted by
Name 01 Reg. No.:
Name 02 Reg. No.:
Name 03 Reg. No.:
Name 04 Reg. No.:
B. Tech. CSE 3rd Semester (Section - I)

INSTITUTE OF TECHNICAL EDUCATION AND RESEARCH


(FACULTY OF ENGINEERING) i
SIKSHA ‘O’ ANUSANDHAN (DEEMED TO BE UNIVERSITY), BHUBANESWAR,
ODISHA
Declaration
We, the undersigned students of B. Tech. of (Write your Branch) Department hereby declare that
we own the full responsibility for the information, results etc. provided in this PROJECT titled
“(TOPIC NAME)” submitted to Siksha ‘O’ Anusandhan Deemed to be University, Bhubaneswar for
the partial fulfillment of the subject Digital Logic Design (EET 1211). We have taken care in all
respect to honor the intellectual property right and have acknowledged the contribution of others
for using them in academic purpose and further declare that in case of any violation of intellectual
property right or copyright we, as the candidate(s), will be fully responsible for the same.

(NAME1) (NAME2)

Registration No.: Registration No.:

(NAME3) (NAME4)

Registration No.: Registration No.:

DATE:

PLACE:

ii
Abstract
(to be written after the project is done. 100 – 200 words)

iii
Contents

Serial Chapter No. Title of the Chapter Page No.


No.

1. 1 Introduction

2. 2 Problem Statement

3. 3 Methodology

4. 4 Implementation

5. 5 Results and interpretation

6. 6 Conclusion

7. References

8. Appendices

iv
1. Introduction

Brief description of the project.

1
2. Problem Statement

I. Explanation of problem and identification of input and output variables.


II. Highlighting the constraints.

2
3. Methodology

I. Generating the solution to the problem by the use of Truth


table/excitation table, K- map and (or) Boolean algebra.
II. Finding out the different digital ICs to be used in the optimized design.

3
4. Implementation
I. Drawing the logic diagram using different logic gates.
II. Program

4
5. Results & Interpretation
Verification of the output for different inputs that satisfies the problem
statement by the use of truth table.

5
6. Conclusion

1
References
(as per the IEEE recommendations)

2
Appendices
Justification of the architecture / digital ICs used for implementation.
(Attach datasheets of the devices/ ICs that you have used)

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