Roll No.

JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

CIA-1 AY 2024-25 (ODD Semester)

Course : B. Tech. Date : 14.10.2024
Semester : V Subject Code : BEC-501
Subject : INTEGRATED CIRCUITS Max. Marks : 20
Time : 1 Hour

COURSE OUTCOMES
C301.1 Analyze and design basic digital IC circuits using CMOS technology
C301.2 Describe the functioning of application specific ICs such as 555 timer, VCO IC 566 and PLL
C301.3 Examine and design Op-amp based circuits and basic components of ICs such as various types of
C301.4 filters.
Implement the concept of Op-amp to design Op-amp based non-linear applications and wave-
shaping circuits
C301.5 Explain complete internal analysis of Op-Amp 741-IC

Section-A
Attempt all the questions of this section (1 X5=5)
Q. Mark
Question CO BL
No. s
a Draw the CMOS logic for NAND gate
The CMOS logic for NAND gate implementation is as shown below
𝐘 = ̅̅̅̅̅̅
𝑨 .𝑩

1 CO BL
1
. 1 1

Fig.: CMOS logic for NAND GATE

 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

b Differentiate between Latch and Flip-Flop

Any 2 difference → 0.5 Mark X 2 Points

Sl.
FLIP-FLOP LATCH
No.
1 Flip-flop is a bistable device i.e., Latch is also a bistable device
it has two stable states that are whose states are also
represented as 0 and 1. represented as 0 and 1.

2 It checks the inputs but changes It checks the inputs continuously

the output only at times defined and responds to the changes in
by the clock signal or any other inputs immediately.
control signal.

3 It is a edge triggered device. It is a level triggered device.

4 Gates like NOR, NOT, AND, These are also made up of gates. CO BL
1
NAND are building blocks of flip 1 1
flops.

5 They are classified into There is no such classification in

asynchronous or synchronous latches.
flipflops.
6 It forms the building blocks of These can be used for the
many sequential circuits like designing of sequential circuits
counters. but are not generally preferred.
7 Flip-flop always have a clock Latches doesn’t have a clock
signal signal
8 Flip-flop can be build from Latches can be build from gates
Latches

9 ex: D Flip-flop, JK Flip-flop ex: SR Latch, D Latch

c What is the role of PUN and PDN in CMOS realization?

CO BL
1 1
0.5
 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

As shown in Figure above, PMOS transistor is used as a pull-up transistor, so

its source is connected to supply voltage and drain is connected to the output
node.

Similarly, the NMOS transistor is used as a pull-down transistor. That means 0.5
its source terminal is connected to ground terminal and drain is connected
to output node and the gate terminals of both PMOS and NMOS transistor is
connected to the input.

d Draw the pin diagram of IC 555 timer

CO BL
1
2 1

e Calculate the pulse duration on monostable multivibrator using 555 timer

with R= 10 KΩ and C=0.01 µF.
𝑻 = 𝟏. 𝟏 𝑹𝑨 𝑪 0.5
CO BL
2 2
T = 1.1 X 10 𝐾𝛺 𝑋 0.01 µ𝑭
𝑻 = 𝟎. 𝟏𝟏 𝒎𝒔𝒆𝒄 0.5

Section-B
Attempt all the questions of this Section
(3X3=9)
Sketch the logic gate symbolic representation of a clocked SR flip-flop using
NAND gate. Also, sketch its CMOS circuit implementation and explain its
operation.

1
CO BL
2.
1 2
 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

OR
Discuss the D flip-flop implementation using CMOS. 1

2
 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Draw the functional block diagram and explain the operation of IC-555
timer.

CO BL
3.
2 2
Functional Block Diagram 1
Explanation 2
OR
Design an Astable Multivibrator using 555 Timer to generate an output
waveform of 2 KHz with a duty cycle of 50%
Given: 𝑓 = 2 𝐾𝐻𝑧 & 𝐷 = 50%
1 1
Solution: 𝑇 = 𝑓 = 2 𝐾𝐻𝑧 = 0.5 msec
We know that for 50% duty cycle,
TON = TOFF i.e., 𝑻𝑪 = 𝑻𝒅 = 𝟎. 𝟐𝟓 𝒎𝑺𝒆𝒄
𝑻𝑪 = 𝟎. 𝟔𝟗𝟑 𝑹𝑨 𝑪
Assuming 𝐶 = 0.01𝜇𝐹
𝑇𝐶
𝑅𝐴 =
0.693 𝐶
0.25 𝑚𝑠𝑒𝑐
= = 36.07 𝐾Ω
0.693 × 0.01 𝜇𝐹
𝑹𝑨 = 𝑹𝑩 = 𝟑𝟔. 𝟎𝟕 𝑲Ω

TON = TOFF i.e., 𝑻𝑪 = 𝑻𝒅 = 𝟎. 𝟐𝟓 𝒎𝑺𝒆𝒄 1

𝑹𝑨 = 𝑹𝑩 𝑪𝒂𝒍𝒄𝒖𝒍𝒂𝒕𝒊𝒐𝒏 1
C𝒊𝒓𝒄𝒖𝒊𝒕 𝑫𝒊𝒂𝒈𝒓𝒂𝒎 1
a. Explain the working principle of astable multivibrator using 555 timer
with functional block diagram. CO BL
4.
2 3
 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Figure: Astable Multivibrator internal diagram

Figure: Astable Multivibrator waveforms

Functional Block diagram & Waveform 1

𝑬𝒙𝒑𝒍𝒂𝒏𝒂𝒕𝒊𝒐𝒏 1

b. For the Astable Multivibrator, 𝑅𝐴 = 4.7 KΩ, 𝑅𝐵 = 1 KΩ and C = 1 µF.

Determine
i. The positive pulse width ' 𝑇𝐶 '
ii. The negative pulse width ' 𝑇𝑑 '
iii. Free-running frequency ' 𝑓 '
iv. Duty cycle.

Given: 𝑅𝐴 = 4.7 KΩ, 𝑅𝐵 = 1KΩ and C = 1µF.

Solution:
i. The positive pulse width ' 𝑻𝑪 '
 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

𝑇𝐶 = 0.693 [𝑅𝐴 + 𝑅𝐵 ]𝐶
𝑇𝐶 = 0.693 [4.7 𝐾Ω + 1 𝐾Ω] × 1µ𝐹
𝑇𝐶 = 3.933 𝑚𝑠𝑒𝑐
ii] The negative pulse width ' 𝑻𝒅 '

𝑇𝑑 = 0.693𝑅𝐵 𝐶
𝑇𝑑 = 0.693 × 1 𝐾Ω × 1 𝐾Ω × 10−6
𝑇𝑑 = 0.69𝑚𝑠𝑒𝑐
iii] Free-running frequency ' 𝒇 '
𝑻 = 𝑻𝑪 + 𝑻𝒅 = 3.933 𝑚𝑠𝑒𝑐 + 0.69 𝑚𝑠𝑒𝑐 = 𝟒. 𝟔𝟐𝟑 𝒎𝒔𝒆𝒄
𝟏
𝒇=
𝑻
1
𝑓=
4.62𝑚𝑠𝑒𝑐
𝒇 = 𝟐𝟏𝟔. 𝟑𝟏 𝑯𝒛

iv] Duty Cycle ‘D’

𝑇𝑐
𝐷= × 100 %
𝑇
3.933 × 10−3
𝐷= × 100
4.623 × 10−3
𝑫 = 𝟖𝟓. 𝟎𝟕 %

Calculation of i, ii, iii & iv 1

OR
Explain the working principle of monostable multivibrator using 555 timer
with functional block diagram and derive the expression for the frequency
of oscillation. Design a Monostable Multivibrator using 555 timer to obtain a
pulse width of 𝟏𝟎 𝐦𝐬𝐞𝐜.

𝑻 = 𝟏. 𝟏 𝑹𝑨 𝑪

𝑇
𝑅𝐴 𝐶 =
1.1 1
10 msec
𝑅𝐴 𝐶 =
1.1
𝑅𝐴 𝐶 = 9.09 msec

9.09msec
𝑅𝐴 = = 9.09 KΩ
1 µF
∴ 𝑹𝑨 = 𝟗. 𝟗 𝐊𝛀
1
1

Functional Block diagram & Waveform

Explanation
 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Monostable Multivibrator

Figure: Input Output waveforms of Monostable Multivibrator

DERIVATION OF PULSE WIDTH:

The voltage across the capacitor increases exponentially and is given

by:
−𝒕
𝑽𝑪 = 𝑽𝑪𝑪 [𝟏 − 𝒆𝑹𝑨 𝑪 ] → (1)
𝟐
At 𝒕 = 𝑻, 𝑽𝑪 = 𝟑 𝑽𝑪𝑪
1
Now equation (1) becomes
2 −𝑇
𝑉𝐶𝐶 = 𝑉𝐶𝐶 [1 − 𝑒 𝑅𝐴𝐶 ]
3
2 −𝑇
= 1 − 𝑒 𝑅𝐴 𝐶
3
 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

2 −𝑇
− 1 = −𝑒 𝑅𝐴𝐶
3
2−3 −𝑇
= −𝑒 𝑅𝐴𝐶
3
1 −𝑇
− = −𝑒 𝑅𝐴𝐶
3
−𝑇 1
𝑒 𝑅𝐴 𝐶 =
3
Taking ln on both sides of above equation
−𝑇 1
= 𝒍𝒏 [ ]
𝑅𝐴 𝐶 3
−𝑇
= −1.0996
𝑅𝐴 𝐶
−𝑇 = −1.0996 𝑅𝐴 𝐶
𝑻 = 𝟏. 𝟏 𝑹𝑨 𝑪 → (2)

1
𝑓=
𝑇
Section-C
Attempt all the questions of this Section (6X1=6)
a) Design 1-bit magnitude comparator.

Fig.: One bit comparator

The truth table for a 1-bit comparator is given below.

Individual Boolean 1-bit comparator
A B A>B A<B A=B
expression Boolean expression

0 0 0 0 1 ̅B
A ̅ ̅𝐁
Y (A=B) = 𝐀 ̅ +AB
CO BL
5.
1 0 1 0 0 ̅
AB ̅
Y (A>B) = 𝐀 𝐁 1 3

0 1 0 1 0 ̅B
A ̅B
Y (A<B) = 𝐀

1 1 0 0 1 AB Clubbed with 1st row

 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

The boolean expression to implement CMOS logic for 1-bit magnitude

comparator is given below for 𝑌(𝐴=𝐵) , 𝑌(𝐴<𝐵) and 𝑌(𝐴>𝐵)

𝒀(𝑨=𝑩) 𝒀(𝑨<𝑩) 𝒀(𝑨>𝑩)

𝒀(𝑨=𝑩) =𝑨 ‾𝑩 ‾ + 𝑨𝑩 𝒀(𝑨<𝑩) =𝑨 ‾𝑩 𝒀(𝑨>𝑩) = 𝐀𝑩 ‾

̅̅̅̅
‾
= ̅̅̅̅̅̅̅̅̅̅̅̅
𝑨‾𝑩 ‾ + 𝑨𝑩 = ̅̅̅̅
𝑨‾𝑩 = 𝐀𝑩
̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
= (𝑨̅̅̅̅
‾𝑩 ‾ ) ⋅ (𝑨𝑩
̅̅̅̅) ̅̅̅̅̅̅̅̅̅̅
= (𝐴‾̅ + 𝐵‾) = (𝐴 + 𝐵̅‾ )
‾
̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅ ̅̅̅̅̅̅̅̅̅̅ 𝒀(𝑨>𝑩) = ̅̅̅̅̅̅̅̅̅̅
(𝑨‾ + 𝑩) 1
̅ ̅
= (𝐴‾ + 𝐵‾) ⋅ (𝐴‾ + 𝐵‾ ) 𝒀(𝑨<𝑩) = (𝑨 +𝑩 ‾)
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐴 + 𝐵) ⋅ (𝐴‾ + 𝐵‾ )
= ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐴𝐴‾ + 𝐴𝐵‾ + 𝐴‾𝐵 + 𝐵𝐵‾
𝒀(𝑨=𝑩) = ̅̅̅̅̅̅̅̅̅̅̅̅
𝑨𝑩 ‾ +𝑨 ‾𝑩

Fig.: CMOS logic for 1-bit Magnitude Comparator

3
 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

b) Realize Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝐃 + 𝐀. (𝐁 + 𝐂) using CMOS logic. 1

OR
a) Sketch the logic gate symbolic representation of a clocked JK flip-flop
using CMOS inverter.

Fig.: Clocked JK Flip-Flop using NAND

̅̅̅̅̅̅̅̅̅̅̅̅̅̅
̅̅̅̅̅̅̅̅̅̅
‾ 𝐶𝐿𝐾 )𝑄‾ ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑄‾ = (𝐾𝑄
̅̅̅̅̅̅̅̅̅̅
𝐶𝐿𝐾 )𝑄
𝑄 = (𝐽𝑄

𝑸 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
( 𝑱‾ + 𝐐 + ̅̅̅̅̅̅
𝑪𝑳𝑲 ) . 𝑸 ‾ ‾ = ( ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
𝑸 𝑲‾ + 𝑸‾ + 𝑪𝑳𝑲
̅̅̅̅̅̅ ) . 𝑸
 Roll No.
JSS MAHAVIDYAPEETHA
JSS ACADEMY OF TECHNICAL EDUCATION, NOIDA
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING

Fig.: CMOS Logic for Clocked JK Flip-Flop using NAND

b) Implement Y = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(𝐀𝐁 + 𝐂)𝐃 using CMOS logic.

Dr. Kamal Kishore U Dr. Preeti Jaidka Dr. Arun Kumar G

5 EC-1 5 EC-2 5 EC-3

Dr. Chandra Shankar/ Dr. Chhaya Grover Dr. Arun Kumar G

Dr. Deependra Sharma NBA Coordinator HOD-ECE
Module Coordinator