Ch4 Modular Design of

Digital Circuits
Lecture 2: Encoders and Decoders

Content Reference: M. Morris Mano, and Michael D. Ciletti, “Digital Design with an introduction to Verilog HDL, VHDL, and
System Verilog”, Sixth Edition, Pearson, 2017
Note: Reference to images may be found as hyperlinks or in slide notes
What is in this lecture?
• Decoder
• Combinational Logic Implementation with Decoders
• Encoders
• Priority Encoder
Outline
Decoder
• Information are represented in digital systems by binary codes
• n bits is capable of representing 2n distinct elements
• Decoder: “A combinational circuit that converts binary information
from n input lines to a maximum of 2n unique output lines”
• If n bit code has unused combinations, decoder may have fewer
output lines
• In general n-to-m-line decoders are used, where m≤2n
• Decoder also refers to converters, e.g.: BCD-to-seven-segment
decoder
Three-to-Eight-Line Decoder
• Three inputs are decoded to 8 outputs
• Each represents a minterm
Truth Table of a Three-to-Eight-Line Decoder
x y z D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Three-to-Eight-Line Decoder cont…
• A particular application of this decoder is binary-to-octal conversion
 NAND Gate Decoders
• Some decoders are constructed with NAND gates
• It becomes more economical to generate the decoder minterms in
their complemented form

A
D0 D1 D2 D3
B
0 1 1 1
Only one output can be equal to
0 at any given time; all other
1 0 1 1 outputs are equal to 1

1 1 0 1

1 1 1 0
Decoders with Enable
• The Decoder is Enabled when E=0 (NAND Gate Decoder)

E
Truth Table
A
x A B D0 D1 D2 D3
B 1 X X 1 1 1 1
D0 0 0 0 0 1 1 1
0 0 1 1 0 1 1
D1 0 1 0 1 1 0 1
0 1 1 1 1 1 0
D2

D3
Decoder as Demultiplexer
• Demultiplexer: “A circuit that receives information from a single line and directs
it to one of 2n possible output lines”
• Thus, a decoder with an enable input is referred to as a decoder – demultiplexer
I

B
A and B decide to which output line the
input “I” should be directed into
Combining Decoders
• Decoders with enable inputs can be connected together to form a
larger decoder circuit

4×16 decoder constructed with two 3×8 decoders

Combinational Logic Implementation
• Any Boolean function can be expressed in sum-of-minterms
• Decoder that generates the minterms
• With an external OR gate that forms their logical sum, of required
minterms, the output function can be generated
• In general, n inputs and m outputs
• Implemented with an n-to-2n-line decoder
• m OR gates
Combinational Logic Example (Full Adder)
• First we need to represent outputs in terms of minterms

x y z C S minterm
0 0 0 0 0 0 𝐶 𝑥, 𝑦, 𝑧 = ෍ 3,5,6,7
0 0 1 0 1 1
0 1 0 0 1 2
0 1 1 1 0 3
1 0 0 0 1 4
1 0 1 1 0 5
1 1 0 1 0 6
1 1 1 1 1 7
Combinational Logic Example (Full Adder)
cont…
• First we need to represent outputs in terms of minterms

x y z C S minterm
0 0 0 0 0 0 𝐶 𝑥, 𝑦, 𝑧 = ෍ 3,5,6,7
0 0 1 0 1 1
0 1 0 0 1 2
𝑆 𝑥, 𝑦, 𝑧 = ෍ 1,2,4,7
0 1 1 1 0 3
1 0 0 0 1 4
1 0 1 1 0 5
1 1 0 1 0 6
1 1 1 1 1 7
Combinational Logic Example (Full Adder)
cont…
• Or gates can be used to get the logical sum

0
1 𝐶 𝑥, 𝑦, 𝑧 = ෍ 3,5,6,7
S
x 22 2
3×8 3 𝑆 𝑥, 𝑦, 𝑧 = ෍ 1,2,4,7
y 21
decoder 4
z 20 5
6
C
7

Implementation of a full adder with a decoder

Complemented Form
• If the number of minterms (say k) of a function F with n inputs is
greater than 2n/2
• Instead of a k input OR gate, a 2n – k input NOR gate can be used
• Minterms of F’ is chosen instead of that of F
• This is done when 2n – k<k

Minterms of S is used Minterms of S’ is used

Combinational Logic with NAND gate
Decoders
• In NAND Gate decoders the minterms go to 0.
• Thus, is if any minterm goes to zero the output should go to 1
• ! Any input goes to zero output goes to 1 is a NAND Gate
• Thus, instead of logical sum with OR, NAND combines the minterns
Encoders
• An encoder is a digital circuit that performs the inverse operation of a
decoder
• It has 2n (or fewer) input lines and n output lines
Octal-To-Binary Encoder
• It is assumed that only one input has a value of 1 at any given time

Truth Table of an Octal-to-Binary Encoder

D0 D1 D2 D3 D4 D5 D6 D7 x y z
1 0 0 0 0 0 0 0 0 0 0
0 1 0 0 0 0 0 0 0 0 1
0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Octal-To-Binary Encoder cont…
• It is assumed that only one input has a value of 1 at any given time

Truth Table of an Octal-to-Binary Encoder

D0 D1 D2 D3 D4 D5 D6 D7 x y z Z is 1 when, input octal digit is, 1, 3, 5 or 7
1 0 0 0 0 0 0 0 0 0 0 Thus,
0 1 0 0 0 0 0 0 0 0 1 z = D1 + D3 + D5 + D7

0 0 1 0 0 0 0 0 0 1 0
0 0 0 1 0 0 0 0 0 1 1
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Octal-To-Binary Encoder cont…
• It is assumed that only one input has a value of 1 at any given time

Truth Table of an Octal-to-Binary Encoder

D0 D1 D2 D3 D4 D5 D6 D7 x y z Z is 1 when, input octal digit is, 1, 3, 5 or 7
1 0 0 0 0 0 0 0 0 0 0 Thus,
0 1 0 0 0 0 0 0 0 0 1 z = D1 + D3 + D5 + D7
Similarly,
0 0 1 0 0 0 0 0 0 1 0 y = D2 + D3 + D6 + D7
0 0 0 1 0 0 0 0 0 1 1 x = D4 + D5 + D6 + D7
0 0 0 0 1 0 0 0 1 0 0
0 0 0 0 0 1 0 0 1 0 1
0 0 0 0 0 0 1 0 1 1 0
0 0 0 0 0 0 0 1 1 1 1
Octal-To-Binary Encoder cont…

D0 D1 D2 D3 D4 D5 D6 D7

z = D1 + D3 + D5 + D7
y y = D2 + D3 + D6 + D7
x = D4 + D5 + D6 + D7

x
Limitations of the OR Gate Design
• Suppose D3 and D6 is 1
D0 D1 D2 D3 D4 D5 D6 D7
simultaneously
z • Then, xyz becomes 111.
• But 111, corresponds to nither
D6 or D3
y
• ! Ambiguity
• Solution:
x • Use priority, e.g.: if D6 is high
lower lines are not considered
(D3 is not considered here)
Limitations of the OR Gate Design cont…
• If all bits are 0 output is xyz is
0 0 0 0 0 0 0 0
000
0 • But that is output for D0
• ! Ambiguity
0
• Solution:
• Add additional output to show
validity (check at least one input
is high)
0
Limitations of the OR Gate Design Summary
• Ambiguity during multiple input highs
• Solution: Priority Encoder
• Ambiguity when all inputs are low
• Solution: Validity bit
Priority Encoder
• A priority encoder is an encoder circuit that includes the priority
function
• If two or more inputs are equal to 1 at the same time, the input
having the highest priority will take precedence
Priority Encoder Example
• 4 input to 2 output encoder
• Higher subscript has higher priority

Increasing Priority

D0 D1 D2 D3 x y
0 0
0 1
1 0
1 1
Priority Encoder Example cont…
• 4 input to 2 output encoder
• Higher subscript has higher priority

Increasing Priority

D0 D1 D2 D3 x y
0 0
0 1
1 0
X X X 1 1 1

If D3 is 1 the value of lower of lower inputs do not matter

Priority Encoder Example cont…
• 4 input to 2 output encoder
• Higher subscript has higher priority

Increasing Priority

D0 D1 D2 D3 x y
0 0
0 1
X X 1 0 1 0
X X X 1 1 1

If D2 is 1 the value of lower of lower inputs do not matter

But the higher priority D3 should be zero
Priority Encoder Example cont…
• 4 input to 2 output encoder
• Higher subscript has higher priority

Increasing Priority

D0 D1 D2 D3 x y
1 0 0 0 0 0
X 1 0 0 0 1
X X 1 0 1 0
X X X 1 1 1
Priority Encoder Example cont…
D 2D 3
• 4 input to 2 output encoder D 0D 1 00 01 11 10

• Higher subscript has higher priority 00

01

Increasing Priority 11

D0 D1 D2 D3 x y 10 0

1 0 0 0 0 0 Map for x
X 1 0 0 0 1
X X 1 0 1 0
X X X 1 1 1
Priority Encoder Example cont…
D 2D 3
• 4 input to 2 output encoder D 0D 1 00 01 11 10

• Higher subscript has higher priority 00

01 0

Increasing Priority 11 0

D0 D1 D2 D3 x y 10 0

1 0 0 0 0 0 Map for x
X 1 0 0 0 1
X X 1 0 1 0
X X X 1 1 1
Priority Encoder Example cont…
D 2D 3
• 4 input to 2 output encoder D 0D 1 00 01 11 10

• Higher subscript has higher priority 00 1

01 0 1

Increasing Priority 11 0 1

D0 D1 D2 D3 x y 10 0 1

1 0 0 0 0 0 Map for x
X 1 0 0 0 1
X X 1 0 1 0
X X X 1 1 1
Priority Encoder Example cont…
D 2D 3
• 4 input to 2 output encoder D 0D 1 00 01 11 10
• Higher subscript has higher priority
00 1 1 1
• D2=1,D3=1
01 0 1 1 1

Increasing Priority 11 0 1 1 1

D0 D1 D2 D3 x y 10 0 1 1 1

1 0 0 0 0 0 Map for x
X 1 0 0 0 1
X X 1 0 1 0
X X X 1 1 1
Priority Encoder Example cont…
D 2D 3
• 4 input to 2 output encoder D 0D 1 00 01 11 10

• Higher subscript has higher priority 00 X 1 1 1

01 0 1 1 1

11 0 1 1 1

10 0 1 1 1

Map for x
𝑥 = 𝐷2 + 𝐷3
Priority Encoder Example cont…
D 2D 3
• 4 input to 2 output encoder D 0D 1 00 01 11 10
• Higher subscript has higher priority
00 X 1 1 0
• D1=1,D3=1
01 1 1 1 0

Increasing Priority 11 1 1 1 0

D0 D1 D2 D3 x y 10 0 1 1 0

1 0 0 0 0 0 Map for y
X 1 0 0 0 1
y = 𝐷3 + 𝐷1 𝐷2′
X X 1 0 1 0
X X X 1 1 1

𝑥 = 𝐷2 + 𝐷3
Priority Encoder Example cont…
• 4 input to 2 output encoder
• Higher subscript has higher priority

D3
y y = 𝐷3 + 𝐷1 𝐷2′
D2

D1

x 𝑥 = 𝐷2 + 𝐷3
D0
Priority Encoder with Validity Output
• Output is valid if any input is high
• Which can be checked with a OR gate

D3
y
D2

D1

V
D0
References
[1] M. Morris Mano, and Michael D. Ciletti, “Digital Design with an
introduction to Verilog HDL, VHDL, and System Verilog”, Sixth Edition,
Pearson, 2017 – Chapter 4.5