M24512

512 Kbit Serial I²C Bus EEPROM

FEATURES SUMMARY
■ Two-Wire I2C Serial Interface Figure 1. Packages
Supports 400 kHz Protocol
■ Supply Voltage Ranges:
– 1.8V to 5.5V (M24512 − R)
– 2.5V to 5.5V (M24512 − W)
■ Write Control Input
■ BYTE and PAGE WRITE (up to 128 Bytes) 8
■ RANDOM and SEQUENTIAL READ Modes
■ Self-Timed Programming Cycle
■ Automatic Address Incrementing 1
■ Enhanced ESD/Latch-Up Protection
■ More than 100,000 Erase/Write Cycles PDIP8 (BN)

■ More than 40-Year Data Retention

Table 1. M24512 devices

Reference Part Number 8
M24512 − W
M24512
M24512 − R 1
SO8 (MW)
208 mil width

1
SO8 (MN)
150 mil width

TSSOP8 (DW)

February 2005 1/24

M24512

TABLE OF CONTENTS
FEATURES SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 1. M24512 devices. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 1. Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Figure 2. Logic Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Signal Names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Power On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. DIP, SO and TSSOP Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Clock (SCL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Serial Data (SDA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Chip Enable (E0, E1, E2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Write Control (WC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus . . . . . . . . . . . . 5
Figure 5. I2C Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 3. Device Select Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 4. Most Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Table 5. Least Significant Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

DEVICE OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Start Condition. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Stop Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Acknowledge Bit (ACK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Data Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Memory Addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. Write Mode Sequences with WC=1 (data write inhibited) . . . . . . . . . . . . . . . . . . . . . . . . . 8
Write Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Byte Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Page Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 7. Write Mode Sequences with WC=0 (data write enabled) . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. Write Cycle Polling Flowchart using ACK . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Minimizing System Delays by Polling On ACK. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 9. Read Mode Sequences . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Read Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Random Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current Address Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Sequential Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Acknowledge in Read Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

INITIAL DELIVERY STATE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

MAXIMUM RATING. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 7. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

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 M24512

DC AND AC PARAMETERS. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 8. Operating Conditions (M24512 – W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 9. Operating Conditions (M24512 – R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 10. AC Measurement Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 10.AC Measurement I/O Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Table 11. Input Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 12. DC Characteristics (M24512 – W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 13. DC Characteristics(1) (M24512 – R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table 14. AC Characteristics (M24512 – W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 15. AC Characteristics(1) (M24512 – R) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 11.AC Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

PACKAGE MECHANICAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12.PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline . . . . . . . . . . . . . . . . . 18
Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data . . . . . . . . . . 18
Figure 13.SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Outline . . . . . . . . 19
Table 17. SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Mechanical Data . 19
Figure 14.SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Outline . . . . . . . . . 20
Table 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data . 20
Figure 15.TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline . . . . . . . . . . . . . . . . . . . 21
Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data . . . . . . . . . . . . 21

PART NUMBERING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 20. Ordering Information Scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

REVISION HISTORY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 21. Document Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

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M24512

SUMMARY DESCRIPTION ter. The Start condition is followed by a Device

2 Select Code and Read/Write bit (RW) (as de-
These I C-compatible electrically erasable pro-
scribed in Table 3.), terminated by an acknowl-
grammable memory (EEPROM) devices are orga-
edge bit.
nized as 64K x 8 bits.
When writing data to the memory, the device in-
serts an acknowledge bit during the 9th bit time,
Figure 2. Logic Diagram following the bus master’s 8-bit transmission.
When data is read by the bus master, the bus
master acknowledges the receipt of the data byte
VCC in the same way. Data transfers are terminated by
a Stop condition after an Ack for Write, and after a
NoAck for Read.
3 Power On Reset
E0-E2 In order to prevent data corruption and inadvertent
SDA
Write operations during Power-up, a Power On
M24512 Reset (POR) circuit is included. At Power-up, the
SCL device will not respond to any command until VCC
has reached the Power On Reset threshold volt-
WC age (this threshold is lower than the VCC min oper-
ating voltage defined in Tables 8 and 9). In the
same way, as soon as VCC drops from the normal
operating voltage, below the Power On Reset
VSS threshold voltage, the device stops to respond to
AI02275 any command.
Prior to selecting and issuing commands to the
memory, a valid and stable VCC voltage must be
applied. This voltage must remain stable and valid
until the end of the transmission of the command
Table 2. Signal Names and, for a Write instruction, until the completion of
the internal write cycle (tW).
E0, E1, E2 Chip Enable

SDA Serial Data Figure 3. DIP, SO and TSSOP Connections

SCL Serial Clock

WC Write Control

VCC Supply Voltage M24512

VSS Ground E0 1 8 VCC

E1 2 7 WC
E2 3 6 SCL
I2C uses a two-wire serial interface, comprising a VSS 4 5 SDA
bi-directional data line and a clock line. The devic-
AI04035B
es carry a built-in 4-bit Device Type Identifier code
(1010) in accordance with the I2C bus definition.
The device behaves as a slave in the I2C protocol,
with all memory operations synchronized by the
serial clock. Read and Write operations are initiat- Note: See PACKAGE MECHANICAL section for package dimen-
ed by a Start condition, generated by the bus mas- sions, and how to identify pin-1.

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 M24512

SIGNAL DESCRIPTION
Serial Clock (SCL). This input signal is used to Chip Enable (E0, E1, E2). These input signals
strobe all data in and out of the device. In applica- are used to set the value that is to be looked for on
tions where this signal is used by slave devices to the three least significant bits (b3, b2, b1) of the 7-
synchronize the bus to a slower clock, the bus bit Device Select Code. These inputs must be tied
master must have an open drain output, and a to VCC or VSS, to establish the Device Select
pull-up resistor must be connected from Serial Code. When not connected (left floating), these in-
Clock (SCL) to VCC. (Figure 4. indicates how the puts are read as Low (0,0,0).
value of the pull-up resistor can be calculated). In Write Control (WC). This input signal is useful
most applications, though, this method of synchro- for protecting the entire contents of the memory
nization is not employed, and so the pull-up resis- from inadvertent write operations. Write opera-
tor is not necessary, provided that the bus master tions are disabled to the entire memory array when
has a push-pull (rather than open drain) output. Write Control (WC) is driven High. When uncon-
Serial Data (SDA). This bi-directional signal is nected, the signal is internally read as VIL, and
used to transfer data in or out of the device. It is an Write operations are allowed.
open drain output that may be wire-OR’ed with When Write Control (WC) is driven High, Device
other open drain or open collector signals on the Select and Address bytes are acknowledged,
bus. A pull up resistor must be connected from Se- Data bytes are not acknowledged.
rial Data (SDA) to VCC. (Figure 4. indicates how
the value of the pull-up resistor can be calculated).

Figure 4. Maximum RP Value versus Bus Parasitic Capacitance (C) for an I2C Bus

VCC
20
Maximum RP value (kΩ)

16
RP RP
12
SDA

8 MASTER C
fc = 100kHz SCL

4
fc = 400kHz C

0
10 100 1000
C (pF)
AI01665b

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M24512

Figure 5. I2C Bus Protocol

SCL

SDA

SDA SDA
START Input Change STOP
Condition Condition

SCL 1 2 3 7 8 9

SDA MSB ACK

START
Condition

SCL 1 2 3 7 8 9

SDA MSB ACK

STOP
Condition
AI00792B

Table 3. Device Select Code

Device Type Identifier1 Chip Enable Address2 RW

b7 b6 b5 b4 b3 b2 b1 b0
Device Select Code 1 0 1 0 E2 E1 E0 RW
Note: 1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared against the respective external pins on the memory device.

Table 4. Most Significant Byte Table 5. Least Significant Byte

b15 b14 b13 b12 b11 b10 b9 b8 b7 b6 b5 b4 b3 b2 b1 b0

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 M24512

DEVICE OPERATION
The device supports the I2C protocol. This is sum- Data (SDA) Low to acknowledge the receipt of the
marized in Figure 5.. Any device that sends data eight data bits.
on to the bus is defined to be a transmitter, and Data Input
any device that reads the data to be a receiver.
The device that controls the data transfer is known During data input, the device samples Serial Data
as the bus master, and the other as the slave de- (SDA) on the rising edge of Serial Clock (SCL).
vice. A data transfer can only be initiated by the For correct device operation, Serial Data (SDA)
must be stable during the rising edge of Serial
bus master, which will also provide the serial clock
for synchronization. The M24512 device is always Clock (SCL), and the Serial Data (SDA) signal
must change only when Serial Clock (SCL) is driv-
a slave in all communication.
en Low.
Start Condition
Memory Addressing
Start is identified by a falling edge of Serial Data
To start communication between the bus master
(SDA) while Serial Clock (SCL) is stable in the
High state. A Start condition must precede any and the slave device, the bus master must initiate
a Start condition. Following this, the bus master
data transfer command. The device continuously
monitors (except during a Write cycle) Serial Data sends the Device Select Code, shown in Table 3.
(on Serial Data (SDA), most significant bit first).
(SDA) and Serial Clock (SCL) for a Start condition,
and will not respond unless one is given. The Device Select Code consists of a 4-bit Device
Stop Condition Type Identifier, and a 3-bit Chip Enable “Address”
(E2, E1, E0). To address the memory array, the 4-
Stop is identified by a rising edge of Serial Data bit Device Type Identifier is 1010b.
(SDA) while Serial Clock (SCL) is stable and driv-
Up to eight memory devices can be connected on
en High. A Stop condition terminates communica-
tion between the device and the bus master. A a single I2C bus. Each one is given a unique 3-bit
code on the Chip Enable (E0, E1, E2) inputs.
Read command that is followed by NoAck can be
followed by a Stop condition to force the device When the Device Select Code is received, the de-
into the Stand-by mode. A Stop condition at the vice only responds if the Chip Enable Address is
end of a Write command triggers the internal Write the same as the value on the Chip Enable (E0, E1,
cycle. E2) inputs.
Acknowledge Bit (ACK) The 8th bit is the Read/Write bit (RW). This bit is
set to 1 for Read and 0 for Write operations.
The acknowledge bit is used to indicate a success-
ful byte transfer. The bus transmitter, whether it be If a match occurs on the Device Select code, the
bus master or slave device, releases Serial Data corresponding device gives an acknowledgment
(SDA) after sending eight bits of data. During the on Serial Data (SDA) during the 9th bit time. If the
9th clock pulse period, the receiver pulls Serial device does not match the Device Select code, it
deselects itself from the bus, and goes into Stand-
by mode.

Table 6. Operating Modes

Mode RW bit WC 1 Bytes Initial Sequence

Current Address Read 1 X 1 START, Device Select, RW = 1

0 X START, Device Select, RW = 0, Address
Random Address Read 1
1 X reSTART, Device Select, RW = 1
Sequential Read 1 X ≥1 Similar to Current or Random Address Read
Byte Write 0 VIL 1 START, Device Select, RW = 0
Page Write 0 VIL ≤ 128 START, Device Select, RW = 0
Note: 1. X = VIH or VIL.

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M24512

Figure 6. Write Mode Sequences with WC=1 (data write inhibited)

WC

ACK ACK ACK NO ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

STOP
R/W

WC

ACK ACK ACK NO ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2
START

R/W

WC (cont'd)

NO ACK NO ACK

PAGE WRITE DATA IN N

(cont'd)
STOP

AI01120C

Write Operations When the bus master generates a Stop condition

Following a Start condition the bus master sends immediately after the Ack bit (in the “10th bit” time
a Device Select Code with the Read/Write bit slot), either at the end of a Byte Write or a Page
(RW) reset to 0. The device acknowledges this, as Write, the internal Write cycle is triggered. A Stop
shown in Figure 7., and waits for two address condition at any other time slot does not trigger the
bytes. The device responds to each address byte internal Write cycle.
with an acknowledge bit, and then waits for the After the Stop condition, the delay tW, and the suc-
data byte. cessful completion of a Write operation, the de-
Writing to the memory may be inhibited if Write vice’s internal address counter is incremented
Control (WC) is driven High. Any Write instruction automatically, to point to the next byte address af-
with Write Control (WC) driven High (during a pe- ter the last one that was modified.
riod of time from the Start condition until the end of During the internal Write cycle, Serial Data (SDA)
the two address bytes) will not modify the memory is disabled internally, and the device does not re-
contents, and the accompanying data bytes are spond to any requests.
not acknowledged, as shown in Figure 6.. Byte Write
Each data byte in the memory has a 16-bit (two After the Device Select code and the address
byte wide) address. The Most Significant Byte (Ta- bytes, the bus master sends one data byte. If the
ble 4.) is sent first, followed by the Least Signifi- addressed location is Write-protected, by Write
cant Byte (Table 5.). Bits b15 to b0 form the Control (WC) being driven High, the device replies
address of the byte in memory. with NoAck, and the location is not modified. If, in-
stead, the addressed location is not Write-protect-

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 M24512

ed, the device replies with Ack. The bus master data starts to become overwritten in an implemen-
terminates the transfer by generating a Stop con- tation dependent way.
dition, as shown in Figure 7. The bus master sends from 1 to 128 bytes of data,
Page Write each of which is acknowledged by the device if
The Page Write mode allows up to 128 bytes to be Write Control (WC) is Low. If Write Control (WC) is
written in a single Write cycle, provided that they High, the contents of the addressed memory loca-
are all located in the same ’row’ in the memory: tion are not modified, and each data byte is fol-
that is, the most significant memory address bits lowed by a NoAck. After each byte is transferred,
(b15-b7) are the same. If more bytes are sent than the internal byte address counter (the 7 least sig-
will fit up to the end of the row, a condition known nificant address bits only) is incremented. The
as ‘roll-over’ occurs. This should be avoided, as transfer is terminated by the bus master generat-
ing a Stop condition.

Figure 7. Write Mode Sequences with WC=0 (data write enabled)

WC

ACK ACK ACK ACK

BYTE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN

START

STOP
R/W

WC

ACK ACK ACK ACK

PAGE WRITE DEV SEL BYTE ADDR BYTE ADDR DATA IN 1 DATA IN 2
START

R/W

WC (cont'd)

ACK ACK

PAGE WRITE DATA IN N

(cont'd)
STOP

AI01106C

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M24512

Figure 8. Write Cycle Polling Flowchart using ACK

WRITE Cycle
in Progress

START Condition

DEVICE SELECT
with RW = 0

NO ACK
Returned

First byte of instruction YES

with RW = 0 already
decoded by the device

Next
NO Operation is YES
Addressing the
Memory
Send Address
and Receive ACK
ReSTART

STOP NO START YES

Condition

DATA for the DEVICE SELECT

WRITE Operation with RW = 1

Continue the Continue the

WRITE Operation Random READ Operation AI01847C

Minimizing System Delays by Polling On ACK – Initial condition: a Write cycle is in progress.
During the internal Write cycle, the device discon- – Step 1: the bus master issues a Start condition
nects itself from the bus, and writes a copy of the followed by a Device Select Code (the first
data from its internal latches to the memory cells. byte of the new instruction).
The maximum Write time (tw) is shown in Table – Step 2: if the device is busy with the internal
14., but the typical time is shorter. To make use of Write cycle, no Ack will be returned and the
this, a polling sequence can be used by the bus bus master goes back to Step 1. If the device
master. has terminated the internal Write cycle, it
The sequence, as shown in Figure 8., is: responds with an Ack, indicating that the
device is ready to receive the second part of
the instruction (the first byte of this instruction
having been sent during Step 1).

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 M24512

Figure 9. Read Mode Sequences

ACK NO ACK
CURRENT
ADDRESS DEV SEL DATA OUT
READ

START

STOP
R/W

ACK ACK ACK ACK NO ACK

RANDOM
ADDRESS DEV SEL * BYTE ADDR BYTE ADDR DEV SEL * DATA OUT
READ
START

START

STOP
R/W R/W

ACK ACK ACK NO ACK

SEQUENTIAL
CURRENT DEV SEL DATA OUT 1 DATA OUT N
READ
START

STOP
R/W

ACK ACK ACK ACK ACK

SEQUENTIAL
RANDOM DEV SEL * BYTE ADDR BYTE ADDR DEV SEL * DATA OUT 1
READ
START

START

R/W R/W

ACK NO ACK

DATA OUT N
STOP

AI01105C

Note: 1. The seven most significant bits of the Device Select Code of a Random Read (in the 1st and 4th bytes) must be identical.

Read Operations this, and outputs the contents of the addressed

Read operations are performed independently of byte. The bus master must not acknowledge the
the state of the Write Control (WC) signal. byte, and terminates the transfer with a Stop con-
dition.
After the successful completion of a Read opera-
tion, the device’s internal address counter is incre- Current Address Read
mented by one, to point to the next byte address. For the Current Address Read operation, following
Random Address Read a Start condition, the bus master only sends a De-
vice Select Code with the Read/Write bit (RW) set
A dummy Write is first performed to load the ad- to 1. The device acknowledges this, and outputs
dress into this address counter (as shown in Fig-
the byte addressed by the internal address
ure 9.) but without sending a Stop condition. Then, counter. The counter is then incremented. The bus
the bus master sends another Start condition, and
master terminates the transfer with a Stop condi-
repeats the Device Select Code, with the Read/ tion, as shown in Figure 9., without acknowledging
Write bit (RW) set to 1. The device acknowledges
the byte.

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M24512

Sequential Read Acknowledge in Read Mode

This operation can be used after a Current Ad- For all Read commands, the device waits, after
dress Read or a Random Address Read. The bus each byte read, for an acknowledgment during the
master does acknowledge the data byte output, 9th bit time. If the bus master does not drive Serial
and sends additional clock pulses so that the de- Data (SDA) Low during this time, the device termi-
vice continues to output the next byte in sequence. nates the data transfer and switches to its Stand-
To terminate the stream of bytes, the bus master by mode.
must not acknowledge the last byte, and must
generate a Stop condition, as shown in Figure 9.
The output data comes from consecutive address-
es, with the internal address counter automatically INITIAL DELIVERY STATE
incremented after each byte output. After the last
memory address, the address counter ‘rolls-over’, The device is delivered with all bits in the memory
and the device continues to output data from array set to 1 (each byte contains FFh).
memory address 00h.

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 M24512

MAXIMUM RATING
Stressing the device outside the ratings listed in this specification, is not implied. Exposure to Ab-
Table 7. may cause permanent damage to the de- solute Maximum Rating conditions for extended
vice. These are stress ratings only, and operation periods may affect device reliability. Refer also to
of the device at these, or any other conditions out- the STMicroelectronics SURE Program and other
side those indicated in the Operating sections of relevant quality documents.

Table 7. Absolute Maximum Ratings

Symbol Parameter Min. Max. Unit
TA Ambient Operating Temperature –40 125 °C
TSTG Storage Temperature –65 150 °C

TLEAD Lead Temperature during Soldering See note (1) °C

VIO Input or Output range –0.50 6.5 V

VCC Supply Voltage –0.50 6.5 V

VESD Electrostatic Discharge Voltage (Human Body model) 2 –4000 4000 V

ECOPACK®
Note: 1. Compliant with JEDEC Std J-STD-020C (for small body, Sn-Pb or Pb assembly), the ST 7191395 specification, and
the European directive on Restrictions on Hazardous Substances (RoHS) 2002/95/EU
2. AEC-Q100-002 (compliant with JEDEC Std JESD22-A114A, C1=100pF, R1=1500Ω, R2=500Ω)

13/24
M24512

DC AND AC PARAMETERS
This section summarizes the operating and mea- ment Conditions summarized in the relevant
surement conditions, and the DC and AC charac- tables. Designers should check that the operating
teristics of the device. The parameters in the DC conditions in their circuit match the measurement
and AC Characteristic tables that follow are de- conditions when relying on the quoted parame-
rived from tests performed under the Measure- ters.

Table 8. Operating Conditions (M24512 – W)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 2.5 5.5 V

TA Ambient Operating Temperature –40 85 °C

Table 9. Operating Conditions (M24512 – R)

Symbol Parameter Min. Max. Unit

VCC Supply Voltage 1.8 5.5 V

TA Ambient Operating Temperature –40 85 °C

Table 10. AC Measurement Conditions

Symbol Parameter Min. Max. Unit

CL Load Capacitance 100 pF

Input Rise and Fall Times 50 ns

Input Levels 0.2VCC to 0.8VCC V

Input and Output Timing Reference Levels 0.3VCC to 0.7VCC V

Figure 10. AC Measurement I/O Waveform

Input Levels Input and Output

Timing Reference Levels
0.8VCC
0.7VCC

0.3VCC
0.2VCC
AI00825B

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 M24512

Table 11. Input Parameters

Symbol Parameter(1,2) Test Condition Min. Max. Unit
CIN Input Capacitance (SDA) 8 pF
CIN Input Capacitance (other pins) 6 pF
Input Impedance
ZL(3) VIN < 0.3VCC 30 kΩ
(E2, E1, E0, WC)
Input Impedance
ZH(3) VIN > 0.7VCC 500 kΩ
(E2, E1, E0, WC)
Pulse width ignored
tNS Single glitch 100 ns
(Input Filter on SCL and SDA)
Note: 1. TA = 25 °C, f = 400 kHz
2. Sampled only, not 100% tested.
3. E2,E1,E0: Input impedance when the memory is selected (after a Start condition).

Table 12. DC Characteristics (M24512 – W)

Symbol Parameter Test Condition Min. Max. Unit

Input Leakage Current VIN = VSS or VCC

ILI ±2 µA
(SCL, SDA, E0, E1, E2) device in Standby mode(1)
ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ±2 µA
VCC = 2.5V, fc=400kHz (rise/fall time < 30ns) 1 mA
ICC Supply Current
VCC = 5.5V, fc=400kHz (rise/fall time < 30ns) 2 mA
VIN = VSS or VCC , VCC = 2.5 V 2 µA
ICC1 Stand-by Supply Current
VIN = VSS or VCC , VCC = 5.5 V 5 µA
Input Low Voltage
VIL –0.45 0.3VCC V
(SCL, SDA, WC)
Input High Voltage
VIH 0.7VCC VCC+1 V
(SCL, SDA, WC)
VOL Output Low Voltage IOL = 2.1 mA, VCC = 2.5 V 0.4 V
Note: 1. When the device is selected (after a START condition), the Ei inputs have a different input impedance, as defined in Table 11.

Table 13. DC Characteristics(1) (M24512 – R)

Symbol Parameter Test Condition Min. Max. Unit
Input Leakage Current VIN = VSS or VCC
ILI ±2 µA
(SCL, SDA, E2, E1, E0) device in Stand-by mode
ILO Output Leakage Current VOUT = VSS or VCC, SDA in Hi-Z ±2 µA
VCC =1.8V, fc = 400kHz (rise/fall time <
ICC Supply Current 1 mA
30ns)
ICC1 Standby Supply Current VIN = VSS or VCC , VCC = 1.8 V 2 µA
VIL Input Low Voltage –0.45 0.3 VCC V
VIH Input High Voltage 0.7VCC VCC+1 V
VOL Output Low Voltage IOL = 0.7 mA, VCC = 1.8 V 0.2 V
Note: 1. The information contained in Table 13. is related to the new M24512 (process letter “A”) and is subject to change without previous
notice.

15/24
M24512

Table 14. AC Characteristics (M24512 – W)

Symbol Alt. Parameter Min. Max. Unit
fC fSCL Clock Frequency 400 kHz
tCHCL tHIGH Clock Pulse Width High 600 ns
tCLCH tLOW Clock Pulse Width Low 1300 ns
tCH1CH2 tR Clock Rise Time 300 ns
tCL1CL2 tF Clock Fall Time 300 ns
tDH1DH2 (2) tR SDA Rise Time 20 300 ns
(2) tF SDA Fall Time 20 300 ns
tDL1DL2
tDXCX tSU:DAT Data In Set Up Time 100 ns
tCLDX tHD:DAT Data In Hold Time 0 ns
tCLQX tDH Data Out Hold Time 200 ns
tCLQV (3) tAA Clock Low to Next Data Valid (Access Time) 200 900 ns

tCHDX (1) tSU:STA Start Condition Set Up Time 600 ns

tDLCL tHD:STA Start Condition Hold Time 600 ns
tCHDH tSU:STO Stop Condition Set Up Time 600 ns
tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns
tW tWR Write Time 5 or 10(4) ms
Note: 1. For a reSTART condition, or following a Write cycle.
2. Sampled only, not 100% tested.
3. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.
4. For M24512 devices whose package marking shows the process letter “A” tW(max) = 5ms whereas for M24512 devices whose
package marking shows the process letter “V” tW(max) = 10ms

Table 15. AC Characteristics(1) (M24512 – R)

Symbol Alt. Parameter Min. Max. Unit
fC fSCL Clock Frequency 400 kHz
tCHCL tHIGH Clock Pulse Width High 600 ns
tCLCH tLOW Clock Pulse Width Low 1300 ns
(3) tF SDA Fall Time 20 300 ns
tDL1DL2
tDXCX tSU:DAT Data In Set Up Time 100 ns
tCLDX tHD:DAT Data In Hold Time 0 ns
tCLQX tDH Data Out Hold Time 200 ns
(4) tAA Clock Low to Next Data Valid (Access Time) 200 900 ns
tCLQV
(2) tSU:STA Start Condition Set Up Time 600 ns
tCHDX
tDLCL tHD:STA Start Condition Hold Time 600 ns
tCHDH tSU:STO Stop Condition Set Up Time 600 ns
tDHDL tBUF Time between Stop Condition and Next Start Condition 1300 ns
tW tWR Write Time 10 ms
Note: 1. The information contained in Table 15. is related to the new M24512 (process letter “A”) and is subject to change without previous
notice.
2. For a reSTART condition, or following a Write cycle.
3. Sampled only, not 100% tested.
4. To avoid spurious START and STOP conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of SDA.

16/24
 M24512

Figure 11. AC Waveforms

tCHCL tCLCH

SCL

tDLCL

SDA In

tCHDX tCLDX SDA tDXCX tCHDH tDHDL

START SDA Change STOP START
Condition Input Condition Condition

SCL

SDA In

tCHDH tW tCHDX
STOP Write Cycle START
Condition Condition

SCL

tCLQV tCLQX

SDA Out Data Valid

AI00795C

17/24
M24512

PACKAGE MECHANICAL

Figure 12. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Outline

b2 E

A2 A

A1 L

b e c
eA

eB
D

E1

1
PDIP-B

Note: Drawing is not to scale.

Table 16. PDIP8 – 8 pin Plastic DIP, 0.25mm lead frame, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 5.33 0.210
A1 0.38 0.015
A2 3.30 2.92 4.95 0.130 0.115 0.195
b 0.46 0.36 0.56 0.018 0.014 0.022
b2 1.52 1.14 1.78 0.060 0.045 0.070
c 0.25 0.20 0.36 0.010 0.008 0.014
D 9.27 9.02 10.16 0.365 0.355 0.400
E 7.87 7.62 8.26 0.310 0.300 0.325
E1 6.35 6.10 7.11 0.250 0.240 0.280
e 2.54 – – 0.100 – –
eA 7.62 – – 0.300 – –
eB 10.92 0.430
L 3.30 2.92 3.81 0.130 0.115 0.150

18/24
 M24512

Figure 13. SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Outline

A2 A
C
B
e CP

E H
1
A1 α L

SO-b

Note: Drawing is not to scale.

Table 17. SO8W – 8 lead Plastic Small Outline, 208 mils body width, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 2.03 0.080
A1 0.10 0.25 0.004 0.010
A2 1.78 0.070
B 0.35 0.45 0.014 0.018
C 0.20 – – 0.008 – –
D 5.15 5.35 0.203 0.211
E 5.20 5.40 0.205 0.213
e 1.27 – – 0.050 – –
H 7.70 8.10 0.303 0.319
L 0.50 0.80 0.020 0.031
α 0° 10° 0° 10°
N 8 8
CP 0.10 0.004

19/24
M24512

Figure 14. SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Outline

h x 45˚

A2 A
C
B
e ddd

E H
1
A1 α L

SO-A

Note: Drawing is not to scale.

Table 18. SO8N – 8 lead Plastic Small Outline, 150 mils body width, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 1.35 1.75 0.053 0.069
A1 0.10 0.25 0.004 0.010
A2 1.10 1.65 0.043 0.065
B 0.33 0.51 0.013 0.020
C 0.19 0.25 0.007 0.010
D 4.80 5.00 0.189 0.197
ddd 0.10 0.004
E 3.80 4.00 0.150 0.157
e 1.27 – – 0.050 – –
H 5.80 6.20 0.228 0.244
h 0.25 0.50 0.010 0.020
L 0.40 0.90 0.016 0.035
α 0° 8° 0° 8°
N 8 8

20/24
 M24512

Figure 15. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Outline
D

8 5
c

E1 E

1 4

A1 L
A A2
CP L1

b e
TSSOP8AM

Note: Drawing is not to scale.

Table 19. TSSOP8 – 8 lead Thin Shrink Small Outline, Package Mechanical Data
millimeters inches
Symbol
Typ Min Max Typ Min Max
A 1.200 0.0472
A1 0.050 0.150 0.0020 0.0059
A2 1.000 0.800 1.050 0.0394 0.0315 0.0413
b 0.190 0.300 0.0075 0.0118
c 0.090 0.200 0.0035 0.0079
CP 0.100 0.0039
D 3.000 2.900 3.100 0.1181 0.1142 0.1220
e 0.650 – – 0.0256 – –
E 6.400 6.200 6.600 0.2520 0.2441 0.2598
E1 4.400 4.300 4.500 0.1732 0.1693 0.1772
L 0.600 0.450 0.750 0.0236 0.0177 0.0295
L1 1.000 0.0394
α 0° 8° 0° 8°
N 8 8

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M24512

PART NUMBERING

Table 20. Ordering Information Scheme

Example: M24512 – W MW 6 T P

Device Type
M24 = I2C serial access EEPROM

Device Function
512 = 512 Kbit (64K x 8)

Operating Voltage
W = VCC = 2.5 to 5.5V
R = VCC = 1.8 to 5.5V

Package
BN = PDIP8
MW = SO8 (208 mil width)
MN = SO8 (150 mil body width)
DW = TSSOP8

Device Grade
6 = Industrial temperature range, –40 to 85 °C.
Device tested with standard test flow

Option
blank = Standard Packing
T = Tape and Reel Packing

Plating Technology
blank = Standard SnPb plating
P or G = Lead-Free and RoHS compliant

For a list of available options (speed, package, device, please contact your nearest ST Sales Of-
etc.) or for further information on any aspect of this fice.

22/24
 M24512

REVISION HISTORY

Table 21. Document Revision History

Date Revision Description of Revision
Lead Soldering Temperature in the Absolute Maximum Ratings table amended
Write Cycle Polling Flow Chart using ACK illustration updated
29-Jan-2001 1.1
LGA8 and SO8(wide) packages added
References to PSDIP8 changed to PDIP8, and Package Mechanical data updated
LGA8 Package Mechanical data and illustration updated
10-Apr-2001 1.2
SO16 package removed
16-Jul-2001 1.3 LGA8 Package given the designator “LA”
02-Oct-2001 1.4 LGA8 Package mechanical data updated
Document becomes Preliminary Data
13-Dec-2001 1.5 Test conditions for ILI, ILO, ZL and ZH made more precise
VIL and VIH values unified. tNS value changed
12-Jun-2001 1.6 Document promoted to Full Datasheet
Table of contents, and Pb-free options added. Minor wording changes in Summary
22-Oct-2003 2.0 Description, Power-On Reset, Memory Addressing, Write Operations, Read Operations.
VIL(min) improved to –0.45V.

LGA8 package is Not for New Design. 5V and -S supply ranges, and Device Grade 5
removed. Absolute Maximum Ratings for VIO(min) and VCC(min) changed. Soldering
02-Sep-2004 3.0
temperature information clarified for RoHS compliant devices. Device grade information
clarified. AEC-Q100-002 compliance. VIL specification unified for SDA, SCL and WC

INITIAL DELIVERY STATE is FFh (not necessarily the same as Erased).

LGA package removed, TSSOP8 and SO8N packages added (see PACKAGE
MECHANICAL section and Table 20., Ordering Information Scheme).
Voltage range R (1.8V to 5.5V) also offered. Minor wording changes.
ZL Test Conditions modified in Table 11., Input Parameters and Note 3. added.
ICC and ICC1 values for VCC = 5.5V added to Table 12., DC Characteristics (M24512 – W).
22-Feb-2005 4.0 Note added to Table 12., DC Characteristics (M24512 – W).
Power On Reset paragraph specified.
tW max value modified in Table 14., AC Characteristics (M24512 – W) and note 4 added.
Plating technology changed in Table 20., Ordering Information Scheme.
Resistance and capacitance renamed in Figure 4., Maximum RP Value versus Bus
Parasitic Capacitance (C) for an I2C Bus.

23/24
M24512

Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences
of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted
by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject
to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not
authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics.

The ST logo is a registered trademark of STMicroelectronics.

ECOPACK is a registered trademark of STMicroelectronics.
All other names are the property of their respective owners

© 2005 STMicroelectronics - All rights reserved

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