CTS Lectures and Labs

Lecture 13 : CTS - Part I

Lecture 14 : CTS - Part II
Lab 7 : Lab7.CTS_1
Lecture 15 : CTS - Part III
Lecture 16 : CTS - Part IV
Lab 8 : Lab8.CTS_2

VLSI Physical Design Fundamemtals

Bach Luong
Tresemi

© Tresemi 2024 VLSI Physical Design Fundamentals 1

Lecture 15

Clock Tree Synthesis (CTS) part III

VLSI Physical Design Fundamentals

Bach Luong
Tresemi

© Tresemi 2024 VLSI Physical Design Fundamentals 2

CTS

Data Import

• Introduction
Floor • Objectives
Planning
• Inputs
• PreCTS Sanity Checks
• CTS Terminologies
Placement • CTS Exceptions
• CTS Spec
• Type of Clock Trees
• CTS Optimization Techniques
CTS
• CTS
• Post CTS optimization
• CTS Outputs
Routing • Review and Qualify CTS Results

Data Export

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Data Import
Virtual clock
• Is a clock without any clock source
Floor • Clock that has been defined without any association with any clock port or pin.
Planning
• Does not exist physically in the design
• Is used as a reference to constrain the interface timing paths (input and output delays)
• User can define desired latency
Placement

CTS

Routing

Data Export

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Data Import
Generated clock
• Is derived from a master clock
Floor • Master clock is a clock associate with a clock port or pin
Planning
• Is a multiple division of a master clock

Placement

CTS

z
Routing

Data Export

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Data Import
Buffer vs Inverter based clock trees
Buffer based clock tree
Floor • Buffer is consisted of two inverters connected back to back
Planning • High power consumption
• Sensitive to OCV
• More area

Placement

CTS

Routing
• To have the equal pulse widths for high and low times, the RC delay observed by the first inverter must be
equal to the RC delay of the second inverter.

Data Export

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Data Import
Buffer vs Inverter based clock trees
Inverter based clock tree
Floor • Maintaining duty cycle
Planning
• Better OCV tolerance
• Lower power consumption
• Less area
Placement

CTS

Routing

Data Export

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CTS Optimization Techniques

Data Import

• Buffering
Floor
Planning • Cell Sizing
• Cloning

Placement • VT- Swapping

• Cell Relocation
• Level Adjustment
CTS
• Dummy load insertion
• Load Splitting
Routing • Useful Skew

Data Export

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CTS Optimization Techniques

Data Import

Floor
Planning
• Buffering

• Cell Sizing
Placement

•
INV2X INV4X
Cloning
CTS

• VT- Swapping

Routing
Power
High VT Standard VT Low VT

Delay
Data Export

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CTS Optimization Techniques

Data Import
Cell Relocation
• Moving or adjusting the location of cells to balance output load
Floor
Planning

Placement

CTS

Routing

Data Export

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CTS Optimization Techniques

Data Import
Level Adjustment
• Move or adjust sinks (FF) level to balance out clock tree sinks
Floor
Planning

Placement

CTS

Routing

Data Export

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CTS Optimization Techniques

Data Import
Dummy Load Insertion
• Add a dummy load on different branches of to clock tree to balance their loadings.
Floor • Add to shortest delay path
Planning

Placement

CTS

Routing Three types of dummy load

• Buffer based dummy cells
• Inverter based dummy cells
• RC based
Data Export

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CTS Optimization Techniques

Data Import
Load Splitting
• Process of inserting buffers to split the fanout loads and resize the
Floor current driver to meet CTS and DRV constraints
Planning

Placement

Load splitting via cloning

CTS

Routing

Load splitting via buffering

Data Export

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CTS Optimization Techniques

Data Import
Useful Skew
• Skew that can be intentionally introduce to fix setup or hold time violations
by adding or removing buffers in the clock paths
Floor
Planning

Placement

CTS

FF1-> FF2 : FF2 ->FF3:

Arrival time = clk_delay + Tdata + Tcp Arrival time = clk_delay + Tdata + Tcp
Routing = 2ns + 9ns + 1ns = 12ns = 2ns + 5ns + 1ns = 8ns
Required time = Tcp + clk_delay -Tsu Required time = Tcp + clk_delay -Tsu
= 10 ns + 2ns - 1ns = 11ns = 10 ns + 2ns - 1ns = 11ns
Setup slack = required time – arrival time Setup slack = required time – arrival time
= 11ns -12ns = -1ns (setup violated) = 11ns -8ns = 3ns (setup met) <= useful skew
Data Export

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CTS Optimization Techniques

Data Import
Useful Skew
• Since FF2-> FF3 has 3ns of useful skew, we can make use of this useful skew for FF1->FF2
by adding 2ns delay to Clock path of FF2 to remove the setup timing violation in FF1->FF2 path
Floor
Planning

2ns
Placement

CTS

FF1-> FF2 : FF2 ->FF3:

Arrival time = clk_delay + Tdata + Tcp Arrival time = clk_delay + Tdata + Tcp
Routing = 2ns + 9ns + 1ns = 12ns = 4ns + 5ns + 1ns = 10ns
Required time = Tcp + clk_delay -Tsu Required time = Tcp + clk_delay -Tsu
= 10 ns + 4ns - 1ns = 13ns = 10 ns + 2ns - 1ns = 11ns
Setup slack = required time – arrival time Setup slack = required time – arrival time
= 13ns - 12ns = 1ns (setup met) = 11ns - 10ns = 1ns (setup met)
Data Export

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Data Import

• Introduction
Floor • Objectives
Planning
• Inputs
• PreCTS Sanity Checks
• CTS Terminologies
Placement • CTS Exceptions
• CTS Spec
• Type of Clock Trees
• CTS Optimization Techniques
CTS
• CTS
• Post CTS optimization
• CTS Outputs
Routing • Review and Qualify CTS Results

Data Export

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Data Import

• Clustering
Floor o Build clock tree based on DRV constraints
Planning
• Balancing
o Balance skew per skew group
Placement o Repeat until skew target is met or exhausted
• Routing clock tree
o All clock nets get detail routed
CTS
• Post Conditioning
o Fix minor timing violations

Routing

Data Export

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Data Import
Clustering
• Step where CTS tool group related clock sinks (FFs) into a clusters
• Each cluster represent a group of sequential cells that share the same clock source
Floor • Clustering help optimize the clock tree by minimizing clock skew and insertion delay
Planning • During this process, a clock tree are built based on DRV rules
• CTS tool build clock tree and place clock drivers at certain location/distance
based on CTS DRV constraints max capacitance load, max fanout, max transition
• At the end of Clustering stage, tool reports the number of buffers/inverters, icg cells are added.
Placement
Three type of clustering
• Top-Down Clustering: Starts with a single cluster containing all sinks and recursively
splits it into smaller clusters.
CTS • Bottom-Up Clustering: Begins with individual sinks and merges them into larger clusters.
• Iterative Clustering: Combines top-down and bottom-up approaches iteratively.
clk1 clk2 clk3 clk4

Routing

Data Export

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Data Import
Clustering log

Floor
Planning

Placement

CTS

Routing

Data Export

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Data Import
Balancing
• During this process, clock tree skew will be balanced
• Tool will balance clock skew per skew group constraints
Floor • Tool will repeat this step until clock skew per groups are met
Planning or already exhausted all options.

clk1 clk2 clk3 clk4

Placement

CTS

Routing

Data Export

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Data Import
Balancing log

Floor
Planning

Placement

CTS

Routing

Data Export

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Data Import
Routing Clock Tree
• During this process, clock tree will be detail routed.
• Tool will route all clock nets in the design
Floor
• All clock nets NDR rules will be obeyed
Planning
• Clock nets are normally routed in higher metal layers

Placement

CTS

Routing

Data Export

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Data Import
Routing Clock Tree log

Floor
Planning

Placement

CTS

Routing

Data Export

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Data Import
Post Conditioning
• Clocks are now propagated (with real delay)
• Fine tune skew
Floor
• This step fix minor timing and drv violations after clock routing
Planning
• These new violations arises as the result of newly routed clock nets, which cause degradation in timing, drv.

Before CTS After CTS

Placement

CTS

Routing clock delay

cppr adjust

Data Export

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CTS

Data Import
Post Conditioning log

Floor
Planning

Placement

CTS

Routing

Data Export

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© Tresemi 2024 VLSI Physical Design Fundamentals
References

▪ vlsi-backend-adventure.com
▪ teamvlsi.com
▪ vlsi-soc.blogspot.com
▪ www.researchgate.net
▪ www.semanticscholar.org
▪ vlsitalks.com
▪ www.vlsi-expert.com
▪ https://www.slideserve.com/
▪ https://semiengineering.com/
▪ https://www.techsimplifiedtv.in/
▪ https://vlsimaster.com/
▪ Cadence RAK

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