Interrupts

In every computer system, the CPU is designed to

continually execute instructions.
An exception is an event recognized by the CPU,
which diverts the CPU from its normal executions to
do something else, called exception processing.
An interrupt is an external event, which diverts the
CPU from its normal executions to do interrupt
processing.
Interrupts

In a broader sense, interrupts are special kinds of

exceptions.
The only difference between exceptions and
interrupts is that the former may originate from the
CPU itself but the latter always originate from
external sources.
Interrupts are essential to every computer system.
Without interrupts, a computer system would be
unable to respond to external events, such as user
inputs, timer events and requests for service from I/
O devices, etc.
Interrupts

Most embedded systems are designed to respond to

external events and handle such events when they
occur.
For this reason, interrupts and interrupts processing
are especially important to embedded systems.
The LCD is a memory mapped device, which does
not use interrupts.
UARTs support interrupts but a simple UART driver
can use polling, not interrupts, for I/O.
Interrupts

The main disadvantage of I/O by polling is that it

does not use the CPU efficiently.

While the CPU is doing I/O by polling, it is constantly

busy and can't do anything else.
In a computer system, I/O should be done by
interrupts whenever possible.
So the UART peripheral can be programmed in an
interrupt driven manner.
For example the UART can indicate with a specific
interrupt that its transmit buffer is full.
Exceptions Vector Table

The ARM processor uses a vector table to handle

exceptions and interrupts.
The vector table defines the entry points of
exceptions and interrupts handlers.
The vector table is located at the physical address
0.
Many ARM based systems begins execution from a
flash memory or ROM, which may be remapped to
OxFFFF0000 during booting.
If the initial vector table is not at 0 in SRAM, it must
be copied to SRAM before remap it to Ox00000000.
This is normally done during system initialization.
Exceptions Vector Table
Exceptions Vector Table - beaglebone
RAM Exception Vectors
The RAM exception vectors enable a simple means for redirecting
exceptions to custom handlers.
Table 26-3 shows content of the RAM space reserved for RAM
vectors. The first seven addresses areARM instructions which load the
value located in the subsequent seven addresses into the PC register.
Theses instructions are executed when an exception occurs since
they are called from the ROM exception vectors.
Undefined, SWI, Unused and FIQ exceptions are redirected to a
hardcoded dead loop. Pre-fetch abort, data abort, and IRQ exception
are redirected to pre-defined ROM handlers.
User code can redirect any exception to a custom handler either by
writing its address to the appropriate location from 4030CE24h to
4030CE3Ch or by overriding the branch (load into PC) instruction
between addresses from 4030CE04h to 4030CE1Ch.
 Exceptions Vector Table – beaglebone black
TRM table 26-3

T
Exception Handlers

Each vector table entry contains an ARM instruction

(B, BL or LDR).
This instruction causes the processor to load the PC
with the entry address of an exception handler
routine.
Reset Exception

A Reset event occurs when the processor is

powering up. This is the highest priority event and
shall be taken whenever it is signaled. Upon entry
to the reset handier. the CPSR is in SVC mode and
both IRQ and HQ interrupts are masked out. The
task of the reset handler is to initialise the system.
This includes setting up stacks of various modes,
configuring the memory and initialising device
drivers. Etc.
Data abort Exception

A Data Abort (DAB) events occur when the memory

controller or MMU indicates that an invalid memory
address has been accessed.
For example, if there is no physical memory for an
address. or the processor does not have access
permission to a region of memory, the date abort
exception is raised.
Data aborts have the second highest priority. This
means that the processor will handle data abort
exceptions first, before handling any interrupts.
FIQ Interrupt

A FIQ interrupt occurs when an external peripheral

sets the FIQ pin to nFIQ.
A FIQ interrupt is the highest priority interrupt.
Upon entry to the FIQ handler. both IRQ and FIQ
interrupts are disabled.
This means that while handling an FIQ interrupt, no
Other interrupts can occur unless they are explicitly
enabled by the software.
In ARM based systems, FIQ is usually used to handle
interrupts from a single interrupt source of extreme
urgency. Allowing multiple FIQ sources would defeat
the purpose of FIQ.
IRQ Interrupt

An IRQ interrupt occurs when an external peripheral

device sets the IRQ pin.
An IRQ interrupt is the second highest priority
interrupt.
The processor will handle an IRQ interrupt if there is
no FIQ interrupt or data abort exception.
Upon entry to the IRQ handler, IRQ interrupts are
masked out.
The CSPR's 1-bit should remain set until the current
interrupt source has been cleared.
Interrupt controller on the Versatilepb
board

Most ARM boards include a Vectored Interrupt

Controller (VIC), which is either the ARM PL190 or
PL192.

The VIC provides the following functionality:

Prioritise interrupt sources
Support vectored interrupts

There are two interrupt controllers on the

versatilepb board the Primary Interrupt Controller
(PIC) and the SIC the Secondary Interrupt Controller
Chapter 3.10 Versatilepb technical
reference – PIC and SIC
PIC Interrupt Controller registers Table 4-45
versatilepb technical ref manual
Interrupt signals to the Primary Interrupt
Controller Table 4-34 versatilepb technical
ref manual
Enable/Disable Interrupts

Each device has a control register or, in some

cases, a separate interrupt control register, which
can be programmed to either allow or disallow the
device to generate interrupt requests.
If a device is to use interrupts, the device interrupt
control register must be configured with interrupts
enabled.
If needed, device interrupts can be disabled
explicitly.
Thus, the terms enable/disable interrupts should be
applied only to devices.
Uart registers PL011 manual – interrupt
mask UARTIMSC

/
Uart registers PL011 manual – interrupt
mask UARTIMSC bits - Table 3-14 UARTIMSC
register
Uart Enable/Disable Interrupts

Uart.c uart_init function has the following to enable

interrupts.

*(up->base+0x38) |= 0x30;

up→base is a char * which points to the Uart registers .

The 0x38 is the offset to the UARTIMSC register

The 0x30 turns activates (masks in) the receive and transmit
interrupts from the UART peripheral.
IRQ_handler() in t.c of example 3.3

// read VIC SIV status registers to find out interrupt

int vicstatus = VIC_STATUS;
int sicstatus = SIC_STATUS;
if (vicstatus & (1<<4)){ // timer0,1=bit4
timer_handler(0); }
if (vicstatus & (1<<12)){ // bit 12: uart0
uart0_handler(); }
if (vicstatus & (1<<13)){ // bit 13: uart1
uart1_handler(); }
if (vicstatus & (1<<31)){
if (sicstatus & (1<<3)){
kbd_handler(); } }
enable UART0 RXIM – t.c example 3.3
Uart raises an interrupt when it receives a
character

// defines.h
#define UART0_IMSC (*((volatile u32 *)
(UART0_BASE_ADDR + 0x038)))

// t.c
UART0_IMSC = 1<<4; // enable UART0 RXIM
interrupt
UART1_IMSC = 1<<4; // enable UART1 RXIM
interrupt
Interrupt Masking

When a device raises an interrupt to the CPU, the

CPU may either accept or not accept the interrupt
immediately, depending on the interrupt masking
bits in the CPUs status register.
For an IRQ interrupt, the ARM CPU accepts the
interrupt if the I bit in the CPSR register is 0,
meaning that the CPU has IRQ interrupts unmasked
or mask-in.
It does not accept the interrupt while the CPSR's I
bit is 1, meaning that the CPU has IRQ interrupts
masked out.
Interrupt Masking

Masked out interrupts are not lost.

They are kept pending until the CPSR's I bit is
changed to 0, at which time the CPU will accept the
interrupt.
Thus, when applied to—the- CPU, enable/disable
interrupts really mean mask-in/mask-out interrupts.
 main() in t.c of example 3.3 – enable
interrupts

/* enable timer0,1, uart0,1 SIC interrupts */

VIC_INTENABLE |= (1<<4); // timer0,1 at bit4
VIC_INTENABLE |= (1<<5); // timer2,3 at bit5

VIC_INTENABLE |= (1<<12); // UART0 at 12

VIC_INTENABLE |= (1<<13); // UART1 at 13
// see PL011 manual
UART0_IMSC = 1<<4; // enable UART0 RXIM
interrupt
UART1_IMSC = 1<<4; // enable UART1 RXIM
interrupt
Clear Device Interrupt Request

When the CPU accepts an IRQ interrupt, it starts to

execute the interrupt handler for that device.
At the end of the interrupt handler it must clear the
interrupt request, which causes the device to drop
its interrupt request, allowing it to generate the
next interrupt.
This is usually done by accessing some of the
device interface registers.
For example, reading the data register of an input
device clears the device interrupt request.
For some output devices, it may be necessary to
disable the device interrupt explicitly when there is
no more data to output.
Table 3-1 ARM Dual-Timer Module (SP804)
TRM – interrupt clear at 0x0C.

W
Timer interrupt clear interrupt

write to the Interrupt Clear Register. Any write to

this register, clears the interrupt output from the
counter.
#define TINTCLR 0x3
TINTCLR is set to 3 because the tp→base is pointer
to an integer.

TIMER *tp = &timer[n];

*(tp->base+TINTCLR) = 0xFFFFFFFF;
uart interrupt handler – read/write to DR
register clears the interrupt

void uart_handler(UART *up)

{
u8 mask, mis;
mis = *(up->base + MIS); // read MIS register

if (mis & 0x10)

do_rx(up); // reads the DR register
if (mis & 0x20)
do_tx(up); // writes to DR register
}
Send EOI to Vectored Interrupt Controller

In a system with multiple interrupt sources, a

Vectored Interrupt Controller (VIC) is usually used to
prioritize the device interrupts, each with a
dedicated vector address.
At the end of handling the current interrupt, the
interrupt handler must inform the VIC that it has
finished processing the current interrupt (of the
highest priority), allowing the VIC to re-prioritize
pending interrupts requests.
Clear Device Interrupt Request

This is referred to as sending an End-of-Interrupt

(EOI) to the interrupt controller.
For the ARM PL190, this is done by writing an
arbitrary value to the VIC vector address register at
base 0x30.

If we operate according to the “simple interrupt flow

sequence” defined in TRM 2.2.2 we don’t require
the EOI
Simple Interrupt service routine – PL190
TRM

T
ts.s has the following irq_handler

irq_handler:

sub lr, lr, #4

stmfd sp!, {r0-r10, fp, ip, lr}

bl IRQ_handler

ldmfd sp!, {r0-r10, fp, ip, pc}^