ECE3110J Electronic Circuits

Current Mirrors
Design of Analog CMOS Integrated Circuits, Chapter 5
Fundamentals of Microelectronics, Chapter 9

Yuljae Cho, PhD

Associate Professor
Joint Institute, SJTU
Current Mirror - Initial Thoughts

The biasing techniques studied for MOS amplifiers till now prove inadequate for high-
performance microelectronic circuits. For example, the bias current of CE (BJT) and CS
(MOS) stages is a function of the supply voltage. However, in practice, this voltage
experiences some variation, e.g. battery in a cellphone or laptop. This mandates the circuits
operate properly across a range of supply voltages.

Another critical issue in biasing relates to ambient temperature variations. A cellphone

must maintain its performance at −20 °C in Finland and +50 °C in Saudi Arabia.
A MOS current source biased by means of a resistive divider suffers from dependence on VDD
and temperature. Since both the mobility and the threshold voltage vary with temperature, I1
is not constant even if VGS is.

The typical biasing schemes that we have seen so far fail to establish a constant collector or
drain current if the supply voltage or the ambient temperature are subject to change.
An elegant method of creating supply- and temperature-independent voltages and
currents exists and appears in almost all microelectronic systems. Called the “bandgap
reference circuit” and employing several tens of devices, this scheme is studied in more
advanced books. However, the complexity of the bandgap reference circuit prohibits its use
for each current source in a large integrated circuit.

golden current

copy the current

Icopy = IREF

A bandgap reference can provide a “golden current” while requiring a few tens of devices.
We must therefore seek a method of “copying” the golden current without duplicating
the entire bandgap circuitry. This can be done by current mirrors.
Comparing the diagram and the circuit, the current mirror resembles the topology on the right
where M1 operates in the saturation region (constant current) and the black box guarantees
Icopy = IREF regardless of temperature or transistor characteristics.

The black box generates an output voltage, VX = VGS,

such that M1 carries a current equal to IREF where
channel length modulation is neglected.
Therefore, the black box must satisfy the following input/output characteristic:

The black box must operate as a square-root circuit, i.e. always in saturation. A diode-
connected MOSFET provides such a characteristic. Diode-connected MOSFET is always in
saturation because VDS ≧ VGS – VTH, or VX ≧ VX – VTH (NMOS)
 1 𝑊
𝐼𝑅𝐸𝐹 = 𝐼𝐷−𝑅𝐸𝐹 = 𝜇𝑛 𝐶𝑜𝑥 ( )𝑅𝐸𝐹 (𝑽𝑮𝑺 − 𝑉𝑇𝐻 )2
2 𝐿
= k’ = Vov-REF

2𝐼𝑅𝐸𝐹
→ 𝑉𝑜𝑣−𝑅𝐸𝐹 =
𝑊
𝑘′( )𝑅𝐸𝐹
𝐿

1 𝑊
𝐼𝑐𝑜𝑝𝑦 = 𝑘′ ( )1 (𝑽𝑿 − 𝑉𝑇𝐻1 )2 where 𝑉𝑋 = 𝑉𝑜𝑣−𝑅𝐸𝐹 + 𝑉𝑇𝐻−𝑅𝐸𝐹
2 𝐿
1 𝑊
= 𝑘′ ( )1 𝑉𝑜𝑣−𝑅𝐸𝐹 + 𝑉𝑇𝐻−𝑅𝐸𝐹 − 𝑉𝑇𝐻1 2
2 𝐿
2
1 𝑊 2𝐼𝑅𝐸𝐹
= 𝑘′ ( )1 + 𝑉𝑇𝐻−𝑅𝐸𝐹 − 𝑉𝑇𝐻1 if VTH-REF = VTH1
2 𝐿 𝑊
𝑘′( 𝐿 )𝑅𝐸𝐹

𝑾
( 𝑳 )𝟏
𝑰𝒄𝒐𝒑𝒚 = ൙𝑾 × 𝑰𝑹𝑬𝑭
( 𝑳 )𝑹𝑬𝑭
We can view the circuit’s operation from two perspectives:
(1) MREF takes the square root of IREF and M1 squares the result, or equivalently
(2) The drain currents of the two transistors can be expressed as

Icopy = IREF if the two transistors and VTH are identical.

 Current
Mirror

Or simply put, two identical MOS devices that have equal VGS and operate in saturation carry
equal currents.

Current mirror allows precise copying of the current with no dependence on process and temperature.
The ratio of Icopy and IREF is given by the ratio of device dimensions, a quantity that can be controlled
with reasonable accuracy.
Multiplication of IREF

Suppose we wish to copy a reference current IREF and generate 2IREF. We employ a “unit”
transistor and create copies by repeating such a device.

Then, how about a current equal to IREF/2 from IREF? The diode-connected device itself must
consist of two units, each carrying IREF/2.
Example 1 Find the drain current of M4 if all of the transistors are in saturation.
Example 2 Calculate the small-signal voltage gain of the circuit.
Cascode Current Mirror
In our discussion of current mirrors thus far, we have neglected channel-length modulation. In
practice, the channel length modulation produces significant error in copying currents.

M1 M2
VDS1 = VGS1 = VGS2
VDS2 may not equal VGS2
Modification of current mirror structure

M1 M2

In order to suppress the effect of channel-length modulation, a cascode current source can be
used. Vb needs to be chosen such that VY = VX, then Iout closely tracks IREF.

Attributed to cascode design, there is minimal changes between VP and VY, i.e. changes in VDS2
by VP is minimal. Therefore, VY remains close to VX and hence ID2 ≈ ID1 with high accuracy.

∆𝑉𝑃
∆𝑉𝑌 ≈ ൘[ 𝑔 + 𝑔
𝑚3 𝑚𝑏3 𝑟𝑂3 ]
VY remains close to VX ?
∆𝑉
∆𝑉𝑌 ≈ 𝑃൘[ 𝑔 + 𝑔
𝑚3 𝑚𝑏3 𝑟𝑂3 ]
Biasing condition for Vb

To ensure VY ≈ VX, we must guarantee Vb – VGS3 = VX.

As VY = VS3 and Vb = VG3, VGS3 = Vb – VY. Comparing VGS3 = Vb – VY and VGS3 = Vb – VX
if VGS3 = Vb – VX we guarantee VY ≈ VX

This indicates that if a VGS3 is added to VX, the required value of Vb can be obtained.
→ circuit modification required.
Re-modification of current mirror structure

VX = Vb – VGS3

As we saw that VX = Vb – VGS3, meaning a VGS3 is added to VX to obtain the required

value of Vb. To achieve this, we add another diode-connected device, M0 in series with M1.

This gives VN = VGS0 + VX as VG0 = VN and VS0 = VX

 VG0 = VN VN
VGS3 VGS3 + VY = VN
= VN
VY

In the modified circuit, VG0 of M0 and M3 = VN. Thus, VN = VGS0 + VX = VGS3 + VY (VX ≈ VY)

𝐖ൗ 𝐖ൗ
𝐋 𝟑 𝐋 𝟐
Current mirror M0 and M3: 𝐖ൗ , Current mirror M1 and M2: 𝐖ൗ
𝐋 𝟎 𝐋 𝟏
 VG0 = VN VN
VGS3 VGS3 + VY = VN
= VN
VY

VGS0 + VX = VGS3 + VY = VN

𝐖ൗ 𝐖ൗ
𝐋 𝟑 𝐋 𝟐
Two currents from current mirrors are identical if 𝐖ൗ = 𝐖ൗ , VGS3 = VGS0, and VX = VY.
𝐋 𝟎 𝐋 𝟏

This can be achieved by a proper choice of the dimensions of M0 with respect to those of M3
yields ID0 (= ID1) = ID3 (= ID2) because VX = VY (VDS) and VGS0 = VGS3.
Example 3 Sketch VX and VY as a function of IREF. If IREF requires 0.5 V to operate as a current source,
what is its maximum value?
Example 3 Sketch VX and VY as a function of IREF. If IREF requires 0.5 V to operate as a current source,
what is its maximum value?
Issues in voltage headroom
All electricity networks have a limit as
to how high or low the voltage is
allowed to go, and how close the
existing voltage is to the limit is
referred to as the voltage headroom.

While operating as a current source with a high output impedance and accurate value, the
modified topology nonetheless consumes substantial voltage headroom.

Assume no body effect and all of the transistors are identical, the minimum allowable
voltage for saturation at node P is VP = VN – VTH
 VP = VN – VTH

because
N
VGS3 = VN – VY
VGS0 VDS3 = VP – VY
Minimum saturation condition VDS = VGS – VTH
VX
Thus, VP – VY = VN – VY – VTH → VP = VN – VTH
=
VGS1

VN = VGS0 + VX = VGS0 + VGS1, and VP = VN – VTH = VGS0 + VGS1 – VTH

= (VGS0 – VTH) + (VGS1 – VTH) + VTH
Meanwhile, the previous model (Left) offers minimum saturation conditions: (VGS2 – VTH2) + (VGS3
– VTH3) as for M2 and M3 in saturation: VDS = VGS – VTH

Therefore, the model (Right) wastes one threshold voltage in the headroom.
The model left, however, suffers from lower accuracy as we discussed, due to the fact that VX ≠ VY.
Re-remodification of current mirror structure

In order to eliminate the accuracy-headroom trade-off, we modify the circuit design again.
Consider the first circuit (left) which is a cascode topology where output is shorted with its
input, Vb needs to be determined so that both M1 and M2 are in saturation.
 VX = VGS1

For M2 in saturation
VDS ≥ VGS – VTH2 where VDS = VX – VA and VGS = Vb – VA
Thus, VX ≥ Vb – VTH2, or Vb ≤ VX (= VGS1) + VTH2

For M1 in saturation
VDS = VA and VGS = VX, thus VA ≥ VX – VTH1
Because VA = Vb – VGS2, Vb – VGS2 ≥ VX – VTH1, or Vb ≥ VX (= VGS1) – VTH1 +VGS2

Thus, finally, VGS1 – VTH1 +VGS2 ≤ Vb ≤ VGS1 + VTH2

(VGS1 – VTH1) + VGS2 ≤ VGS1 + VTH2, or VGS2 – VTH2 ≤ VTH1

We must therefore size M2 down such that its overdrive voltage remains less than one
threshold voltage.
Low voltage cascode current mirror

We now modified the current mirror as shown above and assume that M1-M4 are in
saturation and proper rationing ensure that VGS2 = VGS4

Referring to the result in previous slide, we set Vb (minimum) = VGS2 + (VGS1 – VTH1), which
gives us biasing condition to M3 and M4 of VGS4 + (VGS3 – VTH3)
 Vb = VGS2 + VGS1 – VTH1
= VGS4 + VGS3 – VTH3

Since VDS4 = VGS4 – VTH4 for sat. minimum

→ VD4 = VG4 – VTH4

= VGS4 + VGS3 – VTH3 – VTH4

Consumes minimum headroom, VD4 = VGS4 + VGS3 – VTH3 – VTH4, while M1 and M3 sustain
equal VDS. Guarantees accurate copying of IREF.

For minimal voltage headroom consumption, VA (= VDS1) = VGS1 – VTH1

And VGS2 = Vb – VA, and thus, approximately Vb = VGS2 + VGS1 – VTH1
Active Current Mirror
Current mirrors can also process signals, i.e., operate as active elements. Particularly useful is a
type of mirror topology used in conjunction with differential pairs.

If M1 and M2 with λ = 0 are identical, the current mirror design left has
Iin = Iout. The circuit performs no inversion, meaning that if Iin
increases by ΔI, so does Iout.

We now combine this current mirror with differential

amplifier. What is the small-signal gain of this circuit?
Approach 1
Ground
λ=0 (1) Gm
γ=0

In small signal

Gain of the circuit is 𝑨𝒗 = 𝑮𝒎 𝑹𝒐𝒖𝒕

In a small signal model to find Gm, M1 and M2 become symmetric when the output is
shorted to ac ground. We use half circuit analysis where there is only one output.

Therefore, 𝐆𝐦 is halved and is 𝐠 𝐦𝟏Τ𝟐 𝛖𝐨𝐮𝐭 = −𝐆𝐦 𝛖𝐢𝐧 𝐑 𝐨𝐮𝐭 , Vout is halved,
then Gm is halved
Approach 1
Ground
λ=0 (1) Gm
γ=0

In small signal

Gain of the circuit is 𝑨𝒗 = 𝑮𝒎 𝑹𝒐𝒖𝒕

In a small signal model to find Gm, M1 and M2 become symmetric when the output is
shorted to ac ground. We use half circuit analysis where there is only one output.

Therefore, 𝐆𝐦 is halved and is 𝐠 𝐦𝟏Τ𝟐 𝛖𝐨𝐮𝐭 = −𝐆𝐦 𝛖𝐢𝐧 𝐑 𝐨𝐮𝐭 , Vout is halved,
then Gm is halved
Recall: If a fully-symmetric differential pair senses differential inputs, then the concept of ‘half
circuit’ can be applied.

We can write VX/Vin1 = −gmRD and VY /(−Vin1) = −gmRD. Thus, (VX − VY)/(2Vin1) = −gmRD.
Recall:
λ=0
γ=0

𝐑𝐃 𝑹𝑫
𝛖𝐨𝐮𝐭𝟏 (𝒗𝑿 ) = − 𝛖𝐢𝐧𝟏 𝝊𝒐𝒖𝒕𝟐 (𝒗𝒀 ) = 𝝊𝒊𝒏𝟏
𝟏 𝟏 𝟏 𝟏
+ +
𝐠 𝒎𝟏 𝐠 𝒎𝟐 𝐠 𝐦𝟏 𝐠 𝐦𝟐

And thus, the overall voltage gain for vin1 is vX – vY

𝟐𝑹𝑫
=− 𝒗 = −𝐠 𝒎 𝑹𝑫 𝒗𝒊𝒏𝟏 if gm1 = gm2 = gm
𝟏 𝟏 𝒊𝒏𝟏
+
𝐠 𝐦𝟏 𝐠 𝐦𝟐
Recall:

2R D
υout1 −υout2 = − υin1 = −g m R D 𝝊𝒊𝒏𝟏
1 1
+
g 𝑚1 g 𝑚2

By the virtue of symmetry, the effect of vin2 at X and Y is identical to that of vin1 except for a
change in the polarities.
2R D
υout1 −υout2 = υin2 = g m R D 𝝊𝒊𝒏𝟐
1 1
+
g 𝑚1 g 𝑚2
𝛖𝐨𝐮𝐭𝟏 −𝛖𝐨𝐮𝐭𝟐
𝐀𝐃𝐌 = = −𝐠 𝐦 𝐑 𝐃
𝛖𝐢𝐧𝟏 −𝛖𝐢𝐧𝟐
(2) Rout
λ≠0

Rout4 = ro4

≈ 1/g 𝑚1

CS stage with a source degeneration (green box)

From the small signal model, 𝐑 𝐨𝐮𝐭 = ro1 + R S + g 𝑚1 + g 𝑚𝑏1 ro1 R S
Rout4 (blue box) = ro4
𝟏 𝐠 𝐫
Rout1,2 (green box) = 𝐫𝐨𝟐 + + 𝒎𝟐 𝐨𝟐.
𝐠 𝐦𝟏 𝐠 𝐦𝟏
𝟏
If M1 and M2 are symmetry, gm1 = gm2, and thus, Rout1,2 = 2ro2 + ≈ 2ro2
𝐠 𝐦𝟏
Finally, total Rout = 2ro2 ║ro4
(2) Rout

λ≠0

Rout4 = ro4

From the small signal model,

Rout4 (blue box) = ro4
(2) Rout

λ≠0

Rout4 = ro4

CS stage with a source degeneration (green box)

From the small signal model,
𝟏 𝐠 𝐫 𝐑 𝐨𝐮𝐭 = ro1 + R S + g 𝑚1 + g 𝑚𝑏1 ro1 R S
Rout1,2 (green box) = 𝐫𝐨𝟐 + + 𝒎𝟐 𝐨𝟐.
𝐠 𝐦𝟏 𝐠 𝐦𝟏
𝟏
If M1 and M2 are symmetry, gm1 = gm2, and thus, Rout1,2 = 2ro1,2 + ≈ 2ro1,2
𝐠 𝐦𝟏
Finally, total Rout = 2ro2 ║ro4
The gain of the circuit above is 𝐴𝑣 = 𝐺𝑚 𝑅𝑜𝑢𝑡 where 𝐠
𝐆𝐦 = 𝐦𝟏ൗ𝟐
Rout = 2rO2 ║rO4
Approach 2

λ≠0
Rout4 = ro4

We also can get a gain by calculating VP/Vin and Vout/VP and multiply the results to obtain Vout/Vin.

(1) 𝑽𝑷ൗ𝑽𝒊𝒏: M1 as a source follower with RS of M2 (= Req).

gm RS
*Gain of source follower = ≈
(gm +gmb +1ൗro1+1ൗR ) (1ൗgm +RS )
S
Req
Thus, 𝑽𝑷ൗ𝑽𝒊𝒏 =
(1ൗgm +Req )
From the small signal analysis, we can find
𝑟
1 + 𝑜4ൗ𝑟𝑜2 1 𝑟𝑜4
𝑅𝑒𝑞 = ≈ +
1
𝑔𝑚2 + ൗ𝑟𝑜2 𝑔 𝑚2 𝑔𝑚2 × 2𝑟𝑜2
Therefore, VP/Vin becomes
𝒓𝒐𝟒
𝑽𝑷 𝟏 + ൗ𝒓𝒐𝟐
ൗ𝑽 ≈ 𝒓
𝒊𝒏 𝟐 + 𝒐𝟒ൗ𝒓𝒐𝟐
 λ≠0
γ≠0

+RS

𝑽𝒐𝒖𝒕
(2) ൗ𝑽𝒑
RS = 0
RD = rO4
Seen from the circuit, it is a CG stage. gm + g mb ro R D + R D rO = rO2
The gain of CG stage (λ ≠ 0 and γ ≠ 0 ) is Av = gmb = 0
ro + R S + R D + gm + g mb ro R S

𝑽𝒐𝒖𝒕 gm2ro2 ro4 + ro4 gm2ro2 + 1 𝐠𝐦𝟐𝐫𝐨𝟐

Therefore, the gain of the circuit is Av = = =r ≈ 𝐫𝐨𝟐
𝑽𝑷 ro2 + ro4 o2ൗ
ro4 + 1 𝟏 + ൗ𝐫𝐨𝟒
 𝑟𝑜4
𝑽𝑷 1+ ൗ𝑟𝑜2 𝑽𝒐𝒖𝒕 𝑔𝑚2𝑟𝑜2
ൗ𝑽 ≈ 𝑟𝑜4 𝑎𝑛𝑑 ൗ𝑽 ≈ 𝑟
𝒊𝒏 2 + ൗ𝑟𝑜2 𝑷 1 + 𝑜2ൗ𝑟𝑜4
Final gain of the active current mirror is
𝑟𝑜4
𝑽𝒐𝒖𝒕 1 + ൗ𝑟𝑜2 𝑔𝑚2𝑟𝑜2 𝑔𝑚2 𝑟𝑜2 𝑟𝑜4 𝒈𝒎𝟐
= 𝑟𝑜4 × 𝑟𝑜2 = = (𝟐𝒓𝒐𝟐 ฮ𝒓𝒐𝟒 )
𝑽𝒊𝒏 2 + ൗ𝑟𝑜2 1 + ൗ𝑟𝑜4 2𝑟𝑜2 + 𝑟𝑜4 𝟐

However, the current circuit topology waste the small-signal drain current of M1
To fully utilize current of M1, we modify the circuit from the left to the right one. The right
design is called a differential pair with active current mirror, or a differential pair with
active load.
A differential pair with active current mirror
Small Signal Analysis
(1) Differential Mode
γ=0
Ro3 ║ 1/gm3 ro4
Vout

Not a virtual node

We cannot apply the half-circuit concept for this as M3 yields a much lower voltage gain
compared to M4, resulting in VX and VY at node P do not cancel each other.
Gm and Rout

Grounded Vout makes the circuit almost

symmetry, and thus we can apply a virtual
ground concept.

Req of M3 stage seen from node X is relatively small ~ 𝟏Τ𝒈𝒎𝟑, and the gain of the diode
connected MOS (M3) is negligibly small (unity). Therefore, node X can be viewed as
ground. This leads to the symmetry of the circuit, and thus we can apply the virtual ground
concept at node P.
Gm

Copy of ID1 = ID3

Vout

ID2
ID1 = ID3

ID1 = gm1Vin/2 and ID2 = −gm2Vin/2 where gm1 = gm2 = gm

Iout = −gmVin
Therefore, Gm = gm
Rout

Ground
Ground

Vout Va = 0

Ground Ground

Open

From a small signal model of the circuit on the right, 𝐼𝑋 = 𝑉𝑋ൗ𝑟𝑂4 + 𝑔𝑚4 𝑉𝑔𝑠 + 𝑉𝑋ൗ𝑟𝑂2 + 𝑔𝑚2 𝑉𝑔𝑠
Approximately, Vgs4 = 0, and thus Req of M4 = rO4
 Ground
Ground

Vout Va = 0

Ground Ground

Open

From a small signal model of the circuit on the right, 𝐼𝑋 = 𝑉𝑋ൗ𝑟𝑂4 + 𝑔𝑚4 𝑉𝑔𝑠 + 𝑉𝑋ൗ𝑟𝑂2 + 𝑔𝑚2 𝑉𝑔𝑠
Approximately, Vgs4 = 0, and thus Req of M4 = rO4
 Ground

Va = 0

From small signal analysis, we get 𝑉𝑋ൗ𝐼𝑋 ~𝑟𝑂4 ฮ2𝑟𝑂2 ~ 𝒓𝑶𝟒 ฮ𝒓𝑶𝟐

Finally, gain of the active current mirror is 𝐠 𝐦 (𝐫𝐎𝟒 ԡ𝐫𝐎𝟐 ). If we compare this with the
exact analysis we can see that there is slight mismatch due to too many approximations
Exact analysis

Another way is to find gain without approximation, i.e. exact analysis, using the small signal
model above.

1/Rout =

rO1 = rO2
Small Signal Analysis
(2) Common Mode

γ=0

Due to a finite output impedance RSS, a change in the input CM level leads to a change in the bias
current of all of the transistors.
∆𝑉𝑜𝑢𝑡
𝐴𝐶𝑀 =
∆𝑉𝑖𝑛,𝐶𝑀
 Parallel MOS
Resistance/2
Transconductance*2

Due to the properties of the common level input, changes in Vin,CM influences both node F and Vout.
E.g. If Vin,CM increases, VF decreases and so does Vout (CS stage). Thus, F and X can be shorted.
Then, we can apply a parallel MOSFET concept to analyze the circuit.
Recall:
λ=0
γ=0

If the circuit is symmetric, VX remains equal to VY. Thus, we can view the circuit as two parallel
transistor circuits.
1 W 2
ID = µnCox VGS − VTH × 2 and the same for the transconductance gm × 𝟐
2 L

𝑅𝐷
ൗ2
From small-signal model, we get 𝐴𝑣,𝐶𝑀 = − 1
ൗ2𝑔𝑚 +𝑅𝑆𝑆
 Req of M3 = 1Τgm3 ฮro3 ~ 𝟏Τ𝐠 𝐦𝟑
Req of M4 = ro4

1 𝑟𝑜3,4
𝑅𝐷 ብ ൗ2
ൗ2 2𝑔𝑚3,4 1 gm1,2
As 𝐴𝑣,𝐶𝑀 = − 1 , the circuit above has 𝐴𝑣,𝐶𝑀 ≈ − 1 =−
ൗ2𝑔𝑚 +𝑅𝑆𝑆 ൗ2𝑔𝑚 1,2 + 𝑅𝑆𝑆 1+2gm1,2 RSS gm3,4
1 𝑟𝑜1,2
by assuming that ≪ 𝑟𝑜3,4 and neglect the effect of Τ2
2𝑔𝑚3,4
𝐴𝐷𝑀 𝑔𝑚1,2 (𝑟𝑜1,2 ฮ𝑟𝑜3,4 )
𝑪𝑴𝑹𝑹 = = g = (1 + 2g m1,2 R SS )g m3,4 (𝑟𝑜1,2 ฮ𝑟𝑜3,4 )
𝐴𝐶𝑀 1 m1,2
( )
1 + 2g m1,2 R SS g m3,4
THE END
 What we have learned in ECE3110J

1. Introduction and Solid-State Electronics

2. Diode and Diode Circuit

3. Bipolar Junction Transistor (BJT)

4. BJT Circuit

5. Basic MOS Device Physics

6. MOS Single Stage Amplifier

7. MOS Differential Amplifier

8. Current Mirror
 *Contents of ECE2150J

Circuit analysis Electric components Power analysis Frequency analysis

Advanced circuits Electronic components Power and Energy Signal processing

Circuit and Design Device and Fab Energy System Communications

& Control

ECE3110J
59
 ECE3110J

Semiconductor devices:
Analog circuits
PN diodes, BJT, MOSFET

Semiconductor physics and devices Digital circuits

Solid state physics Other circuit courses
Electronics, photonics etc. IC Design etc.

Materials Device and Fab Circuit and design Architecture

Electronics industry
Field of EE

+ CE/CS
Broader views e.g. AI industry

Hardware Software App

Semiconductor Model Consumer

Fab Design Network Memory

Enterprise
Data center Cloud

Data center infra Industry

Data Infra
Energy Develop Equip Manage

62
ECE

63
Studying one subject is..
All the knowledges

You now have the vast

area to explore

64
Enlarged the total knowledge for human beings,
meaning that we keep expanding our knowledges.
Learning/studying is always humiliating. It is a painful process in which one must always
objectify one's own ignorance. And since the world is not fair, someone can achieve it easily.