PART – B: BASIC ELECTRONICS ENGINEERING

UNIT I
Semiconductor Devices

Semiconductor Devices
Introduction – Types of semiconductor devices – Operation and Characteristics of PN Junction
Diode, Zener Effect, Zener Diode and its Characteristics. Bipolar Junction Transistor -Principle of
operation and CB, CE, CC Configurations— Elementary Treatment of Small Signal CE Amplifier.

1
Introduction to semiconductor
❖ A semiconductor material is one whose electrical properties (resistivity) lie in between those of
insulators and conductors. Ex: germanium (Ge) and silicon (Si).
❖ Semiconductors have negative temperature co-efficient of resistance i.e. the resistance of a
semiconductor decreases with the increase in temperature and vice-versa.
❖ When a suitable metallic impurity (e.g. arsenic, gallium etc.) is added to a semiconductor, its
current conducting properties change appreciably.

❖ In terms of energy bands as shown in Fig.1, semiconductors can be defined as those materials
which have almost an empty conduction band and almost filled valence band with a very
narrow energy gap (of the order of ≈1 eV) separating the two.

Fig. 1 Energy band diagrams of germanium (Ge) and silicon (Si) atoms

Therefore, relatively small energy is needed by their valence electrons to cross over to the
conduction band. Even at room temperature, some of the valence electrons may acquire
sufficient energy to enter into the conduction band and thus become free electrons. However, at
this temperature, the number of free electrons available is very small. Therefore, at room
temperature, a piece of germanium or silicon is neither a good conductor nor an insulator. For
this reason, such substances are called semi - conductors.

(a) (b)

Fig. 2 Formation of Covalent Bonds in a) Ge b) Si atoms

2
Effect of Temperature on Semiconductors
i) At absolute zero
At absolute zero temperature, all the electrons are tightly held by
the semiconductor atoms. The inner orbit electrons are bound
whereas the valence electrons are engaged in co-valent bonding as
shown in Fig.2. At this temperature, the co-valent bonds are very
strong and there are no free electrons. Therefore, no valence
electron can reach the conduction band to become free electron as
shown in Fig.3. Therefore, the semiconductor crystal behaves as a
perfect insulator. Fig. 3 Energy band diagram
at absolute zero
ii) At above absolute zero
When the temperature is raised, some of the covalent bonds in the
semiconductor break due to the thermal energy supplied. The
breaking of bonds sets those electrons free which are engaged in
the formation of these bonds. The result is that a few free
electrons exist in the semiconductor. These free electrons can
constitute a tiny electric current if potential difference is applied
across the semiconductor crystal. This shows that the resistance
of a semi-conductor decreases with the rise in temperature i.e. it
has negative temperature coefficient of resistance. It may be
added that at room temperature, current through a semiconductor
is too small to be of any practical value. Fig. 4 Energy band diagram at
As the temperature is raised, some of the valence electrons above absolute zero
acquire sufficient energy to enter into the conduction band and thus become free electrons as
shown in Fig.4. Under the influence of electric field, these free electrons will constitute electric
current, i.e., electron current.
It may be noted that each time a valence electron
enters into the conduction band, a hole is created in
the valence band i.e. a missing electron in the
covalent bond. This missing electron is called a
hole which acts as a positive charge, this
constitutes hole current due to the movement of
valence electrons from one covalent bond to
another bond. For one electron set free, one hole is
created. Therefore, thermal energy creates hole-
electron pairs; there being as many holes as the
free electrons. Fig. 5 Energy band diagram for Hole
From Fig.5, due to thermal energy, an electron leaves Current
the valence band to enter into the conduction band, this leaves a vacancy at L. Now the valence
electron at M comes to fill the hole at L. The result is that hole disappears at L and appears at M.
Next, the valence electron at N moves into the hole at M. Consequently, hole is created at N. It is
clear that valence electrons move along the path PNML whereas holes move in the opposite
direction i.e. along the path LMNP.

3
 Types of Semiconductors
Semiconductor may be classified as under:

Intrinsic Semiconductors:
An intrinsic semiconductor is one which is made of the semiconductor material in its extremely
pure form.
Examples of such semiconductors are: pure germanium and silicon which have forbidden energy
gaps of 0.72 eV and 1.1 eV respectively. The energy gap is so small that even at ordinary room
temperature; there are many electrons which possess sufficient energy to jump across the small
energy gap between the valence and the conduction bands.
In an intrinsic semiconductor, even at room temperature, hole-electron pairs are created. When
electric field is applied across an intrinsic semiconductor, the current conduction takes place by
two processes, namely; by free electrons and holes as shown in Fig.6. The free electrons are
produced due to the breaking up of some covalent bonds by thermal energy. At the same time,
holes are created in the covalent bonds as shown in Fig.7. Under the influence of electric field,
conduction through the semi-conductor is by both free electrons and holes. Therefore, the total
current inside the semiconductor is the sum of currents due to free electrons and holes.

Fig. 6 Current distribution Fig. 7 Energy Band description

It may be noted that current in the external wires is fully electronic i.e. by electrons. Referring to
Fig.6, holes being positively charged move towards the negative terminal of supply. As the holes
reach the negative terminal B, electrons enter the semiconductor crystal near the terminal and
combine with holes, thus cancelling them. At the same time, the loosely held electrons near the
positive terminal A are attracted away from their atoms into the positive terminal. This creates new
holes near the positive terminal which again drift towards the negative terminal.

4
 Extrinsic Semiconductors:
The intrinsic semiconductor has little current conduction capability at room temperature. To be
useful in electronic devices, the pure semiconductor must be altered so as to significantly
increase its conducting properties. This is achieved by adding a small amount of suitable
impurity to a semi-conductor. It is then called impurity or extrinsic semiconductor. The
process of adding impurities to a semiconductor is known as doping. Depending on the type of
doping material used, extrinsic semiconductors can be sub-divided into two classes:

(i) N-type semiconductors and

(ii) P-type semiconductors.

(i) N-type Semiconductor:

When a small amount of pentavalent impurity is added to a pure semiconductor, it is known as n-
type semiconductor. Such impurities which produce n-type semiconductor are known as donor
impurities because they donate or provide free electrons to the semi-conductor crystal.

When a small amount of pentavalent impurity like arsenic

(Atomic. No. 33) is added to germanium crystal, a large
number of free electrons become available in the crystal.
Arsenic is pentavalent i.e. its atom has five valence
electrons. An arsenic atom fits in the germanium crystal in
such a way that its four valence electrons form covalent
bonds with four germanium atoms. The fifth valence
electron of arsenic atom finds no place in co-valent bonds
and travels to the conduction band, i.e., as a free electron as
shown in Fig.8.
Therefore, for each arsenic atom added, one free electron (a) Bonding diagram
will be available in the germanium crystal. Though each
arsenic atom provides one free electron, yet an extremely
small amount of arsenic impurity provides enough atoms
to supply millions of free electrons.
Thermal energy of room temperature still generates a few
hole-electron pairs. However, the number of free
electrons provided by the pentavalent impurity far
exceeds the number of holes. It is due to this
predominance of electrons over holes that it is called n-type (b) Energy Band diagram
semiconductor (n stands for negative). Fig.8

(ii) P-type Extrinsic Semiconductor:

When a small amount of trivalent impurity is added to a pure semiconductor, it is called p-type
semiconductor. Such impurities which produce p-type semiconductor are known as acceptor
impurities because the holes created can accept the electrons.
When a small amount of trivalent impurity like gallium (Atomic no. 31) is added to germanium
crystal, there exists a large number of holes in the crystal. Gallium is trivalent i.e. its atom has
5
three valence electrons. Each atom of gallium fits into the
germanium crystal but now only three co-valent bonds can
be formed as shown in Fig.9. It is because three valence
electrons of gallium atom can form only three single co-
valent bonds with three germanium atoms as shown in Fig.
In the fourth co-valent bond, only germanium atom
contributes one valence electron while gallium has no
valence electron to contribute as all its three valence
electrons are already engaged in the co-valent bonds with
neighboring germanium atoms. In other words, fourth
(a) Bonding diagram
bond is incomplete; being short of one electron.
This missing electron is called a hole. Therefore, for each
gallium atom added, one hole is created. A small amount of
gallium provides millions of holes. The addition of trivalent
impurity has produced a large number of holes.
However, there are a few conduction band electrons due to
thermal energy associated with room temperature. But the
holes far outnumber the conduction band electrons.

It is due to the predominance of holes over free electrons that (b) Energy Band diagram
it is called p-type semiconductor (p stands for positive). Fig.9

Majority and Minority Carriers:

N-type material has a large number of free electrons whereas p-type material has a large
number of holes. However, it may be recalled that even at room temperature, some of the co-
valent bonds break, thus releasing an equal number of free electrons and holes. An n-type material
has its share of electron-hole pairs (released due to breaking of bonds at room temperature) but in
addition has a much larger quantity of free electrons due to the effect of impurity. These impurity-
caused free electrons are not associated with holes. Consequently, an n-type material has a large
number of free electrons and a small number of holes as shown in Fig.10(i). The free electrons in
this case are considered majority carriers — since the majority portion of current in n-type
material is by the flow of free electrons — and the holes are the minority carriers. Similarly, in a
p-type material, holes outnumber the free electrons as shown in Fig.10(ii). Therefore, holes are the
majority carriers and free electrons are the minority carriers.

(i) (ii)

Fig.10

6
Semiconductor Diode
When a p-type semiconductor is suitably joined to n-type semiconductor, the contact surface is
called pn junction as shown in Fig.11a. A pn junction is known as a semi-conductor or crystal
diode. A crystal diode is usually represented by the schematic symbol shown in Fig.11b.

b) Schematic Symbol
a) Pn Junction

Fig.11
Properties of pn Junction:
At the instant of pn-junction formation, the free electrons near
the junction in the n region begin to diffuse across the junction into the
p region where they combine with holes near the junction. The result is
that n region loses free electrons as they diffuse into the junction. This
creates a layer of positive charges (pentavalent ions) near the junction.
As the electrons move across the junction, the p-region loses holes as
the electrons and holes combine. The result is that there is a layer of
negative charges (trivalent ions) near the junction. These two layers of
positive and negative charges form the depletion region (or depletion
layer) as shown in Fig.12(i). The term depletion is due to the fact that
near the junction, the region is depleted (i.e. emptied) of charge carries
(free electrons and holes) due to diffusion across the junction. The
depletion layer is formed very quickly and is very thin compared to
the n-region and the p region.
Fig.12
Once pn junction is formed and depletion layer created, the diffusion of
free electrons stops. In other words, the depletion region acts as a barrier
to the further movement of free electrons across the junction. The
positive and negative charges set up an electric field as shown by a black
arrow in Fig.12 (ii). The electric field is a barrier to the free electrons in
the n-region. There exists a potential difference across the depletion layer
and is called barrier potential (V0). The barrier potential of a pn junction
depends upon several factors including the type of semiconductor
material, the amount of doping and temperature.
Fig.13
The typical barrier potential is approximately: For silicon, V0 = 0.7 V; for germanium, V0 = 0.3 V;
shows the potential (V0) distribution curve in Fig.13.

7
Operation of pn junction diode
Biasing:
In electronics, the term bias refers to the use of d.c. voltage or applying d.c voltage across pn
junction to establish certain operating conditions for an electronic device. In relation to a pn
junction, there are following two bias conditions:
1. Forward biasing
2. Reverse biasing
1. Forward biasing:
When external D.C. voltage applied to the junction is in such a direction that it cancels the
potential barrier, thus permitting current flow, it is called forward biasing.
To apply forward bias, connect positive terminal of the battery to p-type and negative terminal to
n-type as shown in Fig.14(i). The applied forward potential establishes an electric field which acts
against the field due to potential barrier. Therefore, the resultant field is weakened and the barrier
height is reduced at the junction as shown in Fig.14(ii).

(i) (ii)

(i) (ii)
Fig.14
As potential barrier voltage is very small (0.1 - 0.3 V), therefore, a small forward voltage (VF) is
sufficient to completely eliminate the barrier. Once the potential barrier is eliminated by the
forward voltage, junction resistance becomes almost zero and a low resistance (called forward
resistance, Rf) path is established for the entire circuit and the diode acts as a closed switch.

2.Reverse biasing:
When the external d.c. voltage applied to the junction is in such a direction that potential barrier is
increased, it is called reverse biasing.
To apply reverse bias, connect negative terminal of the battery to p-type and positive terminal to n-
type as shown in Fig.15(i). The applied reverse voltage (VR) establishes an electric field which
acts in the same direction as the field due to potential barrier. Therefore, the resultant field at the
junction is strengthened and the barrier height is increased as shown in Fig.15 (ii).

8
 The increased potential barrier prevents the flow of charge carriers across the junction. Thus, a
high resistance (called reverse resistance, Rr) path is established for the entire circuit and hence the
current does not flow. Therefore, the diode acts as an open switch.

Volt-Ampere (V-I) Characteristics of pn Junction diode:

Volt-ampere or V-I characteristic of a pn junction (also called a crystal or semiconductor

diode) is the curve between voltage across the junction and the circuit current. Usually, voltage is
taken along x- axis and current along y-axis. The characteristics are analyzed in 3 conditions,
namely - zero external voltage, forward bias and reverse bias.
i) Zero external voltage (no bias): When the external voltage is zero, the potential barrier at the
junction does not permit current flow. Therefore, the circuit current is zero as indicated by point O
in Fig. 16.

Fig.15

Fig.16
ii) Forward bias:
At some forward voltage (0.7V - Si and 0.3V - for Ge), the potential barrier is altogether
eliminated and current starts flowing in the circuit. This forward voltage at which the current
through the junction starts to increase rapidly is known as Knee voltage. Therefore, the knee
voltage for silicon diode is 0.7 V and 0.3 V for germanium diode as shown in Fig.17.

Fig.17
From the forward characteristic, it is seen that at first (region OA), the current increases very
slowly and the curve is non-linear. It is because the external applied voltage is used up in
9
overcoming the potential barrier. However, Once the applied forward voltage exceeds the knee
voltage, the current starts increasing rapidly in linear manner. Thus, a rising curve AB is obtained
with forward bias as shown in Fig. 16. and the pn junction behaves like an ordinary conductor.

iii) Reverse bias:

With reverse bias to the pn junction potential barrier at the junction is increased. Therefore, the
junction resistance becomes very high and practically no current flows through the circuit.
However, in practice, a very small current (of the order of µA) flows in the circuit with reverse
bias as shown in the reverse characteristic in Fig. 16. This is called reverse saturation current
(Is) and is due to the minority carriers (few free electrons in p-type material and a few holes in n-
type material) produced due to breaking of some co-valent bonds at room temperature as shown in
Fig. 15(i).
If reverse voltage is increased continuously, the kinetic energy of electrons (minority
carriers) may become high enough to knock out electrons from the semiconductor atoms. At this
stage breakdown of the junction occurs, characterized by a sudden rise of reverse current and a
sudden fall of the resistance of barrier region. This may destroy the junction permanently. The
minimum reverse voltage at which pn junction breaks down with sudden rise in reverse current is
called as Breakdown Voltage.

Avalanche breakdown
Avalanche breakdown occurs in a pn junction diode which is lightly doped and has a thick
junction, so in avalanche breakdown usually occurs when apply a high reverse voltage across the
diode.
(The width of the depletion region is determined by the requirement that the total charge on the
p-side equals the total charge on the n-side, maintaining overall charge neutrality. In a lightly
doped region, the concentration of free carriers is low, so it takes a larger physical distance (a
wider depletion region) to accumulate enough immobile ions to balance the charge from the other
side. Conversely, in a heavily doped region, there is a high concentration of impurity atoms and
therefore more charge per unit area. This means it takes less physical distance (a narrower
depletion region) to accumulate enough charge to achieve balance).
If applied reverse voltage is Va and the depletion layer width is d; then the generated electric field
can be Ea =Va / d.
Even at room temperature, some hole-electron pairs (minority carriers) are produced in the

(ii)
(i)
Fig.18 Avalanche Breakdown
depletion layer as shown in Fig. 18(i). The generated electric field exerts a force on the electrons
10
 at junction and it frees them from covalent bonds. These free electrons will gain acceleration and
it will start moving across the junction with high velocity. This results in collision with other
neighboring atoms. These collisions in high velocity will generate further free electrons as shown
in Fig. 18(ii). In this way, an avalanche of free electrons is occurred. These electrons will start
drifting and electron-hole pair recombination occurs across the junction. This results in net current
that rapidly increases. Therefore, the pn junction conducts a very large reverse current. Once the
breakdown voltage is reached, the high reverse current may damage the junction. Therefore, care
should be taken that reverse voltage across a pn junction is always less than the breakdown
voltage.

Zener Diode
A properly doped crystal diode which has a sharp breakdown voltage is known as a zener diode.
The breakdown or zener voltage depends upon the amount of doping. If the diode is heavily
doped, depletion layer will be thin and consequently the breakdown of the junction will occur
at a lower reverse voltage compared to crystal diode / pn junction diode.
Fig. 19 (i) shows the symbol of a zener diode. It is just like
an ordinary diode except that the bar is turned into z-shape.
From Fig. 19(ii), the following points may be noted about the
zener diode: (i)

(i) A zener diode is like an ordinary diode except that it is

heavily doped so as to have a sharp breakdown voltage.
(ii) A zener diode is always reverse connected i.e. it is
always reverse biased.
(iii) A zener diode has sharp breakdown voltage, called zener
voltage VZ.
(iv) When forward biased, its characteristics are just those of
ordinary diode.
(ii)

Fig.19 Zener Diode

11
Comparison between Zener Breakdown vs Avalanche Breakdown:

Zener Breakdown Avalanche Breakdown

Fig. 20

Aspect Avalanche Breakdown Zener Breakdown

Doping Level Lightly doped (wide depletion region) Heavily doped (narrow depletion region)
Breakdown Voltage Higher, typically >5V Lower, typically <5V
Quantum tunneling due to strong electric
Mechanism Carrier multiplication through collisions
field
Reverse Current Increases gradually after breakdown Increases sharply after breakdown
Voltage regulation and low-voltage
Application High-voltage protection
protection

12
 TRANSISTOR

Transistor: A transistor consists of two pn junctions formed by sandwiching either p-type or n-

type semiconductor between a pair of opposite types.
There are two types of transistors, are (i) n-p-n transistor (ii) p-n-p transistor

Fig. 21
In each type of transistor:
(i) These are two pn junctions. Therefore, a transistor may be regarded as a combination of
two diodes connected back-to-back.
(ii) There are three terminals, one taken from each type of semiconductor.
(iii) The middle section is a very thin layer. This is the most important factor in the function of a
transistor.

A transistor (pnp or npn) has three sections of doped semiconductors. The section on one
side is the emitter and the section on the opposite side is the collector. The middle section is
called the base and forms two junctions between the emitter and collector.

(i) Emitter (E): The section on one side that emits or supplies charge carriers (electrons or
holes) is called the emitter. The emitter is always forward biased w.r.t. base so that it can supply a
large number of majority carriers.

In Fig. 22 (i), the emitter (p-type) of pnp transistor is forward biased and supplies holes to
its junction with the base. Similarly, in Fig. 22 (ii), the emitter (n-type) of npn transistor has a
forward bias and supplies free electrons to its junction with the base.

(ii) Collector (C): The section on the other side that collects the charges carriers is called the
collector. The Collector is always reverse biased. Its function is to remove charges from its junction
with the base.
In Fig. 22 (i), the collector (p-type) of pnp transistor has a reverse bias and receives holes
that flow in the output circuit. Similarly, in Fig. 22 (ii), the collector (n-type) of npn transistor has
reverse bias and receives electrons.

(iii) Base (B): The middle section which forms two pn-junctions between the emitter and
collector is called the base. The base-emitter junction is forward biased, allowing low resistance
for the emitter circuit. The base-collector junction is reverse biased and provides high resistance
in the collector circuit.

13
 Fig. 22
1. The base is much thinner than the emitter while collector is wider than both (During
transistor operation, much heat is produced at the collector junction. The collector is made larger to
dissipate the heat) as shown in Fig.22. However, for the sake of convenience, it is customary to
show emitter and collector to be of equal size.
2. The emitter is heavily doped so that it can inject a large number of charge carriers (electrons or
holes) into the base. The base is lightly doped and very thin; it passes most of the emitter injected
charge carriers to the collector. The collector is moderately doped.
3. The transistor has two pn junctions i.e. it is like two diodes. The junction between emitter and
base may be called emitter-base diode or simply the emitter diode. The junction between the base
and collector may be called collector-base diode or simply collector diode. The emitter diode is
always forward biased (low resistance), whereas collector diode is always reverse biased (high
resistance).

Working of Bipolar Junction Transistor (BJT):

A transistor or Bipolar Junction Transistor (BJT) is a three terminal (E, B & C) semiconductor
device in which the conduction depends on both majority and minority charge carriers and hence the
name bipolar. A BJT operates based on the control of current flow between the emitter and collector
by manipulating the flow of charge carriers through the base (B) region.
npn Transistor:
Fig. 23 Shows the npn transistor with forward bias to emitter-base junction and reverse bias to
collector-base junction. The forward bias causes the electrons in the n-type emitter to flow
towards the base. This constitutes the emitter current IE, as these electrons flow through the p-type
base, they tend to combine with holes. As the base is lightly doped and very thin, therefore only a
few electrons combine with holes to constitute base current IB. The remainder more than 95 %
cross over into the collector region to constitute collector current IC. In this way almost the entire
emitter current flows in the collector circuit. It is clear that emitter current is the sum of collector
and base currents. i.e., IE=IB+IC
IC is independent of VCB and depends upon IE only. The transistor is always operated in this region.
i.e., Active region.

Fig. 23 npn transistor

14
pnp Transistor:
Fig. 24 shows that the basic connection of a pnp transistor. The forward bias causes the holes in the
p-type emitter to flow towards the base. The constitutes the emitter current IE. As these holes cross
into n-type base, they tend to combine with the electrons. As the base is lightly doped and very thin
therefore only a few holes (less than 5%) combine with the electrons. The remainder (more than
95%) cross into the collector region to constitute collector current IC. In this way, almost the entire
emitter current flows in the collector circuit. It may be noted that current conduction within pnp
transistor is by holes. However, in the external connecting wires, the current is still by electrons.

Fig. 24 pnp transistor

Transistor Symbols:

Fig. 25

Note that emitter is shown by an arrow which indicates the direction of conventional current flow
with forward bias. For npn connection, it is clear that conventional current flows out of the
emitter as indicated by the outgoing arrow in Fig. 25 (i). Similarly, for pnp connection, the
conventional current flows into the emitter as indicated by inward arrow in Fig. 25 (ii).

15
CONFIGURATION OF TRANSISTOR CIRCUIT
There are three leads in a transistor viz., emitter, base and collector terminals. However, when a
transistor is to be connected in a circuit, require four terminals; two for the input and two for the
output. This difficulty is overcome by making one terminal of the transistor common to both input
and output terminals. The input is fed between this common terminal and one of the other two
terminals. The output is obtained between the common terminal and the remaining terminal.
Accordingly; a transistor can be connected in a circuit in the following three ways:

TYPES OF CONFIGURATIONS

1) Common base (CB) configuration

2) Common emitter (CE) configuration
3) Common collector (CC) configuration

COMMON BASE (CB) CONFIGURATION:

In this circuit arrangement, input is applied between emitter and base and output is taken from
collector and base. Here, base of the transistor is common to both input and output circuits and
hence the name common base connection. In Fig. 26 (i), a common base npn transistor circuit is
shown whereas Fig. 26 (ii) shows the common base pnp transistor circuit.

Fig. 26 CB Configuration for i) npn transistor ii) pnp transistor

Input characteristics:

It is the curve between emitter current IE and emitter-base

voltage VEE or VEB at constant collector-base voltage VCB.
1. When VCB = 0, the emitter-base junction is forward
biased and the junction behaves as a forward biased
diode. The emitter current IE increases rapidly with small
increase in emitter-base voltage VEB. It means that input
resistance is very small.
2. When VCB is increased keeping VEB constant, the
collector – base junction gets more and more reverse
biased, the width of the depletion region will increase and
due to this, the base region is narrower. Then, less voltage is required to forward bias the emitter-
base junction. This results in an increase in IE.

16
Output characteristics:

It is the curve between collector current IC and collector-base voltage VCB at constant emitter current IE.

1. When the value of VCB is raised above 1 − 2 V, the collector current becomes constant as indicated by
straight horizontal curves. It means that now IC is independent of VCB and depends upon IE only. The
transistor is always operated in this region. i.e.,
Active region.

2. The collector current IC varies with VCB only at

very low voltages (< 1V). The transistor is never
operated in this region. i.e., Cut-off and Saturation
region.

When VCB is negative (forward biased),

electrons which have entered into the base region
from the emitter will not be able to cross the
collector junction and due to that, collector current
starts to reducing. So, whenever, both emitter-base
junction and the collector-base junction are forward
biased then the BJT will operate in Saturation Region.

When VEE is negative (Reverse biased), the emitter current IE will be zero. At this time, even if
increase the collector to base voltage (VCB ), the IC almost remains zero (except current due to minority
charge carriers, i.e., reverse saturation current. So, whenever, both emitter-base junction and the collector-
base junction are reverse biased then the BJT will operate in Cut-off Region.

Mode Emitter -base junction Collector-base junction Region of Operation

I Forward Biased Reverse Biased Active Region
II Reverse Biased Forward Biased Inverse Active Region
III Forward Biased Forward Biased Saturation Region
IV Reverse Biased Reverse Biased Cut – off region

COMMON EMITTER (CE) CONFIGURATION:

In this circuit arrangement, input is applied between base and emitter and output is taken from the
collector and emitter. Here, emitter of the transistor is common to both input and output circuits
and hence the name common emitter connection. Fig. 27 (i) shows common emitter npn transistor
circuit whereas Fig. 27. (ii) shows common emitter pnp transistor circuit.

Fig. 27 CE Configuration for i) npn transistor ii) pnp transistor

17
 Input characteristics:
It is the curve between base current IB and base-emitter
voltage VBB or VBE at constant collector-emitter voltage
VCE or VCC.
1. The characteristic resembles that of a forward biased
diode curve, since the base-emitter section of transistor is
a diode and it is forward biased.
2. When VCE is increased (VCE = VCB + VBE ), the width of
the depletion region at the reverse biased collector – base
junction will increase. This will reduce the effective width
of the base region and due to this, the probability of recombination is reduced. Then, most of the
electrons will get collected at the collector terminal and leads to decrease in the base current IB. In
order to provide the same amount of IB, VBE should be increased. Hence, the curves appear to the
right as VCE increases.

Output characteristics:

It is the curve between collector current IC and collector-emitter voltage VCE at constant base
current IB.

In the active region, the collector current IC varies

with VCE for VCE between 0 and 1V only. A small
increase in IC with increasing VCE is caused by the
collector depletion layer getting wider and capturing a
few more majority carriers before electron-hole
combinations occur in the base area. After this,
collector current becomes almost constant and
independent of VCE. This value of VCE upto which
collector current IC changes with VCE is called the
knee voltage (Vknee). The transistors are always
operated in the region above knee voltage.

When the VCE falls, the IC also decreases rapidly. The collector-base junction of the transistor
always in forward bias and work saturate. In the saturation region, the collector current becomes
independent and free from the input current IB.

In cut-off region, if IB = 0, collector current IC have finite magnitude unlike CB configuration.

18
COMMON COLLECTOR (CC) CONFIGURATION:
In this circuit arrangement, input is applied between base and collector while output is taken
between the emitter and collector. Here, collector of the transistor is common to both input and
output circuits and hence the name common collector connection. Fig. 28 (i) shows common
collector npn transistor circuit whereas Fig. 28 (ii) shows common collector pnp circuit.

VCC VCC

VEE VEE
Fig. 28 CC Configuration for i) npn transistor ii) pnp transistor

Input characteristics:
It is the curve between base current IB and base-collector voltage VCB at constant collector-emitter
voltage VCE.
For the fixed value of VCE, as increase the VCB, then
the base current IB reduces. Because, VCE = VCB +
VBE, as VCB increases, the width of the collector –
base junction increases and effective base width
decreases.
For the fixed value of VCB , as increase the
voltage VCE , the voltage VBE get increased and it
pushes the more electrons into the base region, then IB
increases.

Output characteristics:
It is the curve between emitter current IE and emitter-collector voltage VCE at constant base current
IB. These characteristics are similar to the CE configuration as the output current, i.e., emitter
current (IE) is almost equal to the collector current (IC).

19
Transistor as an Amplifier

A transistor raises the strength of a weak signal and thus acts as an amplifier. Fig. 29
shows the basic circuit of a transistor amplifier. The weak signal is applied between emitter base
junction and output is taken across the load RC connected in the collector circuit. In order to
achieve faithful amplification, the input circuit should always remain forward biased. To do so, a
d.c voltage VEE is applied in the input circuit in addition to the signal.

Fig. 29

SINGLE STAGE CE AMPLIFIER:

Fig. 30(i) shows the common emitter (CE) npn amplifier circuit. A battery VBB is connected in the
input circuit in addition to the signal voltage. This d.c. voltage is known as bias voltage and its
magnitude is such that it always keeps the emitter-base junction forward biased regardless of the
polarity of the signal source.

(i) (ii)

Fig. 30 Transistor as an Amplifier in CE Arrangement

Operation:
During the positive half-cycle of the signal, the forward bias across the emitter base junction is
increased. Therefore, more electrons flow from the emitter to the collector via the base. This
causes an increase in collector current. The increased collector current produces a greater voltage
drop across the collector load resistance RC. However, during the negative half- cycle of the signal,
the forward bias across emitter-base junction is decreased. Therefore, collector current decreases.
This results in the decreased output voltage (in the opposite direction). Hence, an amplified output
is obtained across the load.

20
Analysis of collector currents:

When no signal is applied, the input circuit is forward biased by the battery VBB. Therefore, a d.c.
collector current IC flows in the collector circuit. This is called zero signal collector current.

When the signal voltage is applied, the forward bias on the emitter base junction increases or
decreases depending upon whether the signal is positive or negative. During the positive half-cycle
of the signal, the forward bias on emitter-base junction is increased, causing total collector current
iC to increase. Reverse will happen for the negative half-cycle of the signal.

Fig. 30 (ii) Shows the graph of total collector current IC versus time. From the graph it is clear that
total current consists of two components namely,
(i) The dc collector current IC (zero signal collector current) due to bias battery VBB. This is the
current that flows in the collector in the absence of signal.
(ii) The a.c collector current ic due to signal

Total collector current iC = ic+IC.

21
Basic Electronic Circuits and Instrumentation
Rectifiers and power supplies: Block diagram description of a dc power supply, working and
analysis of a Half wave and full wave bridge rectifier, capacitor filter (no analysis), working of
simple Zener voltage regulator.
Electronic Instrumentation: Block diagram of an electronic instrumentation system, Digital
Voltmeter (DVM), Cathode Ray Oscilloscope (CRO).
REGULATED POWER SUPPLY
An electronic circuit that produces a stable DC voltage of fixed value across the load
terminals irrespective of changes in the load is known as regulated power supply. The primary
function of a regulated power supply is to convert an AC power into a steady DC power. The
regulated supply is sometimes called as a linear power supply. The block diagram of regulated
power supply is shown in Fig.1.

Fig.1 Block diagram description of a dc power supply

The basic building blocks of a regulated DC power supply are as follows:
1. Transformer
2. Rectifier
3. Smoother / Filter.
4. Regulator
Transformer:
A transformer modifies the alternating current (AC) mains voltage to a required value, and its
primary function is to step up or step down the voltage. A step-down transformer, for example, is
used in a transistor radio, while a step-up transformer is used in a CRT.
Rectifier:
The rectifier circuit is used to convert the input AC voltage into a DC voltage. The input to a
rectifier is AC whereas its output is pulsating DC. Rectification process can be carried out for
the entire cycle or only for half-cycle. Broadly there are two types of rectifiers such as i) half-
wave rectifier, and ii) full-wave rectifier. Full-wave rectifier is used for full wave rectification
and half-wave rectifier provides rectification for half-cycle.
Smoother/ Filter:
The rectifier's output is pulsating DC with large ripple content and hence, the rectifier's output is
undesirable. A filter is used to provide a pure ripple-free DC. The filter circuit converts the
pulsating DC voltage into a constant direct voltage with almost zero ripple content. Different types
of filter circuits such as capacitor (C) filter, choke input (L) filter, CLC filter and LC filter.
Regulator:
The output voltage may change or fluctuate due to any change in the input ac voltage or the change
in load or change in physical parameters such as temperature of the circuit. This problem can be
eliminated with the help of a regulator. A regulator maintains the output constant even when
changes at the input voltage or any other changes occur. Different types of regulator circuits such
as Zener diode operating in Zener region, transistor in series and IC regulators are available.
HALF-WAVE RECTIFIER
In half-wave rectification, the rectifier conducts current only during the positive half-cycles of
input a.c. supply. The negative half-cycles of a.c. supply are suppressed i.e. during negative half-
cycles, no current is conducted and hence no voltage appears across the load. Therefore, current
always flows in one direction (i.e., d.c.) through the load though after every half-cycle.

(i) (ii)
Fig.2
Circuit details:
Fig. 2(i) shows the circuit where a single crystal diode acts as a half-wave rectifier. The a.c. supply
is given through a transformer and it can be used to step up or step down the a.c. input voltage &
also isolates the rectifier circuit from power line and thus reduces the risk of electric shock.
The a.c. supply Vin = Vm Sin(t) is applied across the secondary winding of the transformer in series
with the diode of resistance Rf and load resistance RL.
Operation:
The a.c. voltage across the secondary winding AB changes polarities after every half-cycle.
During the positive half-cycle of input a.c. voltage, end A becomes positive w.r.t. end B. This
makes the diode forward biased (acts as a closed switch) and hence it conducts current. Apply
KVL to the circuit, which gives Vout = Vin & Iout = I = Vout / RL. It indicates that, the output follows
the input and is shown in Fig. 2(ii).
During the negative half-cycle, end A is negative w.r.t. end B. Under this condition, the
diode is reverse biased (acts as an Open switch) and it conducts no current, then Vout & Iout = 0.
Therefore, current flows through the diode during positive half-cycles of input a.c. voltage only;
it is blocked during the negative half-cycles is shown in Fig. 2(ii). In this way, current flows
through load RL always in the same direction. Hence d.c. output is obtained across R L. It may be
noted that output across the load is pulsating d.c. These pulsations in the output are further
smoothened with the help of filter circuits.
DC Power:
The output current is pulsating direct current. Therefore, in order to find d.c. power, average
current has to be found out.
Area under curve over the full cycle
Iavg = Idc = (1)
base length over the full cycle

2π π 2π π π Vm sint 2Vm
Area = ∫0 i . dt = ∫0 i . dt + ∫π i . dt = ∫0 i . dt + 0 = ∫0 . dt = (2)
Rf +RL Rf +RL

From eqn (1) and (2),

𝟏 𝟐𝐕𝐦 𝐈𝐦
𝐈𝐚𝐯𝐠 = 𝐈𝐝𝐜 = ∗ = (3)
𝟐𝛑 𝐑𝐟 +𝐑𝐋 𝛑

Vm
Where, Im = Rf +RL

𝐈 𝟐
⸫ DC output power, Pdc = Idc 2 ∗ R L = ( 𝛑𝐦 ) ∗ R L (4)

AC Power: The a.c. power input is given by,

Pac = Irms 2 ∗ (R f + R L ) (5)

RMS value of load current can be obtained as,

Area under squared curve over the full cycle

Irms = Iac = √
base length over the full cycle

𝟏 𝛑 𝟐𝛑 𝟏 𝛑 𝐈𝐦
𝐈𝐫𝐦𝐬 = √𝟐𝛑 (∫𝟎 𝐢𝟐 . 𝐝𝐭 + ∫𝛑 𝐢𝟐 . 𝐝𝐭 ) = √𝟐𝛑 (∫𝟎 (𝐈𝐦 𝐬𝐢𝐧𝐭)𝟐 . 𝐝𝐭 ) = (6)
𝟐

From eqn (5) and (6),

I 2
⸫ Pac = ( 2m ) ∗ (R f + R L ) (7)

Rectifier Efficiency:
The ratio of d.c. power output to the applied input a.c. power is known as rectifier efficiency.

𝐈 𝟐
𝐝𝐜 𝐩𝐨𝐰𝐞𝐫 𝐨𝐮𝐭𝐩𝐮𝐭 ( 𝐦 ) ∗ RL 𝟎.𝟒𝟎𝟔 RL 𝟎.𝟒𝟎𝟔
𝛑
ɳ= = I 2 = = Rf (8)
𝐈𝐧𝐩𝐮𝐭 𝐚𝐜 𝐩𝐨𝐰𝐞𝐫 ( m ) ∗ (Rf + RL ) (Rf + RL ) 𝟏+
2 RL

The efficiency will be maximum if Rf is negligible as compared to RL.

∴ Max. rectifier efficiency = 40.6%
This shows that in half-wave rectification, a maximum of 40.6% of a.c. power is converted into
d.c. power.
FULL-WAVE BRIDGE RECTIFIER
In full-wave rectification, current flows through the load in the same direction for both half-cycles
of input a.c. voltage. This can be achieved with two diodes working alternately. For the positive
half-cycle of input voltage, one diode supplies current to the load and for the negative half-cycle,
the other diode does so; current being always in the same direction through the load. Therefore, a
full-wave rectifier utilises both half-cycles of input a.c. voltage to produce the d.c. output.

(i)
(ii)
Fig.3
It contains four diodes D1, D2, D3 and D4 connected to form bridge as shown in Fig.3(i). The a.c.
supply to be rectified is applied to the diagonally opposite ends of the bridge through the
transformer. Between other two ends of the bridge, the load resistance RL is connected.
Operation:
During the positive half-cycle of secondary voltage, the end P of the secondary winding becomes
positive and end Q negative. This makes diodes D1 and D3 forward biased while diodes D2 and
D4 are reverse biased. Therefore, only diodes D1 and D3 conduct. These two diodes will be in
series through the load RL as shown in Fig. 4 (i). The conventional current flow is shown by dotted
arrows. It may be seen that current flows from A to B through the load RL.
During the negative half-cycle of secondary voltage, end P becomes negative and end Q positive.
This makes diodes D2 and D4 forward biased whereas diodes D1 and D3 are reverse biased.
Therefore, only diodes D2 and D4 conduct. These two diodes will be in series through the load RL
as shown in Fig. 4 (ii). The current flow is shown by the solid arrows. It may be seen that again
current flows from A to B through the load i.e. in the same direction as for the positive half-cycle.
Therefore, d.c. output is obtained across load RL.

(i) (ii)
Fig.4
DC Power:
The output current is pulsating direct current. Therefore, in order to find d.c. power, average
current has to be found out.
Area under curve over the full cycle
Iavg = Idc = (9)
base length over the full cycle

2π π 2π π Vm sint 2π Vm sint 4Vm

Area = ∫0 i . dt = ∫0 i . dt + ∫π i . dt = ∫0 . dt + ∫π . dt = (10)
Rf +RL Rf +RL Rf +RL

From eqn (9) and (10),

𝟏 𝟒𝐕𝐦 𝟐𝐈𝐦
𝐈𝐚𝐯𝐠 = 𝐈𝐝𝐜 = ∗ = (11)
𝟐𝛑 𝐑𝐟 +𝐑𝐋 𝛑

Vm
Where, Im = Rf +RL

𝟐𝐈𝐦 𝟐
⸫ DC output power, Pdc = Idc 2 ∗ R L = ( 𝛑
) ∗ RL (12)

AC Power: The a.c. power input is given by,

Pac = Irms 2 ∗ (R f + R L ) (13)

RMS value of load current can be obtained as,

Area under squared curve over the full cycle

Irms = Iac = √
base length over the full cycle

𝟏 𝛑 𝟐𝛑 𝟏 𝛑 𝟐𝛑 𝐈𝐦
𝐈𝐫𝐦𝐬 = √ (∫𝟎 𝐢𝟐 . 𝐝𝐭 + ∫𝛑 𝐢𝟐 . 𝐝𝐭 ) = √ (∫𝟎 (𝐈𝐦 𝐬𝐢𝐧𝐭)𝟐 . 𝐝𝐭 + ∫𝛑 (𝐈𝐦 𝐬𝐢𝐧𝐭)𝟐 . 𝐝𝐭 ) = (14)
𝟐𝛑 𝟐𝛑 √𝟐

From eqn (5) and (6),

I 2
⸫ Pac = ( m ) ∗ (R f + R L )
√2
(15)

Rectifier Efficiency:
The ratio of d.c. power output to the applied input a.c. power is known as rectifier efficiency.

𝟐𝐈 𝟐
𝐝𝐜 𝐩𝐨𝐰𝐞𝐫 𝐨𝐮𝐭𝐩𝐮𝐭 ( 𝐦 ) ∗ RL 𝟎.𝟖𝟏𝟐 RL 𝟎.𝟖𝟏𝟐
𝛑
ɳ= = I 2 = = Rf
𝐈𝐧𝐩𝐮𝐭 𝐚𝐜 𝐩𝐨𝐰𝐞𝐫 ( m ) ∗ (Rf + RL ) (Rf + RL ) 𝟏+
√2 RL

The efficiency will be maximum if Rf is negligible as compared to RL.

∴ Max. rectifier efficiency = 81.2 % (16)
This is double the efficiency due to half-wave rectifier. Therefore, a full-wave rectifier is twice as
effective as a half-wave rectifier.
RIPPLE FACTOR
The ratio of r.m.s. value of a.c. component to the d.c. component in the rectifier output is known
as ripple factor (RF) i.e.,

RMS value of a.c component Iac 𝐼 2

Ripple factor (RF) = = = √( 𝑅𝑀𝑆 ) − 1
value of dc component Idc 𝐼𝑑𝑐

The output of a rectifier consists of a d.c. component and an a.c. component (also known as ripple).
The a.c. component is undesirable and accounts for the pulsations in the rectifier output. The
effectiveness of a rectifier depends upon the magnitude of a.c. component in the output; the
smaller this component, the more effective is the rectifier.
(i) For Half – wave rectifier:
Im Im
Irms = ; Idc = , then Ripple factor = 1.21 = 121 %.
2 π

It is clear that a.c. component exceeds the d.c. component in the output of a half-wave rectifier.
This results in greater pulsations in the output. Therefore, half-wave rectifier is ineffective for
conversion of a.c. into d.c.
(ii) For Full – wave rectifier:
Im 2Im
Irms = ; Idc = , then Ripple factor = 0.48 = 48 %.
√2 π

This shows that in the output of a full-wave rectifier, the d.c. component is more than the a.c.
component. Consequently, the pulsations in the output will be less than in half-wave rectifier. For
this reason, full-wave rectification is invariably used for conversion of a.c. into d.c.

FILTER CIRCUITS
A filter circuit is a device which removes the a.c. component of rectifier output but allows the d.c.
component to reach the load.

Fig. 5
A filter circuit should be installed between the rectifier and the load as shown in Fig. 5.
Capacitor (C) filter:
Fig. 6(i) shows a typical capacitor filter circuit. It consists of a capacitor C placed across the
rectifier output in parallel with load RL. The pulsating direct voltage of the rectifier as shown in
Fig. 6(ii) is applied across the capacitor.

(i)
(ii)
Fig.6
As the rectifier voltage increases,
it charges the capacitor and also
supplies current to the load. At
the end of quarter cycle [Point A
in Fig. 7], the capacitor is charged
to the peak value Vm of the
rectifier voltage. Now, the
rectifier voltage starts to
decrease. As this occurs, the
capacitor discharges through the
load and voltage across it (i.e.
across parallel combination of R- Fig. 7
C) decreases as shown by the line AB in Fig. 7. The voltage across load will decrease only slightly
because immediately the next voltage peak comes and recharges the capacitor. This process is
repeated again and again and the output voltage waveform becomes ABCDEFG. It may be seen
that very little ripple is left in the output. Moreover, output voltage is higher as it remains
substantially near the peak value of rectifier output voltage.
ZENER DIODE AS VOLTAGE REGULATOR/STABILISER
Equivalent
Circuit of Zener Diode:

OFF state

ON state

Fig. 8 Zener Diode Characteristics

(i) “On” state:

When reverse voltage across a zener diode is equal to or more than break down voltage VZ, the
current increases very sharply as shown in Fig. 8. In this region, the curve is almost vertical. It
means that voltage across zener diode is constant at VZ even though the current through it changes.
Therefore, in the breakdown region, an ideal zener diode can be represented by a battery of voltage
VZ as shown in Fig. 9(ii). Under such conditions, the zener diode is said to be in the “ON” state.

Fig. 9
(ii) “OFF” state:
When the reverse voltage across the zener diode is less than VZ but greater than 0 V, the zener
diode is in the “OFF” state. Under such conditions, the zener diode can be represented by an open-
circuit as shown in Fig. 10(ii).
 Fig. 10
Voltage Regulator functioning:
A zener diode can be used as a voltage regulator to provide a constant voltage from a source whose
the input voltage Ei and load resistance RL may vary over a wide range. The circuit arrangement
is shown in Fig. 11(i). The zener diode of zener voltage VZ is reverse connected across the load
RL across which constant output is desired. It may be noted that the zener will maintain a
constant voltage VZ (= E0) across the load so long as the input voltage does not fall below VZ.

Fig. 11
(i) Suppose the input voltage increases. Since the zener is in the breakdown region, the zener
diode is equivalent to a battery VZ as shown in Fig. 11(ii). The excess voltage is dropped across
the series resistance R, because output voltage remains constant at VZ (= E0). This will cause an
increase in the value of total current I. The zener will conduct the increase of current in I while
the load current remains constant. Hence, output voltage E0 remains constant irrespective of the
changes in the input voltage Ei.
(ii) Now suppose that input voltage is constant but the load resistance RL decreases. This will
cause an increase in load current IL. The extra current cannot come from the source because source
voltage will not change as the zener is within its regulating range. The additional load current will
come from a decrease in zener current IZ. Consequently, the output voltage stays at constant value.
ELECTRONIC INSTRUMENTATION SYSTEM

Fig.12 Block diagram of an electronic instrumentation system

The block diagram of generalized electronics instrumentation system as shown in Fig., in

which number ofelements worked together to perform a desired function accurately i.e. to
measure the measurand quantity and display it or record it.
Measurand (physical quantity or electrical quantity):
• The physical or electrical quantity which is to be measured is called as measurand. If
the input to the instrumentation is parameter like pressure, force, level, strain,
displacement, temperature, flow, velocity etc. then these parameters are physical
measurand. These measurand are applied to the transducer element.
• If the input is current, voltage and frequency then these parameters are called electrical
measurand. These measurand are applied to the electrical conversion element.
Transducer and electrical conversion elements:
• If the measurand is physical quantity then it is converted into equivalent electrical signal
with help of element which is called transducer.
• If the measurand is electrical signal like voltage, current or frequency then it is given
to the electrical conversion element which convert the signal into more suitable form
of signals.
Signal processing or signal conditioning:
• In electronic instrumentation system, filter, modulator, A/D converters, D/A converter,
amplifiers, integrators, differentiators are the important signal conditioningcircuits.
• This stage is required to convert the transducer output into an electrical quantity
suitable for proper operation of the last stage or indicator.
Data transmission element:
• This element provides a transmission path for the modified signals to travel from
transducer element to the rest of instrumentation elements like recorders, controllers,
displays etc.
• In electronic instrumentation system, typically the transmission path is a conducting
line (i.e. electrical cables).
Data presentation element:
• Function performed by this stage may be demodulation, amplification, filtering, A/D
conversion etc.
• This element modifies the signals in such a way that the signals are accepted by
recorders, displays, indicators, printers, announcing systems etc. The output of the
 data presentation element is provided to the recorders, controllers, and indicators as
per the requirement of the user or operator or observer.
Output devices:
• The last stage of instrumentation system is required to provide the information about
the measurand for immediate reorganization by the operator whatever output is
presented on indicator.
• If the system is control system in that case the measured data not only displayed or
recorded but also compared with some reference value and control action is
generatedwhich is used to remove the error.
Power supply:
• This is a common unit for all instrumentation system. This provides power to all
elements working in the instrumentation setup.

DIGITAL VOLTMETER (DVM)

Voltmeter is an electrical measuring instrument used to measure potential difference
between two points. The voltage to be measured may be AC or DC. Two types of voltmeters
are available for the purpose of voltage measurement i.e. analog and digital.
Analog voltmeters generally contain a dial with a needle moving over it according
to the measure andhence displaying the value of the same. Digital voltmeters display the
value of AC orDC voltage being measured directly as discrete numerical decimal number
system instead of a pointer deflection on a continuous scale as in analog instruments.

Fig.13 Block diagram of a Digital Voltmeter (DVM)

Working:
• Unknown voltage signal (I/P) is fed to the pulse generator which generates a train of
rectangular pulse whose width is proportional to the input signal.
• Output of pulse generator is fed to one leg of the AND gate and the input signal to the other
leg of the AND gate is a train of pulses.
• AND gate gives high output only when both the inputs are high. When a train pulse is fed
to it along with rectangular pulse, it provides us an output having train pulses with duration
as same as the rectangular pulse from the pulse generator. Then, Output of AND gate is
positive triggered train of duration same as the width of the pulsegenerated by the pulse
generator.
• The positive triggered train is fed to the inverter which converts it into a negative triggered
train.
• Output of the inverter is fed to a counter which counts the number of triggers in the duration
which is proportional to the input signal i.e. voltage under measurement.
CATHODE RAY OSCILLOSCOPE (CRO)
Cathode Ray Oscilloscope is a versatile laboratory instrument used for studying wave shape of
alternating current and voltage as well as for the measurement of voltage, power and frequency.
The waveform is generated in such a way that the amplitude of the signal is represented along
Y-axis and the variation in the time is represented along X-axis. Essentially, an oscilloscope
consists of the following components as shown in Fig.14.
1. Cathode ray tube (CRT)
2. Low and high voltage (LV & HV) power supply
3. Time base generator
4. Vertical and horizontal amplifiers

Fig.14 Block diagram of a CRO

1. CATHODE RAY TUBE
It is the heart of a CRO. It is used to bombard electrons towards the fluorescent screen. CRT
is an evacuated tube where an electron gun is fitted, which emits electrons towards the
fluorescent screen. A detailed representation of a CRT is given in Fig.15. The major
components of CRT are electron gun, deflection system, fluorescent screen and evacuated
glass envelop.
 Fig.15 Schematic of cathode ray tube (CRT)
a) Electron Gun:
Electron gun is a source of electrons. It provides a sharply focused electron beam directed
towards the fluorescent coated screen. It consists of a heated cathode, control grid, pre-
accelerating anode, focusing anode, and an accelerating anode. The thermally heated cathode
emits electrons in many directions. The control grid provides an axial direction for the electron
beam and controls the number & speed of electrons in the beam. The momentum of the
electrons determines the intensity or brightness of the light emitted from the fluorescent coating
due to the electron bombardment. Because electrons are negatively charged, a repulsion force
is created by applying a negative voltage to the control grid, to adjust their number and speed.
A more negative voltage results in a smaller number of electrons in the beam and hence
decreased brightness of the beam spot. Since the electron beam consists of many electrons, the
beam tends to diverge. This is because the similar (negative) charges on the electrons repulse
each other. To compensate for such repulsion forces, an adjustable electrostatic field is created
between two cylindrical anodes, called the focusing anodes. The variable positive voltage on
the second anode cylinder is therefore used to adjust the focus or sharpness of the bright spot.

(b) Deflection System:

Fig. 16 CRO Screen

The deflection system consists of two pairs of parallel plates, referred to as the vertical and
horizontal deflection plates. One of the plates in each set is permanently connected to the
ground (zero volt), whereas the other plate of each set is connected to input signals or triggering
signal of the CRO and the electron beam passes through the deflection plates. As shown in
Fig.16, a positive voltage applied to the 'Y' input terminal causes the electron beam to deflect
vertically upward, due to attraction forces, while a negative voltage applied to the 'Y' input
terminal causes the electron beam to deflect vertically downward, due to repulsion forces.
Similarly, a positive voltage applied to the 'X' input terminal will cause the electron beam to
deflect horizontally toward the right, while a negative voltage applied to the 'X' input terminal
will cause the electron beam to deflect horizontally toward the left of the screen. The amount
of vertical or horizontal defection is directly proportional to the corresponding applied voltage.
When the electrons hit the screen, the phosphor emits light and a visible light spot is seen on
the screen. Since the amount of deflection is proportional to the applied voltage, actually the
voltages Vy and Vx determine the coordinates of the bright spot created by the electron beam.
(c) Fluorescent Screen:
The light produced by the screen does not disappear immediately when bombardment by
electrons ceases i.e., when the signal becomes zero. The time period for which the trace remains
on the screen after the signal becomes zero is known as persistence. The persistence may be as
short as a few microseconds, or as long as tens of seconds or even minutes. The screen is coated
with a fluorescent material called phosphor which emits light when bombarded by electrons.
There are various phosphors available which differ in colour, persistence and efficiency.
(d) Evacuated Glass Envelope:
All the components of a CRT are enclosed in an evacuated glass tube called envelope. This
allows the emitted electrons to move about freely from one end of the tube to the other end.

2. LOW AND HIGH VOLTAGE POWER SUPPLY

The power supply block provides the voltages required by CRT to generate and accelerate an
electron beam and voltages required by other circuits of the oscilloscope like horizontal
amplifier, vertical amplifier etc.
There are two sections of a power supply block. The high voltage section and low voltage
section. The high voltages of the order of 1000 to 1500V are required by CRT. Such high
negative voltages are used for CRT. The low voltage is required for the heater of the electron
gun, which emits the electrons. This is a positive voltage of the order of few hundred volts.
3. TIME BASE GENERATOR
The generator which generates a wave form which is responsible for the movement of a spot-
on screen horizontally is called time base generator or sweep generator. This produces a saw-
tooth wave form which is used as horizontal deflection voltage of CRT.
4. VERTICAL AMPLIFIER
The vertical amplifier receives the input from the signal which is to be measured and then
amplifies it so that the signal of high intensity is supplied to the vertical deflection plate.
If a low-intensity signal strikes the vertical deflection plate, the electron beam will not be
deflected effectively to create the bright spots on desired points on the screen. Thus, the vertical
amplifier is a significant device.

5. HORIZONTAL AMPLIFIER
The horizontal amplifier generates the signal which provides voltage to horizontal deflection
plates. The horizontal deflection plates deflect the beam along the horizontal direction. This is
helpful to create the waveform along with the time domain.
The horizontal amplifier is the crucial part. This is because the deflection of the electron
beam in the horizontal direction will be effective only when the signal applied from the output
of the horizontal amplifier is high enough to create the bright spots at the desired location on
the phosphor screen.
6. DELAY LINE CIRCUIT
When the signal from the vertical amplifier is fed to the vertical deflection plates, then some
part of the amplified signal is supplied to the time base generator. This trigger pulse generated
from the time-based generator is amplified with the help of the horizontal amplifier.
After this, it is fed to horizontal deflection plates. This process requires approximately
100ns. Thus, it is crucial to delay the signal generated by the vertical amplifier too in order to
maintain synchronization.
DIGITAL LOGIC FUNDAMENTALS
Overview of Number Systems – Binary, Hexa-decimal and BCD numbers. Boolean
Algebra - Basic Theorems - Truth Tables and Functionality of Logic Gates – NOT,
OR, AND, NOR, NAND, XOR and XNOR. Simple combinational circuits–Half and
Full Adders. Introduction to sequential circuits, Clocked S-R and J-K Flip-flops,
Simple examples of two-bit Registers and Counters.
INTRODUCTION ABOUT DIGITAL SYSTEM
A Digital system is an interconnection of digital modules and it is a system that manipulates discrete
elements of information that is represented internally in the binary form.

Now a day’s digital systems are used in wide variety of industrial and consumer products such as
automated industrial machinery, pocket calculators, microprocessors, digital computers, digital
watches, TV games and signal processing and so on.
Characteristics of Digital systems
• Digital systems manipulate discrete elements of information. Discrete elements are nothing but the
digits such as 10 decimal digits or 26 letters of alphabets and so on.
• Digital systems use physical quantities called signals to represent discrete elements.
• In digital systems, the signals have two discrete values (0 or 1) and are therefore said to be binary.
A signal in digital system represents one binary digit called a bit. The bit has a value either 0 or 1.

OVERVIEW OF NUMBER SYSTEMS

Modern computers communicate and operate with binary numbers which use only the digits 0 &1.
Basic number system used by humans is Decimal number system.
To define any number system, specify
• Base or radix indicates the total number of digits available in the number system such as 2 for Binary
number system,8 for octal number system,10 for decimal number system and 16 for Hexa decimal
number system.
• The leftmost digit in any number representation, which has the greatest positional weight out of all
the digits present in that number, is called the most significant digit (MSD) and the rightmost digit,
which has the least positional weight out of all the digits present in that number, is called the least
significant digit (LSD).

1. Binary Number System:

❖ The binary number has a radix of 2. As r = 2, only two digits are needed, and these are 0 and 1.
❖ A binary digit is called a bi and binary number consists of a sequence of bits.
❖ The binary number system is a positional weighted system and weight is expressed as power of 2.
❖ The binary point separates the integer and fraction parts. Each digit (bit) carries a weight based
on its position relative to the binary point. The weight of each bit position is one power of 2 greater
than the weight of the position to its immediate right.
❖ The binary number system is used in digital computers because the switching circuits used in these
computers use two-state devices such as transistors, diodes, etc. A transistor can be OFF or ON, a
switch can be OPEN or CLOSED, a diode can be OFF or ON, etc. These devices have to exist in
one of the two possible states. So, these two states can be represented by the symbols 0 and 1,
respectively.
a) Binary to Decimal Conversion:

❖ The decimal value of the binary number is the sum of the products of all its bits multiplied by the
weights of their respective positions.
❖ In general, a binary number with an integer part of (n + 1) bits and a fraction part of k bits can be
written as Binary Point

dn dn−1 dn−2 … d1 d0 . d−1 d−2 d−3 … d−k

Its decimal equivalent is

(dn ∗ 2𝑛 ) + (dn−1 ∗ 2𝑛−1 ) + ⋯ (d1 ∗ 21 ) + (d0 ∗ 20 ) + (d−1 ∗ 2−1 ) + (d−2 ∗ 2−2 ) …

Ex: Convert 10101(2) to decimal

Positional Weights 24 23 22 21 20
Binary Number 1 0 1 0 1

10101 = (1 * 24) + (0 * 23) + (1 * 22) + (0 * 21) + (1 * 20) = 16 + 0 + 4 + 0 + 1 = 21(10)

Ex: Convert 11011.101(2) to decimal

Positional Weights 24 23 22 21 20 2−1 2−2 2−3

Binary Number 1 1 0 1 1 . 1 0 1

11011.101 = (1 * 24) + (1 * 23) + (0 * 22) + (1 * 21) + (1 * 20) + (1 * 2-1) + (0 * 2-2) + (1 * 2-3)

= 16 + 8 + 0 + 2 + 1 + 0.5 + 0 + 0.125 = 27.625(10)

b) Decimal to Binary Conversion:

❖ In this method, the decimal integer number is converted to the binary integer number by
successive division by 2, and the decimal fraction is converted to binary fraction by successive
multiplication by 2. This is also known as the double-dabble method.
❖ In the successive division-by-2 method, the given decimal integer number is successively
divided by 2 till the quotient is zero. The last remainder is the MSB. The remainders read from
bottom to top give the equivalent binary integer number.

Ex: Convert 52(10) to binary

Reading the remainders from bottom to top, the result is 52(10) = 110100(2)
In the successive multiplication-by-2 method, the given decimal fraction and the subsequent
decimal fractions are successively multiplied by 2, till the fraction part of the product is 0 or till the
desired accuracy is obtained. The first integer obtained is the MSB. Thus, the integers read from top
to bottom give the equivalent binary fraction.

Ex: Convert 0.75(10) to binary

Reading the integers from top to bottom, 0.75(10) = 0.11(2).

To convert a mixed number to binary, convert the integer and fraction parts separately to binary
and then combine them.

Ex: Convert 105.15(10) to binary

 2. Hexadecimal Number System
❖ Binary numbers are long. These numbers are fine for machines but are too lengthy to be handled
by human beings. So, there is a need to represent the binary numbers concisely. One number
system developed with this objective is the hexadecimal number system (or Hex) and it has become
the most popular means of direct data entry and retrieval in digital systems.
❖ The hexadecimal number system is a positional-weighted system. The base or radix of this number
system is 16, that means, it has 16 independent symbols. The symbols used are 0, 1, 2, 3, 4, 5, 6,
7, 8, 9, A, B, C, D, E, and F.
❖ Since its base is 16 = 24, every 4 binary digit combination can be represented by one hexadecimal
digit. So, a hexadecimal number is 1/4th the length of the corresponding binary number, yet it
provides the same information as the binary number. A 4-bit group is called a nibble. Since
computer words come in 8 bits, 16 bits, 32 bits and so on, that is, multiples of 4 bits, they can be
easily represented in hexadecimal. The hexadecimal system is particularly useful for human
communications with computers.

Hexadecimal Decimal Binary

0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
A 10 1010
B 11 1011
C 12 1100
D 13 1101
E 14 1110
F 15 1111

a) Binary to Hexadecimal Conversion:

Ex: Convert 1011011011(2) to hexadecimal.

Make groups of 4 bits from LSB, and replace each 4-bit group by a hex digit.
LSB
Given binary number is 1011011011
Groups of four bits are 0010 1101 1011
Convert each group to hex 2 D B
The result is 2DB (16)
Ex: Convert 01011111011.011111(2) to hexadecimal.

Given binary number is 01011111011.011111

Groups of four bits are 0010 1111 1011 . 0111 1100
Convert each group to hex 2 F B . 7 C
The result is 2FB.7C (16)

b) Hexadecimal to Binary Conversion:

Ex: Convert 4BAC16 to binary

Given hex number is 4 B A C

Convert each hex digit to 4-bit binary 0100 1011 1010 1100
The result is 0100101110101100 (2)

Ex: Convert 3A9E.B0D (16) to binary

Given hex number is 3 A 9 E . B 0 D

Convert each hex digit to 4-bit binary 0011 1010 1001 1110 . 1011 0000 1101
The result is 0011101010011110.101100001101(2)

C) Hexadecimal to Decimal Conversion:

To convert a hexadecimal number to decimal, multiply each digit in the hex number by its position
weight and add all those product terms.

If the hex number is 𝐝𝐧 𝐝𝐧−𝟏 𝐝𝐧−𝟐 … 𝐝𝟏 𝐝𝟎 . 𝐝−𝟏 𝐝−𝟐 𝐝−𝟑 … 𝐝−𝐤 , its decimal equivalent is

(dn ∗ 16𝑛 ) + (dn−1 ∗ 16𝑛−1 ) + ⋯ (d1 ∗ 161 ) + (d0 ∗ 160 ) + (d−1 ∗ 16−1 ) + (d−2 ∗ 16−2 )
+⋯

Ex: Convert 5C7(16) to decimal.

Multiply each digit of 5C7 by its position weight and add the product terms.
5C716 = (5 *162) + (12 * 161) + (7 * 160)
= 1280 + 192 + 7
= 1479(10)

Ex: Convert A0F9.0EB (16) to decimal.

A0F9.0EB16 = (10 *163) + (0 *162) + (15 *161) + (9 *160) + (0 *16-1) + (14 *16-2) + (11 *16-3)
= 40960 + 0 + 240 + 9 + 0 + 0.0546 + 0.0026
= 41209.0572(10)
d) Decimal to Hexadecimal Conversion:

To convert a decimal integer number to hexadecimal, successively divide the given decimal number
by 16 till the quotient is zero. The last remainder is the MSB. The remainders read from bottom to
top give the equivalent hexadecimal integer.

To convert a decimal fraction to hexadecimal, successively multiply the given decimal fraction and
subsequent decimal fractions by 16, till the product is zero or till the required accuracy is obtained,
and collect all the integers to the left of the decimal point. The first integer is the MSB and the integers
read from top to bottom give the hexadecimal fraction. This is known as the hex dabble method.

Ex: Convert 2598.675(10) to hex

The given decimal number is a mixed number. Convert the integer and the fraction parts separately
to hex.

Note: Conversion of very large decimal numbers to binary and very large binary numbers to
decimal is very much simplified if it is done via the hex route.

Ex: Convert 49056(10) to binary

The given decimal number is very large. It is tedious to convert this number to binary directly.
So, convert this to hex first, and then convert the hex to binary.
Ex: Convert 1011011101101110 (2) to decimal.

The given binary number is very large. So, perform the binary to decimal conversion via the
hex route.

Binary Coded Decimal (BCD) Numbers:

Numeric codes are codes which represent numeric information, i.e. only numbers as a series of 0s
and 1s. Numeric codes used to represent the decimal digits are called Binary Coded Decimal (BCD)
codes.
A BCD code is one, in which the digits of a decimal number are encoded - one at a time - into
groups of four binary digits. These codes combine the features of decimal and binary numbers. There
are a large number of BCD codes. In order to represent decimal digits 0, 1, 2,…,9 it is necessary to
use a sequence of at least four binary digits.

Ex: 8421, 2421, 5211

LOGIC GATES

❖ Logic gates are the fundamental building blocks of digital systems, it produces one output level
when some combinations of input levels are present, and a different output level when other
combinations of input levels are present.

❖ Inputs and outputs of logic gates can occur only in two levels. These two levels are termed HIGH
and LOW, or TRUE and FALSE, or ON and OFF, or simply 1 and 0.

❖ A table which lists all the possible combinations of input variables and the corresponding outputs
is called a truth table. It shows how the logic circuit’s output responds to various combinations
of logic levels at the inputs.

❖ Logic Gates are mainly classified as

1. Basic gates - AND, OR and NOT.
2. Universal gates – NAND, NOR.

BASIC GATES:

1) The AND GATE

An AND gate has two or more inputs but only one output. The
A X = A.B
output assumes the logic 1 state, only when each one of its inputs
is at logic 1 state. The output assumes the logic 0 state even if one B or AB
of its inputs is at logic 0 state.
Fig.1 Logic Symbol
The AND gate may, therefore, be defined as a device whose output is 1, if and only if all its inputs
are 1. Hence the AND gate is also called an all or nothing gate.

With the input variables to the AND gate represented by A, B, the output can be written as X = A.B
which is read as ‘X is equal to A and B . . .’ or ‘X is equal to AB . . .’, or ‘X is equal to A dot B.

The logic symbol two-input AND gate is shown in Fig.1 and truth table mentioned in Table1.

0 0
0 0 Inputs Output
0 1 A B X
0 0 0
0 1 0
1 0 0
1 1
0 1 1 1 1
0 1
Table1. Truth Table
Similarly, the logic symbol three-input AND gate is shown in Fig.2 and truth table mentioned in
Table2.

Inputs Output
A B C X
0 0 0 0
A 0 0 1 0
X = A.B.C
B 0 1 0 0
or ABC
C 0 1 1 0
1 0 0 0
Fig.2 Logic Symbol 1 0 1 0
1 1 0 0
1 1 1 1

Table2. Truth Table

2) The OR GATE:
Like an AND gate, an OR gate may have two or more inputs but only one output. The output assumes
the logic 1 state, even if one of its inputs is in logic 1 state. Its output assumes the logic 0 state, only
when each one of its inputs is in logic 0 state.
An OR gate may, therefore, be defined as a device whose output is 1, A
even if one of its inputs is 1. Hence an OR gate is also called an any X=A+B
or all gate. B
Fig.3 Logic Symbol

It can also be called an inclusive OR gate because it includes the condition ‘both the inputs can be
present’.
The symbol for the OR operation is ‘+’. With the input variables to the OR gate represented by A, B
the output can be written as X = A + B. This is read as ‘X is equal to A or B’, or ‘X is equal to A plus
B’.
The logic symbol and the truth table of a two-input OR gate are shown in Fig.3 and truth table
mentioned in Table 3.

0 0 Inputs Output
0 1
0 1 A B X
0 0 0
0 1 1
1 1 1 0 1
1 1 1 1 1
0 1
Table 3. Truth Table
Similarly, the logic symbol and the truth table of a three-input OR gate are shown in Fig.4 and truth
table mentioned in Table 4.

Inputs Output
A A B C X
B X=A+B+C 0 0 0 0
C 0 0 1 1
Fig.4 Logic Symbol 0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 1

Table 4. Truth Table

3. The NOT GATE (INVERTER):

A NOT gate, also called an inverter, has only one input and only one output.
It is a device whose output is always the complement of its input. That is, the output of a NOT gate
assumes the logic 1 state when its input is in logic 0 state and assumes the logic 0 state when its input
is in logic 1 state.
The logic symbol and the truth table of an NOT gate are shown in shown in Fig.5 and truth table
mentioned in Table 5.
Input Output
0 1 A X
A ̅
X= 𝐀
0 1
1 0 1 0

Fig.5 Logic Symbol Table 5. Truth Table

The symbol for NOT operation is ‘–’ (bar). When the input variable to the NOT gate is represented
̅ . This is read as ‘X is equal
by A and the output variable by X, the expression for the output is X = 𝐀
to A bar’.
UNIVERSAL GATES
1. The NAND GATE:
NAND means NOT - AND, i.e. the AND output is NOTed. So, a NAND gate is a combination of an
AND gate and a NOT gate.

A AB A
AB X = AB
B B

An AND gate followed by a NOT gate A two – input NAND gate

Fig.6 Logic Symbol

The expression for the output of the NAND gate can, therefore, be Inputs Output
written as X = ̅̅̅̅
𝐀𝐁 and is read as ‘X is equal to AB whole bar’. The A B X
output is logic 0 level, only when each of the inputs assumes a logic 1 0 0 1
level. For any other combination of inputs, the output is a logic 1 level. 0 1 1
The logic symbol for a two-input NAND gate is shown in Fig.6 and 1 0 1
its truth table mentioned in Table.6. 1 1 0

Table 6. Truth Table

0 0 1 1
1 0
1 1

The logic symbol for a three-input NAND gate is shown in Fig.7 and its truth table mentioned in
Table.7.

Inputs Output
A A B C X
B X = ABC 0 0 0 1
C 0 0 1 1
0 1 0 1
Fig.7 Logic Symbol
0 1 1 1
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0
Table 7. Truth Table
 ❖ A NAND gate can also be used as an NOT gate (inverter) by tying all its input terminals
together and applying the signal to be inverted to the common terminal.

X X=X

❖ The bubbled NAND gate is equivalent to OR gate

A
X=AB=A+B
B

2. The NOR GATE:

NOR means NOT OR, i.e. the OR output is NOTed. So, a NOR gate is a combination of an OR gate
and a NOT gate.

A A+B A
A+B X = A+B
B B

An AND gate followed by a NOT gate A two – input NAND gate

Fig.8 Logic Symbol

The expression for the output of the NOR gate is, X = 𝐀 ̅̅̅̅̅̅̅̅
+ 𝐁 and is Inputs Output
read as ‘X is equal to A plus B whole bar’. The output is logic 1 level, A B X
only when each one of its inputs assumes a logic 0 level. For any other 0 0 1
combination of inputs, the output is a logic 0 level. The logic symbol 0 1 0
for a two-input NAND gate is shown in Fig.8 and its truth table 1 0 0
mentioned in Table.8.
1 1 0

Table 8. Truth Table

0 1 1 1
0 0
1 1

The logic symbol for a three-input NOR gate is shown in Fig.9 and its truth table mentioned in Table.9
 A Inputs Output
B X = A+B+C A B C X
C 0 0 0 1
0 0 1 0
Fig.9 Logic Symbol
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 0

Table 9. Truth Table

❖ A NOR gate can also be used as an NOT gate (inverter), by tying all its input terminals
together and applying the signal to be inverted to the common terminal.

X X=X

❖ The bubbled NOR gate is equivalent to an AND gate

A
X = A + B = AB
B

The EXCLUSIVE-OR (X-OR) GATE:

❖ An X-OR gate is a two input, one output logic circuit, whose output assumes a logic 1 state when
one and only one of its two inputs assumes a logic 1 state. Under the conditions when both the
inputs assume the logic 0 state, or when both the inputs assume the logic 1 state, the output assumes
a logic 0 state.

❖ Since an X-OR gate produces an output 1 only when the inputs are not equal, it is called an anti-
coincidence gate or inequality detector.

❖ The name Exclusive-OR is derived from the fact that its output is a 1, only when exclusively one
of its inputs is a 1 (it excludes the condition when both the inputs are 1).

The logic symbol and truth table of a two-input X-OR gate is shown in below Fig. 10 and
Table. 10. If the input variables are represented by A and B and the output variable by X, the
̅ B + A𝐁
expression for the output of this gate is written as X = A + B = 𝐀 ̅ and read as ‘X is equal to A
ex-or B’.
 0 0 Inputs Output
0 1
0 1 A B X
A X=A +B
0 1 1 1 0 0 0
B
1 0 0 1 1
1 0 1
Fig.10 Logic Symbol
1 1 0

Table.10 Truth Table

The EXCLUSIVE-NOR (X-NOR) GATE:

❖ An X-NOR gate is a combination of an X-OR gate and a NOT gate. The X-NOR gate is a two
input, one output logic circuit, whose output assumes a 1 state only when both the inputs assume a 0
state or when both the inputs assume a 1 state. The output assumes a 0 state, when one of the inputs
assumes a 0 state and the other a 1 state.

❖ It is also called a coincidence gate, because its output is 1 only when its inputs coincide. It can be
used as an equality detector because it outputs a 1 only when its inputs are equal.

The logic symbol and truth table of a two-input X-NOR gate is shown in below Fig. 11 and Table.
11. If the input variables are represented by A and B and the output variable by X, the expression for
the output of this gate is written as as X = A . B = AB + 𝐀̅𝐁̅ and read as ‘X is equal to A ex-nor B’.

Inputs Output
0 1 1 1 A B X
0 1
A X=A . B 0 0 1
0 0 1 0
B 0 1 0
1 0
1 0 0
Fig.11 Logic Symbol 1 1 1
Table.11 Truth Table

BOOLEAN ALGEBRA
❖ Boolean algebra is an algebraic system consisting of the set of elements (0,1), two binary
operators called OR and AND and one unary operator called NOT. It is the basic mathematical
tool in the analysis and synthesis of switching circuits / logic circuits.
❖ Boolean algebra differs from both the ordinary algebra and the binary number system. In Boolean
algebra, A + A = A and A . A = A, because the variable A has only a logical value. It doesn’t have
any numerical significance. In ordinary algebra, A + A = 2A and A. A = A2, because the variable
A has a numerical value here. In Boolean algebra, 1 + 1 = 1, whereas in the binary number system,
1 + 1 = 10, and in ordinary algebra, 1 + 1 = 2.
❖ There is nothing like subtraction or division in Boolean algebra. Also, there are no negative or
fractional numbers in Boolean algebra. In Boolean algebra, the multiplication and addition of the
variables and functions are also only logical. They actually represent logic operations. Logical
multiplication is the same as the AND operation, and logical addition is the same as the OR
operation.

LAWS OF BOOLEAN ALGEBRA:

1. Complementation Laws
The term complement simply means to invert, i.e. to change 0s to 1s and 1s to 0s.

2. AND Laws

3. OR Laws

4. Commutative Laws
Commutative laws allow change in position of AND or OR variables. There are two commutative
laws.
Law 1: A + B = B + A
This law states that, A OR B is the same as B OR A, i.e. no difference which input of an OR gate
is connected to A and which to B.
Law 2: A . B = B. A
This law states that A AND B is the same as B AND A, i.e. no difference which input of an AND
gate is connected to A and which to B.

5. Associative Laws
The associative laws allow grouping of variables. There are two associative laws.

Law 1: (A + B) + C = A + (B + C)

Law 2: (A.B).C = A.(B.C)

6. Distributive Laws

Law 1: A(B + C) = AB + AC

Law 2: A + BC = (A + B)(A + C)

7. Idempotence Laws

Law 1: A . A = A

Law 2: A + A = A
De Morgan’s Theorem:

𝐋𝐚𝐰 𝟏 ∶ ̅̅̅̅̅̅̅̅
𝐀+𝐁= 𝐀 ̅𝐁
̅

This law states that the complement of a sum of variables is equal to the product of their individual
complements.

It shows that the NOR gate is equivalent to a bubbled AND gate.

̅̅̅̅ = 𝐀
𝐋𝐚𝐰 𝟐 ∶ 𝐀𝐁 ̅ +𝐁
̅

This law states that the complement of the product of variables is equal to the sum of their
individual complements.

It shows that the NAND gate is equivalent to a bubbled OR gate.

Operator Precedence:
The operator precedence for evaluating Boolean expression is (i) parenthesis (ii) NOT (iii) AND
and (iv) OR. In other words, the expression inside the parenthesis must be evaluated before all
other operations. The next operation that holds precedence is the complement, then follows the
AND and finally the OR.
Ex: Reduce the expression 𝐟 = 𝐀 [𝐁 + 𝐂 ̅̅̅̅̅̅̅̅̅̅̅̅
̅ (𝐀𝐁 + 𝐀𝐂̅ )]
The given expression is
̅̅̅̅̅̅̅̅̅̅̅̅
𝐟 = 𝐀 [𝐁 + 𝐂̅ (𝐀𝐁 + 𝐀𝐂̅ )
̅̅̅̅ . ̅̅̅̅
𝐟 = 𝐀 [𝐁 + 𝐂̅ (𝐀𝐁 𝐀𝐂̅ ) - (DE Morgan’s Law - 1)
𝐟 = 𝐀 [𝐁 + 𝐂̅ (𝐀
̅+𝐁 ̅ + 𝐂)]
̅ ) (𝐀 - (DE Morgan’s Law - 2)
𝐟 = 𝐀 [𝐁 + 𝐂̅ (𝐀
̅𝐀̅+𝐀 ̅𝐂 + 𝐁 ̅+ 𝐁
̅𝐀 ̅ 𝐂 )] - (Distributive Law - 1)
𝐟 = 𝐀 [𝐁 + 𝐂̅ 𝐀
̅ + 𝐂̅ 𝐀 ̅ 𝐂 + 𝐂̅ 𝐁 ̅ + 𝐂̅ 𝐁
̅𝐀 ̅𝐂 ] - (Idempotence Laws)
̅ ̅ ̅ ̅
𝐟 = 𝐀 [𝐁 + 𝐂 𝐀 + 𝟎 + 𝐂 𝐁 𝐀 + 𝟎 ]̅ - (AND Laws)
𝐟 = 𝐀𝐁 + 𝐀𝐂̅ 𝐀̅ + 𝐀𝐂̅ 𝐁 ̅𝐀̅ - (Distributive Law - 1)
𝐟 = 𝐀𝐁 + 𝟎 + 𝟎 - (AND Laws)
𝐟 = 𝐀𝐁

̅ )𝐃]
Ex: Reduce the expression 𝐟 = 𝐀 + 𝐁 [𝐀𝐂 + (𝐁 + 𝐂
The given expression is
𝐟 = 𝐀 + 𝐁 [𝐀𝐂 + (𝐁 + 𝐂̅ )𝐃]
𝐟 = 𝐀 + 𝐁 [𝐀𝐂 + 𝐁𝐃 + 𝐂̅ 𝐃 ] - (Distributive Law - 1)
𝐟 = 𝐀 + 𝐁𝐀𝐂 + 𝐁𝐁𝐃 + 𝐁𝐂̅ 𝐃 - (Distributive Law - 1)
𝐟 = 𝐀 + 𝐁𝐀𝐂 + 𝐁𝐃 + 𝐁𝐂̅ 𝐃 - (Idempotence Laws)
𝐟 = 𝐀(𝟏 + 𝐁𝐂) + 𝐁𝐃(𝟏 + 𝐂̅ ) - (Factor)
𝐟 = 𝐀(𝟏) + 𝐁𝐃(𝟏) - (OR Laws)
𝐟 = 𝐀 + 𝐁𝐃

̅̅̅̅̅̅̅̅̅̅
Ex: Reduce the expression 𝐟 = (𝐀 ̅̅̅̅)(𝐀𝐁
+ 𝐁𝐂 ̅ + 𝐀𝐁𝐂)

̅ 𝐂)(𝐁 + 𝐃)
Ex: Reduce the expression 𝐟 = 𝐁 + (𝐁𝐂)(𝐁 + 𝐁
 ̅ 𝐂 + 𝐁𝐂̅ = 𝐀𝐂 + 𝐁𝐂̅
Ex: Show that 𝐀𝐁 + A𝐁

̅ 𝐂 + 𝐁 + 𝐁𝐃
Ex: Show that A𝐁 ̅ + 𝐀𝐁𝐃
̅ +𝐀
̅𝐂 = 𝐁 + 𝐂
COMBINATIONAL CIRCUITS

❖ A combinational circuit consists of input variables, logic gates, and output variables as shown in
Fig.12.
❖ The output of a combinational circuit depends on its present inputs only.
❖ For ‘n’ input variables, there are 2n possible combinations of binary input values. For each
possible input combination, there is one and only one possible output combination.

Fig.12 The block diagram of a combinational circuit

Half-Adder:
A combinational circuit that performs the addition of two bits is called a half-adder, with two binary
inputs (augend and addend bits) and two binary outputs (sum and carry bits). It adds the two inputs
(A and B) and produces the sum (S) and the carry (C) bits. The truth table and block diagram of a
half-adder are shown in Fig.13.

Fig.13 Half-adder

This simple addition consists of 4 possible operations, Carry

0 + 0 = 0, 0 + 1 = 1, 1 + 0 = 1, and 1 + 1 = 10
The first three operations produce a sum whose length is one digit, but when both augend and addend
bits are equal to 1, the binary sum consists of two digits. The higher significant bit of this result is
called a carry. When the augend and addend numbers contain more significant digits, the carry
obtained from the addition of two bits is added to the next higher-order pair of significant bits.
In the sum column, the output is HIGH (1) when either input is HIGH (1) but not when both inputs
are the same and in the carry column, the output is HIGH (1) when both inputs are the HIGH (1).
Therefore,
̅ B + A𝐁
The sum (S) is the X-OR of A and B, S = A + B = 𝐀 ̅ and
The carry (C) is the AND of A and B, C = AB
A half-adder can, therefore, be realized by using one X-OR gate and one AND gate as shown in
Fig.14.

Fig.14 Logic diagrams of half-adder

Full-Adder:
A combinational circuit that performs the addition of three bits (two significant bits and previous
carry) is called a full-adder and outputs a sum bit and a carry bit.
The full-adder adds the bits A and B and the carry from the previous column called the carry-in Cin
and outputs the sum bit S and the carry bit called the carry-out Cout. The variable S gives the value
of the least significant bit (LSB) of the sum. The variable Cout gives the output carry. The truth table
and the block diagram of a full-adder are shown in Fig.15.

Fig.15 Full-adder
The eight rows under the input variables (A, B, & Cin) designate all possible combinations of 1s and
0s. The 1s and 0s for the output variables (S & Cout) are determined from the arithmetic sum of the
input bits.
1. When all the bits are 0s, the output is 0.
2. The S output is equal to 1 when only 1 input is equal to 1 or when all the inputs are equal to 1.
3. The Cout has a carry of 1 if two or three inputs are equal to 1.
From the truth table, a circuit that will produce the sum and carry bits in response to every possible
combination of A, B, and Cin is described by

̅𝐁
S=𝐀 ̅ 𝐂𝐢𝐧 + 𝐀
̅ 𝐁𝐂̅𝐢𝐧 + 𝐀𝐁
̅ 𝐂̅𝐢𝐧 + 𝐀𝐁𝐂𝐢𝐧 = (𝐀
̅ 𝐁 + 𝐀𝐁
̅ )𝐂̅𝐢𝐧 + (𝐀
̅𝐁̅ + 𝐀𝐁)𝐂𝐢𝐧 = 𝐀 + 𝐁 + 𝐂𝐢𝐧 &

̅ 𝐁𝐂𝐢𝐧 + 𝐀𝐁
𝐂𝐨𝐮𝐭 = 𝐀 ̅ 𝐂𝐢𝐧 + 𝐀𝐁𝐂̅𝐢𝐧 + 𝐀𝐁𝐂𝐢𝐧 = 𝐀𝐁 + (𝐀 + 𝐁) 𝐂𝐢𝐧 = 𝐀𝐁 + 𝐀𝐂𝐢𝐧 + 𝐁𝐂𝐢𝐧

The logic diagram of the full-adder using two X-OR gates and two AND gates (i.e. two half-adders)
and one OR gate is shown in Fig.16.

Fig.16 Logic diagrams of full-adder

INTRODUCTION TO SEQUENTIAL CIRCUITS
❖ Basically, switching circuits may be combinational switching circuits or sequential switching
circuits.
❖ In Combinational switching circuits any prior input level conditions have no effect on the present
outputs, because combinational logic circuits have no memory.
❖ In, sequential switching circuits output levels at any instant of time are dependent not only on the
present inputs level, but also on the state of the circuit, i.e. on the prior input level conditions (i.e.
on its past inputs). The past history is provided by feedback from the output back to the input. It
means that sequential switching circuits have memory. Sequential circuits are thus made of
combinational circuits and memory elements. The past history is provided by feedback from the
output back to the input.
Ex: Counters, shift registers, serial adders, sequence generators, logic function generators,
etc.

Fig.17 shows a block diagram of a sequential circuit. The memory elements are connected to the
combinational circuit as a feedback path.

Fig.17 Block diagram of a sequential circuit

The information stored in the memory element at any given time defines the present state of the
sequential circuit. The present state and the external inputs determine the outputs and the next state
of the sequential circuit.

❖ The sequential circuits may be classified as synchronous sequential circuits and asynchronous
sequential circuits depending on the timing of their signals.
▪ The sequential circuits which are controlled by a clock are called synchronous
sequential circuits (Flip-Flops). These circuits will be active only when clock signal
is present.
▪ The sequential circuits which are not controlled by a clock are called asynchronous
sequential circuits (Latches), i.e. the sequential circuits in which events can take place
any time the inputs are applied are called asynchronous sequential circuits.
FLIP-FLOPS:
Flip-flops are the basic building blocks of most sequential circuits. A flip-flop (FF), known more
formally as a bistable multivibrator, has two stable states (0 or 1). It can remain in either of the states
indefinitely. Its state can be changed by applying the proper triggering signal. It is also called a binary
or one-bit memory.

Fig.18 Flip-Flop symbol

Fig.18 shows the general type of symbol used for a flip-flop. The flip-flop has two outputs, labelled
Q and Q̅ . The Q output is the normal output of the flip-flop and Q ̅ is the inverted output. The output
as well as its complement are available for each flip-flop. The state of the flip-flop always refers to
the state of the normal output Q. The inverted output Q ̅ is in the opposite state. A flip-flop is said
to be in HIGH state or logic 1 state or SET state when Q = 1, and in LOW state or logic 0 state or
RESET state or CLEAR state when Q = 0.

Clocked S-R Flip-Flop

The S and R inputs of the S-R flip-flop are called the synchronous control inputs because data on
these inputs affect the flip-flop’s output only on the triggering (positive going or negative going) edge
of the clock pulse (CLK). Without a clock pulse, the S and R inputs cannot affect the output. So, it is
also called a Synchronous S-R Flipflop. The logic diagram & the logic symbol are shown in Fig.19.
and truth table & waveforms are shown in Fig.21 respectively.

S
S
Q
Q

CLK CLK

Q
Q
R R

(a) Logic Diagram (b) Logic Symbol

Fig.19 Clocked S-R Flip Flop

Qn represents the state of the flip-flop before applying the inputs (i.e. the present state PS of the
flip-flop). Qn+1 represents the state of the flip-flop after the application of the inputs (i.e. the next
state NS of the flip-flop).
A. S= 0, R= 0: NO CHANGE (NC)
̅ will remain in whatever
This is the normal resting state and it has no effect on the output state. Q and Q
state they were prior to the occurrence of this input condition.
0 1 0 1
Q=0 Qn 0 Qn+1

1 1

0 0
1 1
0 0 1 Qn+1
Q=1
(i) Qn = 0

0 1 0 1
Q=1 Qn 1 Qn+1

1 1

1 1
1 1
0 0 0 Qn+1
Q=0
(ii) Qn = 1
CASE A: S= 0, R= 0 & CLK = 1

B. S=0, R = 1: RESET
This will always reset Q = 0, where it will remain even after RESET returns to 0.

0 1 0 1
Q=0 Qn 0 Qn+1

1 1
0
0 0
0
1 1 1 Qn+1
Q=1

(i) Qn = 0

0 1 0 1
Q=1 Qn 0 Qn+1

1 1
0
1 0
0
1 1 1 Qn+1
Q=1
(ii) Qn = 1
CASE B: S= 0, R= 1 & CLK = 1
C. S=1, R = 0: SET
This will always set Q = 1, where it will remain even after SET returns to 0.

1 0 1 0
Q=0 Qn 1 Qn+1

1 1

0 1
1 1
0 0 0 Qn+1
Q=1

(i) Qn = 0

1 0 1 0
Q=1 Qn 1 Qn+1

1 1

1 1
1 1
0 0 0 Qn+1
Q=0
(ii) Qn = 1
CASE C: S= 1, R= 0 & CLK = 1

D. S=1, R = 1: INDETERMINATE
This condition tries to SET and RESET at the same time, and it produces Q = Q ̅ = 1. If the inputs
are returned to zero simultaneously, the resulting output state is erratic and unpredictable. This input
condition should not be used. It is forbidden.

1 0 1 0
Q=0 Qn 1 Qn+1

1 1

0 1
0 0
1 1 1 Qn+1
Q=1

(i) Qn = 0

1 0 1 0
Q=1 Qn 1 Qn+1

1 1

1 1
0 0
1 1 1 Qn+1
Q=1
(ii) Qn = 1
CASE D: S= 1, R= 1 & CLK = 1
 ̅ may be HIGH, or
If both the inputs are made HIGH, the output is unpredictable, i.e. both Q and Q
both may be LOW or any one of them may be HIGH and the other LOW. This condition is described
as not allowed, unpredictable, invalid or indeterminate.

Fig. 20 Edge Triggering

The process of applying the control signal to change the state of a flip-flop is called triggering. There
are two types of triggering the flip-flops: level triggering and edge triggering.
In edge triggering, the input signals affect the flip-flop only if they are present at the positive
going or negative going edge of the clock pulse as shown in Fig.20.

CLK S R Qn Qn+1 State

0 0 0 0 No Change
0 0 1 1 (NC)
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 X (0 or 1)
X – don’t Indeterminate
1 1 1
care
0 X X 0 0 No Change
0 X X 1 1 (NC)

(a) Truth Table (b) Waveforms: positive edge-triggered

Fig.21

1. Initially, S = 0 and R = 0 and Q is assumed to be HIGH.

2. At the positive-going transition of the first clock pulse (i.e. at a), both S and R are LOW. So, no
change of state takes place. Q remains HIGH and Q ̅ remains LOW.
3. At the leading edge of the second clock pulse (i.e. at b), S = 0 and R = 1. So, the flip-flop resets.
Hence, Q goes LOW and Q ̅ goes HIGH.
4. At the positive-going edge of the third clock pulse (i.e. at c), S = 1 and R = 0. So, the flip-flop sets.
Hence, Q goes HIGH and Q ̅ goes LOW.
5. At the rising edge of the fourth clock pulse, S = 1 and R = 0. Since the flip-flop is already in a SET
state, it remains SET. That is, Q remains HIGH and Q ̅ remains LOW.
6. The fifth pulse resets the flip-flop at its positive-going edge because S = 0 and R = 1 is the input
condition and Q = 1 at that time.
7. The sixth pulse sets the flip-flop at its rising edge because S = 1 and R = 0 is the input condition
and Q = 0 at that time.
Clocked J-K Flip-Flop

The J-K flip-flop is very versatile and also the most widely used. The J and K designations for the
synchronous control inputs have no known significance. The functioning of the J-K flip-flop is
identical to that of the S-R flip-flop, except that it has no invalid state like that of the S-R flip-flop.
The logic diagram & the logic symbol are shown in Fig.22 and truth table & waveforms are shown
in Fig.23 respectively.

J
Q J
Q
CLK
CLK

Q
K Q
K
(a) Logic Diagram (b) Logic Symbol

Fig.22 Clocked J-K Flip Flop

❖ When J = 0 and K = 0, no change of state takes place even if a clock pulse is applied.
❖ When J = 0 and K = 1, the flip-flop resets at the edge of the clock pulse.
❖ When J = 1 and K = 0, the flip-flop sets at the edge of the clock pulse.
❖ When J = 1 and K = 1, the flip-flop toggles, i.e. goes to the opposite state at edge of the clock
pulse. In this mode, the flip-flop toggles or changes state for each occurrence of the of the
clock pulse.

CLK J K Qn Qn+1 State

0 0 0 0 No Change
0 0 1 1 (NC)
0 1 0 0
Reset
0 1 1 0
1 0 0 1
Set
1 0 1 1
1 1 0 1
Toggle
1 1 1 0
0 X X 0 0 No Change
0 X X 1 1 (NC)

(a) Truth Table (b) Waveforms: negative edge-triggered

Fig.23
1. Initially J = 0, K = 0 and CLK = 0. Assume that the initial state of the flip-flop is a 1, i.e. 𝐐 = 1
initially.
2. At the negative-going edge of the first clock pulse (i.e. at a), J = 1 and K = 0. So, Q remains as a 1
and, therefore, Q̅ as a 0.
3. At the trailing edge of the second clock pulse (i.e. at b), J = 0 and K = 1. So, the flip-flop resets.
That is, Q goes to a 0 and Q̅ to a 1.
4. At the falling edge of the third clock pulse (i.e. at c), both J and K are a 1. So, the flip-flop toggles.
That is, Q changes from a 0 to a 1 and Q ̅ from a 1 to a 0.
5. At the negative-going transition of the fourth clock pulse (i.e. at d), J = 0 and K = 1. So, the flip-
flop RESETS, i.e. Q goes to a 0 and Q ̅ to a 1.
6. At the negative going edge of the fifth clock pulse (i.e. at d), J = 0 and K = 1. So the flipflop remains
reset, i.e. Q remains as 0 and Q̅ remains as 1.

SHIFT REGISTERS
❖ Shift registers are a type of logic circuits, are used basically for the storage and transfer of digital
data.
❖ A flip-flop (FF) can store only one bit of data, a 0 or a 1, it is referred to as a single-bit register.
When more bits of data are to be stored, a number of FFs are used. A register is a set of FFs used
to store binary data.
❖ A register might be used to accept input data from an alphanumeric keyboard and then present
the data at the input of a microprocessor chip.
❖ Data may be available (I/P) in parallel form or in serial form.
▪ Multi-bit data is said to be in parallel form when all the bits are available (accessible)
simultaneously. The data is said to be in serial form when the data bits appear sequentially
(one after the other, in time) at a single terminal.
❖ Data may also be transferred (O/P) in parallel form or in serial form.
▪ Parallel data transfer is the simultaneous transmission of all bits of data from one device
to another. Serial data transfer is the transmission of one bit of data at a time from one
device to another. Serial data must be transmitted under the synchronization of a clock,
since the clock provides the means to specify the time at which each new bit is sampled.

Fig. 24 Data transfer in registers

 (a) Using J-K FFs (b) Using S-R FFs

Fig. 25 2-bit serial-in, serial-out, (SISO) shift register

A shift register can be constructed using J-K FFs or S-R FFs as shown in Fig. 25a and 25b,
respectively. The data is applied at the J(S) input of the first FF. The complement of this is fed to the
K(R) terminal of the first FF. The Q output of the first FF is connected to J(S) input of the second FF.
The input (data) is applied at the leftmost of the FF (MSB) while the output is taken from the right
most FF (LSB).
MSB LSB
Input: 1 0

1. Initially, say all the bits of the register are 0. So, whenever there is no clock pulse (CLK), then
irrespective of the input, all the FF will store its current data (No change state). i.e., Q1 = Q2 = 0.
2. Starting from LSB, to shift it into the shift register, apply the value (here it is 0) at the input terminal.
Before CLK, all values are zero and once clock edge (here it is negative edge triggering) arrives,
then all the FFs will respond to their present inputs. For CLK -1, Q1 = 0 (J1 = 0: RESET state); Q2
= 0 (due to previous Q1, i.e., value at CLK-0, Q1 = J2 = 0) and for CLK -2, Q1 = 1 (J1 = 1: SET
state); Q2 = 0 (value at CLK-1, Q1 = J2 = 0).

CLK Input Q1 Q2
NO 0 X 0 0 Previous stored data in the last FF (FF-2) is discarded after zero clock
1 0 0 0
Discarded after first clock
2 1 1 0
Output at Q2 of FF-2
3 - - 1
COUNTERS
❖ A digital counter is a set of flip-flops (FFs) whose states change in response to pulses applied at
the input to the counter.
❖ The FFs are interconnected such that their combined state at any time is the binary equivalent of
the total number of pulses that have occurred up to that time. Thus, as its name implies, a counter
is used to count pulses.
❖ A counter used to perform the timing function as in digital watches, to create time delays, to
produce non-sequential binary counts, to generate pulse trains, and to act as frequency counters,
etc.

Two-bit Ripple Up-counter:

The 2-bit up-counter counts in the order 0, 1, 2, 3, 0, 1, …, i.e. 00, 01, 10, 11, 00, 01,…, etc. Fig.26
shows a 2-bit ripple up-counter, using negative edge-triggered J-K FFs, and its timing diagram.

(a) Logic Diagram (b) Timing Diagram

Fig.26
❖ The counter is initially reset to 00. When the first clock pulse is applied, FF1 toggles at the
negative-going edge of this pulse, therefore, Q1 goes from LOW to HIGH. This becomes a
positive-going signal at the clock input of FF2. So, FF2 is not affected, and hence, the state of
the counter after one clock pulse is Q1 = 1 and Q2 = 0, i.e. 01.
❖ At the negative-going edge of the second clock pulse, FF1 toggles. So, Q1 changes from HIGH
to LOW and this negative-going signal applied to CLK of FF2 activates FF2, and hence, Q2
goes from LOW to HIGH. Therefore, Q1 = 0 and Q2 = 1, i.e. 10 is the state of the counter after
the second clock pulse.
❖ At the negative-going edge of the third clock pulse, FF1 toggles. So Q1 changes from a 0 to a
1. This becomes a positive-going signal to FF2, hence, FF2 is not affected. Therefore, Q2 = 1
and Q1 = 1, i.e. 11 is the state of the counter after the third clock pulse.
❖ At the negative-going edge of the fourth clock pulse, FF1 toggles. So, Q1 goes from a 1 to a
0. This negative-going signal at Q1 toggles FF2, hence, Q2 also changes from a 1 to a 0.
Therefore, Q2 = 0 and Q1 = 0, i.e. 00 is the state of the counter after the fourth clock pulse.
❖ For subsequent clock pulses, the counter goes through the same sequence of states with Q1 as
the LSB and Q2 as the MSB. The counting sequence is thus 00, 01, 10, 11, 00, 01,…, etc.
Two-bit Ripple Down-counter:
A 2-bit down-counter counts in the order 0, 3, 2, 1, 0, 3,…, i.e. 00, 11, 10, 01, 00, 11, …, etc. Fig.27
shows a 2-bit ripple down-counter, using negative-edge triggered J-K FFs, and its timing diagram.

(a) Logic Diagram (b) Timing Diagram

Fig.27
❖ For down counting, ̅̅ Q̅1̅ of FF1 is connected to the clock of FF2. Let initially all the FFs be
reset, i.e. let the count be 00. At the negative-going edge of the first clock pulse, FF1 toggles,
so, Q1 goes from a 0 to a 1 and ̅Q̅̅1̅ goes from a 1 to a 0. This negative-going signal at Q ̅̅̅1̅
applied to the clock input of FF2, toggles FF2 and, therefore, Q2 goes from a 0 to a 1. So, after
one clock pulse Q2 = 1 and Q1 = 1, i.e. the state of the counter is 11.
❖ At the negative-going edge of the second clock pulse, Q1 changes from a 1 to a 0 and Q ̅̅̅1̅ from
a 0 to a 1. This positive-going signal at ̅̅Q̅1̅ does not affect FF2 and, therefore, Q2 remains at
a 1. Hence, the state of the counter after the second clock pulse is 10.
❖ At the negative-going edge of the third clock pulse, FF1 toggles. So, Q1 goes from a 0 to a 1
and Q̅̅̅1̅ from a 1 to a 0. This negative-going signal at Q
̅̅̅1̅ toggles FF2 and, so, Q2 changes from
a 1 to a 0. Hence, the state of the counter after the third clock pulse is 01.
❖ At the negative-going edge of the fourth clock pulse, FF1 toggles. So, Q1 goes from a 1 to a 0
and Q̅̅̅1̅ from a 0 to a 1. This positive-going signal at Q ̅̅̅1̅ does not affect FF2. So, Q2 remains
at a 0. Hence, the state of the counter after the fourth clock pulse is 00. For subsequent clock
pulses the counter goes through the same sequence of states, i.e. the counter counts in the
order 00, 11, 10, 01, 00, and 11 …