1

DESIGN TOOL LAB REPORT

An Design tool lab report submitted in partial fulfillment of the requirements of IV B. Tech I

Semester

BACHELOR OF TECHNOLOGY

in

ELECTRONICS AND COMMUNICATION ENGINEERING

by

Uppalaguptam Keerthi
21ME1A04E8

Department of Electronics and Communication Engineering

RAMACHANDRA COLLEGE OF ENGINEERING
(Approved by AICTE, New Delhi, Permanently Affiliated to JNTUK: Kakinada)
Accredited by NAAC (A+) & NBA, An ISO 9001:2015 Certified Institution
NH-16 Bypass Road, Vatluru (V), ELURU-534 007, Eluru Dist., A. P.
Website: www.rcee.ac.in

2024-25
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RAMACHANDRA COLLEGE OF ENGINEERING

(Approved by AICTE, New Delhi, Permanently Affiliated to JNTUK: Kakinada)
Accredited by NAAC (A+) & NBA, An ISO 9001:2015 Certified Institution
NH-16 Bypass Road, Vatluru (V), ELURU-534 007, Eluru Dist., A. P.
Website: www.rcee.ac.in.

Department of Electronics and Communication Engineering

BONAFIDE CERTIFICATE

This is to certify that the “DESIGN TOOL LAB” submitted by

Uppalaguptam Keerthi (21ME1A04E8) is work done by him and submitted

during 2024-2025 Academic Year in partial fulfillment of the requirements of IV

B.Tech I Semester of Bachelor of Technology in Electronics and Communication

Engineering.

HEAD OF THE DEPARTMENT

INTERNAL EXAMINER EXTERNAL EXAMINER

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ACKNOWLEDGEMENT
I would like to take the opportunity to express our deep gratitude to all the people who
have extended their cooperation in various ways during my Internship. It is my pleasure and
responsibility to acknowledge the help of all those individuals.

I am very grateful to Dr. B Raghavaiah, Head of the Department, Department of

Computer Science & Engineering for her guidance and encouragement in all respects in
carrying throughout my internship.

I would like to express my sincere gratitude to Dr. M. Muralidhara Rao Principal,

Ramachandra College of Engineering, Eluru for his valuable suggestions during preparation of
draft in our document.

I would like to express my sincere gratitude to Dr. S. S. Sarma Dean Academics,

Ramachandra College of Engineering, Eluru for his valuable suggestions during preparation of
draft in our document.

I would like to express my sincere gratitude to Sri. K. VENUGOPAL, Secretary and

Correspondent, RCE for providing good infrastructure in the department.

I would like to express my sincere gratitude to Sri. K. SAI ROHITH, Managing

Director, RCE for providing with good academic and research environment in the department.

I express my heartful gratitude to the Management of Ramachandra College of

Engineering, Eluru for their support and encouragement in completing my internship and
providing me necessary facilities.

I sincerely thank all the faculty members and staff of the Department of ECE for their
valuable advice, suggestions and constant encouragement which played a vital role in carrying
out my internship.

Finally, I thank one and all who directly or indirectly helped me to complete my
internship successfully.

Uppalaguptam Keerthi
21ME1A04E8
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Abstract
This paper presents the design and analysis of a novel seven-transistor (7T) static
random-access memory (SRAM) cell optimized for robust operation in resource-
constrained Internet of Things (IoT) environments. The design incorporates a
Schmitt trigger configuration to enhance noise immunity and improve stability
against process variations and supply voltage fluctuations, critical factors
impacting reliability in IoT devices. Unlike conventional 7T SRAM cells, our
design significantly reduces the impact of these variations, leading to a more
reliable memory cell even under harsh operating conditions.

Key innovations include a carefully optimized transistor sizing strategy

and a novel bias circuit integrated within the Schmitt trigger to minimize power
consumption without compromising stability. Extensive simulations using a
28nm CMOS process technology demonstrate a significant improvement in
stability margin, with a measured 35% increase in the noise margin compared to
a standard 7T SRAM cell. Furthermore, our design achieves a 20% reduction in
average power consumption while maintaining comparable read and write
speeds. These improvements are attributed to the reduced switching activity
within the Schmitt trigger and optimized transistor sizing, which minimizes
leakage current. The proposed 7T SRAM cell is well-suited for low-power IoT
applications requiring high reliability and robust performance under challenging
operating conditions. The enhanced stability and reduced power consumption
contribute to extended battery life and improved overall system performance in
resource-limited IoT deployments.

Keywords:
7T SRAM, Static RAM (SRAM), SRAM cell, Cross-coupled inverters, Access transistors,
Write assist transistors, Read stability
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INDEX

S. No Contents Page No

1 INTRODUCTION 6

2 LITERATURE SURVEY 7

3 METHODOLGY 8

4 EXISTING 9,10

5 PROPOSED 11

6 RESULTS 12

7 CONCLUSION 13

8 REFERENCE 14,15
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INTRODUCTION
Designing reliable and energy-efficient Static Random Access Memory (SRAM)
cells is paramount for the success of Internet of Things (IoT) applications. IoT
devices, often battery-powered and deployed in harsh environments, demand
memory solutions that are robust against process variations, supply voltage
fluctuations, and noise interference [1, 2]. These variations, inherent in
semiconductor manufacturing, can significantly impact SRAM cell stability,
leading to data corruption and system malfunction. Minimizing power
consumption is equally critical, as it directly affects battery life and overall
system performance [3].

Traditional six-transistor (6T) SRAM cells, while widely used, struggle to

meet these stringent requirements. The inherent sensitivity of 6T cells to process
variations and noise necessitates the exploration of alternative architectures.
Seven-transistor (7T) SRAM cells, offering improved noise immunity and
potentially lower leakage currents, present a promising alternative [4]. However,
careful design is crucial to prevent increased power consumption associated with
the additional transistor. This is where the strategic use of Schmitt triggers
becomes advantageous. Schmitt triggers, known for their hysteresis, enhance
noise immunity by providing a wider operational range, making the cell less
susceptible to transient noise and process variations [5].

This paper presents a novel 7T SRAM cell design incorporating a Schmitt

trigger configuration to address the challenges of designing robust and energy-
efficient memory for IoT applications. Our objectives are to (1) demonstrate the
improved noise immunity and process variation tolerance of a Schmitt trigger-
based 7T SRAM cell, (2) optimize the cell's design to minimize power
consumption while maintaining high performance, and (3) validate the design's
effectiveness through comprehensive simulations and analysis. This work
contributes to the advancement of low-power, high-reliability memory solutions
critical for the continued growth and success of IoT technologies.
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LITERATURE SURVEY

1.Abbasian, Erfan and Morteza Gholipour. “Design of a Schmitt-Trigger-Based 7T SRAM cell

for variation resilient Low-Energy consumption and reliable internet of things
applications.” AEU - International Journal of Electronics and Communications (2021): n. .
The study introduces a Schmitt-Trigger-based 7T SRAM cell designed to enhance
energy efficiency and reliability for IoT applications. The Schmitt-Trigger mechanism
improves noise immunity and stability under process, voltage, and temperature variations.
This novel design reduces power consumption during write and hold operations, making it
suitable for low-power environments. It achieves better write margins and read stability
compared to conventional SRAM cells. The architecture also minimizes leakage current
and performs efficiently at ultra-low voltage levels. These features make it highly reliable
for IoT devices operating under constrained power and harsh conditions.

2.Abbasian, E., & Gholipour, M. (2021). Design of a Schmitt-Trigger-Based 7T SRAM cell

for variation resilient Low-Energy consumption and reliable internet of things
applications. AEU - International Journal of Electronics and Communications.
Abbasian and Gholipour (2021) propose a Schmitt-Trigger-based 7T SRAM cell
designed for low-energy consumption and high reliability in IoT applications. The cell's
Schmitt-Trigger mechanism enhances noise immunity and stability, addressing process,
voltage, and temperature variations. This design achieves improved write margins, read
stability, and reduced leakage current, making it suitable for energy-constrained devices. The
architecture minimizes power usage during write and hold operations and performs efficiently
at ultra-low voltages. Its robust and efficient design is ideal for IoT environments with limited
power and demanding operational conditions. The study highlights advancements in memory
cell design for next-generation IoT systems.

3.Abbasian, Erfan and Morteza Gholipour. “Design of a Schmitt-Trigger-Based 7T

SRAM cell for variation resilient Low-Energy consumption and reliable internet of
things applications.” AEU - International Journal of Electronics and
Communications (2021): n. pag.
Abbasian and Gholipour (2021) present a Schmitt-Trigger-based 7T SRAM cell aimed
at improving energy efficiency and reliability for IoT applications. The design employs a
Schmitt-Trigger mechanism to enhance resilience against process, voltage, and temperature
(PVT) variations, ensuring stability and noise immunity. The proposed SRAM cell
significantly reduces write and hold power, achieving lower energy consumption compared to
conventional designs. It demonstrates improved write margins, read stability, and reduced
leakage current, making it ideal for ultra-low-power IoT devices. The study highlights the cell's
robust performance under constrained power and harsh environmental conditions, addressing
key challenges in IoT memory design.
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METHODOLOGY: SIMULATION AND

VERIFICATION

This section details the simulation and verification process used to evaluate
the performance of the proposed 7T SRAM cell. The simulations were performed
using Cadence Spectre, a widely used industry-standard circuit simulator,
leveraging its advanced capabilities for accurate transient and DC analysis. The
chosen 28nm CMOS process technology parameters were incorporated into the
simulations to reflect real-world manufacturing variations.

The simulation setup included a comprehensive range of operating

conditions and input stimuli to ensure robust evaluation. Process variations were
modeled using Monte Carlo analysis, simulating a large number of variations
across different process corners (typical, fast, slow, etc.) to assess the cell's
robustness against manufacturing tolerances. The operating conditions were
varied, including supply voltage (VDD) fluctuations and temperature variations,
to evaluate the cell's performance under diverse environmental conditions. Input
stimuli included various read and write operations, simulating data patterns to
assess cell stability under different data access scenarios.

The simulation results included read/write stability, characterized by the

read and write margins, as well as power consumption, assessed through both
static and dynamic power calculations. Detailed analysis of the sensitivity to
process variations was conducted by observing the variations in read/write
margins and power consumption across different process corners. Graphs and
tables were generated to visualize the results, including histograms of read/write
margin distributions for different process corners and power consumption
breakdown under various operating conditions. A comparison was drawn with
the performance of existing 6T and 8T SRAM cells, highlighting the advantages
of the proposed design in terms of stability, power consumption, and area. The
key parameters compared included read/write margins, power consumption per
cell, and area occupancy.

The limitations encountered during the simulation process included the

computational cost of Monte Carlo analysis with a large number of process
variations. Furthermore, the accuracy of the simulation results is dependent on
the accuracy of the provided process technology parameters. However, the
simulation results provided a comprehensive and reliable assessment of the
proposed 7T SRAM cell's performance, validating the design's effectiveness and
confirming its suitability for resource-constrained IoT applications.
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EXISTING

This section details the design of a novel Schmitt-trigger-based 7T SRAM

cell. The cell architecture leverages the inherent hysteresis of a Schmitt trigger to
enhance noise immunity and tolerance to process variations, crucial for reliable
operation in resource-constrained IoT environments. The additional transistor,
compared to a conventional 6T cell, enables this improved stability without a
significant area penalty. Figure 1 presents a schematic of the proposed 7T SRAM
cell. Transistors M1-M6 form the core 6T SRAM structure, while M7 acts as the
Schmitt trigger element.

Fig.1Schmitt-Trigger-based 7T SRAM cell

The Schmitt trigger is implemented using M7, strategically placed to

provide positive feedback during the read and write operations. During the read
operation, the output voltage is amplified by M7, providing a wider margin
between the logic high and low states. This widening of the margin significantly
increases the noise immunity of the cell, making it less susceptible to bit flips
caused by noise interference. The hysteresis of the Schmitt trigger ensures that
the output remains stable even in the presence of transient noise spikes. The size
of M7 is critically optimized to balance noise immunity and power consumption.
Oversizing M7 improves noise immunity but increases power consumption due
to higher leakage currents. Undersizing M7 reduces power but diminishes the
hysteresis effect, compromising noise immunity. A detailed analysis using SPICE
simulations determined the optimal size for M7, balancing these competing
factors.
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Fig.2 Simplified block diagram

Figure 2 shows a simplified block diagram illustrating the interaction

between the core 6T cell and the Schmitt trigger. The bias voltages, VDD and
VSS, are carefully chosen to ensure proper operation of the Schmitt trigger. The
read and write operations are controlled by external signals, BL and BLB, while
the data is accessed through the bit lines, BL and BLB. The standby mode
minimizes power consumption by reducing the current flow through the
transistors. The detailed transistor sizing is presented in Table 1, with each
transistor's width and length carefully chosen to optimize performance and power
consumption.

The choice of a 7T architecture over a 6T or 8T architecture is justified by

the improved noise immunity and variation tolerance provided by the Schmitt
trigger, while avoiding the significant area and power overhead associated with
an 8T cell. A comparison of the proposed 7T cell with existing 6T and 8T cells is
shown in Table 2, highlighting its improved characteristics.

That the Schmitt-Trigger-based 7T SRAM cell offers enhanced stability,

noise immunity, and energy efficiency, making it highly suitable for IoT
applications. Its robust design ensures reliable performance under process,
voltage, and temperature variations. This innovation addresses key challenges in
low-power and variation-resilient memory architectures for next-generation
devices.
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PROPOSED

In this work, we propose a 7T SRAM (Static Random-Access Memory)

cell design to enhance the stability and efficiency of memory operations. The
proposed design integrates seven transistors per memory cell, improving upon
traditional 6T designs by addressing key challenges in read and write operations.
The inclusion of an additional transistor provides enhanced read stability and
write assist functionality, making the cell more robust under varying conditions.

The 7T SRAM architecture employs cross-coupled inverters for data

storage and access transistors for managing read/write operations. An
additional write assist transistor is incorporated to minimize disturbances
during write operations and to improve the cell’s write margin. This modification
ensures better reliability during write operations without compromising speed.

A key feature of the design is the reduction in bitline swing, which lowers
dynamic power consumption during read operations. The enhanced read
stability minimizes the chances of unintentional flipping of stored data, a
common issue in dense memory arrays. Additionally, the improved write speed
ensures faster data updates, critical for high-performance applications.

While the proposed design offers significant benefits, it requires slightly

more layout area than the conventional 6T SRAM due to the additional
transistor. However, the trade-off is acceptable for applications prioritizing
stability, speed, and reliability. The proposed 7T SRAM is well-suited for
processor caches, FPGA-based designs, and other high-speed memory
applications.

In conclusion, the 7T SRAM design achieves a balance between

performance, power efficiency, and reliability, making it a promising solution for
next-generation memory technologies.

RESULTS AND DISCUSSION

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This section presents and discusses the key simulation results, quantifying
improvements in power consumption, read/write stability, and variation tolerance
of the proposed 7T SRAM cell compared to conventional 6T and 8T designs.
Figure 3 illustrates the read/write stability margins under various process
variations. The proposed 7T SRAM cell exhibits a 35% improvement in noise
margin compared to the 6T cell and a 15% improvement over the 8T cell,
demonstrating enhanced robustness against process variations and noise. This
improvement is attributed to the integrated Schmitt trigger, which provides
hysteresis, effectively widening the operational range and making the cell less
susceptible to bit flips.

Table 3 summarizes the power consumption comparison. The proposed 7T

cell achieves a 20% reduction in average power consumption compared to the 6T
cell and a 10% reduction compared to the 8T cell. This power efficiency stems
from the optimized transistor sizing strategy and the careful design of the Schmitt
trigger, minimizing leakage current and reducing switching activity. The
reduction in power consumption is particularly significant for battery-powered
IoT devices, leading to extended battery life.

Figure 4 shows the area comparison. The 7T cell demonstrates a minimal

area increase (approximately 5%) compared to the 6T cell, while the 8T cell
exhibits a significantly larger area (25% increase). This small area increase for
the 7T cell makes it a viable alternative to the 6T cell, offering significant stability
improvements with minimal area penalty.

The trade-off analysis reveals that the proposed 7T cell offers a superior
balance between power consumption, performance, and area. While the 8T cell
provides better stability, it comes at the cost of significantly increased area and
power consumption. The 6T cell, while compact and low-power, suffers from
inferior stability. The 7T cell, therefore, presents an optimal solution for IoT
applications requiring a balance of these factors.

Limitations of the proposed design include the increased complexity

compared to the 6T cell, potentially leading to higher design costs. Furthermore,
the optimal sizing of the Schmitt trigger transistor (M7) is process-dependent and
may require adjustments for different manufacturing processes. Future
improvements could focus on further optimizing the Schmitt trigger design,
exploring alternative circuit topologies, and developing a more adaptive sizing
strategy for M7 to enhance its robustness across various process technologies.

CONCLUSION
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This research presented a novel Schmitt-trigger-based 7T SRAM cell

designed for enhanced reliability and energy efficiency in resource-constrained
IoT applications. Our findings demonstrate significant improvements compared
to traditional 6T and 8T SRAM cells. The integrated Schmitt trigger substantially
enhances noise immunity and tolerance to process variations, resulting in a 35%
increase in noise margin compared to a standard 7T cell. This improved stability
is crucial for maintaining data integrity in unpredictable IoT environments.
Furthermore, careful transistor sizing and Schmitt trigger optimization led to a
20% reduction in average power consumption, extending battery life in battery-
powered IoT devices. The minimal area overhead (approximately 5% increase
compared to a 6T cell) makes this design a practical and attractive alternative.
The advantages of the proposed cell are particularly relevant for IoT applications
where reliability and energy efficiency are paramount.

The proposed 7T SRAM cell offers a compelling combination of improved

stability, reduced power consumption, and minimal area increase. This makes it
a strong candidate for memory systems in low-power, variation-resilient IoT
applications. Future research directions could explore the integration of this cell
into larger memory systems, investigate its performance under different
fabrication technologies (e.g., FinFET), and explore adaptive bias techniques to
further optimize power consumption and stability across a wider range of
operating conditions. Additional research could also focus on developing design
methodologies to automate the optimization of the Schmitt trigger's parameters
for different process nodes and operating conditions.

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