CHAPTER ONE: INTEL MACHINE ARCHITECTURE

Over view of Computer system components

A computer is made up of hardware and software. The hardware of a computer consists of four
types of components:

Processor: - The processor is responsible for performing all of the computational

operations and the coordination of the usage of resources of a computer. A computer
system may consist of one or multiple processors. A processor may perform general
purpose computation or Special purpose computation.
Input devices: - A computer is designed to execute programs that manipulate certain
data. Input devices are needed to enter the program to be executed and data to be
processed into the computer. There are a wide variety of input devices: keyboards,
keypads, scanners, bar code readers, sensors, and so on.
Output devices: - No matter if the user uses the computer to do certain computation or
to find information from the Internet or a database; the end results must be displayed or
printed on paper so that the user can see them. There are many media and devices that
can be used to present the information: CRT displays, flat-panel displays, seven-
segment displays, printers, light-emitting diodes (LEDs),
Memory devices: - Programs to be executed and data to be processed must be stored
in memory devices so that the processor can readily access them.

The Processor
A processor is also called the central processing unit CPU). The processor consists
of at least the following three components:
A. Registers: - A register is a storage location inside the CPU. It is used to hold data
and/or a memory address during the execution of an instruction. Because the
register is very close to the CPU, it can provide fast access to operands for program
execution. The number of registers varies greatly from processor to processor.
B. Arithmetic logic unit (ALU):- The ALU performs all the numerical computations
and logical evaluations for the processor. The ALU receives data from the memory,
performs the operations, and, if necessary, writes the result back to the memory.
Today's supercomputer can perform trillions of operations per second.

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 C. Control unit:-The control unit contains the hardware instruction logic. The control
unit decodes and monitors the execution of instructions. The control unit also acts
as an arbiter as various portions of the computer system compete for the resources
of the CPU. The activities of the CPU are synchronized by the system clock. The
clock rates of modern microprocessors have exceeded 3.0 GHz at the time of this
writing, where 1 GHz = 1 billion cycles per second The period of a 1-GHz clock
signal is 1 ns (10-9 second).

Typical Features of processors

 Smaller size
 Lower cost
 higher reliability
 Lower power consumption
 More power full
 Versatility
80x86 Microprocessor
8086 microprocessor is an enhanced version of 8085 microprocessor that was designed
by Intel in 1976.
Features of 80x86 Microprocessor:
1. Intel 8086 was launched in 1978.
2. It was the first 16-bit microprocessor.
3. This microprocessor had major improvement over the execution speed of
8085.
4. It is available as 40-pin Dual-Inline-Package (DIP).
5. It is available in three versions:
a. 8086 (5 MHz)
b. 8086-2 (8 MHz)
6. It consists of 29,000 transistors
N.B In 80x86, x represents version number

SIGNAL DESCRIPTIONS OF 8086

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The microprocessor 8086 is a 16-bit CPU available in three clock rates, i.e. 5, 8 and 10
MHz, packaged in a 40 pin DIP or plastic package. The 8086 operates in single
processor or multiprocessor configurations to achieve high performance. The pin
configuration is shown in the following figure. Some of the pins serve a particular
function in minimum mode (single processor mode) and others function in maximum
mode (multiprocessor mode) configuration.

The 8086 signals can be categorized in three groups. The first are the signals having
common functions in minimum as well as maximum mode, the second are the signals,
which have special functions for minimum mode, and the third are the signals having
special functions for maximum mode.

The following signal descriptions are common for both the minimum and maximum
modes.

AD15-AD0 these are the time multiplexed memory I/0 address and data lines. Address
remains on the lines during T, state, while the data is available on the data bus during
T2,T3,Tw, and T4 Here T1,T2,T3,T4 and Tw, are the clock states of a machine cycle.
Tw is a wait state. These lines are active high and float to a tristate during interrupt
acknowledge and local bus hold acknowledge cycles.

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Fig1: The Pin Configuration of 8086

A19/S6, A18/S5, A17/S4, A16/S3 these are the time multiplexed address and status
lines. During T1, these are the most significant address lines for memory operations.
During I/0 operations, these lines are low. During memory or I/0 operations, status
information is available on those lines for T2, T3, Tw, and T4. The status of the interrupt
enable flag bit (displayed on S5) is updated at the beginning of each clock cycle.

Table1: Bus High Enable/Status

The S4 and S3 combination indicate which segment register is presently being used for
memory accesses as shown in Table above. These lines float to tri-state off (tristated)
during the local bus hold acknowledge. The status line S6 is always low (logical). The
address bits are separated from the status bits using latches controlled by the ALE
signal.

BHE/S7-Bus High Enable/Status The bus high enable signal is used to indicate the
transfer of data over the higher order (D15-D8) data bus as shown in Table below. It
goes low for the data transfers over D15-D8 and is used to derive chip selects of odd
address memory bank or peripherals. BHE is low during T1 for read, write and interrupt
acknowledge cycles, whenever a byte is to be transferred on the higher byte of the data
bus. The status information is available during T2, T3 and T4. The signal is active low

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and is tristated during 'hold'. It is low during T1 for the first pulse of the interrupt
acknowledges cycle.

Table2: Bus High Enable/Status

RD-Read Read signal, when low, indicates the peripherals that the processor is
performing a memory or I/0 read operation. RD is active low and shows the state for
T2, T3, Tw of any read cycle. The signal remains tristated during the 'hold
acknowledge'.

READY This is the acknowledgement from the slow devices or memory that they have
completed the data transfer. The signal made available by the devices is synchronized
by the 8284A clock generator to provide ready input to the 8086. The signal is active
high.

INTR-interrupt Request this is a level triggered input. This is sampled during the last
clock cycle of each instruction to determine the availability of the request. If any interrupt
request is pending, the processor enters the interrupt acknowledge cycle. This can be
internally masked by resetting the interrupt enable flag. This signal is active high and
internally synchronized.

TEST This input is examined by a 'WAIT' instruction. If the TEST input goes low,
execution will continue, else, the processor remains in an idle state. The input is
synchronized internally during each clock cycle on leading edge of clock.

NMI Non-maskable Interrupt this is an edge-triggered input which causes a Type2

interrupt. The NMI is not maskable internally by software. A transition from low to high
initiates the interrupt response at the end of the current instruction. This input is

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internally synchronized. RESET This input causes the processor to terminate the
current activity and start execution from FFFF0H. The signal is active high and must be
active for at least four clock cycles. It restarts execution when the RESET returns low.
RESET is also internally synchronized.

CLK Clock Input:-the clock input provides the basic timing for processor operation and
bus control activity. Its an asymmetric square wave with 33% duty cycle. The range of
frequency for different 8086 versions is from 5MHz to 10MHZ.

Vcc +5V power supply for the operation of the internal circuit.

GND ground for the internal circuit.

MN/MX The logic level at this pin decides whether the processor is to operate in either
minimum (single processor) or maximum (multiprocessor) mode. The following pin
functions are for the minimum mode operation of 8086.

M/I/O -Memory/IO this is a status line logically equivalent to 92 in maximum mode.

When it is low, it indicates the CPU is having an 1/0 operation, and when it is high, it
indicates that the CPU is having a memory operation. This line becomes active in the
previous T4 and remains active till final T4 of the current cycle. It is tristated during local
bus "hold acknowledge".

INTA - Interrupt Acknowledge this signal is used as a read strobe for interrupt
acknowledge cycles. In other words, when it goes low, it means that the processor has
accepted the interrupt. It is active low during T2, T3 and Tw of each interrupt
acknowledge cycle.

ALE-Address Latch Enable This output signal indicates the availability of the valid
address on the address/data lines, and is connected to latch enable input of latches.
This signal is active high and is never tristated.

DT/R Data Transmit/Receive This output is used to decide the direction of data flow
through the transreceivers (bi-directional buffers). When the processor sends out data,
this signal is high and when the processor is receiving data, this signal is low.

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Logically, this is equivalent to S, in maximum mode. Its timing is the same as M/I/O.
This is tristated during 'hold acknowledge'.

DEN-Data Enable This signal indicates the availability of valid data over the
address/data lines. It is used to enable the transreceivers (bi-directional buffers) to
separate the data from the multiplexed address/data signal. It is active from the middle
of T2 until the middle of T4 DEN is tristated during ‘hold acknowledge' cycle

HOLD, HLDA - Hold/Hold Acknowledge When the HOLD line goes high, it indicates to
the processor that another master is requesting the bus access. The processor, after
receiving the HOLD request, issues the hold acknowledge signal on HLDA pin, in the
middle of the next clock cycle after completing the current bus (instruction) cycle. At the
same time, the processor floats the local bus and control lines. When the processor
detects the HOLD line low, it lowers the HLDA signal. HOLD is an asynchronous input,
and it should be externally synchronized. If the DMA request is made while the CPU is
performing a memory or I/O cycle, it will release the local bus during T4 provided:

1. The request occurs on or before T2 state of the current cycle.

2. The current cycle is not operating over the lower byte of a word (or operating on an odd
address).
3. The current cycle is not the first acknowledge of an interrupt acknowledge sequence.
4. A Lock instruction is not being executed.
So far we have seen the pin descriptions of 8086 in minimum mode.

The following pin functions are applicable for maximum mode operation of 8086.

S2, S1, and S0 - Status Lines These are the status lines which reflect the type of
operation, being carried out by the processor. These status lines are encoded in the
Table

Table3
Status
Lines

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 This output pin indicates that other system bus masters will be prevented from
gaining the system bus, while the LOCK signal is low. The LOCK signal is activated by
the 'LOCK’ prefix instruction and remains active until the completion of the next
instruction. This floats to tri-state off during 'hold acknowledge". When the CPU is
executing a critical instruction, which requires the system bus, the LOCK prefix
instruction ensures that other processors connected in the system will not gain the
control of the bug. The 8086, while executing the prefixed instruction, asserts the bus
lock signal output, which may be connected to an external bus controller.

QS1, QS0-Queue Status These lines give information about the status of the code-
prefetch queue. These are active during the CLK cycle after which the queue operation
is performed. These are encoded as shown in Table below4.

Table below4 Queue Status

This modification in a simple fetch and execute architecture of a conventional
microprocessor offers an added advantage of pipelined processing of the instructions.
The 8086 architecture has a 6-byte instruction prefetch queue. Thus even the largest (6-
bytes) instruction can be prefetched from the memory and stored in the prefetch queue.
This results in a faster execution of the instructions. In 8085, an instruction (opcode and
operand) is fetched, decoded and executed and only after the execution of this
instruction, the next one is fetched. By prefetching the instruction, there is a
considerable speeding up in instruction execution in 8086. This scheme is known as
instruction pipelining.

The instruction execution cycle is never broken for fetch operation. After decoding the
first byte, the decoding circuit decides whether the instruction is of single opcode byte or

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double opcode byte. If it is single opcode byte, the next bytes are treated as data bytes
depending upon the decoded instruction length, otherwise, the next byte in the queue
are treated as the second byte of the instruction opcode. The second byte is then
decoded in continuation with the first byte to decide the instruction length and the
number of subsequent bytes to be treated as instruction data. The queue is updated
after every byte is read from the queue but the fetch cycle is initiated by BIU only if at
least two bytes of the queue are empty and the EU may be concurrently executing the
fetched instructions.

The next byte after the instruction is completed is again the first opcode byte of
the next instruction. A similar procedure is repeated till the complete execution of the
program. The main point to be noted here is that the fetch operation of the next
instruction is overlapped with the execution of the current instruction. As shown in the
architecture, there are two separate units, namely, execution unit and bus interface unit,
while the execution unit is busy in executing an instruction, after it is completely
decoded, the bus interface unit may be fetching the bytes of the next instruction from
memory, depending upon the queue status.

Other local bus masters, in maximum mode, to force the processor to release
the local bus at the end of the processor’s current bus cycle, use these pins. Each of the
pins is bi-directional with RQ/GT0 having higher priority than RQ/GT1. RQ/GT pins have
internal pull-up resistors and may be left unconnected. The request/ grant sequence is
as follows:

1. A pulse one clock wide from another bus master requests the bus access to 8086.
2. During T4 (current) or T, (next) clock cycle, a pulse one clock wide from 8086 to the
requesting master, indicates that the 8086 has allowed the local bus to float and that
it will enter the "hold acknowledge" state at next clock cycle. The CPU's bus interface
unit is likely to be disconnected from the local bus of the system.

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 3. A one clock wide pulse from another master indicates to 8086 that the 'hold' request
is about to end and the 8086 may regain control of the local bus at the next clock
cycle.

Thus each master-to-master exchange of the local bus is a sequence of 3

pulses. There must be at least one dead clock cycle after each bus exchange. The
request and grant pulses are active low. For the bus requests those are received while
8086 is performing memory or 1/0 cycle, the granting of the bus is governed by the rules
as discussed in case of HOLD, and HLDA in minimum mode.

80x86 CPU functional units

The 80x86 CPU is divided into two independent functional parts, the bus Interface unit
or BIU, and the execution unit or EU. Dividing the work between these two units
speeds up processing. Which is 20-bits long, is generated using segment and offset
registers, each 16-bits long.
For generating a physical address from contents of these two registers, the content of a
segment register also called as segment address is shifted left bit-wise four times and to
this result, content of an offset register also called as offset address is added, to
produce a 20-bit physical address. Thus the segment addressed by the segment value
1005H can have offset values from 0000H to FFFFH within it, i.e. maximum 64K
locations may be accommodated in the segment. Thus the segment register indicates
the base address of a particular segment, while the offset indicates the distance of the
required memory location in the segment from the base address. Since the offset is a
16-bit number, each segment can have a maximum of 64K locations. The bus interface
unit has a separate adder to perform this procedure for obtaining a physical address
while addressing memory. The segment address value is to be taken from an
appropriate segment register depending upon whether code, data or stack are to be
accessed, while the offset may be the content of IP, BX, SI, DI,SP or an immediate 16-
bit value, depending upon the addressing mode.

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 Fig. Block Diagram of Intel 8086
Bus Interface Unit (BIU)
The function of BIU is to:
 Fetch the instruction or data from memory.
 Write the data to memory.
 Write the data to the port.
 Read data from the port.
Instruction Queue
1. To increase the execution speed, BIU fetches as many as six instruction bytes
ahead to time from memory.
2. All six bytes are then held in first in first out 6 byte register called instruction
queue.
3. Then all bytes have to be given to EU one by one.
4. This pre fetching operation of BIU may be in parallel with execution operation
of EU, which improves the speed execution of the instruction.

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Execution Unit (EU) the EU contains control circuitry, which directs internal operations.
A decoder in the EU translates instructions fetched from memory into a series of
actions, which the EU carries out. The EU has a 16-bit arithmetic logic unit which can
add, subtract, AND, OR, XOR, increment, decrement, complement, or shift binary
numbers.
The functions of execution unit are:
 To tell BIU where to fetch the instructions or data from.
 To decode the instructions.
 To execute the instructions.
CPU Registers
General Purpose Registers of 8086
These registers can be used as 8-bit registers individually or can be used as 16-bit in
pair to have AX,BX, CX, and DX.

Data Registers
 AX (Accumulator Register): AH and AL
 BX (Base Register): BH and BL
 CX (Count Register): CH and CL
 DX (Data Register): DH and DL
N.B

o AH, BH, CH, DH are the high bytes

o AL, BL, CL, and DL are the low bytes

1. AX Register: AX register is also known as accumulator register that stores operands

for
Arithmetic operation like divided, rotate.
2. BX Register: This register is mainly used as a base register. It holds the starting
base
location of a memory region within a data segment.
3. CX Register: It is defined as a counter. It is primarily used in loop instruction to store
loop

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 counter.
4. DX Register: DX register is used to contain I/O port address for I/O instruction.

Address registers
A. Pointer and Index Registers
 SI (Source Index) is a 16-bit register. SI is used for indexed, based indexed and
register indirect addressing, as well as a source data address in string manipulation
instructions
 DI (Destination Index) is a 16-bit register. DI is used for indexed, based indexed and
register indirect addressing, as well as a destination data address in string
manipulation instructions.
 SP (Stack Pointer) is a 16-bit register pointing to program stack
 BP (Base Pointer) is a 16-bit register pointing to data in stack segment. BP register
is usually used for based, based indexed or register indirect addressing
 IP (Instruction Pointer)
B. Segment Registers
Additional registers called segment registers generate memory address when combined
with other in the microprocessor. In 8086 microprocessor, memory is divided into 4
segments
CS (Code Segment): The CS register is used for addressing a memory location in the
Code
Segment of the memory, where the executable program is stored.
DS (Data Segment): The DS contains most data used by program. Data are accessed
in the
Data Segment by an offset address or the content of other register that holds the offset
address.
SS (Stack Segment): SS defined the area of memory used for the stack.
ES (Extra Segment): ES is additional data segment that is used by some of the string
to hold
the destination data.
FLAG Registers

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Flag Register determines the current state of the processor. They are modified
automatically by CPU after mathematical operations, this allows to determine the type of
the result, and to determine conditions to transfer control to other parts of the program
Flag Register is modified automatically by CPU after mathematical operations, this
allows to determine the type of the result, and to determine conditions to transfer control
to other parts of the program.
8086 has 9 flags and they are divided into two categories:

1. Conditional Flags
2. Control Flags

1. Conditional Flags
Conditional flags represent result of last arithmetic or logical instruction executed.
Conditional flags are as follows:
Carry Flag (CF): This flag indicates an overflow condition for unsigned integer
arithmetic. It is also used in multiple-precision arithmetic.
Auxiliary Flag (AF): If an operation performed in ALU generates a carry/barrow
from
Lower nibble (i.e. D0 – D3) to upper nibble (i.e. D4 – D7), the AF flag is set i.e.
carry given by D3 bit to D4 is AF flag. This is not a general-purpose flag, it is
used internally by the processor to perform Binary to BCD conversion.
Parity Flag (PF): This flag is used to indicate the parity of result. If lower order
8-bits of the result contains even number of 1’s, the Parity Flag is set and for odd
number of 1’s, the Parity Flag is reset.
Zero Flag (ZF): It is set; if the result of arithmetic or logical operation is zero else
it is reset.

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 Sign Flag (SF): In sign magnitude format the sign of number is indicated by
MSB bit. If the result of operation is negative, sign flag is set.
Overflow Flag (OF): It occurs when signed numbers are added or subtracted.
An OF
indicates that the result has exceeded the capacity of machine.
2. Control Flags
Control flags are set or reset deliberately to control the operations of the execution unit.
Control flags are as follows:
1. Trap Flag (TP):
a. It is used for single step control.
b. It allows user to execute one instruction of a program at a time for debugging.
c. When trap flag is set, program can be run in single step mode.
2. Interrupt Flag (IF):
a. It is an interrupt enable/disable flag.
b. If it is set, the maskable interrupt of 8086 is enabled and if it is reset, the
interrupt is
disabled.
c. It can be set by executing instruction sit and can be cleared by executing CLI
instruction.
3. Direction Flag (DF):
a. It is used in string operation.
b. If it is set, string bytes are accessed from higher memory address to lower
memory
Address.
c. When it is reset, the string bytes are accessed from lower memory address to
higher
memory address.
Program Counter (PC) or Instruction Pointer (IP)
Holds address of next instruction to fetch
Instruction Register (IR)
 Stores the instruction fetched from memory
Fetch-Execute process
 Read an instruction from memory addressed by PC
 Increment program counter
 Execute fetched instruction in IR
 Repeat process

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Individual assignment (10 marks)

1. discuss the role of microprocessors in modern computing

2.compare different types of microprocessor families like 4001, 8085,8088,8086

3. discuss different processor manufacturing companies .

4. what is the relationship of microprocessor and assembly language?

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Chapter two

Basics of Assembly Language Programs

Early computer systems were literally programmed by hand. Front panel switches were
used to enter instructions and data. These switches represented the address, data and
control lines of the computer system.To enter data into memory, the address switches
were toggled to the correct address, the data switches were toggled next, and finally the
WRite switch was toggled. This wrote the binary value on the front panel data switches
to the address specified. Once all the data and instruction were entered, the run switch
was toggled to run the program.

The programmer also needed to know the instruction set of the processor. Each
instruction needed to be manually converted into bit patterns by the programmer so the
front panel switches could be set correctly. This led to errors in translation as the
programmer could easily misread 8 as the value B. It became obvious that such
methods were slow and error prone.

With the advent of better hardware which could address larger memory, and the
increase in memory size (due to better production techniques and lower cost), programs
were written to perform some of this manual entry. Small monitor programs became
popular, which allowed entry of instructions and data via hex keypads or terminals.
Additional devices such as paper tape and punched cards became popular as storage
methods for programs.

Programs were still hand-coded, in that the conversion from mnemonics to instructions
was still performed manually. To increase programmer productivity, the idea of writing a
program to interpret another was a major breakthrough. This would be run by the
computer, and translate the actual mnemonics into instructions. The benefits of such a
program would be

 reduced errors
 faster translation times

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  changes could be made easier and faster

As programmers were writing the source code in mnemonics anyway, it seemed the
logical next step. The source file was fed as input into the program, which translated the
mnemonics into instructions, then wrote the output to the desired place (paper-tape etc).
This sequence is now accepted as common place.

The only advances have been the increasing use of high level languages to increase
programmer productivity. Assembly language programming is writing machine
instructions in mnemonic form, using an assembler to convert these mnemonics into
actual processor instructions and associated data.

THE PROGRAM TRANSLATION SEQUENCE

developing a software program to accomplish a particular task, the implement or
chooses an appropriate language, develops the algorithm (a sequence of steps, which
when carried out in the order prescribed, achieve the desired result), implements this
algorithm in the chosen language (coding), then tests and debugs the final result.

here is also a probable maintenance phase also associated. The chosen language will
undoubtedly need to be converted into the appropriate binary bit-patterns which make
sense to the target processor (the processor on which the software will be run). This
process of conversion is called translation.

The following diagram illustrates the translation sequence necessary to generate

machine code from specific languages.

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Translator software

The other type of system software that you need to know is translator software. This is
software that allows new programs to be written and run on computers, by converting
source code into machine code. There are three types that we'll cover in a lot more
detail shortly:

 Assembler - converts assembly code into machine code

 Interpreter - converts HIGH LEVEL languages such as javascript into machine
code one line at a time
 Compiler - converts HIGH LEVEL languages such as C++ into machine code all
at once

ASSEMBLY LANGUAGE PROGRAMMING

Assemblers are programs which generate machine code instructions from a source
code program written in assembly language. The features provided by an assembler
are,

 Allows the programmer to use mnemonics when writing source code programs.
 variables are represented by symbolic names, not as memory locations
 symbolic code is easier to read and follow
 error checking is provided
 changes can be quickly and easily incorporated with a re-assembly
 programming aids are included for relocation and expression evaluation

In writing assembly language programs for micro-computers, it is essential that a

standardized format be followed. Most manufacturers provide assemblers, which are
programs used to generate machine code instructions for the actual processor to
execute.

The assembler converts the written assembly language source program into a format
which run on the processor. Each machine code instruction (the binary or hex value) is

Machine architecture and assembly language Page 19

replaced by a mnemonic. A mnemonic is an abbreviation which represents the actual
instruction.

+----------+---------+-----------------+
| Binary | Hex | Mnemonic |
+----------+---------+-----------------+
| 01001111 | 4F | CLRA | Clears the A accumulator
+----------+---------+-----------------+
| 00110110 | 36 | PSHA | Saves A acc on stack
+----------+---------+-----------------+
| 01001101 | 4D | TSTA | Tests A acc for 0
+----------+---------+-----------------+

Mnemonics are used because they

 are more meaningful than hex or binary values

 reduce the chances of making an error
 are easier to remember than bit values

Each personal computer has a microprocessor that manages the computer's

arithmetical, logical, and control activities. Each family of processors has its own set of
instructions for handling various operations such as getting input from keyboard,
displaying information on screen and performing various other jobs. These set of
instructions are called 'machine language instructions'.A processor understands only
machine language instructions, which are strings of 1's and 0's. However, machine
language is too obscure and complex for using in software development. So, the low-
level assembly language is designed for a specific family of processors that represents
various instructions in symbolic code and a more understandable form.

Advantages of using assembly language are:

 It requires less memory and execution time;

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  It allows hardware-specific complex jobs in an easier way;
 It is suitable for time-critical jobs;
 It is most suitable for writing interrupt service routines and other memory resident
programs.
 The symbolic programming of Assembly Language is easier to understand and
saves a lot of time and effort of the programmer.
 It is easier to correct errors and modify program instructions.
 Assembly Language has the same efficiency of execution as the machine level
language. Because this is one-to-one translator between assembly language
program and its corresponding machine language program.
Disadvantages Assembly Language:

 One of the major disadvantages is that assembly language is machine

dependent. A program written for one computer might not run in other
computers with different hardware configuration.
 the programmer requires knowledge of the processor architecture and
instruction set
 many instructions are required to achieve small tasks
 source programs tend to be large and difficult to follow
 programs are machine dependent, requiring complete rewrites if the
hardware is changed

Assembly - Variables

NASM provides various define directives for reserving storage space for variables.
The define assembler directive is used for allocation of storage space. It can be used to
reserve as well as initialize one or more bytes.

Allocating Storage Space for Initialized Data

The syntax for storage allocation statement for initialized data is −

[variable-name] define-directive initial-value [,initial-value]...

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Where, variable-name is the identifier for each storage space. The assembler
associates an offset value for each variable name defined in the data segment.

There are five basic forms of the define directive −

Directive Purpose Storage Space

DB Define Byte allocates 1 byte
DW Define Word allocates 2 bytes
DD Define Doubleword allocates 4 bytes
DQ Define Quadword allocates 8 bytes
DT Define Ten Bytes allocates 10 bytes

Following are some examples of using define directives −

choice DB 'y'
number DW 12345
neg_number DW -12345
big_number DQ 123456789
real_number1 DD 1.234
real_number2 DQ 123.456

Please note that −

 Each byte of character is stored as its ASCII value in hexadecimal.

 Each decimal value is automatically converted to its 16-bit binary equivalent and
stored as a hexadecimal number.
 Processor uses the little-endian byte ordering.
 Negative numbers are converted to its 2's complement representation.
 Short and long floating-point numbers are represented using 32 or 64 bits,
respectively.

Allocating Storage Space for Uninitialized Data

Machine architecture and assembly language Page 22

The reserve directives are used for reserving space for uninitialized data. The reserve
directives take a single operand that specifies the number of units of space to be
reserved. Each define directive has a related reserve directive.

There are five basic forms of the reserve directive −

Directive Purpose
RESB Reserve a Byte
RESW Reserve a Word
RESD Reserve a Doubleword
RESQ Reserve a Quadword
REST Reserve a Ten Bytes

Multiple Definitions

You can have multiple data definition statements in a program. For example −

choice DB 'Y' ;ASCII of y = 79H

number1 DW 12345 ;12345D = 3039H
number2 DD 12345679 ;123456789D = 75BCD15H

The assembler allocates contiguous memory for multiple variable definitions.

Multiple Initializations

The TIMES directive allows multiple initializations to the same value. For example, an
array named marks of size 9 can be defined and initialized to zero using the following
statement −

marks TIMES 9 DW 0

The TIMES directive is useful in defining arrays and tables.

Machine architecture and assembly language Page 23

Assembly - Constants

There are several directives provided by NASM that define constants. We have already
used the EQU directive in previous chapters. We will particularly discuss three
directives −

 EQU
 %assign
 %define

The EQU Directive

The EQU directive is used for defining constants. The syntax of the EQU directive is as
follows −

CONSTANT_NAME EQU expression

For example,

TOTAL_STUDENTS equ 50

You can then use this constant value in your code, like −

movecx, TOTAL_STUDENTS
cmpeax, TOTAL_STUDENTS

The operand of an EQU statement can be an expression −

LENGTH equ20
WIDTH equ10
AREA equ length * width

Above code segment would define AREA as 200.

The %assign Directive

Machine architecture and assembly language Page 24

The %assign directive can be used to define numeric constants like the EQU directive.
This directive allows redefinition. For example, you may define the constant TOTAL as −

%assign TOTAL 10

Later in the code, you can redefine it as −

%assign TOTAL 20

This directive is case-sensitive.

The %define Directive

The %define directive allows defining both numeric and string constants. This directive
is similar to the #define in C. For example, you may define the constant PTR as −

%define PTR [EBP+4]

The above code replaces PTR by [EBP+4].

This directive also allows redefinition and it is case-sensitive.

Components of Assembly Language

1. Label: is the text string much like variable name in the high level language

Some rules of label

 Begin in the first column

 It must not be reserved word
 Must be unique

2. opcode (operation code):-this instruction contains the assembly language

command that the processor is supposed to execute this line of code

Machine architecture and assembly language Page 25

3.operand:-contains data or operand that the assembly command that the assembly
language instruction needs for execution

4.comment:- statement after comment is not executed

Label <Opcode> <operand>;comment

up : MOV AX,BX;

Definition of instruction set (OPCODES)

An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. The entire group of instructions that a microprocessor supports is called Instruction
Set. 8086 has more than 20,000 instructions

CLASSIFICATION OF INSTRUCTIONS
The 8086 microprocessor supports 6 types of instructions

1. Data Transfer Instructions

2. Arithmetic Instructions
3. Bit Manipulation Instructions
4. String Instructions
5. Program Execution Transfer Instructions (Branch & Loop Instructions)
6. Processor Control Instructions
1. DATA TRANSFER INSTRUCTION
1.1. General-Purpose Byte or Word Transfer Instructions:
MOV Copy byte or word from specified source to specified destination.
PUSH Copy specified word to top of stack.
POP Copy word from top of stack to specified location.
XCHG Exchange bytes or exchange words.
XLAT Translate a byte in AL using a table in memory.
1.2. Simple Input Output Port Transfer Instructions:

IN Copy a byte or word from specified port to accumulator.

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 OUT Copy a byte or word from accumulator to specified port.

1.3. Special Address Transfer Instructions:

LEA Load effective address of operand into specified register.
LDS Load DS register and other specified register from memory.
LES Load ES register and other specified register from me
1.4. Flag Transfer Instructions
LAHF Load (copy to) AH with the low byte of the flag register.
SAHF Store (copy) AH registers to low byte of flag register.
PUSHF Copy flag register to top of stack.
POPF Copy word at top of stack to flag register.

2. ARITHMETIC INSTRUCTIONS
2.1. Addition Instructions
ADD Add specified byte-to-byte or specified word to word.

ADC Add byte + byte + carry flag or word + word + carry flag.
INC Increment specified byte or specified word by 1.
AAA ASCII adjust after addition.
DAA Decimal (BCD) adjust after addition.
2.2. Subtraction Instructions:
SUB Subtract byte from byte or word from word.
SBB Subtract byte and carry flag from byte or word and carry flag
From word.
DEC Decrement specified byte or specified word by 1.
NEG Negate-Invert each bit of a specified byte or word and add 1
(Form 2’s complement).
CMP Compare two specified bytes or two specified words.
AAS ASCII adjust after subtraction.
DAS Decimal (BCD) adjust after subtraction.
2.3. Multiplication Instructions
MUL multiply unsigned byte-by-byte or unsigned word by word.
IMUL multiply signed byte by byte or signed word by word.
AAM ASCII adjust after multiplication.

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 2.4. Division Instructions:
DIV Divide unsigned word by byte or unsigned double word by word.
IDIV Divide signed word by byte or signed double word by word.
AAD ASCII adjust before division.

CBW Fill upper byte of word with copies of sign bit of lower byte.

CWD Fill upper word of double word with sign bit of lower word.

3. BIT MANIPULATION INSTRUCTIONS

3.1. Logical Instructions:
NOT Invert each bit of a byte or word.
AND AND each bit in a byte or word with the corresponding bit in
Another byte or word.
OR OR each bit in a byte or word with the corresponding bit in another
Byte or word.
XOR Exclusive OR each bit in a byte or word with the corresponding bit
in another byte or word.
TEST AND operands to update flags, but don't change operands.

3.2. Shift Instructions:

SHL/SAL Shift bits of word or byte left, put zero(s) in LSB(s).
SHR Shift bits of word or byte right, put zero(s) in MSB(s).
SAR Shift bits of word or byte right, copy old MSB into new MSB
3.3. Rotate Instructions:
ROL Rotate bits of byte or word left, MSB to LSB and to CF.
ROR Rotate bits of byte or word right, LSB to MSB and to CF.
RCL Rotate bits of byte or word left, MSB to CF and CF to LSB.
RCR Rotate bits of byte or word right, LSB to CF and CF to MSB
4. STRING INSTRUCTIONS
REP An instruction prefix. Repeat the following instruction

Until CX = 0.

REPE/REPZ An instruction prefix. Repeat instruction until CX = 0 or

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 Zero flag ZF ≠ 1.

REPNE/REPNZ An instruction prefix. Repeat until CX = 0 or ZF = 1.

MOVS/MOVSB/MOVSW Move byte or word from one string to another.

COMPS/COMPSB/COMPSW Compare two string bytes or two string words.
SCAS/SCASB/SCASW Scan a string. Compare a string byte with
a

Byte in AL or a string word with a word

in AX.

LODS/LODSB/LODSW Load string byte into AL or string word into AX.

STOS/STOSB/STOSW Store byte from AL or word from AX into
string.

5. PROGRAM EXECUTION TRANSFER INSTRUCTIONS

5.1. Unconditional Transfer Instructions:
CALL Call a procedure (subprogram), save return address on stack.
RET Return from procedure to calling program.
JMP Go to specified address to get next instruction.
5.2. Conditional Transfer Instructions:
JA/JNBE Jump if above/jump if not below or equal.
JAE/JNB Jump if above or equal/jump if not below.
JB/JNAE Jump if below/jump if not above or equal.
JBE/JNA Jump if below or equal/jump if not above.
JC Jump if carry flag CF = 1.
JE/JZ Jump if equal/jump if zero flag ZF = 1.
JG/JNLE Jump if greater/jump if not less than or equal.
JGE/JNL Jump if greater than or equal/ Jump if not less than.
JL/JNGE Jump if less than/jump if not greater than or-equal.
JLE/JNG Jump if less than or equal/jump if not greater than.
JNC Jump if no carry (CF = 0).
JNE/JNZ Jump if not equal/jump if not zero (ZF = 0).
JNO Jump if no overflow (overflow flag OF = 0).
JNP/JPO Jump if not parity/jump if parity odd (PF = 0).

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 JNS Jump if not sign (sign flag SF= 0).
JO Jump if overflow flag OF = 1.
JP/JPE Jump if parity/jump if parity even (PF = 1).
JS Jump if sign (SF=1)

5.3. Iteration Control Instructions:

LOOP Loop through a sequence of instructions until CX = 0.
LOOPE/LOOPZ Loop through a sequence of instructions while ZF =1
and CX ≠ 0.
LOOPNE/LOOPNZ Loop through a sequence of instructions while ZF =
0 and CX ≠ 0.
JCXZ Jump to specified address if CX = 0.
5.4. Interrupt Instructions

INT Interrupt program execution, call service procedure (ISR-

Interrupt Service Routine).
INTO Interrupt program execution if OF = 1.
IRET Return from interrupt service procedure to main
Program.
6. PROCESSOR CONTROL INSTRUCTIONS:
6.1. Flag Set/clear Instructions:
STC Set carry flag CF to 1.
CLC Clear carry flag CF to 0.
CMC Complement the state of the carry flag CF.
STD Set direction flag DF to 1 (decrement string pointers).
CLD Clear direction flag DF to 0.
STI Set interrupt enable flag to 1 (enable INTR input).
CLI Clear interrupt enable flag to 0 (disable INTR input).

6.2. External Hardware Synchronization Instructions:

HLT Halt (do nothing) until interrupt or reset.
WAIT Wait (do nothing) until signal on the TEST pin is low.
ESC Escape to external coprocessor such as 8087 or 8089

Machine architecture and assembly language Page 30

 LOCK An instruction prefix. Prevents another processor
From taking the bus (in MAX mode)

6.3. No Operation Instruction:

NOP No action except fetch and decode.

3.3 DETAILED DISCUSSION ON INSTRUCTIONS

1.3.1 Data Transfer Instructions

MOV---Copy a Word or Byte---MOV Destination, Source

The MOV instruction copies a word or byte of data from a specified source to a specified
destination. The destination can be a register or a memory location. The source can be a
register, a memory location, or an immediate number. The source and destination in an
instruction cannot both be memory locations. The source and destination in a MOV
instruction must both be of type byte, or they must both be of type word. MOV
instructions do not affect any flags.
EXAMPLES:
MOV CX, 037AH Put the immediate number 037AH in CX
MOV BL, [437AH] Copy byte in DS at offset 437AH to BL
MOV AX, BX Copy contents of register BX to AX
MOV DL, [BX] Copy byte from memory at [BX] to DL.
MOV DS, BX Copy word from BX to DS register

1.3.2 PUSH-PUSH Source

The PUSH instruction decrements the stack pointer by 2 and copies a word from a
specified source to the location in the stack segment where the stack pointer then points.
The source of the word can be a general- purpose register, a segment register, or
memory. The stack segment register and the stack pointer must be initialized before this
instruction can be used. PUSH can be used to save data on the stack so that it will not

Machine architecture and assembly language Page 31

 be destroyed by a procedure. It can also be used to put data on the stack so that a
procedure can access it there as needed. No flags are affected by this instruction.

EXAMPLES:
PUSH BX Decrement SP by 2, copy BX to stack
PUSH DS Decrement SP by 2, copy DS to stack
PUSH AL Illegal, must push a word
PUSH TABLE [BX] Decrement SP by 2, copy word from memory in
DS at EA = TABLE + [BX] to stack

1.3.3 POP-POP Destination

The POP instruction copies a word from the stack location pointed to by the stack pointer to a
destination specified in the Instruction. The destination can be a general-purpose register, a
segment register, or a memory location. The data in the stack is not changed. After the word is
copied to the specified destination, the stack pointer is automatically incremented by 2 to point
to the next word on the stack. No flags are affected by the POP instruction. NOTE: POP CS is
illegal.

EXAMPLES:
POP DX Copy a word from top of stack to DX Increment SP by 2
POP DS Copy a word from top of stack to DS Increment SP by 2
POP TABLE [BX] Copy a word from top of stack to memory in DS with EA =
TABLE + [BX]

1.3.4 XCHG-XCHG Destination, Source

The XCHG instruction exchanges the contents of a register with the contents of
another register or the contents of a register with the contents of memory locations). The
XCHG cannot directly exchange the contents of two memory locations. A memory location
can be specified as the source or as the destination by any of the 24 addressing modes. The
source and destination must both be words, or they must both be bytes. The segment
registers cannot be used in this instruction. No flags are affected by this instruction.
EXAMPLES:
XCHG AX,DX Exchange word in AX with word in DX
XCHG BL, CH Exchange byte in BL with byte in CH

Machine architecture and assembly language Page 32

 XCHG AL, PRICES [BX] Exchange byte in AL with byte in memory at EA = PRICES
[BX] in DS

1.3.5 XLAT/XLATB-Translate a Byte in AL

The XLATB instruction is used to translate a byte from one code to another code. The
instruction replaces a byte in the AL register with a byte pointed to by BX in a lookup table in
memory. Before the XLATB instruction can be executed, the lookup table containing the
values for the new code must be put in memory, and the offset of the starting address of the
lookup table must be loaded in BX. The code byte to be translated is put in AL. To point to
the desired byte in the lookup table, the XLATB instruction adds the byte in AL to the offset of
the start of the table in BX. It then copies the byte from the address pointed to by (BX + AL)
back into AL. XLATB changes no flags.
EXAMPLE

8086 routine to convert ASCII code byte to EBCDIC equivalent.

ASCII code byte is in AL at start. EBCD IC code in AL at end.

MOV BX, OFFSET EBCDIC_TABLE Point BX at start of EBCDIC table in DS

XLATB Replace ASCII in AL with EBCDIC from table the

XLATB instruction can be used to convert any

code

of 8 bits or less to any other code of 8 bits or less.

1.4 Simple Input Output Port Transfer Instructions:

1.4.1 IN-Copy Data from a Port--IN Accumulator, Port
The IN instruction will copy data from a port to the AL or AX register. If an 8-bit port is
read, the data will go to AL. If a 16-bit port is read, the data will go to AX. The IN
instruction has two possible formats, fixed port and variable port. For the fixed-port type,
the 8-bit address of a port is specified directly in the instruction.
EXAMPLES:
IN AL, 0C8H Input a byte from port 0C8H to AL

Machine architecture and assembly language Page 33

 IN AX, 34H Input a word from port 34H to AX A_TO_D EQU 4AH
IN AX, A_TO_D Input a word from port 4AH to AX

For the variable-port-type IN instruction, the port address is loaded into the DX register before
the IN instruction. Since DX is a 16-bit register, the port address can be any number between
0000H and FFFFH. Therefore, up to 65,536 ports are addressable in this mode.
MOV DX, 0FF78H Initialize DX to point to port
IN AL, DX Input a byte from 8-bit port 0FF78H to AL
IN AX, DX Input a word from 16-bit port 0FF78H to AX
The variable-port IN instruction has the advantage that the port address can be computed or
dynamically determined in the program
1.4.2 OUT Port, Accumulator AL or AX
The OUT instruction copies a byte from AL or a word from AX to the specified port. The
OUT instruction has two possible forms, fixed port and variable port.

For the fixed-port form, the 8-bit port address is specified directly in the instruction. With this
form, any one of 256 possible ports can be addressed.

EXAMPLES:

OUT 3BH, AL Copy the contents of AL to port 3BH

OUT 2CH, AX Copy the contents of AX to port 2CH for the variable-port form of the
OUT instruction, the contents of AL or AX will be copied to the port at an address
contained in DX. Therefore, the DX register must always be loaded with the desired port
address before this form of the OUT instruction is used. The advantage of the variable-
port form of addressing is described in the discussion of the IN instruction. The OUT
instruction does not affect any flags.

MOV DX, 0FFF8H Load desired port address in

DX OUT DX, AL Copy contents of AL to port FFF8H

OUT DX, AX Copy contents of AX to port FFF8H

Machine architecture and assembly language Page 34

1.5 Arithmetic Instructions
1.5.1
ADC-Add with Carry-ADC Destination, Source

ADD-Add-ADD Destination, Source

These instructions add a number from some source to a number from some destination
and put the -result in the specified destination. The Add with Carry instruction, ADC,
also adds the status of the carry flag into the result. The source may be an immediate
number, a register, or a memory location specified by any one of the 24 addressing
modes. The destination may be a register or a memory location specified by any one of
the 24 addressing modes. The source and the destination in an instruction cannot both
be memory locations. The source and the destination must be of the same type. In other
words, they must both be byte locations, or they must both be word locations. If we want
to add a byte to a word, we must copy the byte to a word location and fill the upper byte
of the word with 0's before adding. Flags affected: AF, CF, OF, PF, SF, ZF.

EXAMPLES:
ADD AL, 74H Add immediate number 74H to contents of AL. Result in AL
ADC CL, BL Add contents of BL plus carry status to contents of CL.
ADD DX, BX Add contents of BX to contents of DX
ADD DX,[SI] Add word from memory at offset [SI]in DS to contents of DX
1.5.2 FLAG RESULTS FOR SIGNED ADDITION EXAMPLE
CF = 0 No carry out of bit 7.
PF = 0 Result has odd parity.
AF = 1 Carry was produced out of bit 3.
ZF = 0 Result in destination was not 0.
SF = 1 Copies most significant bit of result; indicates negative result if we are
Adding signed numbers.
OF= 1 Set to indicate that the result of the addition was too large to fit in the lower 7
bits of the destination used to represent the magnitude of a signed number. In other
words, the result was greater than + 127 decimal, so the result overflowed into the sign
bit position and incorrectly indicated that the result was negative. If we are adding two

Machine architecture and assembly language Page 35

 signed 16-bit values, the OF will be set if the magnitude of the result is too large to fit in
the lower 15 bits of the destination. NOTE: PF is meaningful only for an 8-bit result. AF
is set only by a carry out of bit 3. Therefore, the DAA instruction cannot be used after
word additions to convert the result to correct BCD.
1.5.3 INC-increment-INC Destination
EXAMPLES:
INC BL Add 1 to contents of BL register
INC CX Add1to contents of CX register
1.5.4 AAA-ASCII Adjust for Addition
EXAMPLE:
Assume AL = 0 0 1 1 0 1 0 1, ASCII 5
BL = 0 0 1 1 1 0 0 1, ASCII 9
ADD AL, BL Result: AL= 0 1 1 0 1 1 1 0 = 6EH,which is incorrect BCD
AAA Now AL = 00000100, unpacked BCD 4.
CF = 1 indicates answer is 14 decimal

1.5.5 DAA-Decimal Adjust AL after BCD Addition

This instruction is used to make sure the result of adding two packed BCD numbers is
adjusted to be a legal BCD number.

EXAMPLES:
AL = 0101 1001 = 59 BCD; BL = 0011 0101 = 35 BCD
ADD AL, BL AL = 1000 1110 = 8EH
DAA Add 01 10 because 1110 > 9 AL = 1001 0100 = 94 BCD
AL = 1000 1000 = 88 BCD BL = 0100 1001 = 49 BCD
ADD AL, BL AL = 1101 0001, AF=1
DAA Add 0110 because AF =1, AL = 11101 0111 = D7H
1101 > 9 so add 0110 0000
AL = 0011 0111= 37 BCD, CF =1
The DAA instruction updates AF, CF, PF, and ZF. OF is undefined after a DAA
instruction.
1.6 Subtraction Instructions

SBB-Subtract with Borrow-SBB Destination, Source

Machine architecture and assembly language Page 36

 SUB-Subtract-SUB Destination, Source
These instructions subtract the number in the indicated source from the number in the
indicated destination and put the result in the indicated destination. For subtraction, the carry
flag (CF) functions as a borrow flag. The carry flag will be set after a subtraction if the number
in the specified source is larger than the number in the specified destination. In other words,
the carry/borrow flag will be set if a borrow was required to do the subtraction. The Subtract
instruction, SUB, subtracts just the contents of the specified source from the contents of the
specified destination. The Subtract with Borrow instruction, SBB, subtracts the contents of the
source and the contents of CF from the contents of the indicated destination.
EXAMPLES:
SUB CX, BX CX - BX. Result in CX
SBB CH, AL Subtract contents of AL and contents of CF from contents of
CH. Result In CH
SUB AX, 3427H Subtract immediate number 3427H from AX
SBB BX,[3427H] Subtract word at displacement 3427H in DS and contents of CF
From BX
SUB PRICES [BX], 04H Subtract 04 from byte at effective address PRICES [BX] if
PRICES declared with DB. Subtract 04 from word at effective
Address PRICES [BX] if PRICES declared with DW.
SBB CX, TABLE [BX] Subtract word from effective address TABLE [BX] and
Status of CF from CX.
SBB TABLE [BX], CX Subtract CX and status of CF from word in memory at
Effective address TABLE [BX].
Example Subtracting unsigned numbers
CL = 10011100 = 156 decimal BH = 00110111= 55 decimal
SUB CL, BH Result: CF, AF, SF, ZF = 0, OF, PF=1, CL=01100101= 101 decimal

Example 1 subtracting signed numbers

CL=00101110 = + 46 decimal BH= 01001010=+ 74 decimal
SUB CL, BH Results: AF, ZF = 0, PF = 1
CL = 11100100 = - 28 decimal CF = 1, borrow required
SF = 1, result negative
OF = 0, magnitude of result fits in 7 bits

Machine architecture and assembly language Page 37

 DEC-Decrement Destination Register or Memory-DEC Destination
This Instruction subtracts 1 from the destination word or byte.
EXAMPLES DEC CL Subtract 1 from contents of CL register
DEC BP Subtract 1 from contents of BP register
DEC BYTE PTR [BX] Subtract 1 from byte at offset [BX]in DS. The BYTE PTR
Directive is necessary to tell the assembler to put in the correct
Code for decrementing a byte in memory

CMP-Compare Byte or Word-CMP Destination, Source

This instruction compares a byte from the specified source with a byte from the specified
destination, or a word from the specified source with a word from the specified destination.
The source can be an immediate number, a register, or a memory location specified by one of
the 24 addressing modes. The destination can be a register or a memory location. However,
the source and the destination cannot both be memory locations in the same instruction The
comparison is actually done by subtracting the source byte or word from the destination byte
or word. The source and the destination are not changed, but the flags are set to indicate the
results of the comparison. AF, OF, SF, ZF, PF, and CF are updated by the CMP instruction.
For the instruction CMP CX, BX CF, ZF, and SF will be left as follows:

CF ZF SF
CX = BX 0 1 0 Result of subtraction is 0

CX > BX 0 0 0 No borrow required, so CF = 0

CX < BX 1 0 1 Subtraction required borrow, so CF = 1
EXAMPLES:
CMP AL, 01H Compare immediate number01H with byte In AL
CMP BH, CL Compare byte in CL with byte in BH
CMP CX, TEMP_MIN Compare word in DS at displacement TEMP_MIN
With word in CX
CMP TEMP-MAX, CX Compare CX with word in DS at displacement TEMP MAX
CMP PRICES [BX], 49H Compare immediate 49H with byte at offset [BX] in array
PRICES

Machine architecture and assembly language Page 38

 AAS--ASCII Adjust for Subtraction
Numerical data coming into a computer from a terminal is usually in ASCII code. In this code
the numbers 0 to 9 are represented by the ASCII codes 30H to 39H. The 8086 allows us to
subtract the ASCII codes for two decimal digits without masking the "3" in the upper nibble of
each. The AAS instruction is then used to make sure the result is the correct unpacked BCD.
Some simple numerical examples will show how this works.
EXAMPLE:
ASCII 9-ASCII 5 (9-5)
AL = 00111001 = 39H = ASCII 9
BL = 001 10101 = 35H = ASCII 5
SUB AL, BL Result: AL = 00000100 = BCD 04 and CF = 0
AAS Result: AL = 00000100 = BCD 04 and CF = 0 no borrow required
ASCII 5-ASCII 9 (5-9) Assume AL = 00110101 = 35H ASCII 5
And BL = 0011 1001 = 39H = ASCII 9
SUB AL, BL Result: AL = 11111100 = - 4 in 2s complement and CF =1
AAS Result: AL = 00000100 = BCD 04 and CF = 1, borrow needed The AAS
Instruction leaves the correct unpacked BCD result in the low nibble of AL
And resets the upper nibble of AL to all 0's

DAS-Decimal Adjust after BCD Subtraction

This instruction is used after subtracting two packed BCD numbers to make sure the result is
correct packed BCD. The result of the subtraction must be in AL for DAS to work correctly. If the
lower nibble in AL after a subtraction is greater than 9 or the AF was set by the subtraction, then
the DAS instruction will subtract 6 from the lower nibble of AL. If the result in the upper nibble is
now greater than 9 or if the carry flag was set, the DAS instruction will subtract 60 from AL.
EXAMPLES:
AL 1000 0110 86 BCD; BH 0101 0111 57 BCD
SUB AL, BH AL 0010 1111 2FH, CF = 0
DAS Lower nibble of result is 1111, so DAS automatically
Subtracts 0000 0110 to give AL = 00101001 29 BCD
AL 0100 1001 49 BCD BH 0111 0010 72 BCD
SUB AL, BH AL 1101 0111 D7H, CF = 1
DAS Subtracts 0110 0000 (- 60H) because 1101 in upper nibble > 9
AL = 01110111= 77 BCD, CF=1 CF=1 means borrow was needed

Machine architecture and assembly language Page 39

The DAS instruction updates AF, CF, SF, PF, and ZF, but OF is undefined.

1.7 Multiplication Instructions

MUL---Multiply Unsigned Bytes or Words---MUL Source
This instruction multiplies an unsigned byte from some source times an unsigned
byte in the AL register or an unsigned word from some source times an unsigned word In the
AX register. The source can be a register or a memory location specified by any one of the 24
addressing modes. When a byte is multiplied by the contents of AL, the result (product) is put
in AX. A 16-bit destination is required because the result of multiplying an 8-bit number by an
8bit number can be as large as 16 bits the most significant byte of the result is put in AH, and
the least significant byte of the result is put in AL.
When a word is multiplied by the contents of AX, the product can be as large as 32 bits.
The most significant word of the result is put in the DX register, and the least significant word of
the result is put in the AX register. If the most significant byte of a 16-bit result or the most
significant word of a 32-bit result is 0, CF and OF will both be 0's. Checking these flags, then,
allows us to detect and perhaps discard unnecessary leading 0's in a result. AF, PF, SF, and
ZF are undefined after a MUL Instruction

EXAMPLES:
MUL BH AL times BH, result in AX
MUL CX AX times CX, result high word in DX, low word in AX
MUL BYTE PTR [BX] AL times byte in DS pointed to by [BX]
MUL CONVERSION_FACTOR [BX] Multiply AL times byte at effective address
CONVERSION-FACTOR [BX] if it was declared as
type byte with DB. Multiply AX time’s word at
Effective address CONVERSION_FACTOR [BX] if
it was declared as type word with DW. ;

Example showing a byte multiplied by a word

MOV AX, MULTIPLICAND_16 Load 16-bit multiplicand into AX
MOV CL, MULTIPLIER_8 Load 8-bit multiplier into CL
MOV CH, 00H Set upper byte of CX to all 0's
MUL CX AX times CX, 32-bit result in DX and AX

Machine architecture and assembly language Page 40

IMUL-Multiply Signed Numbers--IMUL Source
This instruction multiplies a signed byte from some source times a signed byte in AL or a
signed word from some source times a signed word in AX. The source can be another register
or a memory location specified by any one of the 24 addressing modes shown. When AL
multiplies a byte from some source, the signed result (product) will be put in AX. A 16-bit
destination is required because the result of multiplying two 8-bit numbers can be as large as
16 bits. The result of this multiplication will be in DX and AX

EXAMPLES:
IMUL BH Signed byte in AL times signed byte in BH, result in AX
IMUL AX AX times AX, result in DX and AX

AAM-BCD Adjust after Multiply

Before we can multiply two ASCII digits, we must first mask the upper 4 bits of each. This
leaves unpacked BCD (one BCD digit per byte) in each byte. After the two unpacked BCD
digits are multiplied, the AAM instruction is used to adjust the product to two unpacked BCD
digits In AX. AAM works only after the multiplication of two un- packed BCD bytes, and it
works only on an operand in AL. AAM updates PF, SF, and ZF, but AF, CF, and OF are left
undefined.

EXAMPLE:
AL 00000101 unpacked BCD 5
BH 00001001 unpacked BCD 9
MUL BH AL x BH; result in AX
AX = 00000000 00101101 = 002DH
AAM AX = 00000100 00000101 = 0405H,
Which is unpacked BCD for 45.
If ASCII codes for the result are desired, use next instruction
OR AX, 3030H Put 3 in upper nibble of each byte.

1.8 Division Instructions

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 This instruction is used to divide an unsigned word by a byte or to divide an unsigned
double word (32 bits) by a word.
When a word is divided by a byte, the word must be in the AX register. The divisor can
be in a register or a memory location. After the division, AL will contain an 8-bit result
(quotient), and AH will contain an 8-bit remainder.
If an attempt is made to divide by 0 or if the quotient is too large to fit in AL (greater than
FFH), the 8086 will automatically do a type 0 interrupt.

EXAMPLES:
DIV BL Divide word in AX by byte in BL. Quotient in AL, remainder in AH
DIV CX Divide double word in DX and AX by word in CX.
Quotient in AX, remainder in DX.
DIV SCALE [BX] AX/(byte at effective address SCALE[BX]), if SCALE[BX] is of
Type byte or (DX and AX)/(word at effective address SCALE
[BX]) if SCALE[BX] is of type word
DIV BH AX = 37D7H = 14,295 decimal BH = 97H = 151 decimal
AX/BH, AL = quotient = 5EH = 94 decimal
AH = remainder = 65H = 101 decimal

IDIV-Divide by Signed Byte or Word-IDIV Source

This instruction is used to divide a signed word by a signed byte, or to divide a signed double
word (32 bits) by a signed word. When dividing a signed word by a signed byte, the word must
be in the AX register. The divisor can be in an 8-bit register or a memory location. After the
division, AL will contain the signed result (quotient), and AH will contain the signed remainder.
The sign of the remainder will be the same as the sign of the dividend.
The 8086 Convert Word to Double word instruction, CWD, will copy the sign bit of AX to all the
bits of DX. EXAMPLES

IDIV BL Signed word in AX/signed byte in BL

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 IDIV BP Signed double word in. DX and AX/signed word in BP
IDIV BYTE PTR [BX] AX/byte at offset [BX] in DS
MOV AL, DIVIDEND Position byte dividend
CBW Extend sign of AL into AH
IDIV DMSOR Divide by byte divisor
AAD -BCD-to-Binary Convert before Division
AAD converts two unpacked BCD digits in AH and AL to the equivalent binary number
in AL. This adjustment must be made before dividing the two unpacked BCD digits in AX by an
unpacked BCD byte. After the division, AL will contain the unpacked BCD quotient and AH will
contain the unpacked BCD remainder. PF, SF, and ZF are updated. AF, CF, and OF are
undefined after AAD
EXAMPLE:
AX = 0607H unpacked BCD for 67 decimal CH = 09H, now
Adjust to binary
AAD Result: AX = 0043 = 43H = 67 decimal
DIV CH Divide AX by unpacked BCD in CH
Quotient: AL = 07 unpacked BCD Remainder:
AH = 04 unpacked BCD Flags undefined after DIV
NOTE: If an attempt is made to divide by 0, the 8086 will do a type 0 interrupt.

CBW-Convert Signed Byte to Signed Word

This instruction copies the sign of a byte in AL to all the bits in AH. AH is then said to be the
sign extension of AL. The CBW operation must be done before a signed byte in AL can be
divided by another signed byte with the IDIV instruction. CBW affects no flags.

EXAMPLE:
AX = 00000000 10011011 155 decimal
CBW Convert signed byte in AL to signed word in AX
Result: AX = 11111111 10011011 155 decimal
For further examples of the use of CBW, see the IDIV instruction description.
CWD-Convert Signed Word to Signed Double word

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CWD copies the sign bit of a word in AX to all the bits of the DX register. In other words it
extends the sign of AX into all of DX. The CWD operation must be done before a signed word
in AX can be divided by another signed word with the IDIV instruction. CWD affects no flags.
EXAMPLE:
DX = 00000000 00000000
AX = 11110000 11000111 3897 decimal
CWD Convert signed word in AX to signed double word in DX:AX
Result DX = 11111111 11111111

AX = 11110000 11000111 3897 decimal

1.9 Bit Manipulation Instructions

Logical Instructions
NOT-Invert Each Bit of Operand-NOT Destination
The NOT instruction inverts each bit (forms the I's complement) of the byte or word at
the specified destination. The destination can be a register or a memory location specified by
any one of the 24 addressing modes. No flags are affected by the NOT Instruction.

EXAMPLES:
NOT BX Complement contents of BX register
NOT BYTE PTR [BX] Complement memory byte at offset IBXI in data segment

AND-AND Corresponding Bits of Two Operands--AND Destination, Source

This instruction ANDs each bit in a source byte or word with the same number bit in a
destination byte or word. The result is put in the specified destination. The contents of the
specified source will not be changed. The result for each bit position will follow the truth table
for a two-input AND gate. In other words, a bit in the specified destination will be a 1 only if that
bit is a 1 in both the source and the destination operands. Therefore, a bit can be masked
(reset) by ANDing it with 0.

EXAMPLES:
AND CX, [SI] AND word in DS at offset [SI] with word in CX register

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 Result in CX register
AND BH, CL AND byte in CL with byte in BH Result in BH
AND BX, 00FFH AND word in BX with immediate 00FFH.
Masks upper byte, leaves lower byte unchanged

BX = 10110011 01011110
AND BX, 00FFH Mask out upper 8 bits of BX
Result: BX = 00000000 01011110 CF, OF, PF, SF, ZF = 0

OR Destination, Source

This instruction ORs each bit in a source byte or word with the corresponding bit in a
destination byte or word. The result is put in the specified destination. The contents of the
specified source will not be changed. The result for each bit will follow the truth table for a two-
input OR gate
OR AH, CL CL ORed with AH, result in AH. CL not changed
OR BP, SI SI ORed with BP, result in BP. SI not changed
OR SI, BP BP ORed with SI, result in SI. BP not changed
OR BL, 80H BL ORed with immediate 80H. Set MSB of BL to a 1
OR CX, TABLE [BX][SI] CX ORed with word from effective address
TABLE [BX][SI] in data segment.
OR CX, 0FF00H CX = 00111101 10100101 ,OR CX with immediate
FF00H, Result in CX = 11111111 10100101
CF=0,OF=0,PF= 1,SF= 1,ZF=0.

1.10 Shift Instructions and Rotate instruction

SAL/SHL-Shift Operand Bits Left, Put Zero in LSB(s)-
SAL/SHL Destination, Count

EXAMPLES:

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 SAL BX, 1 Shift word in BX1bit position left, 0 in LSB

MOV CL, 02H Load desired number of shifts in CL

SAL BP, CL Shift word in BP left (CL) bit positions, 0's in 2 LSBs

Rotate Instructions

ROL-Rotate All Bits of Operand Left, MSB to LSB-ROL Destination, Count this
instruction rotates all the bits in a specified word or byte to the left some number of bit
positions. The operation can be thought of as circular, because the data bit rotated out
of the MSB is circled back into the LSB. The data bit rotated out of the MSB is also
copied to CF during ROL. In the case of multiple bit rotates, CF will contain a copy of
the bit most recently moved out of the MSB. See the following diagram

The destination operand can be in a register or in a memory location specified by any one of
the addressing modes. If we want to rotate the operand one bit position, we can specify this by
putting a 1 in the count position

1.11 String Instructions

This instruction copies a byte or a word from a location in the data segment to a location in the
extra segment. The offset of the source byte or word in the data segment must be in the SI
register. The offset of the destination in the extra segment must be contained in the DI register.
For multiple-byte or multiple-word moves, the number of elements to be moved is put in the CX
register so that it can function as a counter.
The rest of instruction will be discussed in the class with teachers

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