Input-Output Organization 1

INPUT-OUTPUT ORGANIZATION

• Peripheral Devices

• Input-Output Interface

• Asynchronous Data Transfer

• Modes of Transfer

• Priority Interrupt

• Direct Memory Access

• Input-Output Processor

• Serial Communication

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Input-Output Organization 2

 I/O: Input- Output

 I/O provides and efficient mode of communication

between the central system and the outside
environment.

 Key Board: allows a person to enter alphanumeric

information directly . Every time a key is depressed,
the terminal sends a binary coded character to the
computer.
 To use a computer efficiently, a large amount of
programs and data must be prepared in advance and
transmitted into a storage medium such as magnetic
tapes and disks. (K/B very slow)

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Input-Output Organization 3

• Input or output devices attached to the computers are

also called peripherals.

• Peripherals are electromechanical and electromagnetic

devices of some complexity.

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Input-Output Organization 4 Peripheral Devices

PERIPHERAL DEVICES

Input Devices Output Devices

• Keyboard • Card Puncher
- Card Reader • CRT
- Bar code reader • Printer (Impact, Ink Jet,
- Digitizer Laser, Dot Matrix)
• Plotter
• Magnetic Input Devices • Analog output device
- Magnetic Stripe Reader
• Screen Input Devices
- Touch Screen
- Light Pen
- Mouse
• Analog Input Devices

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Input-Output Organization 5 Input/Output Interfaces

INPUT/OUTPUT INTERFACES

I/O interface provides a method for transferring information between

internal storage and external I/O devices.

Peripherals connected to a computer need special communication link

for interfacing them with the CPU.

The purpose of the communication link is to resolve the differences that

exist between the central computer and each peripheral.

-Peripherals - Electromechanical and electromagnetic Devices

CPU or Memory - Electronic Device
(A conversion of signal values may be required)

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Input-Output Organization 6

• - Data Transfer Rate

• Peripherals - Usually slower
• CPU or Memory - Usually faster than peripherals
• (Some kinds of Synchronization mechanism may be needed)

• -Data codes and formats in peripheral differ from the word format in the
CPU and memory

• - Operating Modes
• Peripherals - Autonomous, Asynchronous
• CPU or Memory - Synchronous

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Input-Output Organization 7

• To resolve these differences, computer systems included

special hardware components between the CPU and peripherals
to supervise and synchronize all input and output transfers.

• These components are called interface units because they

interface between the processor bus and the peripheral device.

• In addition, each device may have its own controller that

supervises the operations of the particular mechanism in the
peripheral.

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Input-Output Organization 8 Input/Output Interfaces

I/O BUS AND INTERFACE MODULES

I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal

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Input-Output Organization 9

• Each interface decodes the address bus and control received

from the I/O bus, interprets them for the peripheral, and
provides signal for the peripheral controller.

• It also synchronizes the data flow and supervises the transfer

between peripheral and processor.

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Input-Output Organization 10

• The I/O bus from the processor is attached to all peripherals

interfaces.
• To communicate with a particular device, the processor places
a device address on the address lines.
• Each interface attached to the I/O bus contains an address
decoder that monitors the address lines.
• When the interface detects its own address, it activates the path
between the bus lines and the device that it controls.
• All peripherals whose address does not correspond to the
address in the bus are disabled by their interface.
• The processor provides a function code(I/O command) once
address of the I/O device is selected.
• There are four types of command- classified as Control, status,
data output and data input.

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Input-Output Organization 11

• Control command: A control command is issues to activate the

peripherals and to inform it what to do.
• Ex: magnetic tape- rewind, move forward etc.
• Status: A status command is used to test various status
conditions in the interface and the peripherals.
• Ex: error status of bits transmitted.
• Output data: A data output command causes the interface to
respond by transferring data from the bus to peripheral devices.
• Input data : In this case the interface receives and item of data
from the peripheral .

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Input-Output Organization 12 Input/Output Interfaces

I/O BUS AND MEMORY BUS

MEMORY BUS is for information transfers between CPU and the Memory.

There are three ways that computer buses can be used to communicate with
memory and I/O.

1. Some computer systems use two separate buses, one to communicate with
memory and the other with I/O interfaces

1. Use one common bus but separate control lines for each.

2. Use one common bus with common control lines.

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Input-Output Organization 13 Input/Output Interfaces

I/O BUS AND MEMORY BUS

IOP: I/O Processor

In the first method, the computer has independent sets of
data, address, and control buses, One for accessing memory
and the other for I/O.
This is done in computers that provide a separate I/O
Processor (IOP) in addition to the CPU.

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Input-Output Organization 14 Input/Output Interfaces

ISOLATED vs MEMORY MAPPED I/O

Isolated I/O
- Separate I/O read/write control lines in addition to memory read/write
control lines
- Separate (isolated) memory and I/O address spaces
- Distinct input and output instructions

Memory-mapped I/O
- A single set of read/write control lines
(no distinction between memory and I/O transfer)
- Memory and I/O addresses share the common address space
-> reduces memory address range available
- No specific input or output instruction
-> The same memory reference instructions can
be used for I/O transfers
- Considerable flexibility in handling I/O operations

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Input-Output Organization 15 Input/Output Interfaces

I/O INTERFACE
Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register

CPU Chip select CS

I/O
Register select RS1 Control Control Device
Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register

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Input-Output Organization 16

• It consists of two data registers called ports, a control

register, a status register, bus buffers, and timing and
control circuits.
• The interface communicates with the CPU through the
data bus.
• The chip select and register select inputs determine the
address assigned to the interface.
• The I/O read and write are two control lines that specify an
input or output respectively.
• The four registers communicate directly with the I/O
device attached to the interface.

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Input-Output Organization 17

• The I/O data to and from the device can be

transferred into either port A or port B.
• A command is passed to the I/O device by sending a
word to the appropriate interface). Register (Control
register).
• Status information is received from the status
register, and data are transferred to and from ports A
and B registers.
• Thus the transfer of data, control and status
information is always via the common data
bus.(Interface register role)

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Input-Output Organization 18

CPU initializes(loads) each port by transferring a byte to the

Control Register
-> Allows CPU can define the mode of operation of each
port
-> Programmable Port: By changing the bits in the control
register, it is possible to change the interface
characteristics.

The bits in the status register are used for status conditions
and for recording errors that may occur during the data
transfer.

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Input-Output Organization 19 Asynchronous Data Transfer
ASYNCHRONOUS DATA TRANSFER

Synchronous - All devices derive the timing

information from common clock line
Asynchronous - No common clock
Asynchronous data transfer between two independent units requires that
control signals be transmitted between the communicating units to indicate
the time at which data is being transmitted.
Two Asynchronous Data Transfer Methods

Strobe pulse
- A strobe pulse is supplied by one unit to indicate the other unit when
the transfer has to occur
Handshaking
- A control signal is accompanied with each data being transmitted to
indicate the presence of data
-The receiving unit responds with another control
signal to acknowledge receipt of the data
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Input-Output Organization 20 Asynchronous Data Transfer

STROBE CONTROL
* Employs a single control line to time each transfer
* The strobe may be activated by either the source or the destination unit

Source-Initiated Strobe Destination-Initiated Strobe

for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe

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Input-Output Organization 21 Asynchronous Data Transfer

HANDSHAKING

Strobe Methods

Source-Initiated

The source unit that initiates the transfer has no way of knowing
whether the destination unit has actually received data

Destination-Initiated

The destination unit that initiates the transfer no way of knowing

whether the source has actually placed the data on the bus

To solve this problem, the HANDSHAKE method introduces a second control

signal to provide a Reply to the unit that initiates the transfer

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Input-Output Organization 22 Asynchronous Data Transfer

SOURCE-INITIATED TRANSFER USING HANDSHAKE

Data bus
Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus
Timing Diagram

Data valid

Data accepted

Sequence of Events Source unit Destination unit

Place data on bus.
Enable data valid.
Accept data from bus.
Enable data accepted
Disable data valid.
Invalidate data on bus.
Disable data accepted.
Ready to accept data
(initial state).
* Allows arbitrary delays from one state to the next
* Permits each unit to respond at its own data transfer rate
* The rate of transfer is determined by the slower unit

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Input-Output Organization 23 Asynchronous Data Transfer

DESTINATION-INITIATED TRANSFER USING HANDSHAKE

Data bus
Block Diagram Source Data valid Destination
unit Ready for data unit

Timing Diagram Ready for data

Data valid

Valid data
Data bus

Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

* Handshaking provides a high degree of flexibility and reliability because the

successful completion of a data transfer relies on active participation by both units
* If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism
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Input-Output Organization 24 Asynchronous Data Transfer

ASYNCHRONOUS SERIAL TRANSFER

Asynchronous serial transfer
Four Different Types of Transfer Synchronous serial transfer
Asynchronous parallel transfer
Synchronous parallel transfer
Asynchronous Serial Transfer
- Employs special bits which are inserted at both
ends of the character code
- Each character consists of three parts; Start bit; Data bits; Stop bits.

1 1 0 0 0 1 0 1
Start Character bits Stop
bit bits
(1 bit) (at least 1 bit)

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Input-Output Organization 25

A character can be detected by the receiver from the knowledge of 4 rules;

- When data are not being sent, the line is kept in the 1-state (idle state)
-The initiation of a character transmission is detected by a Start Bit ,
-which is always a 0.
- The character bits always follow the Start Bit
- After the last character , a Stop Bit is detected when
the line returns to the 1-state for at least 1 bit time

The receiver knows in advance the transfer rate of the bits and the number of
information bits to expect

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Input-Output Organization 26 Asynchronous Data Transfer
UNIVERSAL ASYNCHRONOUS RECEIVER-TRANSMITTER
- UART -
A typical asynchronous communication interface available as an IC
Transmit
Bidirectional Transmitter Shift data
data bus Bus register register
buffers

Control Transmitter Transmitter

clock

Internal Bus
register control
and clock
Chip select CS
Register select Status Receiver Receiver CS RS Oper. Register selected
RS Timing clock
register control 0 x x None
I/O read and and clock 1 0 WR Transmitter register
RD Control 1 1 WR Control register
I/O write Receive 1 0 RD Receiver register
WR Receiver Shift data
1 1 RD Status register
register register

Transmitter Register
- Accepts a data byte(from CPU) through the data bus
- Transferred to a shift register for serial transmission
Receiver
- Receives serial information into another shift register
- Complete data byte is sent to the receiver register
Status Register Bits
- Used for I/O flags and for recording errors
Control Register Bits
- Define baud rate, no. of bits in each character, whether
to generate and check parity, and no. of stop bits

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Input-Output Organization 27

• Modes of Transfer
– Data transfer to and from peripherals may be handled
in a variety of modes.
1) Programmed I/O :

2) Interrupt-initiated I/O :

3) Direct Memory Access (DMA)

4) I/O Processor (IOP) :

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Input-Output Organization 28

• Programmed I/O:
• Programmed I/O operations are the result of I/O instructions
written in the computer program.
• Each data item transfer is initiated by an instruction in the
program.
• Drawback: Transferring data under program control
requires monitoring of the peripherals by the CPU (Waste of
time)
• Interrupt initiate I/O:
• When the interface determines that the device is ready for
data transfer, it generates an interrupt request to the
computer. Then , the CPU momentarily stops the task its is
processing, branches to a service program to process the I/O
transfer, and then returns to the task it was originally
performing.
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Input-Output Organization 29

• DMA: Direct Memory Access

• The transfer of data under PIO is between CPU and
peripherals.
• In DMA, the interface transfers data into and out of the
memory unit through memory bus.
• The CPU supplies the interface with the starting address
and the number of words needed to be transferred and
then proceeds to execute other tasks.
• IOP:
• Many computers combine the interface logic with the
requirements for DMA into one unit and call it an I/O
processor.
• The IOP can handle many peripherals through a DMA and
interrupt facility.

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Input-Output Organization 30

Program interrupted I/O- Data transfer

from I/O device to CPU

Data bus Interface I/O bus

Address bus Data register

Data valid I/O

CPU
I/O read device

Status
I/O write F
register Data accepted

F = Flag bit

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Input-Output Organization 31

Read status register

Check flag bit

= 0
Flag

= 1

Read data register

Transfer data to memory

Operation no
complete ?

yes

Continue
with
program

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Input-Output Organization 32

• Interrupt –Initiated I/O

• The CPU responds to the interrupt signal by storing the
return address from the PC into a memory stack and then
control braches to a service routine that processes the
required I/O transfer.
• Vectored interrupt:
• The source that interrupts supplies the branch information
to the computer. This information is called the interrupt
vector.
• Non vectored interrupt:
• The branch address is assigned to a fixed location in
memory.
•

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Input-Output Organization 33

Direct Memory Access(DMA)

• The transfer of data between a fast storage device such as
magnetic disk and memory is often limited by the speed of
the CPU.
• Removing the CPU from the path and letting the peripheral
device manage the memory buses directly would improve the
speed of transfer.
• This transfer technique is called direct memory access
(DMA).
• A DMA controller takes over the buses to manage the
transfer directly between the I/O device and memory.

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Input-Output Organization 34

• The CPU may be place in an idle state in a variety of ways.

One common method extensively used in microprocessor is
to disable the buses through special control signals.

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Input-Output Organization 35

• The bus request (BR) input is used by the DMA controller

to request the CPU to relinquish control of the buses.
• When this input is active, the CPU terminates the execution
of the current instruction and places the address bus, the
data bus, and read and write lines into a high impedance
state.
• The CPU activates the bus grant (BG) output to inform the
external DMA that the buses are in the high impedance
state.
• The DMA can now take the control of the buses to conduct
memory transfers without processor intervention.
• When the DMA terminates the transfer , it disable the bus
request line.
• The CPU returns to the normal operation.

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Input-Output Organization 36

Interrupt
BG Random access
CPU
memory (RAM)
BR

RD WR Address Data RD WR Address Data

Read control
Write control
Data bus
Address bus

Address
select

RD WR Address Data
DMA acknowledge
DS
RS Direct memory I/O
access (DAM) Peripheral
BR controller device
DMA request
BG
Interrupt

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Input-Output Organization 37

Burst Transfer
• When the DMA takes control of the bus system, it
communicates directly with the memory.
• DMA burst transfer: a block sequence consisting of a
number of memory words is transferred in a continuous
burst.
• This mode of transfer is needed for fast devices such as
magnetic disks, where data transmission cannot be stopped
or slowed down until an entire block is transferred.
• Cycle stealing:
• It allows the DMA controller to transfer one data word at a
time(one memory cycle), after which it must return control
of the buses to the CPU.

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Input-Output Organization 38

DMA Initialization
• 1.The starting address of the memory block where data are
available (for read) or where data are to be stored (write).
• 2.The word count, which is the number of words in the
memory block.
• 3. Control to specify the mode of transfer such as read or
write.
• 4.A control to start the DMA transfer.
• The starting address is stored in the address register. The
word count is stored in the word count register, and the
control information in the control register.
• Once the DMA is initialized , the CPU stops
communicating with the DMA unless it receives an
interrupt signal or if it wants to check how many words
have been transferred.

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Input-Output Organization 39

VAD
» One stage of the daisy-chain priority
INTACK
PI
arrangement
Priority in : Fig. 11-13
Enable
Vector address

INT Priority out

RF PO
Interrupt S Q
request
from device PI RF PO Enable
R
 0 0 0 0
Delay  0 1 0 0
Open-collector  1 0 1 0
inverter Interrupt request to CPU  1 1 1 1

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Input-Output Organization 40

– Parallel Priority
Interrupt

» Priority Encoder를 이용한 register

VAD
to CPU
disk 0
Parallel Priority : Fig. 11-14 I0
y
x
• Interrupt Enable F/F (IEN) : set or cleared Printer 1
I1
Priority 0
by the program encoder
0
• Interrupt Status F/F (IST) : set or cleared Reade
r
2
I2
0
by the encoder output
0
Keyboard 3
I3
» Priority Encoder Truth 0
0

Table : Tab. 11-2 Enable

IEN IST
• I0 가 제일 높은 우선 순위
– Interrupt Cycle
0
» At the end of each Interrupt
to CPU
instruction
SP  SP  1
cycle, CPU 1

: Decrement stack point

checks
Branch to ISR
IEN
M [ SP ]  PC and IST
: Push PC into stack
2 INTACK
from CPU
INTACK  1 : Enable INTACK
» if both
PC  VAD
IEN and IST equal
: Transfer VAD to PC
3

to “1”
IEN  0 : Disable further interrupts Mask
register

Go to Fetch next instruction

» CPU goes to an Instruction
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Input-Output Organization 41

– Software Routines
Address 현재 main program의 749 번지를 실행
» CPU가
도중에 KBD interrupt 발생 I/O service programs
Memory
» KBD0 service
JMP DISKprogram의DISK
255 번지를 실행 도중에
Program to service
magnetic disk
DISK
1 JMP PDR 발생
interrupt
2 JMP RDR PTR Program to service
line printer
3 JMP KBD
KBD Int. Here
749 RDR Program to service
character reader
750 Main program
KBD Program to service
Keyboard
Stack 256
256
750 DISK Int. Here
255

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Input-Output Organization 42

» Initial Operation of ISR

• 1) Clear lower-level mask register bit (낮은 순위 Int. 발생 방지)
• 2) Clear interrupt status bit IST
• 3) Save contents of processor registers
• 4) Set interrupt enable bit IEN (높은 순위 Int. 발생을 원할 때만)
Fig. 11-14
• 5) Proceed with service routine

» Final Operation of ISR

• 1) Clear interrupt enable bit IEN (아래 2, 3, 4, 5 실행 중 Int. 발생 방지)
• 2) Restore contents of processor registers
• 3) Clear the bit in the interrupt register belonging to the source that has been
serviced
• 4) Set lower-level priority bits in the mask register (낮은 순위 Int. 발생 허용)
• 5) Restore return address into PC and set IEN

• 11-6 Direct Memory Access (DMA)

BR BR
DBUS Address bus
High-impedance
Bus request ABUS Data bus
DMA (disable)
– DMA Controller
CPU
RD Read
when BG is
enabled
BG BG
» DMA controller takes over the buses to manage
Bus grant WR Write

the transfer directly between the I/O device and

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Input-Output Organization 43

– Transfer Modes
» 1) Burst transfer : Block 단위 전송
» 2) Cycle stealing transfer : Byte 단위 전송
– DMA Controller ( Intel 8237 DMAC )Address
: Fig.bus11-17
» DMA Initialization Process
• 1) Set Address register : Data bus Address bus
Data bus buffers
– memory address for read/write buffers

• 2) Set Word count register :

– the number of words to transfer

Internal bus
• 3) Set transfer mode : DMA select CS Address register

– read/write, Register select RS

– burst/cycle stealing, Read RD Word count register

– I/O to I/O, Write WR

Control
– I/O to Memory, Bus request BR logic Control register
– Memory to Memory Bus grant BG
– Memory search Interrupt Interrupt
DMA request

– I/O search DMA Acknowledge

to I/O device

• 4) DMA transfer start : next section

• 5) EOT (End of Transfer) :
– Interrupt 발생
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Input-Output Organization 44

– DMA Transfer (I/O to Memory)

» 1) I/O Device sends a DMA request Interrupt
Random access
» 2) DMAC activates the BR line BG
BR
CPU
memory (RAM)

» 3) CPU responds with BG line RD WR Address Data RD WR Address Data

Read control
» 4) DMAC sends a DMA acknowledge Write control
Data bus
to the I/O device Address bus

» 5) I/O device puts a word in the data

Address

bus (for memory write) select

» 6) DMAC write a data to the address RD WR Address Data

DMA acknowledge
DS

specified by Address register RS Direct memory

access (DAM)
I/O
Peripheral
BR controller device
DMA request
» 7) Decrement Word count register BG
Interrupt

» 8) Word count register = 0 이면

EOT interrupt 발생하여 CPU에 알림
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Input-Output Organization 45

• 11-7 Input-Output Processor (IOP)

– IOP : Fig. 11-19
» Communicate directly with all I/O devices
» Fetch and execute its own instruction
• IOP instructions are specifically
Central Processing designed to facilitate I/O transfer
• DMAC must be setunitup(CPU)
entirely by the CPU
Memory bus

Peripheral devices
»Memory
Designed
unit
to handle the details
PD PD PD
ofPDI/O
processing
Input-output
processor (IOP) I/O bus

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Input-Output Organization 46

– CPU - IOP Communication : Fig. 11-20

» Memory units acts as a message center :
CPU operations IOP operations

Information 전달 영역
Send instruction
Transfer status word
to test IOP path
• each processor leaves information for the other
to memory location

Message Center
If status OK. , send
start I/O instruction Access memory for
to IOP IOP program

Conduct I/O transfer IOP Program

CPU continues with
using DMA ; prepare
another program
CPU Program status report

I/O transfer completed

interrupt CPU

Request IOP status

Transfer status word

to memory location

Check status word

for correct transfer

Continue

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Input-Output Organization 47

– IBM 370 I/O Channel

» Channel = I/O Processor in IBM 370 computer
» Three types of channel
• 1) Multiplexer channel : slow-medium speed device, operating with a number of
I/O devices simultaneously
• 2) Selector channel : high-speed device, one I/O operation at a time
• 3) Block-Multiplexer channel : 1) + 2)

» I/O instruction format : Fig. 11-21(a)

Operation Channel Device
• Operation code : 8 개 code address address

– Start I/O, Start I/O fast release (less CPU time), (a) I/O instruction format
Test I/O, Clear I/O, Halt I/O, Halt device,
Test channel, Store channel ID
Key Address Status Count

» Channel Status Word : Fig. 11-21(b) (b) Channel status word format
• Always stored in Address 64 in memory
• Key : Protection used to prevent unauthorized Command
Data address Flags Count
access code

• Address : Last channel command word address (c) Channel command word format
used by channel
• Count : 0 (if successful transfer)
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Input-Output Organization 48

» Channel Status Word : Fig. 11-21(c)

• Always stored in Address 72 in memory
• Command Code
– Write : transfer data from memory to I/O device
– Read : transfer data I/O device to memory
– Read backwards : read magnetic tape with tape moving backward
– Control : rewinding of tape, positioning a disk-access mechanism (HDD head
control)
– Sense : inform the channel status word to the address 64 (Status Read)
– Transfer in channel : channel jump command (Channel change)
• Flags
– 100000 : data chaining (same record) Memory Separate record Tape
– 010000 : command chaining (same device) same device
– 000000 : separate record,and End of I/O3000
operation 40
40
Command of
» Example Address Flags Count
a channel program : Tab. 11-3
Write tape 4000 100000 60 4000 60

Write tape 6000 010000 20 +

6000
Write tape 3000 000000 40 20

80
Same record
same device

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Input-Output Organization 49

» Location of information in the IBM 370 : Fig. 11-22

Memory unit
 Address 72 에 I/O channel program의
시작 Address (xxxx) 를 미리 설정 Fig. 11-21(b)  Channel status word 64

 CPU에 의해 Start I/O 명령 실행

 I/O channel program이 실행  Channel address word 72 xxxx

 실행 결과를 Address 64에 저장 xxxx

Channel command word 1

Fig. 11-21(a)  Channel command word 2 I/O channel

program
Channel command word 3

Fig. 11-21(c)  Start I/O instruction CPU

program

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Input-Output Organization 50

– Intel 8089 IOP : Fig. 11-23  Location of Information : Fig. 11-

24
Control block Parameter block Task block

8086
CPU Busy CCW TB address
  8089
PB address Memory address
IOP
attention
Channel
Interrupt

program
Select

Bus System
Controller bus
Memory unit Byte count

Device address

8089 Local bus Track and sector

IOP

Status
Interface Interface

Input device Output device  Channel Command Word (CCW) : message

center
» Start command
 CPU enables channel attention » Suspend command
» Resume command
 Select one of two channels of 8089 » Halt command
 8089 gets attention of the CPU by
sending an interrupt request

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Input-Output Organization 51
“Data Communication” 교과 참고

• 11-8 Serial Communication

– Difference between I/O Processor and Data Communication
Processor
» I/O Processor
• communicate with peripherals through a common I/O bus (data, address,
control bus)

» Data Communication Processor

• communicate with each terminal through a single pair of wires
– Modem ( = Data Sets, Acoustic Couplers )
» Convert digital signals into audio tones to be
transmitted over telephone lines
» Various modulation schemes are used (FM,
AM, PCM)
– Block transfer
» An entire block of characters is transmitted
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Input-Output Organization 52

– Data Link
» The communication lines, modems, and other
equipment used in the transmission of
information between two or more stations
– Data Link Protocol
» 1) Character-Oriented Protocol
SYN SYN SOH Header STX Text ETX BCC
» 2) Bit-Oriented Protocol
– Character-Oriented Protocol
» Message format for Character-Oriented
Protocol : Fig. 11-25

• TEXT : 전송할 내용
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– Data Transparency
» Character-Oriented Protocol에서 Binary
Information을 전송하면, 이를 Control
Character로 오인하여 문제가 발생
» 따라서 Character-Oriented Protocol에서 Data
Transparency를 해결하기 위해서 DLE (Data Link
Escape) Character를 사용
– DLE
» Inserting a DLE character (bit pattern =
00010000) before each control character
• Exam) DLE ETX DLE SYN
Flag Address Control Information Frame check Flag
» 그러나
01111110 DLE
8 bits character
8 bits is inefficient
any number of bits 16 and
bits 01111110
somewhat complicated to implement
» 따라서 Bit-Oriented Protocol을 사용
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» Zero Insertion
• Prevent a flag from occurring in the middle of a data frame
• Zero (0) is inserted by transmitting station after any succession of five
continuous 1’s
– Example of zero insertion
1 2 3
: 01111110 4
(data)5 011111010
6 7 8
Information transfer : 0 N S P/F N r

• Receiver always removes a 0 that follows a succession of five 1’s

» Control field format : Fig. 11-27

Supervisory : 1 0 Code P/F Nr

Unumbered : 1 1 Code P/F Code

NS Send count P/F Poll/final

Nr Receive count Code Binary code

Security를 위하여 임의로 정의하여 사용함

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» Control Fields
• Ns : send frame count
• Nr : error free 한 receive frame count
• P/F :
– P = 1 : primary station is finished and ready for the secondary station
to respond
P = 0 : each frame sent to the secondary station from the primary
station
– F = 1 : secondary station sends the last frame
F = 0 : secondary station responds with a number of frame (when
primary station is finished)
• Code : type of command/response

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