ALU and Datapath

Processor structure and function: processor

organization, registers organization, ALU design,
barrel shifter, and building a simple datapath.
Control unit: Control unit function, Micro-
operations, hardwired and microprogrammed
control unit
 Generation
• First Generation: Vacuum Tubes
• Second Generation Transistors
• Third Generation Integrated Circuits
• Fourth Generation Microprocessors
• Fifth Generation Artificial Intelligence
 RISC and CISC
RISC stands for 'Reduced Instruction Set
Computer Whereas, CISC stands for
Complex Instruction Set Computer.

The RISC processors have a smaller set of

instructions with few addressing nodes.

The CISC processors have a larger set of

instructions with many addressing nodes
 Comparison

The most common RISC

Examples of CISC processors are the
microprocessors are Alpha, ARC,
System/360, VAX, PDP-11, Motorola
ARM, AVR, MIPS, PA-RISC, PIC,
68000 family, AMD, and Intel x86 CPUs
Power Architecture, and SPARC
 CPU Function
• CPU must:
– Fetch instructions
– Interpret/decode instructions
– Fetch data
– Process data
– Write data
 Registers
• CPU must have some working space
(temporary storage) - registers
• Number and function vary between
processor designs - one of the major
design decisions
• Top level of memory hierarchy
 User Visible Registers
• General Purpose
• Data
• Address
• Condition Codes
 General Purpose Registers (1)
• May be true general purpose
• May be restricted
• May be used for data or addressing
• Data: accumulator (AC)
• Addressing: segment (cf. virtual memory),
stack (points to top of stack, cf. implicit
addressing)
 General Purpose Registers (2)
• Make them general purpose
– Increased flexibility and programmer options
– Increased instruction size & complexity,
addressing
• Make them specialized
– Smaller (faster) but more instructions
– Less flexibility, addresses implicit in opcode
 How Many GP Registers?
• Between 8 - 32
• Less = more memory references
• More takes up processor Space
 How big?
• Large enough to hold full address
• Large enough to hold full data types
• But often possible to combine two data
registers or two address registers by using
more complex addressing (e.g., page and
offset)
 Condition Code Registers – Flags
• Sets of individual bits, flags
– e.g., result of last operation was zero
• Can be read by programs
– e.g., Jump if zero – simplifies branch taking
• Can not (usually) be set by programs
 Control & Status Registers
• Program Counter (PC)
• Instruction Register (IR)
• Memory Address Register (MAR) –
connects to address bus
• Memory Buffer Register (MBR) – connects
to data bus, feeds other registers
 Program Status Word
• A set of bits
• Condition Codes:
– Sign (of last result)
– Zero (last result)
– Carry (multiword arithmetic)
– Equal (two latest results)
– Overflow
• Interrupts enabled/disabled
• Supervisor/user mode
 ALU

• An arithmetic logic unit (ALU)

– Performs arithmetic and logic
operations
– A fundamental building block of
the Central Processing Unit (CPU)
of a computer
– Even the simplest microprocessors
contain one for purposes such as
maintaining timers
– A combinational logic circuit
 Design of ALU
The ALU will take in two 32-bit values, and 2 control lines. Depending on the value of
the control lines, the output will be the addition, subtraction, bitwise AND or bitwise OR
of the inputs. Schematically, here is what is required to build:
 Design of ALU

Output
nput A Input B (A ⊕ B)
0 0 0
0 1 1
1 0 1
1 1 0
Design of ALU
Design of ALU
Recall: The Instruction Processing “Cycle”

q FETCH
q DECODE
q EVALUATE ADDRESS
q FETCH OPERANDS
q EXECUTE
q STORE RESULT

20
Instruction Processing Viewed Another Way
n Instructions transform Data (AS) to Data’ (AS’)
n This transformation is done by functional units
q Units that “operate” on data
n These units need to be told what to do to the data

n An instruction processing engine consists of two components

q Datapath: Consists of hardware elements that deal with and
transform data signals
n functional units that operate on data
n hardware structures (e.g., wires, muxes, decoders, tri-state bufs)
that enable the flow of data into the functional units and registers
n storage units that store data (e.g., registers)
q Control logic: Consists of hardware elements that determine
control signals, i.e., signals that specify what the datapath
elements should do to the data
21
Single-cycle vs. Multi-cycle: Control & Data
n Single-cycle machine:
q Control signals are generated in the same clock cycle as the
one during which data signals are operated on
q Everything related to an instruction happens in one clock cycle
(serialized processing)

n Multi-cycle machine:
q Control signals needed in the next cycle can be generated in
the current cycle
q Latency of control processing can be overlapped with latency
of datapath operation (more parallelism)

22
Review: Performance Analysis
n Execution time of a single instruction
q {CPI} x {clock cycle time} CPI: Cycles Per Instruction

n Execution time of an entire program

q Sum over all instructions [{CPI} x {clock cycle time}]
q {# of instructions} x {Average CPI} x {clock cycle time}

n Single-cycle microarchitecture performance

q CPI = 1
q Clock cycle time = long
n Multi-cycle microarchitecture performance
q CPI = different for each instruction In multi-cycle, we have
n Average CPI à hopefully small two degrees of freedom
q Clock cycle time = short to optimize independently
23
 Datapath
• A datapath is a collection of functional units such
as arithmetic logic units or multipliers that perform data
processing operations, registers, and buses. Along with
the control unit it composes the central processing unit
(CPU). A larger datapath can be made by joining more
than one datapaths using multiplexers.

• A data path is the ALU, the set of registers, and the

CPU's internal bus(es) that allow data to flow between
them.
Single bus datapath
 Components of a Data path
1. Program Counter (PC):
1. The PC holds the address of the instruction that is currently being executed or is next in
line to be executed.
2. Memory Address Register (MAR):
1. The MAR holds the address of the memory location that is to be accessed, either to
fetch an instruction or to fetch/store data.
3. Memory Data Register (MDR):
1. The MDR is used to temporarily hold the data read from or written to the memory.
4. Instruction Register (IR):
1. The IR stores the instruction currently being executed. Instructions fetched from
memory are loaded into the IR.
5. Instruction Decoder and Control Logic:
1. This component decodes the instruction in the IR and generates the necessary control
signals to orchestrate the execution of the instruction by controlling the flow of data and
the operation of other components.
6. General Purpose Registers (R0 to R(n-1)):
These registers hold operands and results of operations. They are general-purpose storage
within the CPU and are accessible at high speeds.
7. Temporary Register (TEMP):
TEMP is used for temporary storage during instruction execution, especially in complex
operations requiring multiple steps.
8. Multiplexer (MUX):
The MUX selects one of several input signals based on a control signal and passes it through
as the output. In this case, it is used to choose between different sources of data for
operations by the ALU.
9. Arithmetic Logic Unit (ALU):
The ALU performs arithmetic and logical operations. It takes inputs from the general-
purpose registers, TEMP register, or directly from the bus and outputs results back to the
bus, which can then be stored back into registers or memory.
10. X and Y Registers:
These are inputs to the ALU, holding the operands for the ALU operations.
11. Single Internal Processor Bus:
This is the central communication pathway that all the other components use to transfer
data among themselves. Data, addresses, and control signals traverse this bus to reach
various parts of the processor.
 Data Flow in the Single Bus System
• When an instruction is executed, the address of the next
instruction is loaded from the PC to the MAR via the bus.
• The MAR accesses this memory location, and the fetched
instruction is placed in the MDR.
• The instruction in the MDR is moved to the IR for decoding.
• The decoded instruction in the IR determines the operation to
be performed, which is executed by the ALU.
• Source data for the ALU may come from the general-purpose
registers, the TEMP register, or other sources, selected via the
MUX.
• The result of the ALU operation can be stored back into one of
the registers or into memory, depending on the instruction
specifics.
 Disadvantage
This single bus architecture simplifies the design
by reducing the number of pathways needed for
communication between components. However,
it can also become a bottleneck, as each data
transfer must occur sequentially, and only one
component can communicate over the bus at a
time. This setup is typical in simpler or older
microprocessors where cost and design
simplicity are critical factors.
Single-Cycle Datapath for
R-Type ALU Instructions
n R-type: 3 register operands

MIPS assembly (e.g., register-register signed addition)

add $s0, $s1, $s2 #$s0=rd, $s1=rs, $s2=rt

Machine Encoding

0 rs rt rd 0 add (32) R-Type

6 bits 5 bits 5 bits 5 bits 5 bits 6 bits

n Semantics
if MEM[PC] == add rd rs rt
GPR[rd] ¬ GPR[rs] + GPR[rt]
PC ¬ PC + 4

31
 (R-Type) ALU Datapath

Add

4
ALU operation
25:21 Read 3
Read register 1
PC address Read
20:16 Read data 1
register 2 Zero
Instruction
Instruction Registers ALU ALU
15:11 Write result
Instruction register
Read
memory data 2
Write
data

RegWrite
1

IF ID EX MEM WB
if MEM[PC] == ADD rd rs rt
GPR[rd] ¬ GPR[rs] + GPR[rt]
Combinational
PC ¬ PC + 4
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
state update logic
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.] 32
I-Type ALU Instructions
n I-type: 2 register operands and 1 immediate

MIPS assembly (e.g., register-immediate signed addition)

addi $s0, $s1, 5 #$s0=rt, $s1=rs

Machine Encoding

addi (0) rs rt immediate I-Type

6 bits 5 bits 5 bits 16 bits

n Semantics
if MEM[PC] == addi rs rt immediate
PC ¬ PC + 4
GPR[rt] ¬ GPR[rs] + sign-extend(immediate)

33
 Datapath for R- and I-Type ALU Insts.

Add

4
3 n
ALU operation
Read
Read 25:21
PC register 1 Mem
address Read
data 1
20:16
Read
Instruction register 2 Zero
Instruction Registers ALU ALU
15:11
Write result Address
Instruction register
Read
memory data 2
Write Data
RegDest data
memo
isItype RegWrite
ALUSrc
Write
data
116
Sign
32
isItype Mem
extend

IF ID EX MEM WB
if MEM[PC] == ADDI rt rs immediate
GPR[rt] ¬ GPR[rs] + sign-extend (immediate)
Combinational
PC ¬ PC + 4 state update logic
**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier. ALL RIGHTS RESERVED.]
 Single-Cycle MIPS Processor
PCSrc1=Jump
Instruction [25– 0] Shift Jump address [31– 0]
left 2
26 28 0 1

PC+4 [31– 28] M M

u u
x x
ALU
Add result 1 0
Add
RegDst Shift PCSrc2=Br Taken
Jump left 2
4 Branch
MemRead
Instruction [31– 26]
Control MemtoReg
ALUOp
MemWrite
ALUSrc
RegWrite

Instruction [25– 21] Read

Read register 1
PC address Read
Instruction [20– 16] data 1
Read
register 2 bcond
Zero
Instruction 0 Registers Read ALU ALU
[31– 0] 0 Read
M Write data 2 result Address 1
Instruction u register M data
u M
memory Instruction [15– 11] x u
1 Write x Data
data x
1 memory 0
Write
data
16 32
Instruction [15– 0] Sign
extend ALU ALU operation
control

Instruction [5– 0]

**Based on original figure from [P&H CO&D, COPYRIGHT 2004 Elsevier.

ALL RIGHTS RESERVED.] JAL, JR, JALR omitted
 What is a barrel shifter?
A barrel shifter is a logic circuit for shifting or
rotating an input by a variable amount. First,
let’s go over what shifting and rotating means:

Shifting: There are two types of shifts: logical

and arithmetic. Remember that in shifts, the bits
that are shifted out of range are simply
discarded.
 What is a barrel shifter?

Arithmetic: The left arithmetic shift is identical to

the left logical shift. However, the right arithmetic
shift is different. For example, if we want to
arithmetic shift the binary data “11001” to the right
by 2 bits, our output would be “11110”. The
difference between an arithmetic and a logical shift
is that in arithmetic shifts, the original positions of
the shifted bits remain the same (highlighted in
bold).
 What is a barrel shifter?

Logical: For example, if we want to logical shift

the binary data “11001” to the right by 2 bits,
our output would be “00110”. The original
positions of the shifted bits are replaced with 0s
(highlighted in bold).
 What is a barrel shifter?

Rotating: For example, if we want to rotate the

binary data “10110” to the right by 3 bit, our
output is “11010”. Unlike shifts, bits that are
pushed out of one end are put back to the
opposite end.
 Control Unit Operation
Control unit generates timing and control
signals for the operations of the
computer. The control unit communicates
with ALU and main memory. It also
controls the transmission between
processor, memory and the various
peripherals. It also instructs the ALU
which operation has to be performed on
data
 Instruction Micro-Operations
• A computer executes a program of
instructions (or instruction cycles)
• Each instruction cycle has a number to
steps or phases:
• Fetch,
• Indirect (if specified),
• Execute,
• Interrupt (if requested)

• These can be seen as micro-operations

– Each step does a modest amount of work
– Atomic operation of CPU
Constituent Elements of its Program Execution
 Types of Micro-operation
• Transfer data between registers

• Transfer data from register to external

• Transfer data from external to register

• Perform arithmetic or logical ops

 Control Signals
u Clock
u One micro-instruction (or set of parallel micro-instructions) per
clock cycle

u Instruction register
u Op-code for current instruction
u Determines which micro-instructions are performed

u Flags
u State of CPU
u Results of previous operations

u From control bus

u Interrupts
u Acknowledgements
 Control Signals - output
• Within CPU
– Cause data movement
– Activate specific functions

• Via control bus

– To memory
– To I/O modules
 Hardware Control Unit
It is implemented with the help of gates, flip flops, decoders etc. in the
hardware. The inputs to control unit are the instruction register, flags, timing
signals etc. This organization can be very complicated if we have to make the
control unit large.
If the design has to be modified or changed, all the combinational circuits
have to be modified which is a very difficult task.
 Microprogrammed Control Unit

It is implemented by using programming

approach. A sequence of micro
operations is carried out by executing a
program consisting of micro-instructions.
In this organization any modifications or
changes can be done by updating the
micro program in the control memory by
the
The programmer
hardwired control unit is designed for the RISC style instruction set. On the
other hand, the microprogrammed control unit was designed for the CISC style
instruction set
 Microprogramming
• The program that creates the ‘control signals’ is called Microprogram. This
microprogram is placed on the processor chip which is fast memory, it is also called
control memory or control store.

• A microprogram has a set of microinstructions, or it is also termed as control word.

Each microinstruction is ‘n’ bit word. Each control signal differs from other control
signal depending on the bit pattern of the control word. Each control
word/microinstruction has a different bit pattern.

• Instruction execution is performed in steps. So, for each step there is a control
word/ microinstruction in the microprogram. A sequence of microinstructions
required to execute a particular instruction is called micro-routine
Microprogrammed Control Unit
OPeration
 Operation
1. In the first step (instruction fetch) the Microinstruction address
generator would fetch the instruction from ‘instruction register’ (IR).
2. In the second step, the microinstruction address generator decodes the
instruction obtained from IR and retrieves the starting address of the micro-
routine required to perform the corresponding operation mentioned in the
instruction. It loads that starting address to microprogram counter.
3. In the third step, the ‘control word’ corresponding to the ‘starting address’ of
‘microprogram counter’ is read and as the execution proceeds, microprogram
address generator will increment the value of microprogram counter to read
the successive control words of the microroutine.
4. In the last microinstruction of a microroutine, there is a bit which we call end
bit. When end bit is set to 1 it denotes successful execution of that
microroutine.
5. After this, the microprogram address generator would return back to Step
1 again to fetch a new instruction. And the cycle goes on.
 Comparison
Pararmeters Hardwired Control Unit Microprogrammed Control Unit
Implementation It is a circuitry approach. This control unit is implemented by
programming

Design RISC style instructions CISC style instructions

Modification Modification is difficult as the Modifications are easy in case of
control unit is hardwired. Modifying microprogrammed control unit as it
it will require the change in will require the in change in the
hardware. code only.

Instructions It works well for simple instructions. It works well for complex
instructions also.
Costing Implementing hardwired structure Implementing microprograms is not
requires a cost. costly.

Control memory No control memory is required Control memory is required

Execution Speed Faster execution Comparatively slow