Module -1 – Introduction and MOS

Transistor
 Introduction to IC
Technology
There is no doubt that our daily lives are significantly affected by electronic engineering technology.
We know revolutionary changes have taken place in a relatively short time and it is also certain that even
more-dramatic advances will be made in the next decade.
Electronics as we know it today is characterized by reliability, low power dissipation, extremely low
weight and volume, and low cost, coupled with an ability to cope easily with a high degree of
sophistication and complexity.
Electronics, and in particular the integrated circuit, has made possible the design of powerful and flexible
processors which provide highly intelligent and adaptable devices for the user.
Integrated circuit memories have provided the essential elements to complement these processors and,
together with a wide range of logic and analog integrated circuitry, they have provided the system
designer with components of considerable capability and extensive application
Micro-
electronics
Evaluation
The invention of the
transistor by William B.
Shockley, Walter H. Brattain
and John Bardeen of Bell
Telephone Laboratories was
followed by the development
of the Integrated Circuit (IC).
The very first IC emerged at
the beginning of 1960 and
since that time there have
already been four
generations of ICs:
SSI (small scale
integration), MSI (medium
scale integration), LSI (large
scale integration), and VLSI
(very large-scale
integration).
Moor’s
Law
Moore's law - prediction made
by American engineer Gordon
Moore in 1965 that the
number of transistors per
silicon chip doubles every
year.
Moore's law - Moore
observed that the number of
transistors on a computer chip
was doubling about every 18–
24 months.
 Basic MOS
Transistors
In particular, let us examine the basic
nMOS enhancement and depletion
mode transistors.
 nMOS Fabrication
even required

1. Processing is carried out on a thin

wafer cut from a single crystal of
silicon of high purity into which the
required p-impurities are introduced
as the crystal is grown.
2. A layer of silicon dioxide (Si02), is
grown all over the surface of the
wafer to protect the surface, act as
a barrier to dopants during
processing, and provide a generally
insulating substrate on to which
other layers may be deposited and
patterned.
3. The surface is now covered with a
photoresist which is deposited onto
the wafer and spun to achieve an
even required thickness.
.
 Continue……
4. The photoresist layer is then
exposed to ultraviolet light through a
mask which defines those regions into
which diffusion is to take place
together with transistor channels.
Assume, for example, that those areas
exposed to ultraviolet radiation are
polymerized (hardened), but that the
areas required for diffusion are
shielded by the mask and remain
unaffected.
5. These areas are subsequently
readily etched away together with the
underlying silicon dioxide so that the
wafer surface is exposed in the
window defined by the mask.
6. The remaining photoresist is
removed and a thin layer of Si02 is
grown over the entire chip surface and
then polysilicon is deposited on top of
this to form the gate structure.
Continue……
7.Further photoresist coating and
masking allows the polysilicon to
be patterned and then the thin
oxide is removed to expose areas
into which n-type impurities are to
be diffused to form the source and
drain as shown.
8.Thick oxide (Si02) is grown
over all again and is then masked
with photoresist and etched to
expose selected areas of the
polysilicon gate and the drain and
source areas where connections
(i.e. contact cuts) are to be made.
9.The whole chip then has metal
(aluminum) deposited over its
surface. This metal layer is then
masked and etched to form the
required interconnection pattern.
 Continue…
It will be seen that the process revolves around the formation or deposition and patterning of three layers,
separated by silicon dioxide insulation. The layers are diffusion within the substrate, polysilicon on oxide
on the substrate, and metal insulated again by oxide.
 There are a number of approaches to CMOS fabrication,
CMOS including the p-well, the n-well, the twin-tub, and the silicon-
on-insulator processes.
Fabrication The p-well process is widely used in practice and the n-well
process is also popular. For the lambda-based rules set out
later, we will assume a p-well process.
P-Well Process
In all other respects-masking, patterning, and diffusion-the
process is similar to nMOS fabrication. In summary, typical
processing steps are:
Mask 1 - defines the areas in which the deep p-well diffusions
are to take place.
Continue….
Mask 2 - defines the thinox regions,
namely those areas where the thick
oxide is to be stripped and thin
oxide grown to accommodate p-
and n-transistors and wires.
Mask 3 - used to pattern the
polysilicon layer which is deposited
after the thin oxide.
Mask 4 - A p-plus mask is now
used (to be in effect “anded" with
Mask 2) to define all areas where
p-diffusion is to take place.
 Mask 5 - This is usually performed using the negative form of
Continue….. the p-plus mask and defines those areas where n-type
diffusion is to take place.
Mask 6 - Contact cuts are now defined.
Mask 7 - The metal layer pattern is defined by this mask.
Mask 8 - An overall passivation (overglass) layer is now
applied and Mask 8 ts needed to define the openings for
access to bonding pads.
N-Well Process
Twin-Tub Process
A logical extension of the p-well and
n-well approaches is the twin-tub
fabrication process. Here we start with
a substrate of high resistivity n-type
material and then create both n-well
and p-well regions.
Through this process it is possible to
preserve the performance of n-
transistors without compromising the
p-transistors.
Doping control is more readily
achieved and some relaxation in
manufacturing tolerances results. This
is particularly important as far as
latch-up is concerned.
 A problem which is inherent in the p-well and n-well
Latch-up in processes is due to the relatively large number of junctions
CMOS which are formed in these structures and as mentioned
earlier, the consequent presence of parasitic transistors and
Process diodes.
Latch-up is a condition in which . The parasitic components
give rise to the establishment of low-resistance conducting
paths between VDD and VSS with disastrous results. Careful
control during fabrication is necessary to avoid this problem.
 Remedies for the latch-up problem include
I. an increase in substrate doping levels with a consequent drop in the value of RS
2. reducing RP by control of fabrication parameters and by ensuring a low contact resistance to
VSS.
3. other more elaborate measures such as the introduction of guard rings.
 MOS Transistor
The Metal oxide semiconductor Field Effect Transistor (MOSFET) is the fundamental building block
of CMOS digital integrated circuits.

Compared to the bipolar junction transistor (BJT), the MOS transistor occupies a relatively smaller
silicon area, and its fabrication involves fewer processing steps.

These technological advantages, together with the relative simplicity of MOSFET operation, have helped
make the MOS transistor the most widely used switching device in VLSI circuits.

The nMOS transistor is used as the primary switching device in virtually all digital circuit applications,
whereas the pMOS transistor is used mostly in conjunction with the nMOS device in CMOS circuits.
However, the basic operation principles of both nMOS and pMOS transistors are very similar to each
other.
 MOSFET as a switch
MOSFET can be considered as a switch which operates with proper biasing.

Field Effect Transistor – The flow of electron is guided by amount of

electric field present in the device.

Biasing – The amount of voltage applied to source , gate and drain.

This helps to give many answers itself (Questions)

1. For what value of gate voltage device will turn ON ( Threshold volatge)

2. What is the resistance between source and drain when device is

turn ON (OFF) .

3. What limit the speed of the device.

MOSFET Structure
 Body terminal

The substrate bias should be connected with the negative most supply in case of NMOS and
Positive most supply in case of PMOS.
MOS symbol
 n-Well Process
NMOS and PMOS are in general made in same wafer , in which one device can placed in local
substrate called as well
 MOS Structure or MOS capacitor
The MOS structure forms a capacitor, with the gate and the substrate acting as the two terminals
(plates) and the oxide layer as the dielectric.

The carrier concentration and its local distribution within the semiconductor substrate can now
be manipulated by the external voltages applied to the gate and substrate terminals.

A basic understanding of the bias conditions for establishing different carrier concentrations in the
substrate will also provide valuable insight
into the operating conditions
 Continued….
The equilibrium concentrations of mobile carriers in a semiconductor always obey the Mass Action
Law given by
……….. (1)

Here, n and p denote the mobile carrier concentrations of electrons and holes, respectively, and ni
denotes the intrinsic carrier concentration of silicon. Assuming that the substrate is uniformly doped
with an acceptor (e.g.,Boron) concentration NA. the equilibrium electron and hole concentrations in the
p-type substrate are approximated by

…………. (2)
 Energy Band Diagram
The location of the equilibrium Fermi level EF within the band-gap is determined by the doping type and the
doping concentration in the silicon substrate.
The Fermi potential φF, which is a function of temperature and doping, denotes the difference between the
intrinsic Fermi level Ei, and the Fermi level EF

…….. (3)

For a p-type semiconductor, the Fermi potential can

be approximated by
….(4)

whereas for an n-type semiconductor (doped with a

donor concentration ND), the Fermi
potential is given by
….(5)

Energy Band diagram of P Type silicon substrate

 Continued….
The electron affinity of silicon, which is the potential difference between the conduction band level and
the vacuum (free-space) level, is denoted by qꭔ.

The energy required for an electron to move from the Fermi level into free space is called the work
function qφs, and is given by
……….(6)
 Energy Band Diagram of MOS
Now consider that the three components of the ideal MOS system are brought into physical contact.
The Fermi levels of all three materials must line up, as they form the MOS capacitor
Because of the work-function difference between the metal and the semiconductor, a voltage
drop occurs across the MOS system.

Part of this built-in voltage drop occurs

across the insulating oxide layer.

The rest of the voltage drop(potential

difference) occurs at the silicon surface

next to the silicon-oxide interface, forcing

the energy bands of silicon to bend in this
region
 Continued….
The resulting combined energy band diagram of the MOS system as shown in figure. Notice that the
equilibrium Fermi levels of the semiconductor (Si) substrate and the metal gate are at the same
potential.
 Problem 1
Consider the MOS structure that consists of a p-type doped silicon substrate, a silicon dioxide layer, and
a metal (aluminum) gate. The equilibrium Fermi potential of the doped silicon substrate is given as
. calculate the built-in potential difference across the MOS system. Assume that the MOS
system contains no other charges in the oxide or on the silicon-oxide interface?
Solution
we have to calculate the work function for the doped silicon, the electron affinity of silicon is 4.15 eV, the
work function qφs is found

calculate the work function difference between the silicon substrate and the aluminum gate. Note
that the work function of aluminum is given as 4.1 eV. the built-in potential difference across this
MOS system

If a voltage corresponding to this potential difference is applied externally between the gate and the substrate,
the bending of the energy bands near the surface can be compensated, i.e., the energy bands become "flat."
Thus, the voltage defined by is called flat band voltage
 The MOS System under External Bias
We now turn our attention to the electrical behavior of the MOS structure under externally applied
bias voltages. Depending on the polarity and the magnitude of VG, three different operating regions
can be observed for the MOS system: accumulation, depletion, and inversion.
The majority carrier concentration near the surface becomes larger than the equilibrium hole
concentration in the substrate; hence, this condition is called carrier accumulation on the surface.
Note that in this case, the oxide electric field is directed towards the gate electrode.

The negative surface

potential also causes the
energy bands to bend
upward near the surface.
 Depletion Mode under Small External Bias
Now a small positive gate bias VG is applied to the gate electrode. Since the substrate bias is zero,
the oxide electric field will be directed towards the substrate in this case. The positive surface
potential causes the energy bands to bend downward near the surface.
The majority carriers, i.e., the holes in the substrate, will be repelled back into the substrate as a
result of the positive gate bias, and these holes will leave negatively charged fixed acceptor ions
behind.

Thus, a depletion region

is created near the
surface.
 Calculation of depletion thickness
The thickness xd of this depletion region on the surface can easily be found as a function of the
surface potential φs.
Assume that the mobile charge in a thin horizontal layer parallel to the surface is
…… (7)

The change in surface potential required to displace this charge sheet dQ by a distance Xd away from
the surface can be found by using the Poisson equation

………(8)
Integrating along the vertical direction

……. (9)
Continued…

………..(10)
Thus, the depth of the depletion region is

……..(11)

the depletion region charge density, which consists solely of fixed acceptor ions in this
region, is given by the following expression

…… (12)
 Inversion Mode under increase External Bias
consider next a further increase in the positive gate bias. As a result of the increasing surface
potential, the downward bending of the energy bands will increase as well.
Eventually, the mid-gap energy level Ei becomes smaller than the Fermi level EFP on the surface,
which means that the substrate semiconductor in this region becomes n-type.
The positive gate potential attracts additional minority carriers (electrons) from the bulk substrate to
the surface.

The n-type region created

near the surface by the
positive gate bias is called
the inversion layer
 Continued….
The surface with a large mobile electron concentration can be utilized for conducting current between
two terminals of the MOS transistor.
As a practical definition, the surface is said to be inverted when the density of mobile electrons on the
surface becomes equal to the density of holes in the bulk (p-type) substrate.
Thus, the depletion region depth achieved at the onset of surface inversion is also equal to the
maximum depletion depth, Xdm, which remains constant for higher gate voltages.
Using the inversion condition φs = - φF

The maximum depletion region depth

…….(13)
 MOSFET operation
The simple operation principle of this device is: control the current conduction between the source and
the drain, using the electric field generated by the gate voltage as a control variable.
Since the current flow in the channel is also controlled by the drain-,to-source voltage and by the
substrate voltage, the current can be considered a function of these external terminal voltages.
We will examine in detail the functional relationships between the channel current (also called the
drain current) and the terminal voltages
 Small VGS
The simplest bias condition that can be applied to the n-channel enhancement-type MOSFET.
The source, the drain, and the substrate terminals are all connected to ground. A positive gate-to-source
voltage VGS is then applied to the gate in order to create the conducting channel underneath the gate.
For small gate voltage levels, the majority carriers (holes) are repelled back into the substrate, and the
surface of the p-type substrate is depleted.
 Increased VGS
Now assume that the VGS is further increased. As soon as the surface potential in the channel region
reaches - F surface inversion will be established, and a conducting n-type layer will form between the
source and the drain diffusion regions.
The value of the gate-to-source voltage VGS needed to cause surface inversion to create the conducting
channel) is called the threshold voltage VT0.
VGS < VT0 is not sufficient to establish an inversion layer thus, the MOSFET can conduct no current
between its source and drain terminals unless VGS > VT0 .
 Threshold Voltage
The threshold voltage is defined as the gate voltage at which the channel is inverted or form.
Physical parameters affecting the threshold voltage VT0 are –
(i) the work function difference between the gate and the channel
(ii) the gate voltage component to change the surface potential
(iii) the gate voltage component to offset the depletion region charge
(IV) the voltage component to offset the fixed charges in the gate oxide and in the silicon-oxide interface.

The work function difference ФGC between the gate and the channel reflects the built-in potential (first
component) of the MOS system. Depending on the gate material, the work function difference is –
for metal gate ……(14)

In second component ,the externally applied gate voltage must be changed to achieve surface inversion,
i.e., to change the surface potential by - 2ФF.
 Continued….
The third includes the gate voltage is necessary to offset the depletion region charge. We can calculate the
depletion region charge density at surface inversion (ФS = - ФF ) using equation (12)
……… (15)

if the substrate (body) is biased at a different voltage level than the source. then the depletion region
charge density can be expressed as a function of the source-to-substrate voltage VSB .
……… (16)

The component that offsets the depletion region charge is then equal to ФB /Cox where Cox is the gate
oxide capacitance per unit area.
……… (17)
 Continued….
The gate voltage component that is necessary to offset this positive charge at the interface is Qox /Cox .
Now, we can combine all of these voltage components to find the threshold voltage. For zero substrate bias,
the threshold voltage VT0 is expressed as follows:
……… (18)

For nonzero substrate bias, threshold voltage can be expressed as

……… (19)

The generalized form of the threshold voltage can also be written as

=

…..(20)
 Continued….
From eq. (15) and (16) -
……… (21)

……… (22)
Where the parameter

where 𝛾is the substrate-bias (or body-effect) coefficient

 Continued……
The substrate Fermi potential ФF is negative in NMOS, positive inPMOS.
The depletion region charge densities QBO and QB are negative in PMOS, positive in PMOS.
The substrate bias coefficient 𝛾is positive in NMOS, negative in PMOS.
The substrate bias voltage VSB is positive in NMOS, negative in PMOS.

Typically, the threshold voltage of an enhancement-type n-channel MOSFET is a positive quantity,

whereas the threshold voltage of a p-channel MOSFET is negative.
The threshold voltage can be adjusted by selective dopant ion implantation into the channel region of the
MOSFET.
For nchannel MOSFETs, the threshold voltage is increased (made more positive) by adding extra p-type
impurities (acceptor ions). Alternatively, the threshold voltage of the nchannel MOSFET can be decreased
(made more negative) by implanting n-type impurities (dopant ions) into the channel region
 Problem 2
Calculate the threshold voltage VTO at VSB = 0, for a polysilicon gate n-channel MOS transistor, with the
following parameters: substrate doping density NA = 1016 cm-3 , polysilicon gate doping density ND = 2 x
1020 cm-3, gate oxide thickness tox = 500 Ao, fermi potentional of gate ФF = 0.55V and oxide-interface
fixed charge density Nox = 4 x 1010 cm-2.?
Solution
First, calculate the Fermi potentials for the p-type substrate and for the n-type polysilicon gate

work function difference between the gate and the channel

The depletion region charge density at VSB = 0 is found as follows:

 Continued……

The oxide-interface charge is:

The gate oxide capacitance per unit area is calculated using the dielectric constant of silicon dioxide and
the oxide thickness tox.

Now, we can combine all components and calculate the threshold voltage.
= 0.90-(-0.70)-(-0.69)-0.09=0.40V
 MOSFET Operation: A Qualitative View
Small VDS (Operating in linear or triode region)
At VGS > VT the inversion layer is established on the surface, an n-type conducting channel forms
between the source and the drain, which is capable of carrying the drain current.
If a small drain voltage VDS > 0 is applied, a drain current proportional to VDS will flow from the source to
the drain through the conducting channel. This operation mode is called the linear region. Thus, in
linear region operation, the channel region acts as a voltage-controlled resistor. The electron velocity in
the channel for this case is usually much lower than the drift velocity limit.
 Increased VDS
As the drain voltage is increased, the inversion layer charge and the channel depth at the drain end start
to decrease . Eventually, for VDS = VDSAT, the inversion charge at the drain is reduced to zero, which is
called the pinch-off point.
Beyond the pinch-off point, VDS > VDSAT a depleted surface region forms adjacent to the drain, This
operation mode of the MOSFET is called the saturation mode or the saturation region.
 Continue…..
For a MOSFET operating in the saturation region, the effective channel length is reduced as the
inversion layer near the drain vanishes.
Note that the pinched-off (depleted) section of the channel absorbs most of the excess voltage drop (VDS
- VDSAT) . Electrons arriving from the source to the channel-end are injected into the drain-depletion
region and are accelerated toward the drain in this high electric field, usually reaching the drift velocity
limit.
 MOSFET current voltage characteristics & Equation
we will use the gradual channel approximation (GCA) for establishing the MOSFET current-
voltage relationships.
Gradual Channel Approximation
consider the cross-sectional view of the n-channel MOSFET operating in the linear mode.
We define the coordinate system for this structure such that the x-direction is perpendicular to the surface,
pointing down into the substrate, and the y-direction is parallel to the surface.

The y-coordinate origin (y = 0) is at the

source end of the channel. The channel
voltage with respect to the source will be
denoted by Vc(y).

Now assume that the threshold voltage .

is constant along the entire channel region,
between y = 0 and y = L.
 Continue…..
Next, assume that the electric field component Ey along the y-coordinate is dominant compared to the
electric field component Ex along the x-coordinate.
Note that the boundary conditions for the channel voltage VC are:
….. (23)
……(24)
Also, it is assumed that the entire channel region between the source and the drain is inverted

……(25)
Let QI(y) be the total mobile electron charge in the surface inversion layer. This charge can be expressed
as a function of VGS and VC(y) as follows –
…(26)
 Continue…..
Figure shows the spatial geometry of the surface inversion layer and indicates its significant dimensions.
Now consider the incremental resistance dR . Assume constant surface mobility μn. Minus sign is due to
negative charge QI.
……..…(27)

voltage drop along the incremental segment dy, in the y-direction.

…(28)

This equation can now be integrated along the

channel, i.e., from y = 0 to y = L,

…(29)
 Continue…..
Substitute the value of QI(y) from eqn (26) to eqn (29).
….(30)

Assuming that the channel voltage VC, is the only variable that depends on the position y, the drain
current is found as follows.
……(31)

…… (32)
where the parameters k is defined as
where
 Continue…..
Note that, in addition to the process dependent constants k and V, the current-voltage relationship is
also affected by the device dimensions, W and L.
The equation (32) is not valid beyond the linear region/ saturation region boundary.
…….(33)
The saturation drain current equation can be found simply by substituting Value of VDS to equation (32)

…….(34)

The drain current ID becomes a function only of the gate-to-source voltage VGS, beyond the saturation
boundary .
 Current-Voltage characteristics
Figure shows the typical drain current versus drain voltage characteristics of an n-channel MOSFET.
The parabolic boundary between the linear and the saturation regions is indicated here by the dashed
line.
The current-voltage characteristics of the MOS transistor can also be visualized by plotting the drain
current as a function of the gate voltage. The current is obviously equal to zero for any gate voltage
smaller than the threshold voltage VT0.
 Problem 3
Consider a process technology for which L= 0.4 μm, tox = 8 nm, μn = 450 cm2/V s, and Vt = 0.7 V.Find
Cox and For a MOSFET with W/L = 8 μm/ 0.8 μm calculate the value of VGS and VDS needed to
operate the transistor in the saturation region with a dc current ID = 100 μA. For the device in (b), find
the value of VGS required to cause the device to operate as a 1000Ω resistor for very smallVDS=1.
Solution

=450(cm2/V.s)×4.32×10-3(F/m2 )
=450×108 (μm2/V.s)×4.32×10-15(F/μm2 ) = 194 μA/V2
For the operation in saturation mode
 Continue…..
; ;
(c) MOSFET in the triode region with VDS very small
 Channel length modulation
we will examine the mechanisms of channel pinch-off and current flow in saturation mode in more detail.
The inversion layer charge at the source end of the channel is
……….(35)
and the inversion layer charge at the drain end of the channel is
……. (36)
Note that at the edge of saturation, i.e., when the drain-to-source voltage reaches VDSAT,
…….(37)
the inversion layer charge at the drain end becomes zero, according to (37). In reality, the channel charge
does not become exactly equal to zero because GCA is just a simple approximation, but it indeed becomes
very small.
……. (38)
Thus we can state channel is pinched off at the drain end
 Channel length modulation
If the drain-to-source voltage VDS is increased even further beyond the saturation edge so that VDS > VDSAT,
an even larger portion of the channel becomes pinched-off.
Consequently, the effective channel length is reduced to ….. (39)
where ΔL is the length of the channel segment with Q = 0. Hence, the pinch off point moves from the drain
end of the channel toward the source with increasing VDS. Since Q(y) = 0 for L'< y < L, the channel voltage
at the pinch-off point remains equal to VDSAT.
……(40)

The gradual channel approximation

is valid in this region. thus, the
channel current

….(41)
 Channel length modulation
Note that this current equation corresponds to a MOSFET with effective channel length L’. We can rewrite
the saturation current as follows
……….(42)

To simplify the analysis, we will use the following empirical relation

...(43)

The slope of the current voltage curve in the saturation

region is determined by the channel length modulation
coefficient λ
 Body Effect (Substrate bias effect)
Until now, we have considered a transistor to be a three-terminal device with gate, source, and drain.
However, the body is an implicit fourth terminal.
When a voltage VSB is applied between the source and body, it change the amount of charge required to invert
the channel, hence, it alter the threshold voltage.

where VTO is the threshold voltage when the source is at the body potential, the substrate-bias effect can
significantly change the value of the threshold voltage.
we finally arrive at a complete first-order characterization of the drain (channel) current as a function of the
terminal voltages.
ID = f (VGS, VDS , VBS)
 MOSFET Scaling

The design of high-density chips in MOS VLSI (Very Large Scale Integration) technology requires that
the packing density of MOSFETs used in the circuits is as high as possible and, consequently, that the
sizes of the transistors are as small as possible.
The reduction of the size, i.e., the dimensions of MOSFETs, is commonly referred to as scaling.

It is expected that the operational characteristics of the MOS transistor will change with the reduction
of its dimensions. Also, some physical limitations eventually restrict the extent of scaling.

There are two basic types of size-reduction strategies: full scaling (also called constant-field scaling)
and constant voltage scaling.

Scaling of MOS transistors is concerned with systematic reduction of overall dimensions of the
devices as allowed by the available technology, while preserving the geometric ratios found in the
larger devices.
 Continue….
The proportional scaling of all devices in a circuit would certainly result in a reduction of the total silicon
area occupied by the circuit, there by increasing the overall functional density of the chip. To describe
device scaling, we introduce a constant scaling factor S > 1.

Rohit Lorenzo, VIT-AP

 Full Scaling (Constant-Field Scaling)
This scaling option attempts to preserve the magnitude of internal electric fields in the MOSFET,
while the dimensions are scaled down by a factor of S.
To achieve this goal, all potentials must be scaled down proportionally, by the same scaling factor.
In order to maintain electric fields charge densities must be increased by a factor of S in order to
maintain the field conditions.

Now consider the influence of full scaling described here upon

the current-voltage characteristics of the MOS transistor.

It will be assumed that the surface mobility μn is not

significantly affected by the scaled doping density.
 Continue…..
The gate oxide capacitance per unit area, on the other hand, is changed as follows.

The aspect ratio WIL of the MOSFET will remain unchanged under scaling. Consequently, the
trans conductance parameter kn will also be scaled by a factor of S.
The linear-mode drain current of the scaled MOSFET can now be found as
Continue…..
Similarly, the saturation-mode drain current is also reduced by the same scaling factor.

the instantaneous power dissipated by the device (before scaling) can be found as:

the power dissipation of the transistor will be reduced by the factor S2

This significant reduction of the power dissipation is one of the most attractive featuresof
full scaling.
 Continue…..
the device area reduction by S2

In addition, the proportional reduction of all dimensions on-chip will lead to a reduction of
various parasitic capacitances and resistances as well, contributing to the overall performance
improvement.
Constant-Voltage Scaling
The full scaling strategy dictates that the power supply voltage and all terminal voltages be
scaled down proportionally with the device dimensions. The scaling of voltages may not be
very practical in many cases.

In particular, the peripheral and interface circuitry may require certain voltage levels for all
input and output voltages which in turn would necessitate multiple power supply voltages and
complicated level shifter arrangements. For these reasons, constant-voltage scaling is
usually preferred over full scaling.

In constant-voltage scaling, all dimensions of the MOSFET are reduced by a factor of S, as in

full scaling. The power supply voltage and the terminal voltages, on the other hand, remain
unchanged. The doping densities must be increased by a factor of s2 in order to preserve the
charge-field relations.
 continue………

The linear mode drain current of the scaled MOSFET can be written as:
Continue….
Also, the saturation-mode drain current will be increased by a factor of S after constant
voltage scaling.

Next, consider the power dissipation. Since the drain current is increased by a factor of S

the power density (power dissipation per unit area) is found to increase by a factor
of S3 after constant-voltage scaling.
 Continue…..

To summarize, constant-voltage scaling may be preferred over full (constant-field) scaling in many
practical cases because of the external voltage-level constraints.
This large increase in current and power densities may eventually cause serious reliability problems
for the scaled transistor, such as electro-migration, hot-carrier degradation, oxide breakdown, and
electrical over-stress.
 Short Channel Effects
A MOSFET can be defined as a short-channel device if the effective channel length Leff approximately
equal to the source and drain junction depth xj.
The short-channel effects that arise in this case are attributed to two physical phenomena:
(i) the limitations imposed on electron drift characteristics in the channel
(ii) the modification of the threshold voltage due to the shortening channel length.

Limitation in electron drift

The lateral electric field EY along the channel increases, as the effective channel length is decreased. The
electron drift velocity Vd trends to saturate at high electric fields. The velocity saturation has very
significant implication on I-V characteristics .

In short-channel MOS transistors, the carrier velocity in the channel is also a function of the normal
(vertical) electric-field component Ex.
 Continue…..
The vertical field influences the scattering of carriers (collisions suffered by the carriers) in the surface
region. The surface electron mobility expressed by following empirical formula –
….. (1)

where μno is the low-field surface electron mobility and ϴ is the empirical factor. The field related mobility
reduction can be approximated by
….. (2)
Where η is an empirical coefficient

Modification of threshold voltage

We see simplified geometry of the gate-induced bulk depletion region and the pn-junction depletion regions
in a short-channel MOS transistor.
 Continue…..
Figure shows bulk depletion region is assumed to be in asymmetric trapezoidal shape. The drain depletion
region is larger than the source due to positive VDS. We recognize that a significant portion is actually due
to the source and drain junction depletion, rather than the bulk depletion induced by the gate voltage.
The bulk depletion charge in the short-channel device is smaller than expected, the threshold voltage
expression must be modified as -
……. (3)
VT0 is at zero bias ΔVT0 is the threshold shift reduction
due to short channel effect.

ΔLS and ΔLD represent the lateral extent of the depletion

regions. the bulk depletion region charge contained within
the trapezoidal region is –

…(4)
 Continue…..
To calculate ΔLS and ΔLD , we will use the simplified geometry as shown in figure. Here, xds and xdD
represent the depth of the pn-junction depletion regions associated with the source and the drain
respectively.
The edges of the source and drain diffusion regions Xj . The vertical extent of the bulk depletion region Xdm.
The junction depletion region depths can be approximated by-

….(5) …(6)

…..(7)
….(8)
Solving ΔLD

..(9
)
 Continue…..
Similarly length ΔLS can be found as follows

….. (10)

the net amount of threshold voltage reduction ΔVT0 due to short-channel effects can be found as

….(11)

The threshold voltage shift term is proportional to xj /L

 Problem 4
Consider an n-channel MOS process with the following parameters: substrate doping density NA = 1016 cm-3
, polysilicon gate doping density ND = 2 x 1020 cm-3 ,gate oxide thickness tox = 50 nm, oxide-interface fixed
charge density Nox = 4 x 1010 cm-2 ,source and drain diffusion doping density ND = 1017 cm-3 .In addition, the
channel region is implanted with p-type impurities (impurity concentration NI =2× 011 cm-3 to adjust the
threshold voltage. The junction depth of the source and drain diffusion regions is Xj = 1.0 μm.
Plot the variation of the zero-bias threshold voltage VT0 as a function of the channel length ( assume that
VDS =VSB =0) also find VT0 for L = 0.7 μm, VDS = 5V, and VSB =0.
Solution
we have to find the zero-bias threshold voltage which is already calculated in problem no. 1 and was found to
be VTo =0. The additional p-type channel implant will increase the threshold voltage by an amount of qNI /
C0x. we find the long-channel zero-bias threshold voltage.
=0.855V
 Continue…..
The source and drain junction built-in voltage is

The depth of source and drain junction depletion regions

the threshold voltage shift VT0, due to short-channel effects can be calculated as a function of the gate
(channel) length L.
 Continue……….
Finally, the zero-bias threshold voltage is found as
 Narrow Channel Effects
MOS transistors that have channel widths W on the same order of magnitude as the maximum
depletion region thickness xdm are defined as narrow-channel devices.
The most significant narrow-channel effect is that the actual threshold voltage of such a device is larger
than that predicted by the conventional threshold voltage formula.
A typical cross-sectional view of a narrow-channel device. The oxide thickness in the channel region is tox,
while the regions around the channel are covered by a thick field oxide (FOX). Since the gate electrode also
overlaps with the field oxide.
Since the gate electrode also overlaps with the field oxid e
Consequently, the gate voltage must also support this
additional depletion charge in order to establish the
conducting channel.

For MOSFETs with small channel widths, however,

the actual threshold voltage increases as a result of
this extra depletion charge.
 Continue……….
Finally, the zero-bias threshold voltage is found as
………(1)
The additional contribution to the threshold voltage due to narrow-channel effects can be modeled as follows:
……….(2)

where K is an empirical parameter depending on the shape of the fringe depletion region. Depletion region
edges are modeled by quarter-circular arcs.
In all cases, we recognize that the additional contribution to VT0 is proportional to (xdm /W).
 Other limitations imposed by small geometries
The small-geometry device characteristics, may severely restrict the operating conditions of the transistor
and imposed limitations upon the practical utility of the device.
Accurate identification and characterization of these small-geometry effects are crucial, especially for
submicron MOSFETs.
Velocity Saturation
At high field strengths, the carriers fail to follow this linear model. In fact, when the electrical field along the
channel reaches a critical value ξC. The velocity of the carriers tends to saturate due to scattering effects
(collisions suffered by the carriers) .
The velocity as a function of the electrical field, plotted in Figure,
can be roughly approximated by the following expression

………(1)
 Continue……
For a short-channel device and for large enough values of VGT, is substantially smaller than 1, hence VDSAT
< VGT. The device enters saturation before VDS reaches VGS - VT. Short-channel devices therefore experience
an extended saturation region, and tend to operate more often in saturation conditions than their long-
channel.
 Drain-Induced Barrier Lowering (DIBL)
If the drain voltage is increased, the potential barrier in the channel decreases leading to drain induced
barrier lowering (DIBL).This is demonstrated by the energy bands along the semiconductor surface
For a long channel device, a drain bias can change the effective channel length, but the barrier at the
source remains constant . For a short-channel device, this same barrier is no longer fixed. The lowering of
the source barrier causes an injection of extra carriers, thereby increasing the current substantially.
 Subthreshold current
The reduction of the potential barrier eventually allows electron flow between the source and the drain, even
if the gate-to-source voltage is lower than the threshold voltage. The channel current that flows under these
conditions (VGS < VT0) is called the subthreshold current. Two-dimensional analysis of the small-geometry
MOSFET yields the following approximate expression for the subthreshold current.

Here, xC is the subthreshold channel depth, Dn is the electron diffusion coefficient, LB is the length of the
barrier region in the channel, and Фr is a reference potential.
 Oxide breakdown and gate oxide tunneling
Another limitation on the scaling of tox is the possibility of oxide breakdown. If the oxide electric field
perpendicular to the surface is larger than a certain breakdown field, the silicon-dioxide layer may sustain
permanent damage during operation, leading to device failure.
Reduction in gate oxide thickness results in an increase in electric field across the oxide. This high electric
field with low oxide thickness results in tunneling of electrons from substrate to gate and also from gate to
substrate through the gate oxide, which results in the gate oxide tunneling.
86 Hot Carrier Injection
The highest field occurs near the drain, and this is the location where most of the anomalous currents originate. The
channel carriers (electrons) go through the high-field region, they acquire extra energy from the field without losing it to
the lattice. These energetic carriers are called hot carriers.
Electrons and holes gaining high kinetic energies in the electric field (hot carriers) may, however, be injected into the
gate oxide, and cause permanent changes in the oxide interface charge distribution, degrading the current-voltage
characteristics of the MOSFET.

Rohit Lorenzo 8/7/2021

 Punch through
The drain and source regions are very much close to each other in short-channel devices. The depletion
region across the drain-substrate and source-substrate junction extends into the channel region. The
separation between the depletion boundaries gradually decreases, as the channel length is reduced. The
increase in Vds further pushes the junction near to each other. Thus, the overall effect of short-channel length
and reverse biased substrate- drain junction leads to the merging of the two depletion regions, which cause
punch through condition. The punch through results the increase in sub-threshold current.
 CMOS Latchup
The MOS technology contains a number of intrinsic bipolar transistors. These are especially troublesome in
CMOS processes, where the combination of wells and substrates results in the formation of parasitic n-p-n-p
structures. Triggering these thyristor-like devices leads to a shorting of the VDD and VSS lines, usually
resulting in a destruction of the chip, or at best a system failure.

Latch-up prevention techniques:

Simply put, latchup prevention/protection includes putting a high resistance in the path so as to limit the
current through supply.

(1) Surrounding PMOS and NMOS

transistors with an insulating oxide
layer (trench).

(2) Latchup Protection Technology

circuitry which shuts off the device
when latchup is detected
 MOSFET Capacitance
In order to examine the transient (AC) response of MOSFETs and digital circuits consisting of MOSFETs, on
the other hand, we have to determine the nature and the amount of parasitic capacitances associated with
the MOS transistor.

In cross-sectional view of figure, the mask length (drawn

length) of the gate is indicated by LM, and the actual
channel length is indicated by L.

The extent of both the gate-source and the gate-drain

overlap are LD; thus, the channel length is given by

….(1)

The source and drain overlap region lengths are usually

equal to each other. Note that both of these overlap
capacitances do not depend on the bias conditions, i.e.,
they are voltage-independent.
 Continue….
P+ doped region, also called the channel-stop implant. this additional p+ region is to prevent the formation of
any unwanted (parasitic) channels between two neighboring n+ diffusion regions. act to electrically isolate
neighboring devices built on the same substrate.
We will identify the parasitic capacitances associated with this typical MOSFET structure as
lumped equivalent capacitances.

The parasitic device capacitances can be classified into two

major groups: oxide-related capacitances and junction
capacitances.
 Oxide related Capacitance
The two overlap capacitances on source and drain as a result of this structural arrangement are called CGD
(overlap) and CGS (overlap). Assume same width W for both the diffusion region. The overlap capacitances
can be found as
……..(2)

The channel region is connected to the source, the drain, and the substrate, we can identify three
capacitances between the gate and these regions, i.e., Cgs, Cgd and Cgb respectively. Cgs and Cgd is actually
gate to channel capacitance.
A simplified view of their bias-dependence can be obtained by observing the conditions in the channel region
during cut-off, linear, and saturation modes.
In cut OFF mode Cgs = Cgd = 0 because of no conducting channel. The gate-to-substrate capacitance can
be approximated by …….(3)
 Continue….
In linear-mode operation, conducting inversion layer on the surface effectively shields the substrate from the
gate electric field; thus, Cgb = 0. In this case, the distributed gate-to-channel capacitance may be viewed as
being shared equally.
…….(4)
 Continue…..
When the MOSFET is operating in saturation mode, the inversion layer on the surface does not extend to the
drain, but it is pinched off. In this case Cgd=0 and Cgb=0. Finally, the distributed gate-to-channel capacitance
can be approximated as
………(4)
we have to combine the distributed Cgs. and Cgd values found here with the relevant overlap capacitance
values, in order to calculate the total capacitance between the external device terminals.
 Junction Capacitances
we consider the voltage-dependent source-substrate and drain-substrate junction capacitances, Csb and Cdb,
respectively. Both of these capacitances are due to the depletion charge surrounding the respective source
or drain diffusion regions embedded in the substrate.
Figure shows the simplified, partial geometry of a typical n-channel enhancement MOSFET, focusing on the
n-type diffusion region within the p-type substrate. the n+ diffusion region forms a number of planar pn-
junctions with the surrounding p-type substrate, indicated here with 1 through 5.

The dimensions of the rectangular box representing

the diffusion region are given as W, Y, and Xj.

we recognize that three of the five planar junctions

shown here (2, 3, and 4) are actually surrounded by
the p+ channel-stop implant.

The junction labeled (1) is facing the channel, and the

bottom junction (5) isfacing the p-type substrate
 Continue….
The junction capacitances associated with these sidewalls will be different from the other junction
capacitances.
To calculate the depletion capacitance of a reverse-biased abrupt pn-junction, consider first the depletion
region thickness, Xd. Assuming that the n-type and p-type doping densities are given by ND and NA,
respectively, and that the reverse bias voltage is given by V (negative), the depletion region thickness can be
found as follows:

…….(5)

where the built-in junction potential is calculated as

…….(6)
 Continue….
The depletion-region charge stored in this area can be written in terms of the depletion region thickness, xd.
……(6)

Here, A indicates the junction area. The junction capacitance associated with the depletion region is defined
as
…….. (7)
By differentiating with respect to the bias voltage V. we can now obtain the expression for the junction
capacitance as follows.
……..(8)

This expression can be rewritten in a more general form, to account for the junction grading.
…….. (9)
 Continue….
The parameter m is called the grading coefficient. Its value is equal to 1/2 for an abrupt junction profile, and
1/3 for a linearly graded junction profile. The zero-bias junction capacitance per unit area Cjo is defined as
……….(10)

The accurate estimation of the junction capacitances under transient conditions is quite complicated. The
problem of estimating capacitance values under changing bias conditions can be simplified, if we calculate a
large-signal average (linear) junction capacitance. This equivalent large-signal capacitance can be defined
as follows:
……(11)

substitute the value from equation (9) in (11).

……(12)
 Continue….
For the special case of abrupt pn-junctions, equation

……(13)

This equation can be rewritten in a simpler form by defining a dimensionless coefficient Keq as follows
……(14)

……(15)

Where Keq is the voltage equivalence factor

 Continue….
As we discuss earlier the sidewalls of a typical MOSFET source or drain diffusion region are
surrounded by a p+ channel-stop implant. the sidewall zero bias capacitance Cj0sw as well as the
sidewall voltage equivalence factor Keq(sw) will be different from those of the bottom junction.
Assuming that the sidewall doping density is given by NA(sw), the zero-bias capacitance per unit area
can be found as follows:

…….(16)
where Фsw is the built-in potential of the sidewall junctions. Since all sidewalls in a typical diffusion
structure have approximately the same depth of xj we can define a zero bias sidewall junction
capacitance per unit length. ……(17)
 Continue….
The sidewall voltage equivalence factor Keq(sw) for a voltage swing between V1 and V2 is defined as follows
. …….(18)

Combining the equations (16) through (18), the equivalent large-signal junction capacitance Ceq(SW) for a
sidewall of length (perimeter) P can be calculated as
….(19)
 Source – Drain Resistance
Another parasitic component which effect the performance is the resistance in series with the source and
drain.
The effect is more pronounced in smaller feature size

Where Rsheet and RC is the sheet and contact resistance

respectively
 Problem 5
Consider a simple abrupt pn-junction, which is reverse-biased with a voltage Vbias. The doping density of the
n-type region is ND =1019 cm-3, and the doping density of the ptype region is given as NA = 1016 cm-3. The
junction area is A = 20 μm x 20 μm .consider Vbias = 5V. Calculate (a) the zero-bias junction capacitance per
unit area, Cj0 , for this structure. (b) equivalent capacitance
 Continue…..
Solution
First, we will calculate the zero-bias junction capacitance per unit area, Cj0 , for this structure. The built-in
junction potential is found as

we can calculate the zero-bias junction capacitance

Next, find the equivalent large-signal junction capacitance assuming that the reverse bias voltage changes
from V1 = 0 to V2 = - 5 V. The voltage equivalence factor for this transition can be found as follows
 Continue…..

Then, the average junction capacitance can be found simply by using

 Problem 6
Consider the n-channel enhancement-type MOSFET shown below. The process parameters are given as
follows:

Substrate doping NA = 2 x 1015 cm-3

Source / drain doping ND = 1019 cm-3
Sidewall (p+) doping NA(sw) = 4 x 1016
cm-3
Gate oxide thickness tox = 45 nm
Junction depth Xj= 1.0 μm
Consider reverse bias voltage from Vbias = 0.5V to 5V
Calculate (a) the zero bias junction capacitance &
Side wall junction capacitance.
(b) calculate the voltage equivalence factors,
for both types of junctions.
 Solutio
We start n
by calculating the built-in potentials for both types of junctions.

Next, we calculate the zero-bias junction capacitances per unit area:

 Continue…..
The zero-bias sidewall junction capacitance per unit length can also be found as follows.

we must now calculate the voltage equivalence factors, Keq and Keq(sw)