Lecture for Logic Family

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 OVERVIEW

Introduction
Logic Family Classification
Fan IN And Fan Out
Noise Margin
Transistor as a Switch
RTL, DTL, TTL and ECL
Elementary data of CMOS

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 Logic Family
A logic family in digital integrated circuit devices is a group of ICs or electronic logic
gates constructed by using compatible and supply voltages for performing various logic
functions

Many logic families were produced as individual components, each containing one or a few related
basic logical functions, which could be used as "building-blocks" to create systems or as so-called
"glue" to interconnect more complex integrated circuits.

A "logic family" may also refer to a set of techniques used to implement logic
within VLSI integrated circuits such as central processors, memories, or other complex functions.

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 Transistor as A Switch

• A circuit that can turn on/off current in electrical circuit is referred to a switching circuit and
transistor can be employed as an electronic switch.

• Solid state switches are one of the main applications for the use of transistor to switch a DC
output “ON” or “OFF”.

• Some output devices, such as LED’s only require a few milliamps at logic level DC voltages and
can therefore be driven directly by the output of a logic gate.

• High power devices such as motors, solenoids or lamps, often require more power than that
supplied by an ordinary logic gate so transistor switches are used.

If the circuit uses the Bipolar Transistor as a Switch, then the areas of operation for a transistor
switch are known as the Saturation Region and the Cut-off Region. This mean that we can
ignore the operating Q-point biasing and voltage divider circuitry required for amplification, and
use the transistor as a switch by driving it back and forth between its “fully-OFF” (cut-off) and
“fully-ON” (saturation) regions as shown below.
 Saturation Region
Cut-off Region Here the transistor will be biased so that the maximum amount
Here the operating conditions of the transistor are zero input of base current is applied, resulting in maximum collector
base current ( IB ), zero output collector current ( IC ) and current resulting in the minimum collector emitter voltage drop
maximum collector voltage ( VCE ) which results in a large which results in the depletion layer being as small as possible
depletion layer and no current flowing through the device. and maximum current flowing through the transistor. Therefore
Therefore the transistor is switched “Fully-OFF”. the transistor is switched “Fully-ON”.
•The input and Base are connected to VCC
•The input and Base are grounded ( 0v ) •• Base-Emitter voltage VBE > 0.7v
•• Base-Emitter voltage VBE < 0.7v •• Base-Emitter junction is forward biased
•• Base-Emitter junction is reverse biased •• Base-Collector junction is forward biased
•• Base-Collector junction is reverse biased •• Transistor is “fully-ON” ( saturation region )
•• Transistor is “fully-OFF” ( Cut-off region ) •• Max Collector current flows ( IC = Vcc/RL )
•• No Collector current flows ( IC = 0 ) •• VCE = 0 ( ideal saturation )
•• VOUT = VCE = VCC = ”1″ •• VOUT = VCE = ”0″
•• Transistor operates as an “open switch” •• Transistor operates as a “closed switch”

Then we can define the “cut-off region” or “OFF mode” when Then we can define the “saturation region” or “ON mode” when
using a bipolar transistor as a switch as being, both junctions using a bipolar transistor as a switch as being, both junctions
reverse biased, VB < 0.7v and IC = 0 forward biased, VB > 0.7v and IC = Maximum.
 Classification

Digital Logic Families

Bipolar Logic Family

ULF(unipolar logic family)

Saturated Non Saturated PMOS(p-channel MOSFET)

NMOS(n-channel MOSFET)
RTL(resistor transistor logic) CMOS
Schottky TTL
DCTL(direct coupled transistor logic)
ECL(emitter coupled logic)
IIL(integrated injection logic)
DTL(diode transistor logic)
HTL(high threshold logic)
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TTL(transistor transistor logic)
 Introduction

Logic families represent kind of digital circuit/methodologies for logic

expression.

Integration levels :
SSI: Small scale integration 12 gates/chip

MSI: Medium scale integration 100 gates/chip

LSI: Large scale integration 1K gates/chip

10K gates/chip
VLSI: Very large scale integration

ULSI: Ultra large scale integration 100K gates/chip

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Fan In
• Fan in or gate is the number of inputs that can practically be supported
without degrading practically input voltage level .
Fan in = 4
Fan Out
•The maximum number of digital input that the output of a single logic
gate can feed and the gate must be same logic family.

•Fan Out is calculated from the amount of current available in the output of a
gate and the amount of current needed in each input of the connecting gate.

•It is specified by manufacturer and is provided in the data sheet.

•Exceeding the specified maximum load may cause a problems because the
circuit will not be able to supply the demanded power.
Fanout = 4
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 Noise Margin

•Noise is present in all real systems. This adds

random fluctuations to voltages representing
logic levels.

•Hence, the voltage ranges defining the logic

levels are more tightly constrained at the output
of a gate than at the input.

•Small amounts of noise will not affect the

circuit. The maximum noise voltage that can be
tolerated by a circuit is termed its noise
immunity (noise Margin).

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 Operating Temperature Ranges

ï For commercial and industrial needs, temperatures

usually range from 0o or -30o C to 55o, 70o or 85o C
ï The military has an universal requirement for operability
from -55o C to 125o C.
ï Advantages of a wide temperature specification are
offset by the increased cost
Propagation Delay

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 Propagation Delay

Two propagation delays associated with a logic gate:

tPHL: The time between a specified reference point on the
input pulse and a corresponding reference point on the
output pulse, with the output changing from the High
level to the Low level.
tPLH: The time between specified reference point on the
input pulse and a corresponding reference point on the
output pulse, with the output changing from the Low level
to the High level.
 Speed

ï The shorter the propagation delay, the higher the speed

of the circuit
ï Propagation delay of a gate:
time interval between the application of an input pulse
and the occurrence of the resulting output pulse.

The reference points are chosen as the 50% of the leading

and trailing edges of the wave forms, or the threshold
voltage (where the input and output voltages of the gate are
equal) point.
 Power Dissipation

ï The currents drawn would be different in logic 0 and 1 states

ï ICC is the average of ICCL and ICCH
ï The power consumed is given by PD = ICC x VCC
ï Current drawn during the transition time would be larger than
either of the steady states
ï Transition peaks create large noise signal on the power supply
line.
ï Needs filtering by using a bypass capacitance very close to the IC
ï Transition component of power dissipation is proportional
to frequency.
ï This frequency dependent power dissipation becomes
significant with regard to quiescent power dissipation only at
very high frequencies.
Low power dissipation is desired in large systems as it
leads to
ï Lower cooling costs
ï Lower power supply and distribution costs,
ï Reduction in mechanical design problems
ï Decrease in power dissipation on a per-gate basis with
higher integration levels
 Packaging

ï Initially most of the digital ICs were made available in

dual-in-line packages (DIP).
ï Commercial ICs come in plastic DIPs
ï Ceramic DIPs are used for operation over a larger
temperature range
ï Increasing integrations lead to a wide range of chip level
packages
 Often the most important one, is the cost of a logic family.
It is not sufficient to compare the cost of logic families at
gate level.
The total system cost is decided by

ïCost of ICs
ï Procurement
ïCost printed wiring board on which the ICs are
ï Testing
mounted
ï Power supply
ï Assembly of circuit board ï Documentation
ïProgramming the programmable devices ïetc. ï Storage
 Resistor Transistor Logic (RTL)
The basic RTL device is a NOR gate.

The inputs represent either logic level HIGH (1) or LOW (0).

The logic level LOW is the voltage that drives corresponding transistor in cut-off
region, while logic level HIGH drives it into saturation region.

If both the inputs are LOW, then both the transistors are in cut-off i.e. they are
turned-off. Thus, voltage Vcc appears at output I.e. HIGH.

If either transistor or both of them are applied HIGH input, the voltage Vcc drops
across Rc and output is LOW.

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Resistor Transistor Logic

A B Y(Out put)
0 0 1
0 1 0
1 0 0
1 1 0
Advantages of RTL Logic circuit:

The primary advantage of RTL technology was that it

involved a minimum number of transistors, which was
an important consideration before integrated circuit
technology, as transistors were the most expensive
component to produce

Limitations:

The obvious disadvantage of RTL is its high current

dissipation when the transistor conducts to overdrive
the output biasing resistor. This requires that more
current be supplied to and heat be
removed from RTL circuits. In contrast, TTL circuits
minimize both of these requirements.
•
(NOR GATE USING RTL)

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 Diode Transistor Logic
The diode-transistor logic, also termed as DTL, replaced RTL family because of greater fan-out
capability and more noise margin.

DTL circuits mainly consists of diodes and transistors that comprises DTL devices.

The basic DTL device is a NAND gate.

Two inputs to the gate are applied through diodes viz. D1, D2 . The diode will conduct only when
corresponding input is LOW.

If any of the diode is conducting i.e. when at least one input is LOW, the voltage at output keeps
transistor T in cut-off and subsequently, output of transistor is HIGH. If all inputs are HIGH, all diodes
are non-conducting, transistor T is in saturation, and its output is LOW.

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Due to number of diodes
used in this circuit, the speed of
the circuit is significantly low.
Hence this family of logic gates
is modified to
transistor-transistor logic i.e.
TTL family which has been
discussed on next slide.

A B C(Out put)
(SATURATING
0 0 1
INVERTER)
0 1 1
1 0 1
1 1 0
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 Transistor Transistor Logic
TTL family is a modification to the DTL. It has come to existence so as to
overcome the speed limitations of DTL family. The basic gate of this family is TTL
NAND gate.
It performs both the logic function and the amplifying function

T1 is called input transistor, which is multi emitter transistor, that drive transistor T2
which is used to control T3.

Diode.

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Transistor Transistor logic

A B Out put
0 0 1
0 1 1
1 0 1
1 1 0
 Emitter Coupled Logic
ECL logic family implements the gates in differential amplifier configuration in
which transistors are never driven in the saturation region thereby improving the
speed of circuit to a great extent. The ECL family is fastest of all logic families.

Based on BJT, but removes problems of delay time by preventing the transistors
from saturating.

Very fast operation - propagation delays of 1ns or less.

Low noise immunity of about 0.2-0.25 V .

The input impedance is high and the output impedance is low. As a result, the
transistors change states quickly, gate delays are low, and the fan out capability is
high.

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 (TRUTH
TABLE)
A B Out put Output2
1
0 0 1 0
0 1 0 1
1 0 0 1
1 1 0 1

(Block Diagram of ECL)

(ECL 2 INPUT OR/NOR GATE)
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Some statistical characteristics data of different logic families

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