TDA7492E

79 W + 79 W dual BTL class-D audio amplifier

Datasheet - production data

• Four selectable, fixed-gain settings of

nominally 20.8 dB, 26.8 dB, 30 dB and
32.8 dB
• Differential inputs minimize common-mode
noise
• Standby, mute and play operating modes
• Short-circuit protection
• Output power limited by PLIMIT function
• Detection of shorted output pins during
PowerSSO-36
startup
exposed pad up
• Thermal overload protection
• ECOPACK® environmentally friendly
Features package
• Wide-range single-supply operation
(7 - 26 V) Description
• Possible output configurations: The TDA7492E is a dual BTL class-D audio
− 2 x PBTL amplifier with single power supply designed for
− 1 x Parallel BTL home audio applications.
• BTL output capabilities (VCC = 26 V): The device is housed in a 36-pin PowerSSO
− 61 W + 61 W, 4 Ω, THD 1% package with exposed pad up (EPU), and as a
− 79 W + 79 W, 4 Ω, THD 10% result of its high efficiency, a simple heatsink is
− 44 W + 44 W, 6 Ω, THD 1% required.
− 57 W + 57 W, 6 Ω, THD 10%
Table 1: Device summary
− 34 W + 34 W, 8 Ω, THD 1%
− 44 W + 44 W, 8 Ω, THD 10% Operating
Order code Package Packaging
temp. range
• Parallel BTL output capabilities (VCC = 26 V):
− 86 W, 3 Ω, THD 1% TDA7492ETR -40 to +85°C
PowerSSO-36 Tape and
− 110 W, 3 Ω, THD 10% EPU reel
• High efficiency

February 2017 DocID027638 Rev 1 1/24

This is information on a product in full production. www.st.com
Contents TDA7492E
Contents
1 Device block diagram...................................................................... 5
2 Pin description ................................................................................ 6
2.1 Pinout ................................................................................................ 6
2.2 Pin list ............................................................................................... 7
3 Electrical specifications .................................................................. 8
3.1 Absolute maximum ratings ................................................................ 8
3.2 Thermal data ..................................................................................... 8
3.3 Electrical specifications ..................................................................... 9
3.4 Stereo BTL application .................................................................... 10
3.5 Parallel BTL (mono) application ...................................................... 10
4 Application information ................................................................ 11
4.1 Gain setting ..................................................................................... 11
4.2 Stereo and mono applications ......................................................... 11
4.3 Smart protections ............................................................................ 11
4.3.1 Overcurrent protection (OCP) .......................................................... 11
4.3.2 Thermal protection............................................................................ 12
4.3.3 Power limit ........................................................................................ 12
4.4 Mode selection ................................................................................ 13
5 Schematic diagram........................................................................ 15
6 Characterization curves ................................................................ 16
6.1 Stereo configuration ........................................................................ 16
7 Package information ..................................................................... 20
7.1 PowerSSO36 EPU package information ......................................... 20
8 Revision history ............................................................................ 23

2/24 DocID027638 Rev 1

TDA7492E List of tables
List of tables
Table 1: Device summary ........................................................................................................................... 1
Table 2: Pin description list ......................................................................................................................... 7
Table 3: Absolute maximum ratings ........................................................................................................... 8
Table 4: Thermal data ................................................................................................................................. 8
Table 5: Electrical specifications ................................................................................................................. 9
Table 6: Stereo BTL application ............................................................................................................... 10
Table 7: Stereo BTL (mono) application ................................................................................................... 10
Table 8: Gain settings ............................................................................................................................... 11
Table 9: Overcurrent protection ................................................................................................................ 11
Table 10: Overcurrent protection (mute mode) ........................................................................................ 12
Table 11: Max effective voltage of PLIMIT pin vs. power supply and load............................................... 13
Table 12: Mode settings............................................................................................................................ 13
Table 13: PowerSSO-36 EPU package mechanical data ........................................................................ 22
Table 14: Document revision history ........................................................................................................ 23

DocID027638 Rev 1 3/24

List of figures TDA7492E
List of figures
Figure 1: Internal block diagram (showing one channel only) .................................................................... 5
Figure 2: Pin connections (top view, PCB view) ......................................................................................... 6
Figure 3: Mono BTL settings ..................................................................................................................... 11
Figure 4: Recommended power limit pin connections .............................................................................. 12
Figure 5: Standby and mute circuits ......................................................................................................... 14
Figure 6: Turn-on/off sequence for minimizing speaker “pop” .................................................................. 14
Figure 7: Application circuit ....................................................................................................................... 15
Figure 8: Output power vs. supply voltage ............................................................................................... 16
Figure 9: THD vs. Pout (Vs = 26 V, f = 1 kHz) .......................................................................................... 16
Figure 10: THD vs. Pout (Vs = 26 V, f = 100 Hz) ..................................................................................... 16
Figure 11: THD vs. Pout (Vs = 26 V, f = 6 kHz) ........................................................................................ 16
Figure 12: THD vs. frequency (Vs = 26 V, Po = 1 W)............................................................................... 17
Figure 13: Frequency response Vs = 26 V ............................................................................................... 17
Figure 14: Signal-to-noise ratio (Vs = 26 V, gain = 32.6 dB, not weighted) ............................................. 17
Figure 15: Signal-to-noise ratio (Vs = 26 V, gain = 20.6 dB, not weighted) ............................................. 17
Figure 16: Signal-to-noise ratio (Vs = 26 V, gain = 32.6 dB, A-weighted) ................................................ 18
Figure 17: Signal-to-noise ratio (Vs = 26 V, gain = 20.6 dB, A-weighted) ................................................ 18
Figure 18: Crosstalk Vs = 26 V ................................................................................................................. 18
Figure 19: FFT (0 dB) Vs = 26 V............................................................................................................... 18
Figure 20: FFT (-60 dB) Vs = 26 V ........................................................................................................... 19
Figure 21: PowerSSO-36 EPU package outline ....................................................................................... 21

4/24 DocID027638 Rev 1

TDA7492E Device block diagram

1 Device block diagram

Figure 1: "Internal block diagram (showing one channel only)" shows the block diagram of
one of the two identical channels of the TDA7492E.
Figure 1: Internal block diagram (showing one channel only)

GAIN
Gain Settings
Power Limit
PLMT

Gate
OUTP
- Driver
+

PWM logic level shift

+
INP + - -
VREF
INN - +
+
+
-
-

Gate
OUTN
Driver

ROSC
Oscillator
SYNCLK

Thermal,Undervoltage
Standby Mute/Play VDD,VSS Regulators
Overcurrent protections

STANDBY MUTE DIAG VDDS VSS

DocID027638 Rev 1 5/24

Pin description TDA7492E

2 Pin description
2.1 Pinout
Figure 2: Pin connections (top view, PCB view)

36 VSS SUB GN D 1

35 SVCC OUTPB 2

34 VR EF OUTPB 3

33 IN NB PGNDB 4

32 IN PB PGNDB 5

31 GAIN PV CCB 6

30 PLIMIT PV CCB 7

29 SVR OUTNB 8

28 DIAG OUTNB 9

27 SGND OUTNA 10

26 VD DS OUTNA 11

25 SYNCLK PV CCA 12

24 ROSC PV CCA 13

23 IN NA PGNDA 14

22 IN PA PGNDA 15

21 MUTE EP OUTPA 16
e xpo sed pa d u p
Con ne ct to g ro un d
20 STBY OUTPA 17

19 VD DPW PGN D 18

6/24 DocID027638 Rev 1

TDA7492E Pin description
2.2 Pin list
Table 2: Pin description list
Number Name Type Description
1 SUB_GND PWR Connect to the frame
2, 3 OUTPB O Positive PWM for right channel
4, 5 PGNDB PWR Power stage ground for right channel
6, 7 PVCCB PWR Power supply for right channel
8, 9 OUTNB O Negative PWM output for right channel
10, 11 OUTNA O Negative PWM output for left channel
12, 13 PVCCA PWR Power supply for left channel
14, 15 PGNDA PWR Power stage ground for left channel
16, 17 OUTPA O Positive PWM output for left channel
18 PGND PWR Power stage ground
3.3 V (nominal) regulator output referred to ground for
19 VDDPW O
power stage
20 STBY I Standby mode control
21 MUTE I Mute mode control
22 INPA I Positive differential input of left channel
23 INNA I Negative differential input of left channel
24 ROSC O Master oscillator frequency-setting pin
25 SYNCLK I/O Clock in/out for external oscillator
3.3 V (nominal) regulator output referred to ground for
26 VDDS O
signal blocks
27 SGND PWR Signal ground
28 DIAG O Open-drain diagnostic output
29 SVR O Supply voltage rejection
30 PLIMIT I Output voltage level setting
31 GAIN I Gain setting input
32 INPB I Positive differential input of right channel
33 INNB I Negative differential input of right channel
34 VREF O Half VDDS (nominal) referred to ground
35 SVCC PWR Signal power supply
36 VSS O 3.3 V (nominal) regulator output referred to power supply
- EP - Exposed pad for heatsink, to be connected to GND

DocID027638 Rev 1 7/24

Electrical specifications TDA7492E

3 Electrical specifications
3.1 Absolute maximum ratings
Table 3: Absolute maximum ratings
Symbol Parameter Value Unit
VCC DC supply voltage for pins PVCCA, PVCCB, SVCC 30 V
Voltage limits for input pins STBY, MUTE, INNA, INPA,
VI -0.3 to +4.6 V
INNB, INPB, GAIN, MODE
Top Operating temperature -40 to +85 °C
Tj Junction temperature -40 to +150 °C
Tstg Storage temperature -40 to +150 °C

3.2 Thermal data

Table 4: Thermal data
Symbol Parameter Min. Typ. Max. Unit
Rth j-case Thermal resistance, junction-to-case - 2.98 °C/W

8/24 DocID027638 Rev 1

TDA7492E Electrical specifications
3.3 Electrical specifications
Unless otherwise stated, the results in Table 5: "Electrical specifications" below are given
for the conditions: VCC = 26 V, RL= 6 Ω, ROSC = 33 kΩ, f = 1 kHz, GV = 20.8 dB and
Tamb = 25 °C.
Table 5: Electrical specifications
Symbol Parameter Condition Min. Typ. Max. Unit
Supply voltage for pins
VCC - 7 - 26 V
PVCCA, PVCCB, SVCC
Iq Total quiescent current Without LC, no load - 40 mA
Quiescent current in
IqSTBY - - 1 - µA
standby
Vi = 0, Av = 20 dB,
VOS Output offset voltage 20 mV
no load
Overcurrent protection
IOCP RL = 0 Ω 9 10 13 A
threshold
Junction temperature at
Tj - 140 150 160 °C
thermal shutdown
Ri Input resistance Differential input 60 - kΩ
Power transistor High side - 0.2 -
RdsON Ω
on-resistance Low side - 0.2 -
GAIN < 0.25*Vdd 20.8 -
0.25*Vdd < GAIN < 0.5*Vdd - 26.8 -
GV Closed-loop gain dB
0.5*Vdd < GAIN < 0.75*Vdd - 30 -
GAIN1>0.75*Vdd - 32.8 -
ΔGV Gain matching - - - ±1 dB
CT Crosstalk f = 1 kHz - 70 - dB
Supply voltage rejection fr = 100 Hz, Vr = 0.5 V,
SVRR - 60 - dB
ratio CSVR = 10 µF
Tr, Tf Rise and fall times PWM signal 50% duty cycle - 24 40 ns
Internal oscillator with
fSW Switching frequency - 500 - kHz
external Rosc = 33 kΩ
Output switching With internal oscillator by
fSWR 450 - 550 kHz
frequency range changing Rosc (1)
VinH Digital input high (H) - 2.0 - -
V
VinL Digital input low (L) - - 0.8
STBY < 0.5 V Mute = 'X' Standby
Function
Standby, Mute, Play STBY > 2.5 V Mute < 0.8 V Mute
mode
STBY > 2.5 V Mute > 2.5 V Play
AMUTE Mute attenuation VMUTE = 1 V 60 80 - dB

Notes:
SW = 10 / [(12 * ROSC + 110) * 4] kHz, fSYNCLK = 2 * fSW (where ROSC is in kΩ and fSW in kHz) with
(1)f 6

Rosc = 33 kΩ.

DocID027638 Rev 1 9/24

Electrical specifications TDA7492E
3.4 Stereo BTL application
All specifications are for VCC = 22 V, Rosc = 33 kΩ, f = 1 kHz, Tamb = 25 °C, unless
otherwise specified.
Table 6: Stereo BTL application
Symbol Parameter Condition Min. Typ. Max. Unit
RL = 6 Ω, THD = 10% - 41 -
RL = 6 Ω, THD = 1% - 32 -

Po Output power RL = 6 Ω, THD = 10%, W

- 57 -
VCC = 26 V
RL = 6 Ω, THD = 1%,
- 44 -
VCC = 26 V
THD Total harmonic distortion Po = 1 W, fin = 1 kHz - 0.04 - %
Inputs shorted and
VN Total output noise connected to GND, - 150 - µV
A curve, GV = 20.8 dB

3.5 Parallel BTL (mono) application

All specifications are for VCC = 22 V, Rosc = 33 kΩ, f = 1 kHz, Tamb = 25 °C, INPB, INNB
connected to VDDS, unless otherwise specified.
Table 7: Stereo BTL (mono) application
Symbol Parameter Condition Min. Typ. Max. Unit
RL = 3 Ω, THD = 10% - 90 -
RL = 3 Ω, THD = 1% - 70 -
RL = 3 Ω, THD = 10%,
Po Output power - 110 - W
Vcc = 26 V
RL = 3 Ω, THD = 1%,
- 86 -
VCC = 26V
THD Total harmonic distortion Po = 1 W, fin = 1 kHz - 0.04 - %
Inputs shorted and
VN Total output noise connected to GND, - 150 - µV
A curve, GV = 20.8 dB

10/24 DocID027638 Rev 1

TDA7492E Application information

4 Application information
4.1 Gain setting
The four gain settings of the TDA7492E are set by GAIN (pin 31). Internally, gain is set by
changing the feedback resistors of the amplifier.
Table 8: Gain settings
Voltage on GAIN pin Total gain Application recommendations
VGAIN < 0.25*VDDS 20.8 dB GAIN pin connected to SGND
0.25*VDDS < VGAIN < 0.5*VDDS 26.8 dB External resistor divider <100 k
0.5*VDDS < VGAIN < 0.75*VDDS 30 dB External resistor divider <100 k
VGAIN > 0.75*VDDS 32.8 dB GAIN pin connected to VDDS

4.2 Stereo and mono applications

The TDA7492E can be used in stereo BTL or in mono BTL configuration. When the input
pins, INPB and INNB of the right channel are directly shorted to VDDS (without input
capacitors) the device is in mono configuration as shown in Figure 3: "Mono BTL settings".
Figure 3: Mono BTL settings

OUTPB
INPA
INNA OUTPA LC
IC Filter
OUTNA
INPB
INNB
OUTNB

4.3 Smart protections

4.3.1 Overcurrent protection (OCP)
If the overcurrent protection threshold is reached, the power stage will be shut down
immediately. The device will recover automatically when the fault is removed.
The overcurrent protection scheme is shown in Table 9: "Overcurrent protection". Two
typical thresholds are as follows.
Table 9: Overcurrent protection
I (Shutdown)
High side (A) 11.2
Low side (A) 10.0

DocID027638 Rev 1 11/24

Application information TDA7492E
The thresholds in MUTE mode are reduced to about 1/2 and two typical thresholds are as
follows.
Table 10: Overcurrent protection (mute mode)
I (Shutdown)
High side (A) 6.2
Low side (A) 5.9

4.3.2 Thermal protection

When internal die temperature exceeds 140 °C, the device enters into Mute by pulling the
MUTE pin low first.
When internal die temperature exceeds 150 °C, the device directly shuts down the power
stage. The TDA7492E automatically recovers when the temperature become lower than
the threshold.

4.3.3 Power limit

A built-in power limit is used to limit the output voltage level below the supply rail by limiting
the duty cycle. The limit level is set through the voltage at PLIMIT (pin 30). The pin voltage
is set by the following equation:
(𝑅𝑅𝑅𝑅𝑅𝑅//400𝑘𝑘)
𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉 = 𝑉𝑉𝐷𝐷𝐷𝐷 � �
(𝑅𝑅𝑅𝑅𝑅𝑅//400𝑘𝑘 + 𝑅𝑅𝑅𝑅𝑅𝑅)

Figure 4: Recommended power limit pin connections

VDDS

Rup
PLIMIT
400 kΩ

Rdn
Power
Limiter

It is recommended that external resistors are less than 40 kΩ if a voltage divider is used as
shown in Figure 4: "Recommended power limit pin connections". The relationship of the
maximum duty cycle (Dmax) and the voltage at PLIMIT is:

𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉𝑉
�8.8 × 2 × 𝑉𝑉𝑐𝑐𝑐𝑐 × 𝑅𝑅𝑅𝑅 + 1�
𝑉𝑉𝑐𝑐𝑐𝑐 −
𝐷𝐷𝐷𝐷𝐷𝐷𝐷𝐷 = 𝑅𝑅𝑙𝑙𝑙𝑙𝑙𝑙𝑙𝑙 × 2 × 𝑅𝑅𝑅𝑅
2

Where VCC is the power supply voltage, VPLIMIT is the voltage applied at the PLIMIT pin, Rs
is the series resistance including Rdson of power transistor, output filter resistance and
bonding wire resistance. Rload is the load resistance.

12/24 DocID027638 Rev 1

TDA7492E Application information
An example of maximum effective control voltage at PLIMIT vs. power supply and load
resistance is shown in Table 11: "Max effective voltage of PLIMIT pin vs. power supply and
load".
Table 11: Max effective voltage of PLIMIT pin vs. power supply and load
Power supply
Rload
7V 13 V 24 V
4Ω 0.71 V 1.32 V 2.44 V
6Ω 0.74 V 1.37 V 2.53 V
8Ω 0.75 V 1.39 V 2.57 V

4.4 Mode selection

The three operating modes of the TDA7492E are set by two inputs: STBY (pin 20) and
MUTE (pin 21).
• Standby mode: all circuits are turned off, very low current consumption.
• Mute mode: inputs are connected to ground and the positive and negative PWM
outputs are at 50% duty cycle
• Play mode: the amplifiers are active.
The protection functions of the TDA7492E are implemented by pulling down the voltages of
the STBY and MUTE inputs shown in Figure 5: "Standby and mute circuits". The input
current of the corresponding pins must be limited to 200 µA.
Table 12: Mode settings
Mode STBY MUTE
Standby L(1) X (don’t care)
Mute H L
Play H H

Notes:
(1)Drive levels defined in Table 5: "Electrical specifications".

DocID027638 Rev 1 13/24

Application information TDA7492E
Figure 5: Standby and mute circuits

Standby R2
20
STBY
3.3 V 33 kΩ

0V C7 2.2 µF
TDA7492E

Mute R4
21
MUTE
3.3 V 33 kΩ

0V C15 2.2 µF

Figure 6: Turn-on/off sequence for minimizing speaker “pop”

14/24 DocID027638 Rev 1

TDA7492E Schematic diagram

5 Schematic diagram
Figure 7: Application circuit

L4
C1
22uH
R15
1uF C3
C2 1nF R6 8R
C28
22R C40 L-OUTPUT
1uF C4 220nF
1nF 220nF Load=6 ohm
C26 L+ 1
C25 C30
J1 C5 INNB *220nF 2
1uF
100nF L-
INPUT 100nF R1 C27 MONO
3 L- OUT C24 C41 J13
For 330pF
R7 47k 220nF
4 L+ Single-Ended 220nF
J7 Input 22R R16 MONO
1 R- OUTPUT
8R L+, L- Only
2 R+ C6 L3
FREQUENCY SHIFT 100nF
22uH
R9 1
MONO VCC
Q1 180K C23 + 2
INPUT 2200uF GND
KTC3875(S)
L+, L- Only 3 35V
R13 L1 J2
C8
1
R3
47k 100nF
2 39K 22uH
R14
PS 100k R17
R5 C18
8R
22R 220nF R-OUTPUT
R10 R11 J11 C42 Load=6 ohm
J6
INNB 220nF R+ 2
100k 100k J10 J5 C19
R12 C31 C20
1
100k 100nF *220nF
J3 J8 1uF R-
INNB C10 MONO J14
For Single-Ended C21 C43
MONO OUT
Input and 100nF C22
Config 330pF 220nF
MONO Config
220nF R18
C11
8R
3V3 1uF C13 L2
PS
C12 1nF
J4 22uH
1uF C14
S2 MUTE
R19 R4 1nF
1 2 C17
3 4.7uF
4.7k
33k + C15
S1 STBY 2.2uF 10V
1 2 R2 16V
3 + C7 C16
750k 10uF
2.2uF
R8 VCC 16V 10V
OUT IC2 IN
1 L4931CZ33 3
1.2k
C29 2 GND C9
2.2uF 100nF

TDA7492E CLASS-DAMPLIFIER

DocID027638 Rev 1 15/24

Characterization curves TDA7492E

6 Characterization curves
Unless otherwise stated, measurements were made under the following conditions:
VCC = 22 V, Rl = 6 Ω, f = 1 kHz, Gv = 20.8 dB, ROSC = 33 kΩ, Tamb = 25 °C.
Note: Maximum output power must be derated according to case temperature.

6.1 Stereo configuration

The following characterization curves were made using the TDA7492E demonstration
board (Figure 7: "Application circuit"). The characterization curves were made under the
following test conditions:
Vs = 7 and 26 V, Rl = 6 Ω, Rosc = 33 kΩ, Cosc = 100 nF, Gain = 20.8 dB and Tamb = 25°C
unless otherwise specified.
Figure 9: THD vs. Pout (Vs = 26 V, f = 1 kHz)
Figure 8: Output power vs. supply voltage 10
5
2
1
0.5 Vs=26V, Rl=6 Ω, f=1kHz
THD (%)
0.2
0.1
0.05
0.02
0.01
0.005
0.002
0.001
10m 20m 50m 100m 200m 500m 1 2 5 10 20 50
Pout (W)

Figure 10: THD vs. Pout (Vs = 26 V, f = 100 Hz) Figure 11: THD vs. Pout (Vs = 26 V, f = 6 kHz)
10 10
5 5

2 2
1 1 Vs=26V, Rl =6 Ω , f=6kHz
Vs=26V, Rl =6 Ω , f=100 Hz
0.5 0.5

0.2 0.2
THD (%)
THD (%)

0.1 0.1
0.05 0.05

0.02 0.02
0.01 0.01
0.005 0.005

0.002 0.002
0.001 0.001
10m 20m 50m 100m 200m 500m 1 2 5 10 20 50 10m 20m 50m 100m 200m 500m 1 2 5 10 20 50
Pout (W) Pout (W)

16/24 DocID027638 Rev 1

TDA7492E Characterization curves
Figure 12: THD vs. frequency (Vs = 26 V, Po = 1 W) Figure 13: Frequency response Vs = 26 V
10 +2
5 +1.5
+1
2 +0.5
1 +0
0.5 Vs=26V, Rl =6 Ω , Po= 1W -0.5
-1
THD (%)

0.2 -1.5

dBrA
0.1 -2 Rl =6 Ω , Po= 1W
-2.5
0.05
-3
0.02 -3.5
0.01 -4
-4.5
0.005
-5
0.002 -5.5
-6
0.001 20 50 100 200 500 1k 2k 5k 10k 20k
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)
Frequency (Hz)

Figure 14: Signal-to-noise ratio (Vs = 26 V, gain = Figure 15: Signal-to-noise ratio (Vs = 26 V, gain =
32.6 dB, not weighted) 20.6 dB, not weighted)

+0 +0
-10 -10
-20 -20
-30 -30
-40 Gain = 32.6dB, No -Weight -40 Gain=20.6dB, No-Weight
-50 Vs=26V,Rl=6 Ω ,Po=1W, f=1kHz -50 Vs=26V, Rl=6 Ω, Po= 1W, f=1kHz
dBrA
dBrA

-60 -60
-70 -70
-80 -80
-90 -90
-100 -100
-110 -110

-120 -120
20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz) Frequency (Hz)

DocID027638 Rev 1 17/24

Characterization curves TDA7492E
Figure 16: Signal-to-noise ratio (Vs = 26 V, gain = Figure 17: Signal-to-noise ratio (Vs = 26 V, gain =
32.6 dB, A-weighted) 20.6 dB, A-weighted)

+0
-10
-20
-30
-40 Gain=20.6dB, A-Weight
-50 Vs=26V, Rl=6 Ω, Po=1W, f=1kHz

dBrA
-60
-70
-80
-90
-100
-110
-120
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)

Figure 18: Crosstalk Vs = 26 V Figure 19: FFT (0 dB) Vs = 26 V

+0 +0
T
-10 -10
-20 -20 Gain=32.6dB, Vs=26V,
-30 -30 Rl =6 Ω , Po=1W, f=1kHz
-40 -40
-50 Gain= 32.6dB, Vs=26V, -50
Rl =6 Ω , Po=1W, f=1kHz -60
dBrA

-60
-70 -70
dB

-80 -80
-90 -90
-100 -100
-110 -110
-120 -120
-130 -130
-140 -140
-150 -150
20 50 100 200 500 1k 2k 5k 10k 20k 20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz) Frequency (Hz)

18/24 DocID027638 Rev 1

TDA7492E Characterization curves
Figure 20: FFT (-60 dB) Vs = 26 V
+0
-10
-20 Gain=32.6dB, Vs=26V,
-30 Rl =6 Ω , Po=1W, f=1kHz
-40
-50
-60
dBrA

-70
-80
-90
-100
-110
-120
-130
-140
-150
20 50 100 200 500 1k 2k 5k 10k 20k
Frequency (Hz)

DocID027638 Rev 1 19/24

Package information TDA7492E

7 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.

7.1 PowerSSO36 EPU package information

The device comes in a 36-pin PowerSSO package with exposed pad up (EPU).
Figure 21: "PowerSSO-36 EPU package outline" shows the package outline and Table 13:
"PowerSSO-36 EPU package mechanical data" gives the dimensions.

20/24 DocID027638 Rev 1

TDA7492E Package information
Figure 21: PowerSSO-36 EPU package outline

7618147_F

DocID027638 Rev 1 21/24

Package information TDA7492E
Table 13: PowerSSO-36 EPU package mechanical data
Dimensions in mm Dimensions in inches
Symbol
Min. Typ. Max. Min. Typ. Max.
A 2.15 - 2.45 0.085 - 0.096
A2 2.15 - 2.35 0.085 - 0.093
a1 0 - 0.10 0 - 0.004
b 0.18 - 0.36 0.007 - 0.014
c 0.23 - 0.32 0.009 - 0.013
D 10.10 - 10.50 0.398 - 0.413
E 7.40 - 7.60 0.291 - 0.299
e - 0.5 - - 0.020 -
e3 - 8.5 - - 0.335 -
F - 2.3 - - 0.091 -
G - - 0.10 - - 0.004
H 10.10 - 10.50 0.398 - 0.413
h - - 0.40 - - 0.016
k 0 - 8 degrees 0 - 8 degrees
L 0.55 - 0.85 0.022 - 0.033
M - 4.30 - - 0.169 -
N - - 10 degrees - - 10 degrees
O - 1.20 - - 0.047 -
Q - 0.80 - - 0.031 -
S - 2.90 - - 0.114 -
T - 3.65 - - 0.144 -
U - 1.00 - - 0.039 -
X 4.10 - 4.70 0.161 - 0.185
Y 4.90 - 7.10 0.193 - 0.280

22/24 DocID027638 Rev 1

TDA7492E Revision history

8 Revision history

Table 14: Document revision history

Date Revision Changes
24-Feb-2017 1 Initial release

DocID027638 Rev 1 23/24

 TDA7492E

IMPORTANT NOTICE – PLEASE READ CAREFULLY

STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and
improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST
products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order
acknowledgement.

Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the
design of Purchasers’ products.

No license, express or implied, to any intellectual property right is granted by ST herein.

Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product.

ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners.

Information in this document supersedes and replaces information previously supplied in any prior versions of this document.

© 2017 STMicroelectronics – All rights reserved

24/24 DocID027638 Rev 1