HCF4015B

DUAL 4-STAGE STATIC SHIFT REGISTER WITH

SERIAL INPUT/PARALLEL OUTPUT

■ MEDIUM SPEED OPERATION 12 MHz (Typ.)

CLOCK RATE AT VDD - VSS = 10V
■ FULLY STATIC OPERATION
■ 8 MASTER-SLAVE FLIP-FLOPS PLUS
INPUT AND OUTPUT BUFFERING
■ HIGH NOISE IMMUNITY
■ QUIESCENT CURRENT SPECIFIED UP TO DIP SOP
20V
■ 5V, 10V AND 15V PARAMETRIC RATINGS
■ INPUT LEAKAGE CURRENT ORDER CODES
II = 100nA (MAX) AT VDD = 18V TA = 25°C PACKAGE TUBE T&R
■ 100% TESTED FOR QUIESCENT CURRENT
DIP HCF4015BEY
■ MEETS ALL REQUIREMENTS OF JEDEC
SOP HCF4015BM1 HCF4015M013TR
JESD13B "STANDARD SPECIFICATIONS
FOR DESCRIPTION OF B SERIES CMOS
DEVICES"
four stages on both registers. All register stages
DESCRIPTION are D-TYPE, MASTER-SLAVE flip-flops. The
HCF4015B is a monolithic integrated circuit logic level present at the DATA input is transferred
fabricated in Metal Oxide Semiconductor into the first register stage and shifted over one
technology available in DIP and SOP packages. stage at each positive going clock transition. The
HCF4015B consists of two identical, independent, resetting of all stages is accomplished by a high
4 stage serial-input/parallel-output registers. level on the reset line. It is possible to expand the
Each register has independent CLOCK and register to 8 stages using one HCF4015B
RESET inputs as well as a single serial DATA package and to expand to more than 8 stages by
input. "Q" outputs are available from each of the using addition HCF4015Bs.

PIN CONNECTION

September 2002 1/10

HCF4015B

INPUT EQUIVALENT CIRCUIT PIN DESCRIPTION

PIN No SYMBOL NAME AND FUNCTION

CLOCK A
1, 9 Clock Input
CLOCK B
RESET A
6, 14 Reset Input
RESET B
DATA A
7, 15 Data Inputs
DATA B
5, 4, 3, 10 QnA Outputs A-Stage
13, 12, 11, 2 QnB Outpus B-Stage
8 VSS Negative Supply Voltage
16 VDD Positive Supply Voltage

FUNCTIONAL DIAGRAM

TRUTH TABLE

CLOCK D R Q1 Qn

L L L Qn - 1
H L H Qn - 1
X L Q1 Qn - (NO CHANGE)
X X H L 0
X : Don’t Care

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 HCF4015B

LOGIC DIAGRAM

ABSOLUTE MAXIMUM RATINGS

Symbol Parameter Value Unit

VDD Supply Voltage -0.5 to +22 V
VI DC Input Voltage -0.5 to VDD + 0.5 V
II DC Input Current ± 10 mA
PD Power Dissipation per Package 200 mW
Power Dissipation per Output Transistor 100 mW
Top Operating Temperature -55 to +125 °C
Tstg Storage Temperature -65 to +150 °C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied.
All voltage values are referred to VSS pin voltage.

RECOMMENDED OPERATING CONDITIONS

Symbol Parameter Value Unit

VDD Supply Voltage 3 to 20 V
VI Input Voltage 0 to VDD V
Top Operating Temperature -55 to 125 °C

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HCF4015B

DC SPECIFICATIONS

Test Condition Value

Symbol Parameter TA = 25°C -40 to 85°C -55 to 125°C Unit

VI VO |IO| VDD
(V) (V) (µA) (V)
Min. Typ. Max. Min. Max. Min. Max.
IL Quiescent Current 0/5 5 0.04 5 150 150
0/10 10 0.04 10 300 300
µA
0/15 15 0.04 20 600 600
0/20 20 0.08 100 3000 3000
VOH High Level Output 0/5 <1 5 4.95 4.95 4.95
Voltage 0/10 <1 10 9.95 9.95 9.95 V
0/15 <1 15 14.95 14.95 14.95
VOL Low Level Output 5/0 <1 5 0.05 0.05 0.05
Voltage 10/0 <1 10 0.05 0.05 0.05 V
15/0 <1 15 0.05 0.05 0.05
VIH High Level Input 0.5/4.5 <1 5 3.5 3.5 3.5
Voltage 1/9 <1 10 7 7 7 V
1.5/13.5 <1 15 11 11 11
VIL Low Level Input 4.5/0.5 <1 5 1.5 1.5 1.5
Voltage 9/1 <1 10 3 3 3 V
13.5/1.5 <1 15 4 4 4
IOH Output Drive 0/5 2.5 <1 5 -1.36 -3.2 -1.1 -1.1
Current 0/5 4.6 <1 5 -0.44 -1 -0.36 -0.36
mA
0/10 9.5 <1 10 -1.1 -2.6 -0.9 -0.9
0/15 13.5 <1 15 -3.0 -6.8 -2.4 -2.4
IOL Output Sink 0/5 0.4 <1 5 0.44 1 0.36 0.36
Current 0/10 0.5 <1 10 1.1 2.6 0.9 0.9 mA
0/15 1.5 <1 15 3.0 6.8 2.4 2.4
II Input Leakage
0/18 Any Input 18 ±10-5 ±0.1 ±1 ±1 µA
Current
CI Input Capacitance Any Input 5 7.5 pF
The Noise Margin for both "1" and "0" level is: 1V min. with VDD =5V, 2V min. with VDD=10V, 2.5V min. with VDD=15V

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 HCF4015B

DYNAMIC ELECTRICAL CHARACTERISTICS (Tamb = 25°C, CL = 50pF, RL = 200KΩ, tr = tf = 20 ns)

Test Condition Value (*) Unit

Symbol Parameter
VDD (V) Min. Typ. Max.
CLOCKED OPERATION
tPLH tPHL Propagation Delay Time 5 160 320
(carry out or decoded out 10 80 160 ns
lines)
15 60 120
tTHL tTLH Transition Time (carry out 5 100 200
or decoded out lines) 10 50 100 ns
15 40 80
fCL Maximum Clock Input 5 3 6
Frequency 10 6 12 MHz
15 8.5 17
tW Clock Pulse Width 5 180 90
10 80 40 ns
15 50 25
tr , tf (1) Clock Input Rise or Fall 5 15
Time 10 15 µs
15 15
tsetup Data Setup Time 5 70 35
10 40 20 ns
15 30 15
RESET OPERATION
tPLH, tPHL Propagation Delay Time 5 200 400
10 100 200 ns
15 80 160
tW Reset Pulse Width 5 200 100
10 80 40 ns
15 60 30
(*) Typical temperature coefficient for all VDD value is 0.3 %/°C.
(1) If more than one unit is cascaded in the parallel clocked application, trCL should be made less than or equal to the sum of the fixed prop-
agation delay at 15 pF and the transmission time of the carry output driving stage of the estimated capacitive load.

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HCF4015B

TEST CIRCUIT

CL = 50pF or equivalent (includes jig and probe capacitance)

RL = 200KΩ
RT = ZOUT of pulse generator (typically 50Ω)

WAVEFORM 1 : MINIMUM PULSE WIDTH, PROPAGATION DELAY TIME (f=1MHz; 50% duty cycle)

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 HCF4015B

WAVEFORM 2 : MINIMUM SETUP TIME (f=1MHz; 50% duty cycle)

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HCF4015B

Plastic DIP-16 (0.25) MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.

a1 0.51 0.020

B 0.77 1.65 0.030 0.065

b 0.5 0.020

b1 0.25 0.010

D 20 0.787

E 8.5 0.335

e 2.54 0.100

e3 17.78 0.700

F 7.1 0.280

I 5.1 0.201

L 3.3 0.130

Z 1.27 0.050

P001C

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 HCF4015B

SO-16 MECHANICAL DATA

mm. inch
DIM.
MIN. TYP MAX. MIN. TYP. MAX.
A 1.75 0.068
a1 0.1 0.2 0.003 0.007
a2 1.65 0.064
b 0.35 0.46 0.013 0.018
b1 0.19 0.25 0.007 0.010
C 0.5 0.019
c1 45˚ (typ.)
D 9.8 10 0.385 0.393
E 5.8 6.2 0.228 0.244
e 1.27 0.050
e3 8.89 0.350
F 3.8 4.0 0.149 0.157
G 4.6 5.3 0.181 0.208
L 0.5 1.27 0.019 0.050
M 0.62 0.024
S 8 ˚ (max.)

PO13H

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HCF4015B

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consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from
its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications
mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information
previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or
systems without express written approval of STMicroelectronics.
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