Chapter 4 (Digital logic and Computer Design-Morris Mano)

Combinational Logic Design

Department of Electrical Engineering

Faculty of Engineering & Computing
National University of Modern Languages
Course Instructor: Dr. Sheraz Alam Khan
[email protected]

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Lecture Outline
• Combinational logic vs Sequential logic
• Design Procedure
• Adders: HA and FA
• Subtractors: HS and FS
• Code conversion
• Analysis Procedure
• Multi-level NAND and NOR Implementation (Optional)
• Exclusive-OR and Exclusive-NOR gates
• Even/odd functions
• Parity generation and checking
 4-1 INTRODUCTION
Logic circuits for digital systems may be combinational or
sequential.
• A combinational circuit consists of logic gates whose
outputs at any time are determined from only the present
combination of inputs.
• In contrast, Sequential circuits employ storage elements in
addition to logic gates. Their outputs are a function of the
inputs and the state of the storage elements.

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 COMBINATIONAL CIRCUITS
• A combinational circuit consists of an interconnection of logic
gates. Combinational logic gates react to the values of the signals
at their inputs and produce the value of the output signal,
transforming binary information from the given input data to a
required output data. A block diagram of a combinational circuit is
shown in Fig. 4.1

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 4-2 DESIGN PROCEDURE
1. Problem statement/Circuit specification (Given)
2. Determine the required number of inputs and outputs
and assign a symbol to each.
3. Derive the truth table
4. Obtain the simplified Boolean functions for each output
(K-Map method)
5. Logic Diagram

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 4-3 ADDERS
Adders are combinational logic circuits that are used for very basic
binary arithmetic operation of addition
• Half Adder (HA):A combinational circuit that performs the
addition of two binary bits is called a half adder
• Full Adder (FA): A combinational circuit that performs the
addition of three binary bits is called a full adder

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Half Adder

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Various logic implementation of
Half Adder

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Full Adder

𝑺 𝒙, 𝒚, 𝒛 = ෍(𝟏, 𝟐, 𝟒, 𝟕)

𝑪 𝒙, 𝒚, 𝒛 = ෍(𝟑, 𝟓, 𝟔, 𝟕)

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Alternate Implementation

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 4-4 SUBTRACTORS
Similar to addition, the subtraction is also very common arithmetic operation.
• Half Subtractor (HS):A combinational circuit that performs the subtraction
of two binary bits is called a half subtractor
• Full Subtractor (FA): A combinational circuit that performs the subtraction
of three binary bits is called a full subtractor
Needs a to borrow 1 from
left which is equivalent of 0 X (input)
2 (binary) 1 Y (input)
1 Difference
(output)

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Half Subtractor

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Full Subtractor

𝑫 𝒙, 𝒚, 𝒛 = ෍(𝟏, 𝟐, 𝟒, 𝟕)

𝑩 𝒙, 𝒚, 𝒛 = ෍(𝟏, 𝟐, 𝟑, 𝟕)
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 4-5 Code Conversion
• The availability of a large variety of codes for the same discrete
elements of information results in the use of different codes by
different digital systems.
• It is sometimes necessary to use the output of one system as the
input to another. A conversion circuit must be inserted between
the two systems if each uses different codes for the same
information.
• Thus, a code converter is a circuit that makes the two systems
compatible even though each uses a different binary code

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Example: BCD to Excess-III code converter
𝑾 𝑨, 𝑩, 𝑪, 𝑫 = ෍(𝟓, 𝟔, 𝟕, 𝟖, 𝟗)

𝑿 𝑨, 𝑩, 𝑪, 𝑫 = ෍(𝟏, 𝟐, 𝟑, 𝟒, 𝟗)

𝒀 𝑨, 𝑩, 𝑪, 𝑫 = ෍(𝟎, 𝟑, 𝟒, 𝟕, 𝟖)

Z 𝑨, 𝑩, 𝑪, 𝑫 = σ(𝟎, 𝟐, 𝟒, 𝟔, 𝟖)

𝒅 𝑨, 𝑩, 𝑪, 𝑫) = ෍(𝟏𝟎, 𝟏𝟏, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒, 𝟏𝟓)

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Example: 84-2-1 to BCD converter
INPUTS OUTPUT
ABCD WXYZ
𝑾 𝑨, 𝑩, 𝑪, 𝑫) = ෍(𝟖, 𝟏𝟓)

𝑿 𝑨, 𝑩, 𝑪, 𝑫) = ෍(𝟒, 𝟗, 𝟏𝟎, 𝟏𝟏)

𝒀 𝑨, 𝑩, 𝑪, 𝑫) = ෍(𝟓, 𝟔, 𝟗, 𝟏𝟎)

𝒁 𝑨, 𝑩, 𝑪, 𝑫) = ෍(𝟓, 𝟕, 𝟗, 𝟏𝟏, 𝟏𝟓)

𝒅 𝑨, 𝑩, 𝑪, 𝑫) = ෍(𝟏, 𝟐, 𝟑, 𝟏𝟐, 𝟏𝟑, 𝟏𝟒)

Don’t Care
Conditions Homework: K-Map
simplification and logic
implementation
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 4-6 Analysis Procedure
The analysis of a combinational circuit requires that we determine the
function that the circuit implements. This task starts with a given logic
diagram and culminates with a set of Boolean functions, a truth table, or,
possibly, an explanation of the circuit operation.
1. Label all gate outputs that are a function of input variables with arbitrary
symbols— but with meaningful names. Determine the Boolean functions
for each gate output.
2. Label the gates that are a function of input variables and previously
labeled gates with other arbitrary symbols. Find the Boolean functions for
these gates.
3. Repeat the process outlined in step 2 until the outputs of the circuit are
obtained.
4. By repeated substitution of previously defined functions, obtain the
output Boolean functions in terms of input variables.
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Example: Analyze the following Logic circuit

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𝑭𝟏 𝑨, 𝑩, 𝑪 = ෍(𝟏, 𝟐, 𝟒, 𝟕)

𝑭𝟐 𝑨, 𝑩, 𝑪 = ෍(𝟑, 𝟓, 𝟔, 𝟕)

Which function does this circuit

performs?
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 4-7 Multi-level NAND and NOR implementation
• Combinational circuits are more conveniently constructed using NAND and
NOR gates rather then AND, OR and NOT.
• NAND and NOR are more common from H/W point of view, because they
are readily available in ICs.
• We can construct any logic diagram by only using NAND or NOR, hence they
are called Universal gates

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Multi-level NAND Implementation

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 Multi-level NAND-Procedure
To obtain the multi-level NAND diagram from the Boolean expression,
proceed as follows:
1. From the given expression, draw the logic diagram with AND, OR, and
inverter gates. Assume that both the normal and complement inputs are
available
2. Convert all AND gates to NAND gates with AND-Invert graphic symbols
3. Convert all OR gates to NAND gates with invert-OR graphic symbols
4. Check all small circles in the diagram. For every small circle that is not
compensated by another small circle along the same line, insert an
inverter (one –input NAND gate) or complement the input variable

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 Analysis Procedure – (NAND to AND-OR diagram)
• NAND diagram is given and objective is to obtained AND-OR-NOT diagram

Solution 1:
• Obtain the Boolean function F from the given
diagram.
• Find canonical forms or draw truth table
• Obtain simplified Boolean expression F using K-
MAP
• Draw SOP or POS implementation

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Solution 2: Direct Conversion

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 Multi-level NOR Implementation
To obtain the multi-level NOR diagram from the Boolean expression, proceed
as follows:
1. From the given expression, draw the logic diagram with AND, OR, and
inverter gates. Assume that both the normal and complement inputs are
available
2. Convert all OR gates to NOR gates with OR-Invert graphic symbols
3. Convert all AND gates to NOR gates with invert-AND graphic symbols
4. Check all small circles in the diagram. For every small circle that is not
compensated by another small circle along the same line, insert an
inverter (one –input Nor gate) or complement the input variable

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Design Procedure-Example

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 Analysis Procedure- NOR to OR-AND diagram
• Given a NOR diagram, objective is to obtain OR-AND diagram

Solution 1:
• Obtain the Boolean function F from the given
diagram.
• Find canonical forms or draw truth table
• Obtain simplified Boolean expression F using K-
MAP
• Draw SOP or POS implementation

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Solution 2: Direct Conversion

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Exclusive-OR and Exclusive-NOR gates

= (𝑥⨀𝑦)
x
y

𝐹 = (𝑥 ⊕ 𝑦 ⊕ 𝑧)/
= 𝑥 ⊕ 𝑦⨀𝑧
= (𝑥⨀𝑦 ⊕ 𝑧)

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Logic Implementation of X-OR gate

Commutative:
Associative:
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 Odd Function and Even Function
• Odd function: When the number of one’s in input combination is odd, the
output is 1

Odd Function

𝑬𝒗𝒆𝒏 𝒇𝒖𝒏𝒄𝒕𝒊𝒐𝒏 = ෍(𝟎, 𝟑, 𝟓, 𝟔)

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Four input odd function
A B C D F

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 Parity Generation and Checking
• A parity bit is an extra bit included with a binary message
to make the number of 1’s either odd or even. The
message, including the parity bit, is transmitted and then
checked at the receiving end for errors. An error is
detected if the checked parity does not correspond with
the one transmitted.
• The circuit that generates the parity bit in the transmitter is
called a parity generator. The circuit that checks the parity
in the receiver is called a parity checker.
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𝑷(𝒙, 𝒚, 𝒛) = ෍(𝟏, 𝟐, 𝟒, 𝟕)

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 Questions are guaranteed in
Life…………….Answers are not!

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