INTERRUPTS I/O

➢ When a program enters a wait loop, it will repeatedly check the device status. During
this period, the processor will not perform any function.
➢ The Interrupt request line will send a hardware signal called the interrupt signal to the
processor.
➢ On receiving this signal, the processor will perform the useful function during the
waiting period.
➢ The routine executed in response to an interrupt request is called Interrupt Service
Routine.

Fig: Transfer of control through the use of interrupts

Program 1 Interrupt Service routine

1
2

Interrupt
occurs i
here
i+1

M
➢ The processor first completes the execution of instruction i Then it loads the
PC(Program Counter) with the address of the first instruction of the ISR.
➢ After the execution of ISR, the processor has to come back to instruction i + 1.
➢ Therefore, when an interrupt occurs, the current contents of PC which point to i +1 is
put in temporary location.
➢ A return from interrupt instruction at the end of ISR reloads the PC from that temporary
storage location, causing the execution to resume at instruction i+1.
➢ When the processor is handling the interrupts, it must inform the device that its request
has been recognized so that it removes its interrupt requests signal.
➢ This may be accomplished by a special control signal called the interrupt
acknowledge signal.
➢ The task of saving and restoring the information can be done automatically by the
processor.
➢ The processor saves only the contents of program counter & status register (i.e.) it
saves only the minimal amount of information to maintain the integrity of the program
execution.
➢ Saving registers also increases the delay between the time an interrupt request is
received and the start of the execution of the ISR. This delay is called the Interrupt
Latency.
➢ Generally, the long interrupt latency in unacceptable.
➢ The concept of interrupts is used in Operating System and in Control Applications,
where processing of certain routines must be accurately timed relative to external
events. This application is also called as real-time processing.
 Hardware Interrupt:
Fig:An equivalent circuit for an open drain bus used to implement a
common interrupt request line

➢ A single interrupt request line may be used to serve „n‟ devices. All devices are
connected to the line via switches to ground.
➢ To request an interrupt, a device closes its associated switch, the voltage on INTR line
drops to 0(zero).
➢ If all the interrupt request signals (INTR1 to INTRn) are inactive, all switches are open
and the voltage on INTR line is equal to Vdd.
➢ When a device requests an interrupts, the value of INTR is the logical OR of the
requests from individual devices.
(ie) INTR = INTR1+…………+INTRn
INTR → It is used to name the INTR signal on common line it is active in the low voltage
state.
➢ Open collector or Open drain is used to drive INTR line.
➢ The Output of the Open collector (or) Open drain control is equal to a switch to the
ground that is open when gates input are in „0‟ state and closed when the gates input is
in „1‟ state.
 ➢ Resistor „R‟ is called a pull-up resistor because it pulls the line voltage upto the high
voltage state when the switches are open.
Enabling and Disabling Interrupts:
➢ The arrival of an interrupt request from an external device causes the processor to
suspend the execution of one program & start the execution of another because the
interrupt may alter the sequence of events to be executed.
➢ INTR is active during the execution of Interrupt Service Routine.
➢ There are 3 mechanisms to solve the problem of infinite loop which occurs due to
successive interruptions of active INTR signals.
➢ The following are the typical scenario.
➔ The device raises an interrupt request.
➔ The processor interrupts the program currently being executed.
➔ Interrupts are disabled by changing the control bits is PS (Processor Status
register)
➔ The device is informed that its request has been recognized & in response, it
deactivates the INTR signal.
➔ The actions are enabled & execution of the interrupted program is resumed.

Handling Multiple Devices:

When several devices requests interrupt at the same time, it raises some questions. They are.
➢ How can the processor recognize the device requesting an interrupt?
➢ Given that the different devices are likely to require different ISR, how can the
processor obtain the starting address of the appropriate routines in each case?
➢ Should a device be allowed to interrupt the processor while another interrupt is being
serviced?
➢ How should two or more simultaneous interrupt requests be handled?

Polling Scheme:
➢ If two devices have activated the interrupt request line, the ISR for the selected device
(first device) will be completed & then the second request can be serviced.
 ➢ The simplest way to identify the interrupting device is to have the ISR polls all the
encountered with the IRQ bit set is the device to be serviced
➢ IRQ (Interrupt Request) -> when a device raises an interrupt requests, the status register
IRQ is set to 1.
Merit:
➢ It is easy to implement.
Demerit:
➢ The time spent for interrogating the IRQ bits of all the devices that may not be
requesting any service.
Vectored Interrupt:
➢ Here the device requesting an interrupt may identify itself to the processor by sending
a special code over the bus & then the processor start executing the ISR.
➢ The code supplied by the processor indicates the starting address of the ISR for the
device.
➢ The code length ranges from 4 to 8 bits.
➢ The location pointed to by the interrupting device is used to store the staring address to
ISR.
➢ The processor reads this address, called the interrupt vector & loads into PC.
➢ The interrupt vector also includes a new value for the Processor Status Register.
➢ When the processor is ready to receive the interrupt vector code, it activate the interrupt
acknowledge (INTA) line.
Interrupt Nesting:
Multiple Priority Scheme:
➢ In multiple level priority scheme, we assign a priority level to the processor that can be
changed under program control.
➢ The priority level of the processor is the priority of the program that is currently being
executed.
➢ The processor accepts interrupts only from devices that have priorities higher than its
own.
➢ At the time the execution of an ISR for some device is started, the priority of the
processor is raised to that of the device.
➢ The action disables interrupts from devices at the same level of priority or lower.
Privileged Instruction:
 ➢ The processor priority is usually encoded in a few bits of the Processor Status word. It
can also be changed by program instruction & then it is writing into PS. These
instructions are called privileged instruction. This can be executed only when the
processor is in supervisor mode.
➢ The processor is in supervisor mode only when executing OS routines.
➢ It switches to the user mode before beginning to execute application program.
Privileged Exception:
➢ User program cannot accidently or intentionally change the priority of the processor &
disrupts the system operation.
➢ An attempt to execute a privileged instruction while in user mode, leads to a special
type of interrupt called the privileged exception.

Fig: Implementation of Interrupt Priority using individual Interrupt request

acknowledge lines

IN TR 1 I N TR p
Processor

Device 1 Device 2 Device p

INTA1 INTA p

Priority arbitration

➢ Each of the interrupt request line is assigned a different priority level.

➢ Interrupt request received over these lines are sent to a priority arbitration circuit in the
processor.
➢ A request is accepted only if it has a higher priority level than that currently assigned
to the processor,
Simultaneous Requests:
Daisy Chain:

➢ The interrupt request line INTR is common to all devices. The interrupt
acknowledge line INTA is connected in a daisy chain fashion such that INTA signal
propagates serially through the devices.
➢ When several devices raise an interrupt request, the INTR is activated & the
processor responds by setting INTA line to 1. this signal is received by device.
➢ Device1 passes the signal on to device2 only if it does not require any service.
➢ If devices1 has a pending request for interrupt blocks that INTA signal & proceeds
to put its identification code on the data lines.
➢ Therefore, the device that is electrically closest to the processor has the highest
priority.
Merits:
➢ It requires fewer wires than the individual connections.
Arrangement of Priority Groups:
➢ Here the devices are organized in groups & each group is connected at a different
priority level.
➢ Within a group, devices are connected in a daisy chain.
Controlling Device Requests:
KEN → Keyboard Interrupt Enable
DEN → Display Interrupt Enable
KIRQ / DIRQ → Keyboard / Display unit requesting an interrupt.
➢ There are two mechanisms for controlling interrupt requests.
➢ At the devices end, an interrupt enable bit in a control register determines whether the
device is allowed to generate an interrupt requests.
➢ At the processor end, either an interrupt enable bit in the PS (Processor Status) or a
priority structure determines whether a given interrupt requests will be accepted.
Initiating the Interrupt Process:
➢ Load the starting address of ISR in location INTVEC (vectored interrupt).
➢ Load the address LINE in a memory location PNTR. The ISR will use this location as a
pointer to store the i/p characters in the memory.
➢ Enable the keyboard interrupts by setting bit 2 in register CONTROL to 1.
➢ Enable interrupts in the processor by setting to 1, the IE bit in the processor status
register PS.
DIRECT MEMORY ACCESS
➢ A special control unit may be provided to allow the transfer of large block of data at
high speed directly between the external device and main memory , without continuous
intervention by the processor. This approach is called DMA.
➢ DMA transfers are performed by a control circuit called the DMA Controller.
➢ To initiate the transfer of a block of words , the processor sends,
✓ Starting address
✓ Number of words in the block
✓ Direction of transfer.

➢ When a block of data is transferred , the DMA controller increment the memory address
for successive words and keep track of number of words and it also informs the
processor by raising an interrupt signal.
➢ While DMA control is taking place, the program requested the transfer cannot continue
and the processor can be used to execute another program.
➢ After DMA transfer is completed, the processor returns to the program that requested
the transfer.
Fig: Registes in a DMA Interface

R/W → Determines the direction of transfer.

When
R/W =1, DMA controller read data from memory to I/O device.
R/W =0, DMA controller perform write operation.
Done Flag=1, the controller has completed transferring a block of data and is ready to receive
another command.
IE=1, it causes the controller to raise an interrupt (interrupt Enabled) after it has completed
transferring the block of data.
IRQ=1, it indicates that the controller has requested an interrupt.
Fig: Use of DMA controllers in a computer system

Main
Processor memory

System bus

Disk/DMA DMA Keyboard

controller controller Printer

Disk Disk Network

Interface

➢ A DMA controller connects a high speed network to the computer bus. The disk
controller two disks, also has DMA capability and it provides two DMA channels.
➢ To start a DMA transfer of a block of data from main memory to one of the disks, the
program write s the address and the word count inf. into the registers of the
corresponding channel of the disk controller.
➢ When DMA transfer is completed, it will be recorded in status and control registers of
the DMA channel (i.e.) done bit=IRQ=IE=1.
Cycle Stealing:
➢ Requests by DMA devices for using the bus are having higher priority than processor
requests.
➢ Top priority is given to high speed peripherals such as,
✓ Disk
✓ High speed Network Interface and Graphics display device.
➢ Since the processor originates most memory access cycles, the DMA controller can be
said to steal the memory cycles from the processor.
➢ This interviewing technique is called Cycle stealing.
Burst Mode:
➢ The DMA controller may be given exclusive access to the main memory to transfer a
block of data without interruption. This is known as Burst/Block Mode
Bus Master:
➢ The device that is allowed to initiate data transfers on the bus at any given time is called
the bus master.
Bus Arbitration:
➢ It is the process by which the next device to become the bus master is selected and the
bus mastership is transferred to it.
Types:
➢ There are 2 approaches to bus arbitration. They are,
✓ Centralized arbitration ( A single bus arbiter performs arbitration)
✓ Distributed arbitration (all devices participate in the selection of next bus
master).
Centralized Arbitration:
➢ Here the processor is the bus master and it may grants bus mastership to one of
its DMA controller.
➢ A DMA controller indicates that it needs to become the bus master by activating
the Bus Request line (BR) which is an open drain line.
➢ The signal on BR is the logical OR of the bus request from all devices connected
to it.
➢ When BR is activated the processor activates the Bus Grant Signal (BGI) and
indicated the DMA controller that they may use the bus when it becomes free.
➢ This signal is connected to all devices using a daisy chain arrangement.
➢ If DMA requests the bus, it blocks the propagation of Grant Signal to other
devices and it indicates to all devices that it is using the bus by activating open
collector line, Bus Busy (BBSY).
 Fig:A simple arrangement for bus arbitration using a daisy chain
B BS Y

BR

Processor

DMA DMA
controller controller
BG1 1 BG2 2

Fig: Sequence of signals during transfer of bus mastership for the

devices

DMA controller 2
asserts the BR signal. Time
Processor asserts
BR
the BG1 signal
BG1 BG1 signal propagates
to DMA#2.
BG2

B BS Y

Bus
master
Processor DMA controller 2 Processor

Processor relinquishes control

of the bus by setting BBSY to 1.

➢ The timing diagram shows the sequence of events for the devices connected to the
processor is shown.
➢ DMA controller 2 requests and acquires bus mastership and later releases the bus.
 ➢ During its tenture as bus master, it may perform one or more data transfer.
➢ After it releases the bus, the processor resources bus mastership
Distributed Arbitration:
➢ It means that all devices waiting to use the bus have equal responsibility in carrying out
the
arbitration process.
Fig:A distributed arbitration scheme

➢ Each device on the bus is assigned a 4 bit id.

➢ When one or more devices request the bus, they assert the Start-Arbitration signal &
place their 4 bit ID number on four open collector lines, ARB0 to ARB3.
➢ A winner is selected as a result of the interaction among the signals transmitted over
these lines.
➢ The net outcome is that the code on the four lines represents the request that has the
highest ID number.
➢ The drivers are of open collector type. Hence, if the i/p to one driver is equal to 1, the
i/p to another driver connected to the same bus line is equal to „0‟(ie. bus the is in low-
voltage state).
E.g.:
➢ Assume two devices A & B have their ID 5 (0101), 6(0110) and their code is 0111.
➢ Each device compares the pattern on the arbitration line to its own ID starting from
MSB.
➢ If it detects a difference at any bit position, it disables the drivers at that bit position. It
does this by placing „0‟ at the i/p of these drivers.

➢ In our e.g. „A‟ detects a difference in line ARB1; hence it disables the drivers on lines
ARB1 & ARB0.

➢ This causes the pattern on the arbitration line to change to 0110 which means that „B‟
has won the contention.