UNIT-5: I/O Organization

Syllabus
Different types of I/O devices and I/O transfer schemes
Programmed Input/output
Interrupts
Direct Memory Access
Interface circuits
Standard I/O Interfaces
I/ O Processors
Different types of I/O devices

Human Readable Machine readable Communication

• Printers • Disk drives • Modems

• Video display unit • Sensors • Network interface
• Keyboard • Controllers card (NIC)
• Mouse • Network routers
 Differences in I/O Devices

• Complexity of control
• Unit of transfer - Data may be transferred as a stream of bytes
for a terminal or in larger blocks for a disk
• Data representation (Encoding schemes)
• Error conditions (Devices respond to errors differently)
 Issue Description Challenges Examples
Managing diverse, Requires device-specific
asynchronous devices drivers, scheduling, and Scheduling I/O in multi-
Complexity of Control
with varying data rates handling interrupt device environments
and buffer needs priority
Byte streams may be
Data is transferred as
inefficient for large data; Streaming for terminals;
Unit of Transfer streams (bytes) or blocks
block transfers require blocks for hard disks
depending on the device
proper buffering
Mismatched encoding
Data must be encoded
can cause data
Data Representation to be interpreted ASCII for text, JPEG for
corruption; different
(Encoding) correctly by both system images
devices require different
and I/O device
encoding schemes
Errors occur during
Need for error detection,
transmission or device Checksums, ECC in
correction, or retry; real-
Error Conditions operation, requiring storage, CRC in
time response needed in
robust handling networking
critical systems
mechanisms
• Each of these issues plays a critical role in designing reliable and efficient I/O systems.
Effective I/O management ensures that devices can communicate with the system
seamlessly, minimizing errors, optimizing performance.
 I/O Module / Interface / Processor

• Mediator between the processor and an I/O

device/devices.
• Facilitate communication and coordinates
between CPU and variety of I/O devices.
• Controls the data exchange between the
external devices and main memory.
• Since there are speed differences between
CPU and I/O devices, the I/O module has
buffering and error detection mechanism.
I/O Addressing
• Just like memory, I/O devices need to be assigned a unique ID or address,
As you know, memory locations also have addresses.
• So how can you tell the difference between an address for an I/O device
and an address for a memory location ?
There are 2 techniques to allow I/O devices to be addressed:
• Memory-mapped I/O
• Isolated I/O
 Memory-mapped I/O
• In the memory-mapped I/O technique, I/O devices and the main memory share the same address
space
• In memory mapped I/O, the manufacturer of the computer system must partition the address space
(the range of address values) into:

• a set of addresses for the main memory

• another set of addresses for IO devices.
I/O mapped I/O (Isolated I/O )
• Memory and I/O have separate address space
• Which has common bus(data and address) for I/O and memory
but separate read and write control lines for I/O.
Feature Memory-Mapped I/O Isolated I/O
Uses the same address space for both Has a separate address space dedicated
Definition
memory and I/O devices. to I/O operations.
I/O devices are treated as memory I/O devices are accessed with special I/O
Addressing locations and can be accessed using instructions (e.g., IN, OUT in x86
regular memory instructions. assembly).
Uses the same instructions for both Requires separate instructions
Instructions Needed
memory and I/O (e.g., LOAD, STORE). specifically for I/O.
Provides a separate, often smaller,
Shares address space with memory,
Address Space Size address space for I/O, so memory
limiting the total available space.
address space is unaffected.
Address type Normal memory address are for both In this I/O address are called ports.
Uses memory control signals (RD, WR) for Requires separate control signals for I/O,
Control Signals
both memory and I/O. which simplifies signal handling.
Slightly more complex as it involves
Simple and requires fewer instructions,
Ease of Implementation separate I/O control signals and
making it easier to implement.
instructions.
Modes of I/O data transfer
• The data that we use is actually binary information that we send and receive
between I/O device and memory storage.
• Processor(CPU) executes any I/O instruction by taking data from memory and then
again writing back the updated data into memory. So, the source and target is
memory unit.

Memory CPU

I/O
• Data Transfer between CPU and I/O devices may be handled in a
variety of modes.
• Some modes use the CPU as an intermediate path ,others transfer
the data directly to and from the memory unit.
• Data transfer to and from peripherals may be handled in one of three
possible modes.
• Programmed I/O
• Interrupt- Initiated I/O
• Direct Memory Access(DMA)
Programmed I/O
• Programmed I/O: It is one simplest form of I/O where CPU has to do
all the work.
• This technique transfer the data between the processor and the I/O module.
• Programmed I/O operations are the result of I/O instructions written in the computer
program.
• Each data item transfer is initiated by an instruction in the program. Usually, the
transfer is to and from a CPU register and peripheral.
• Transferring data under program control requires constant monitoring of the peripheral
by the CPU.
• Once a data transfer is initiated, the CPU is required to monitor the interface to see
when a transfer can again be made.
• It is up to the programmed instructions executed in the CPU to keep close tabs on
everything that is taking place in the interface unit and the I/O device.
Examples:
• Reading data from a keyboard or a mouse where the CPU continuously polls the device
for keypresses or mouse movements.
• Writing data to a printer where the CPU initiates the print operation, checks the printer
status, and transfers data in small chunks.
Advantages:
• Simple to implement
• Very Little hardware support
Disadvantages
• Busy waiting as CPU need to continuously monitor the I/O devices to check whether
I/O devices are ready for transfer or not.
• Programmed I/O can be inefficient, especially for high-speed devices or large data
transfers, as it keeps the CPU busy and may lead to a waste of processing time.
• The CPU is dedicated to managing the I/O operation, limiting its ability to perform other
tasks parallelly.
 Interrupt –initiated I/O

• The disadvantage of programmed I/O(continues busy waiting of CPU) is overcome

by this technique
• This uses the interrupt facility
• This interrupt facility along with special commands issue an interrupt request
signal whenever data is ready for transfer.
• Whenever interrupt is received for the data transfer by the CPU. Then the CPU
performs the data transfer.
• While in the other time, when data transfer is not being performed, then CPU
performs some other program execution.
• The Interface meanwhile keeps monitoring the I/O devices.
• When I/O device is ready for data transfer it initiates an interrupt
request signal to the computer.
• When CPU receives this “Interrupt request signal”, the CPU stops
the current task and shifts to perform the I/O data transfer .
• After I/O data transfer is completed then again CPU moves the
previous task and continues that task.
Different I/O Transfer Schemes
I/O Transfer
CPU Involvement Pros Cons Best Suited For
Scheme
Simple, CPU wasted on
Programmed I/O High Low-speed devices
straightforward waiting
Moderate data rate,
Complex interrupt
Interrupt-Driven I/O Medium CPU can multitask real-time
handling
applications
High-speed, large
Direct Memory Efficient, reduces Requires additional
Low data volume
Access CPU overhead hardware (DMA)
transfers
Buses
➢A bus protocol is the set of rules that govern the behavior of
various devices connected to the bus ie, when to place
information in the bus, assert control signals etc.
➢The bus lines used for transferring data is grouped into 3 types.
They are,
✓Address line
✓Data line
✓Control line.
Control signals-> Specifies that whether read / write
operation has to performed. It also carries timing infn/. (ie) they
specify the time at which the processor & I/O devices place the
data on the bus & receive the data from the bus.
➢During data transfer operation, one device plays the role of a
„Master‟.
➢Master device initiates the data transfer by issuing read / write
command on the bus. Hence it is also called as „Initiator‟.
➢The device addressed by the master is called as Slave / Target.
Types of Buses:
➢There are 2 types of buses. They are,
✓Synchronous Bus
✓Asynchronous Bus.
Synchronous Bus:-
➢In synchronous bus, all devices derive timing information
from a common clock line.
➢Equally spaced pulses on this line define equal time.
➢During a „bus cycle‟, one data transfer on take place.
➢The „crossing points‟ indicate the tone at which the
patterns change.
➢A „signal line’ in an indeterminate / high impedance state
is represented by an intermediate half way between the
low to high signal levels.
• Fig:Timing of an input transfer of a synchronous bus.
T ime
Bus clock

Address and
command

Data

t0 t1 t2

Bus cycle
Master places the
device address and Addressed slave places
command on the bus, data on the data lines Master “strobes” the data
and indicates that on the data lines into its
it is a Read operation. input buffer, for a Read
operation.
➢At time to, the master places the device address on the address
lines & sends an appropriate command on the control lines.
➢In this case, the command will indicate an input operation &
specify the length of the operand to be read.
➢The clock pulse width t1 – t0 must be longer than the maximum
delay between devices connected to the bus.
➢The clock pulse width should be long to allow the devices to
decode the address & control signals so that the addressed
device can respond at time t1.
➢The slaves take no action or place any data on the bus before t1.
• Fig:A detailed timing diagram for the input transfer

T ime
Address & Bus clock
command Data reaches
Seen by
appear on the master tAM the master.
bus. Address and
command

Data
Address & tDM
command reach
Seen by slave
the slave. tAS
Address and Data appears
command on the bus.

Data
tDS

t0 t1 t
2
Multiple Cycle Transfer:-
➢During, clock cycle1, the master sends address & cmd
infn/. On the bus‟ requesting a „read‟ operation.
➢The slave receives this information & decodes it.
➢At the active edge of the clock (i.e.) the beginning of clock
cycel2, it makes accession to respond immediately.
➢The data become ready & are placed in the bus at clock
cycle3.
➢At the same times, the slave asserts a control signal called
„slave-ready‟.
➢The master which has been waiting for this signal, strobes,
the data to its i/p buffer at the end of clock cycle3.
➢The bus transfer operation is now complete & the master
sends a new address to start a new transfer in clock cycle4.
➢The „slave-ready‟ signal is an acknowledgement form the
slave to the master confirming that valid data has been
sent.
• Fig:An input transfer using multiple clock cycles
Asynchronous Bus:-
➢An alternate scheme for controlling data transfer on.
The bus is based on the use of „handshake‟ between
Master & the Slave. The common clock is replaced
by two timing control lines.
➢They are
✓Master–ready
✓Slave ready.
Fig:Handshake control of data transfer during an
input operation
➢The handshake protocol proceed as follows :
➢At t0 à The master places the address and command
information on the bus and all devices on the bus begin to
decode the information
➢At t1 à The master sets the Master ready line to 1 to inform the
I/O devices that the address and command information is ready.
➢The delay t1 – t0 is intended to allow for any skew that may
occurs on the bus.
➢The skew occurs when two signals simultaneously transmitted
from one source arrive at the destination at different time.
➢Thus to guarantee that the Master ready signal does not arrive
at any device a head of the address and command information
the delay t1 – t0 should be larger than the maximum possible
bus skew.
➢ At t2 à The selected slave having decoded the address and command information
performs the required i/p operation by placing the data from its data register on the
data lines. At the same time, it sets the “slave – Ready” signal to 1.
➢ At t3 à The slave ready signal arrives at the master indicating that the i/p data are
available on the bus.
➢ At t4 à The master removes the address and command information on the bus. The
delay between t3 and t4 is again intended to allow for bus skew. Errorneous
addressing may take place if the address, as seen by some device on the bus, starts to
change while the master – ready signal is still equal to 1.
➢ At t5 à When the device interface receives the 1 to 0 tranitions of the Master – ready
signal. It removes the data and the slave – ready signal from the bus. This completes
the i/p transfer.
➢ In this diagram, the master place the output data on the data lines and at the same
time it transmits the address and command information.
➢ The selected slave strobes the data to its o/p buffer when it receives the Master-ready
signal and it indicates this by setting the slave – ready signal to 1.
➢ At time t0 to t1 and from t3 to t4, the Master compensates for bus.
➢ A change of state is one signal is followed by a change is the other signal. Hence this
scheme is called as Full Handshake.
➢ It provides the higher degree of flexibility and reliability.
 Interface circuits
• A mediator between the system.
• How communication media is connected to sender or how
communication media is connected to receiver is called interface
circuit.
• End Port Connectivity is called interface circuit.
Communication Media
Sender Receiver
Communication Media

Interface Circuit Interface Circuit

• Port: It is a point at which external device attaches to
computer system. This sends /receives the data

• There are two ways we can connect interface

• (i) Parallel Port
• (ii) Serial Port
Parallel Port:
• More data(8 bit or 16 bit) can be transferred between the systems
simultaneously by using more number of bits.

• Fast Transmission.

• Only when all the systems are close to each other parallel port is possible
because many wires are used.
Keyboard Interface:
• A typical keyboard consists of mechanical switches that are normally open.
When a key is pressed, its switch closes and establishes a path for an
electrical signal.
• This signal is detected by an encoder circuit that generates the ASCII code for
the corresponding character.
• The output of the encoder consists of the bits that represents the encoded
character and one control signal called valid, which indicates that a key is
being pressed.
• This information is sent to the interface circuit, which contains a data
register DATAIN, and a status flag SIN.
• When a key is pressed, the valid signal changes from o to 1 causing the ASCII
code to be loaded into DATAIN and SIN to be set to 1.
• SIN is cleared to 0 when the processor reads the contents of the DATAIN register.

• The interface circuit is connected to an asynchronous bus on which transfers are

controlled using the handshake signals Master-ready and Slave-ready. The third
control line, R/W’ distinguishes read and write transfers.
Printer Interface:
• When the printer is ready to accept a new character for printing, it asserts
its idle signal (meaning it is ready for data).
• The interface circuit then places the new character on the data lines and
activates the valid signal, indicating the availability of new data.
• In response to the valid signal, the printer starts printing the new character.
• Once the printer begins printing, it negates the idle signal, which causes the
interface to deactivate the valid signal.
• The interface circuit contains a data register (DATAOUT), which holds the
data to be sent to the printer.
• A status flag (SOUT) is associated with the printer. The SOUT flag is set to 1
when the printer is ready to accept data, indicating that it can receive new
characters.
Serial Port:
• Transfer of data is only one way is possible, two way(simultaneously) is
not possible.
• One bit at a time can only be transferred.
• Slow Transmission.
• This is applicable even when systems are loaded at longer distance.
• They are not costly.
• From the figure, the input shift register accepts bit serial input from
the I/O devices. When all 8 bit have been received, the contents of this
shift register are loaded in parallel into the DATAIN register.
• Similarly, output data in the DATAOUT register are loaded into the
DATAOUT register, i.e output registe from which the bits are shifted
out and sent to the I/OM devices.
• The status flags set to 1 when new data are loaded in DATAIN, it is
cleared to 0 when the processor reads the contents of DATAIN.
• Serial transmission is convenient for connecting devices that are
physically for away from the computer.
• The speed of the transmission, often given as a bit rate, depends on the
nature of the devices connected.
• Output Shift Register: It converts the data in the DATAOUT register into a serial
format to be sent out.

• Chip and Register Select: This block manages data routing and access, ensuring that
data is read from or written to the correct location. It includes address and control
signals (like R/W for read/write) to facilitate communication.

• Status and Control: This component monitors and controls the status of the data
transfer process. It includes the INTR (interrupt) line, which signals when data
transfer is complete or when the system is ready for new data.

• Clocks: Separate receiving and transmission clocks ensure synchronization for data
flow in and out.
• Key Functions of Interface Circuits
• Interface circuits are crucial because they manage several aspects of communication,
including:
1.Signal Conversion: They often need to convert signals to be compatible with different
devices. For instance, digital signals may need to be converted to analog or vice versa.
2.Voltage Level Shifting: Different devices may operate at different voltage levels, so
interface circuits adjust voltages accordingly to ensure compatibility and prevent
damage.
3.Data Synchronization: Interface circuits handle the timing and synchronization of
data transfer, as various devices can operate at different speeds.
4.Control and Status Signals: These circuits help in generating control signals required
for data transfer, and they often manage status signals that indicate the readiness of a
device to send or receive data.
5.Error Detection and Correction: Some interfaces include error-checking mechanisms
to ensure data integrity during transfer.
Also learn about
• Memory Interfaces, Bus Interfaces, Network Interfaces
 Standard I/O Interface
• Used to connect I/O to the computer.

Types of Standard I/O Interface

1) Peripheral Component Interconnected (PCI) Bus
2) Small Computer System Interface(SCSI) Bus
3) Universal Serial Bus(USB)
1) PCI BUS
• Host is the processor
• Introduced in the 1990s, it serves as an internal expansion bus for connecting
hardware components like graphics cards, network cards, sound cards, and other
peripherals, allowing these components to communicate with the CPU and system
memory efficiently.
• PCI Bus is communication channel between host, main memory and all the set of I/O
devices.
• The data from I/O devices is send to the host and main memory using PCI Bus.
• The PCI bridge deviates the data between main memory and host.
• It will connect only I/O devices and its corresponding memory location
• This is less expensive
Key Features of PCI Bus
• High Data Transfer Speed: PCI enables faster data transfer rates compared to
previous standards like ISA (Industry Standard Architecture).
• Plug-and-Play: PCI supports plug-and-play, meaning that new devices can be
automatically detected and configured by the system without needing manual
configuration.
• Multiple Device Support: PCI can support multiple devices connected to the same
bus, allowing them to communicate with the CPU over shared pathways.
• Supports 32-bit and 64-bit Data Widths: PCI can handle both 32-bit and 64-bit wide
data paths, which affects the amount of data transferred in each clock cycle.
• Parallel Communication: The bus uses parallel communication, which allows data to
be sent on multiple channels simultaneously.
Example Scenario
• Suppose we have a computer with a PCI-based graphics card (GPU) and a network card both
connected to the CPU via the PCI bus. Here’s a step-by-step explanation of how the PCI bus
works to manage these devices’ requests and interactions with the CPU.

1. Device Initialization and Plug-and-Play Setup

• When the computer powers on, the operating system detect the connected PCI devices
(graphics card and network card in this case) and assign resources.
• The operating system configures each device’s I/O addresses and interrupt requests (IRQs)
automatically. This is part of the PCI’s plug-and-play capability.
2. Bus Arbitration
• Both the graphics card and network card may need to communicate with the CPU
at the same time. The PCI bus arbiter (a part of the PCI controller) decides which
device gets access first.
• Let's say the graphics card has a higher priority than network card has a slightly
lower priority as it handles less time-sensitive data.

3. Synchronous Data Transfer via Clock Signal

• Once the graphics card gains access to the PCI bus, it starts communicating data
to the CPU with the help of the system clock signal.
• PCI uses a synchronous clock, meaning that each data transfer is synced with the
clock pulse, typically at 33 MHz (or higher for newer versions).
• Data moves from the graphics card to the CPU in small, timed chunks or bursts to
match the clock speed. This synchronization allows reliable, predictable data
transfer rates.
4. Data Transmission from Graphics Card to CPU
• The graphics card starts a data burst to transfer image data to the CPU or
memory.
• The PCI controller begins the data transfer by issuing a start signal and
identifying the target device's address on the PCI bus.
• Each burst is a group of multiple data packets sent sequentially, allowing
high-speed transmission and reducing latency.
• During each data packet transfer, error-checking is performed to ensure no
data corruption. If an error is detected, the packet may be retransmitted.
5. Network Card Request and Interrupt Handling
• While the graphics card transfers data, the network card might also have data packets
arriving from an internet connection that it needs to pass to the CPU.
• Once the graphics card completes its data transfer, the network card requests access
to the PCI bus. The bus arbiter then grants the network card access.
• The network card transfers data packets to the CPU, but this time, it might generate an
interrupt to notify the CPU of the data’s arrival (e.g., incoming data from an online
video stream).
• The CPU temporarily stops its current task to process the interrupt, retrieves data
from the network card, and then resumes its regular operations.
6. Automatic Configuration and Memory Mapping
• Throughout this process, the PCI bus’s configuration setup allows the CPU and
devices to use I/O addresses and memory mappings for efficient communication.
• The plug-and-play feature ensures that each device is correctly configured and does
not interfere with others on the bus.
2) SCSI Bus
• It was developed by American national standard interface(ANSI)
• It doesnot support plug and play
• Can transfer only 16 data lines
• Two types
• 1) Narrow SCSI Bus which can hold 8 data lines
• 2) Wide SCSI Bus which can hold 16 data lines.
Key Features of SCSI
• Multi-Device Support: A single SCSI bus can connect up to 8 or 16 devices (depending on
the SCSI version), including the host adapter.
• High-Speed Data Transfer: SCSI offers faster data transfer rates compared to older
interfaces like IDE.
• Daisy-Chaining: Devices are connected in series (daisy-chained) using a single cable, with
termination at both ends of the chain.
• Wide Compatibility: SCSI supports a variety of devices, from storage to input/output
devices.
• Intelligent Communication: Devices on the SCSI bus can negotiate data transfer speeds
and modes for optimal performance.
• Independent Operation: Devices can operate independently, allowing simultaneous data
transfers between the CPU and multiple devices.
Example of SCSI in Action
• Suppose a computer has a SCSI hard drive, a SCSI scanner, and a SCSI printer connected to a single SCSI bus.
Device Initialization:
• Each device is assigned a unique SCSI ID during setup.
• The host adapter scans the bus during startup to identify all connected devices.
Hard Drive Access:
• The CPU, through the SCSI host adapter, issues a read command to the hard drive (target).
• The hard drive reads the data and sends it back to the CPU via the SCSI bus.
Simultaneous Operations:
• While the hard drive transfers data to the CPU, the scanner may begin scanning a document, and the printer
can start printing a job.
• The SCSI bus's capability to handle independent operations allows this parallel processing.
Bus Arbitration:
• If both the scanner and printer request the bus simultaneously, the device with the higher priority (lower SCSI
ID) gains access first.
Efficient Termination:
• The bus is terminated at both ends, ensuring smooth communication without data corruption.
3) USB
• Supports plug and play

• Supports dual speed of operation(1.5 megabits/12 megabits)

• Also supports high speed-USB(2.0)(480 megabits/s)

Features of USB:
1.Plug-and-Play: Devices are detected and configured automatically
upon connection, without requiring a system restart.
2.Hot-Swapping: Devices can be connected or disconnected while
the computer is running.
3.Versatility: Supports a wide range of devices, from storage to audio
and video peripherals.
4.Power Delivery: USB can supply power to devices, eliminating the
need for separate power sources for smaller peripherals.
5.Scalability: Supports multiple devices using hubs.
Working of USB:
1.Host and Device:
1. USB uses a master-slave architecture where the computer acts as the host and the
connected devices act as slaves.
2. The host controls the communication and manages data transfers.
2.Communication Protocols:
1. USB communication is based on packets containing data and instructions.
• Token Packets: Carry control information to direct the communication.
• Data Packets: Contain the actual data being transferred.
• Handshake Packets: Provide feedback to ensure successful data transfer.
2. The host initiates communication and assigns bandwidth to each connected device.
3.Data Transfer Modes:
1. Control Transfers: Used for device configuration.
2. Bulk Transfers: For large amounts of data (e.g., file transfers to a USB drive).
3. Interrupt Transfers: For low-latency communication (e.g., mouse or keyboard input).
4. Isochronous Transfers: For real-time applications (e.g., audio and video streaming).
4.Speeds and Versions:
1. USB has evolved through multiple versions, each offering higher data transfer rates:
1. USB 1.0/1.1: 1.5 Mbps (Low Speed) / 12 Mbps (Full Speed)
2. USB 2.0: 480 Mbps (High Speed)
3. USB 3.0/3.1: 5 Gbps (SuperSpeed) / 10 Gbps (SuperSpeed+)
4. USB 4.0: Up to 40 Gbps (similar to Thunderbolt 3/4)
 I/ O Processors

• The concept of DMA operation can be extended to relieve the CPU further
from getting involved with the execution of I/O operations.
• This gives rise to the development of special purpose processors called Input-
Output Processor (IOP) or IO channels.
• The Input-Output Processor (IOP) is just like a CPU that handles I/O
operations.
• The IOP can fetch and execute instructions that are specifically related to I/O
transfers.
• In addition to the I/O-related tasks, it can also perform other processing tasks
like arithmetic, logic, branching, and code translation.
• The main memory related to this, is communicated with processor via DMA.
• The Input-Output Processor is a specialized processor which loads and stores data in
memory along with the execution of I/O instructions.

• CPU only needs to specify a sequence of I/O activity to I/O processor.

• It acts as an interface between the system and devices. It involves a sequence of events
to execute I/O operations and then store the results in memory.
Differences Between CPU and IOP

Feature CPU IOP

Primary Function Executes program instructions Handles I/O operations
Instruction Set General-purpose Specialized for I/O tasks
Communication Controls all processes Communicates with devices
Features of an Input-Output Processor
• Specialized Hardware: An IOP is equipped with specialized hardware that is
optimized for handling input/output operations. This hardware includes
input/output ports, DMA controllers, and interrupt controllers.
• DMA Capability: An IOP has the capability to perform Direct Memory Access
(DMA) operations. DMA allows data to be transferred directly between peripheral
devices and memory without going through the CPU, thereby freeing up the CPU
for other tasks.
• Interrupt Handling: An IOP can handle interrupts from peripheral devices and
manage them independently of the CPU. This allows the CPU to focus on
executing application programs while the IOP handles interrupts from peripheral
devices.
• Protocol Handling: An IOP can handle communication protocols for different types
of devices such as Ethernet, USB, and SCSI. This allows the IOP to interface with a
wide range of devices without requiring additional software support from the
CPU.
• Buffering: An IOP can buffer data between the CPU and peripheral
devices. This allows the IOP to handle large amounts of data without
overloading the CPU or the peripheral devices.

• Command Processing: An IOP can process commands from

peripheral devices independently of the CPU. This allows the CPU to
focus on executing application programs while the IOP handles
peripheral device commands.

• Parallel Processing: An IOP can perform input/output operations in

parallel with the CPU. This allows the system to handle multiple
tasks simultaneously and improve overall system performance.
Working of I/O Processors
Applications of I/O Processors
• Data Acquisition Systems: I/O processors can be used in data acquisition
systems to acquire and process data from various sensors and input devices. The
I/O processor can handle high-speed data transfer and perform real-time
processing of the acquired data.
• Multimedia Applications: I/O processors can be used in multimedia applications
to handle the input and output of multimedia data, such as audio and video. The
I/O processor can perform real-time processing of multimedia data, including
decoding, encoding, and compression. (EX. Graphic cards)
• Network Communication Systems: I/O processors can be used in network
communication systems to handle the input and output of data packets. The I/O
processor can perform packet routing, filtering, and processing, and can also
perform encryption and decryption of the data. (Ex. NIC cards)
• Storage Systems: I/O processors can be used in storage systems to handle the
input and output of data to and from storage devices. The I/O processor can
handle high-speed data transfer and perform data caching and prefetching
operations. (Ex. RAID Controllers)
Advantages of Input-Output Processor
• The I/O devices can directly access the main memory without the intervention of
the processor in I/O processor-based systems.
• It is used to address the problems that arise in the Direct memory access method.
• Reduced Processor Workload: With an I/O processor, the main processor doesn’t
have to deal with I/O operations, allowing it to focus on other tasks. This results
in more efficient use of the processor’s resources and can lead to faster overall
system performance.
• Improved Data Transfer Rates: Since the I/O processor can access memory
directly, data transfers between I/O devices and memory can be faster and more
efficient than with other methods.
• Increased System Reliability: By offloading I/O tasks to a dedicated processor, the
system can be made more fault-tolerant. For example, if an I/O operation fails, it
won’t affect other system processes.
• Scalability: I/O processor-based systems can be designed to scale easily,
allowing for additional I/O processors to be added as needed. This can be
particularly useful in large-scale data centres or other environments where the
number of I/O devices is constantly changing.
Disadvantages of Input-Output Processor
• Cost: I/O processors can add significant costs to a system due to the
additional hardware and complexity required. This can be a barrier to
adoption, especially for smaller systems.
• Increased Complexity: The addition of an I/O processor can increase the
overall complexity of a system, making it more difficult to design, build, and
maintain. This can also make it harder to diagnose and troubleshoot issues.
• Limited Performance Gains: While I/O processors can improve system
performance by offloading I/O tasks from the main processor, the gains may
not be significant in all cases. In some cases, the additional overhead of the
I/O processor may actually slow down the system.
• Synchronization Issues: With multiple processors accessing the same
memory, synchronization issues can arise, leading to potential data
corruption or other errors.
• Lack of Standardization: There are many different I/O processor
architectures and interfaces available, which can make it difficult to develop
standardized software and hardware solutions. This can limit
interoperability and make it harder for vendors to develop compatible
products.
• Solution 1: CPU Utilization
Q) It is required to transfer 512 bytes of information from a device. 2 designs
are suggested. One with DMA and other with interrupt I/O. Calculate the
minimum performance gain that Direct Memory Access (DMA) can achieve
compared to the interrupt transfer process described. Assume that DMA
requires 50 clock cycles for transferring the entire block of 542 bytes and 2
clocks/byte is needed for transfer. The ISR is used to interrupt transfer.
A pseudo-code for transferring data using ISR:
1. Place device address in AR // 1 clock cycle
2. Place count 542 in CR // 1 clock cycle
Loop:
1. Load byte from device // 2 clock cycles
2. Store it in memory (at AR) // 2 clock cycles
3. Increment AR // 1 clock cycle
4. Decrement CR // 1 clock cycle
5. Branch to Loop if CR ≠ 0 // 1 clock cycles
Q) A processor with a clock speed of 50 MHz is used for data transfer.
The following details are provided:
Direct Memory Access (DMA) Parameters:
1. Initialization and termination time: 1500 clock cycles.
2. File size to transfer: 40 KB (kilobytes).
3. Device transfer speed: 2000 KBps.
Calculate the percentage of processor time utilized by the DMA process during
the file transfer.