AP6682SR3 EVB
AP6682SR3 EVB
Address:
6F., No. 21, Huanke 1st Rd., Zhubei City, Hsinchu County 302047 , Taiwan
(R.O.C.)
Website: http://www.ampak.com.tw/
AP6682SR3 Evaluation Board User Manual
Revision
6F., No. 21, Huanke 1st Rd., Zhubei City, Hsinchu County 302047 , Taiwan (R.O.C.) http://www.ampak.com.tw
i
AP6682SR3 Evaluation Board User Manual
Contents
1. EVB Introduction .................................................................................................... 2
2. WiFi Function Verification Step ............................................................................... 3
2.1 WiFi SDIO ....................................................................................................... 3
2.2 Hardware Setup .............................................................................................. 5
2.3 WiFi Software Setup ........................................................................................ 5
3. Bluetooth Function Verification Step ........................................................................ 6
6F., No. 21, Huanke 1st Rd., Zhubei City, Hsinchu County 302047 , Taiwan (R.O.C.) http://www.ampak.com.tw
ii
AP6682SR3 Evaluation Board User Manual
1. EVB Introduction
AP6682SR3 Evaluation board (EVB) likes as figure1. That is designed for IEEE802.11
a/b/g/n/ac/ax WLAN with integrated Bluetooth application. It is subject to provide a convenient
environment for customer’s verification on WiFi or Bluetooth function. There are many controller
pins and reserved GPIO on Evaluation board which describes as below.
Interface highlights:
1. U200: AP6682SR3 SIP module.
2. J16: UART interface connects with UART transport board for BT measuring
3. J15: Enable(H) or disable(L) Bluetooth, Wi-Fi function
4. J20: 5V/2A DC USB type-C input connector.
5. J8: Standard SDIO interfaces for Wi-Fi performance measured.
6. J21: WL_HOST_WAKE/BT_HOST_WAKE/BT_DEV_WAKE/WL_GPIOs/PCM I/F.
7. J32: 1.8V voltage level for SDIO I/F.
8. J33: 3.3V voltage level for SDIO I/F.(Need U7 placeed)
9. U7: level shift IC(TI-LSF0108) for VDDIO=3.3V(When SoC voltage level is 3.3V)
10. J17: VBAT jumper.
11. J18: VDDIO jumper.
* U7 : TI – LSF0108QPWRQ1(Package : TSSOP)
Hardware Setup:
❖ Refer to Figure5 UART pin definition connects the J16 interface of AP6682SR3 evaluation
board to Host UART control interface.
❖ Connects an external antenna at SMA connector on the evaluation board.
❖ Note to the VDDIO voltage level should be the same as GPIO voltage level of Host CPU.