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Apr May 2019

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10 views4 pages

Apr May 2019

question paper

Uploaded by

pandyselvi.eee
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Reg.No:[ TT TTT TTT Question Paper Code : 80126 B.E/B.Tech. DEGREE EXAMINATIONS, APRIL/MAY 2019. ‘Third Semester Electrical and Electronics Engineering EE 8351 — DIGITAL LOGIC CIRCUITS (Common to Electronics and Instrumentation Engineering/Instrumentation and Control Engineering) (Regulation 2017) Time-: Three hours Maximum : 100 marks 10. ul. Answer ALL questions. PART A— (10 x 2= 20 marks) Convert (101.01), to decimal number. Give each one example for error detecting code and error correcting code. Determine the exact number of half adders and full adders required for performing the addition of two binary numbers of 5-bits length each. Find the result of A+A'D+AC'. Write down the characteristic table of JK flip-flop: What is FSM? List its two basic types. Define metastable state. Draw the structure of PAL. State the purpose of test bench. Write a VHDL program for an EX-NOR gate using behavioural coding, PART B — (5 x 13 = 65 marks) (a) @ Design a 3-input NAND gate circuit using TTL logic. (1) Gi) Explain in detail, the generation of Hamming code for 4-bit data. (6) Or 12, 13, 14. 15, (b) (a) (b) (a) (b) (a) (b) (a) (b) @ Gi) @ Gi) @ Gi) @ Gi) @ Gi) Gi) Gi) @ Gi) ) Design a 2 input NOR gate using CMOS logic 0) Explain the operation of RTL inverter circuit with relevant diagrams. © Design a 3 x 8 decoder using 2 x 4 decoders. Draw the truth table. @ Design a full adder circuit using logic gates. © Or Simplify and implement the logic function F(A, B,C)= (0,1, 4,5,7) using logic gates, O) Design a 4 * 2 priority encoder using logic gates. © Design a 2-bit synchronous sequential down counter, @ Explain the operation of a 3-bit universal shift register. © . Or Explain Moore and Mealy models with the help of block diagrams, Gy Draw the state table for the following state diagram. © X24 ra Come aie X=4 Design a Modulo-6 asynchronous binary up-counter. @ Implement the functions F(X,Y,Z)=2(1, 2, 4,5), = £(0,13,4) and A(X,Y,Z)=2(23,6,7) using a single PROM grid. 6) Or tiate PAL, and PLA implementations with the help of the same example F,(a,b,c)= (0, 1,3, 4, 6,7). @ Explain the structure of CPLD with the help of a block diagram. (6) Draw the VLSI design flow chart used for IC design and fabrication. @ Write down a VHDL code for 8 x 1 Demultiplexer. © Or Illustrate the two approaches used in VHDL coding with full adder design as your example. @ What are components in VHDL? Show step-by-step how a NOR gate component can be created and added in the library. © 2 80126 16. (a) b) PART C —(1 x 15 = 15 marks) Design a synchronous sequential logic circuit that goes through the sequence 0, 2, 4, 6, 8, 10, 12,14 repeatedly. Use D flip flops for your design, (15) Or Simplify the following function and implement it using NAND gates only: F(w,x,y,z)=5(1,3,5, 7, 9,11, 13, 15), with don’t care states d(w,x,y,2)=3(0;2, 4, 6,8). (5) 3 80126

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