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You are on page 1/ 356

NOTICE

The information in this guide is subject to change without notice.

COMPAQ COMPUTER CORPORATION SHALL NOT BE LIABLE FOR TECHNICAL OR EDITORIAL

ERRORS OR OMISSIONS CONTAINED HEREIN; NOR FOR INCIDENTAL OR CONSEQUENTIAL
DAMAGES RESULTING FROM THE FURNISHING, PERFORMANCE, OR USE OF THIS
MATERIAL.

This guide contains information protected by copyright. No part of this

guide may be photocopied or reproduced in any form without prior written
consent from Compaq Computer Corporation.

Copyright 1992 Compaq Computer Corporation.

COMPAQ, DESKPRO, LTE, FASTART

Registered U. S. Patent and Trademark Office.

The software described in this guide is furnished under a license agreement

or non-disclosure agreement. The software may be used or copied only in
accordance with the terms of the agreement.

Product names mentioned herein may be trademarks and/or registered

trademarks of their respective companies.

TECHNICAL REFERENCE GUIDE

COMPAQ LTE Lite Family of Personal Computers

First Edition (November 1992)

Part Number 140097-001

1.1 ABOUT THIS GUIDE

This guide presents hardware and firmware (ROM) information for the COMPAQ
LTE Lite Family of Personal Computers for developers, engineers,
technicians, and programmers who need technical information in order to
design products for or maintain the system.

This guide covers the following 386-based models of the COMPAQ LTE Lite
Family of Personal Computers:

o COMPAQ LTE Lite/25C

o COMPAQ LTE Lite/25e
o COMPAQ LTE Lite/25
o COMPAQ LTE Lite/20

This guide assumes an understanding of the Intel 80386SL microprocessor

superset and personal computer technology based on this microprocessor.
This guide supplements but does not replace the following Intel
publications:

o Intel386 SL Microprocessor Superset System Design Guide (part no. 240816)

o Intel386 SL Microprocessor Superset Programmer's Reference Manual

(part no. 240815)

o Intel386 SL Microprocessor Superset Data Book (part no. 240814)

o The Lotus/Intel/Microsoft Expanded Memory Specification, Version 4.0

(part no. 300275-005)

o Intel 80387 Coprocessor Programmer's Reference Manual (part no. 231917)

1.2 NOTATIONAL CONVENTIONS

Values

I/O addresses and other values are in hexadecimal notation when shown with
the letter h after them. Memory addresses are in hexadecimal when
expressed as SSSS:OOOO (SSSS 16-bit segment, OOOO 16-bit offset). All
other numbers are in decimal notation.

Ranges

Ranges or limits for a parameter are shown as a pair of values separated by

two dots. For example, 4..0 includes the numbers 4 and 0, and every number
in between (3, 2, and 1).

Signal Labels

Signal values are labeled A0, A1, A15, etc. Signal names are in uppercase
letters. Signals that are negative true, or active low, are indicated by a
dash (-) suffix.

Register Notation and Usage

The standard Intel naming conventions are used for the 386SX registers. The
names of the general registers when used as word-length (16-bit) registers
are AX, BX, CX, and DX. The names of the general registers when they are
used as byte-length (8-bit) registers are AH, AL, BH, BL, CH, CL, DH, and
DL.

SI, DI, and BP denote the Source Index, Destination Index, and Base Pointer
registers, respectively.

CS, DS, SS, and ES denote the four segment registers: Code Segment, Data
Segment, Stack Segment, and Extra Segment, respectively. CS is used with
the IP (Instruction Pointer) register, and SS is used with the SP (Stack
Pointer) register.

FL is the Flag register used to return the status of some operations.

Status is given as the state of one of the flags within the register: CF
for Carry Flag, IF for Interrupt Flag, etc.

The contents of AX are not guaranteed to be preserved across all calls.

Always reload the function code in AH and the parameter in AL (if any) to
repeat a call. Register contents are always preserved across BIOS calls,
unless the register is used to return a value.
Bit Notation

Bit values are labeled so that bit <0> represents the least-significant bit
and bit <7> the most-significant bit of a byte.

Bit fields within a byte or word are shown as a range of decimal numbers
separated by two dots enclosed in angle brackets with the higher number,
representing the most-significant bit, on the left. For example, <15..12>
refers to the four most-significant bits in a word.

1.3 COMMON ACRONYMS AND ABBREVIATIONS

The following acronyms and abbreviations are used throughout this guide:

Table 1-1. Acronyms and Abbreviations

=======================================================
====================
Acronym/Abbreviation Meaning
=======================================================
====================
A ampere

AC alternating current

ACE asynchronous communications element

ACK acknowledge

ASIC application specific integrated circuit

BCD binary coded decimal

BIOS basic input/output system

bpi bits per inch

bps bits per second

CEMM COMPAQ Expanded Memory Manager

CF Carry Flag

CGA Color graphics adapter

CH channel

CLIM COMPAQ LOTUS INTEL MICROSOFT

cm centimeter

CMOS complementary metal-oxide

CNTLR controller

CPU central processing unit

dBm decibel referred to 1 milliwatt

DC direct current

DCC diskette controller chip

DF direction flag

DIP dual in-line package

DMA direct memory access

DRAM dynamic random access memory

---------------------------------------------------------------------------
Acronym/Abbreviation Meaning
---------------------------------------------------------------------------
DRQ data request

dword 32-bit double word

ECC error correction code

EGA enhanced graphics adapter

EIA Electronic Industries Association

EMS Expanded Memory Specification

FRI flux reversals per inch

GB gigabyte

h hexadecimal

HW hardware

Hz Hertz

IF interrupt flag

I/F interface

in inch

INT interrupt

IPS inch per second

IRQ interrupt request

ISA industry standard architecture

Kb kilobit (1024 bits)

---------------------------------------------------------------------------
Acronym/Abbreviation Meaning
---------------------------------------------------------------------------
KB kilobyte (1024 bytes)

Kb/s kilobits per second

kg kilogram

kHz kilohertz

kv kilovolt

lb pound

LSI large scale integration

m meter

mA milliampere

Mb megabit (1 x 106 bits)

MB megabyte (1 x 106 bytes)

Mb/s megabit per second

MB/s megabyte per second

MDA monochrome display adapter

MFM modified frequency modulation

MHz megahertz

ms millisecond [10(-3)]

N variable parameter/value

NiCd nickel-cadmium

NiMH nickel metal hydride

ns nanosecond [10(-9)]

NVRAM non-volatile random access memory

PF parity flag
pF picofarad

PTR pointer

RAM random access memory

RF resume flag

ROM read-only memory

RPM revolutions per minute

RTC real-time clock

SF sign flag

SRAM static random access memory

SW software

TF trap flag

TFT thin-film transistor

TPI tracks per inch

TTL transistor transistor logic

UART universal asynchronous receiver/transmitter

us microsecond [10(-6)]

V volt

VGA video graphics adapter

VGC video graphics controller

VLSI very large scale integration

W watt

ZF zero flag
=======================================================
====================

2.1 INTRODUCTION

This chapter describes the key design and technical features of 386-based
COMPAQ LTE Lite products.

The COMPAQ LTE Lite Personal Computer, shown in Figure 2-1, is a laptop
computer weighing 6 pounds and providing over three hours of continuous use
on a single battery charge. The computer incorporates special features that
allow the user to conserve battery power while maintaining operating
efficiency. The computer may be connected to the optional Desktop Expansion
Base to become a system with full desktop functionality.

ILLUSTRATION OF Figure 2-1a. COMPAQ LTE Lite Personal Computers

(Part 1 of 2)

ILLUSTRATION OF Figure 2-1b. COMPAQ LTE Lite Personal Computers

(Part 2 of 2)

2.2 STANDARD FEATURES

The following features are standard on all 386-based COMPAQ LTE Lite
Personal Computers:

o 386SL microprocessor

o Socket for 387SL numeric coprocessor

o BIOS in flash ROM for convenient upgrading

o 3 1/2-Inch 1.44-Megabyte Diskette Drive

o Video Graphics Array (VGA) system with simultaneous external monitor

support

o External interfaces for:

- Serial communications device
- Parallel communications device
- External VGA monitor
- External keyboard or pointing device
- External numeric keypad
- Desktop Expansion Base or External Storage Module

o Enhanced option slot supporting optional communications module

o AC Adapter with fast charging function for the battery pack

o Auxiliary battery that allows battery pack changes without shutting down
the system

o Power management features

2.3 DIFFERENCE DATA

Table 2-1 lists the differences in functionality among the various COMPAQ
LTE Lite products.

Table 2-1. 386-Based COMPAQ LTE Lite Difference Data

=======================================================
====================
Feature LTE Lite/20 LTE Lite/25 LTE Lite/25C LTE Lite/25E
---------------------------------------------------------------------------
Processor Speed 20-MHz 25-MHz 25-MHz 25-MHz
Cache Memory None 16-Kbyte 64-Kbyte 64-Kbyte

Standard Memory 2 Mbytes 4 Mbytes 4 Mbytes 4 Mbytes

Maximum Memory 18 Mbytes 20 Mbytes 20 Mbytes 20 Mbytes

LCD Passive Passive Active Active

Monochrome Monochrome Color Monochrome

Integrated Track
Ball No No Yes Yes

Standard Battery NiCd NiMH NiMH NiMH

=======================================================
====================

2.4 SYSTEM ARCHITECTURE

The COMPAQ LTE Lite Personal Computer utilizes a concurrent bus

architecture (Figure 2-2) that allows the microprocessor to operate more
efficiently with the memory, cache/coprocessor, and peripheral subsystems.

COMPAQ LTE Lite products feature the Intel SL Superset that includes the
386SL Microprocessor and the 82360SL ISA Peripheral Controller. The 386SL
microprocessor provides processing, power management, memory management,
ISA bus control, and, on 25-MHz versions, cache memory control. The 82360SL
peripheral controller provides peripheral power management, real-time
clock, and memory map functions. The 82360SL also includes the DMA and
interrupt controllers and the serial and parallel ports.

The diskette and hard drive interfaces, enhanced option slot interface, and
keyboard/pointing device interfaces are contained in a custom
application-specific integrated circuit (ASIC). This ASIC also provides
distribution control of DMA and interrupt functions

The video subsystem includes a video controller ASIC, 256- or 512-Kbytes of

video RAM, and either a monochrome or color liquid crystal display (LCD).

The subsystems of the COMPAQ LTE Lite are described in the paragraphs
following Figure 2-2.

ILLUSTRATION OF Figure 2-2. 386-Based COMPAQ LTE Lite System Architecture

Block Diagram

Microprocessor

The COMPAQ LTE Lite Family of Personal Computers uses the 386SL
microprocessor. The 386SL microprocessor is similar to the 386SX
microprocessor. The architecture provides 32-bit processing internally
while interfacing with external subsystems over a 16-bit data bus. The
386SL also includes an integrated bus controller, memory controller, and,
in the 25-MHz version, a cache controller. The 386SL microprocessor employs
a static design that allows the system clock to be shut off to preserve
battery power. The 386SL is compatible with software written for 386DX,
286, and 8086 microprocessors.

All 386-based COMPAQ LTE Lite products include a socket for the 387SL math
coprocessor. When installed, the math coprocessor provides accelerated
performance for numeric-intensive applications.

BIOS Flash ROM

The Basic Input/Output System (BIOS) is contained in flash ROM. Flash ROM
retains data without power just like standard ROM. Unlike standard ROM,
however, data can be rewritten into flash ROM. This allows the BIOS to be
easily updated as necessary by using special BIOS update utility software.

Four-Way Set-Associative Cache

The COMPAQ LTE Lite/25 features a 16-Kbyte cache memory. The COMPAQ LTE
Lite/25e and COMPAQ Lite/25C feature a 64-Kbyte cache memory. The cache
memory is arranged into four degrees of associativity as opposed to the
normal one or two degrees offered by other cache designs. For most
situations, the four-way set-associative cache design provides the
performance of larger cache memories and services over 90 percent of
processor requests with zero wait-state performance.

System Memory

The system memory provides temporary storage of programs and data being
used. The COMPAQ LTE Lite Family of Personal Computers uses 70-ns enhanced
page RAM that operates at processor speed. Up to 20-megabytes of memory may
be installed using 2-, 4-, 8-, and 16-megabyte 70-ns extended refresh
memory cards that are easily installed without disassembling the unit.

NOTE: COMPAQ LTE Lite products will accept the 4-megabyte 80-ns (normal
refresh) memory card designed for the COMPAQ LTE 386s/20 Personal
Computer. However, memory access times will be extended and power
consumption will be increased. Conversely, all memory cards designed
for COMPAQ LTE Lite products will work in the COMPAQ LTE 386s/20 with
no degradation in performance.

Mass Storage

The COMPAQ LTE Lite Personal Computer comes standard with a 3 1/2-Inch
1.44-Megabyte Diskette Drive. The 3 1/2-Inch 1.44-Megabyte Diskette Drive
reads and writes to both 1.44-megabyte and 720-Kbyte diskettes. The COMPAQ
LTE Lite Personal Computer accommodates one internal hard drive. Original
models of the COMPAQ LTE Lite Family include a 40-, 60-, 84-, or
120-megabyte hard drive.

The optional External Storage Module, which connects to the rear of the
COMPAQ LTE Lite, allows an additional diskette drive or tape drive to be
added to the system.

Video Subsystem

The COMPAQ LTE Lite video subsystem consists of a VGA controller, 256- or
512-Kbytes of video RAM, and a liquid crystal display (LCD). The COMPAQ LTE
Lite/20 and COMPAQ Lite/25 feature a video subsystem that supports VGA,
EGA, and CGA video modes and provides up to 64 shades of gray. The COMPAQ
LTE Lite/25e features an active matrix black and white video subsystem that
provides high contrast gray scaling (up to 64 shades). The COMPAQ LTE
Lite/25C features an active matrix color video subsystem that supports
between 256 simultaneous colors in 640 x 480 VGA resolution.

In addition to the integrated LCD, the video controller on all models can
simultaneously support either the Reduced Emissions Video Graphics Color
Monitor, the Video Graphics Color Monitor, or the Video Graphics Monochrome
Monitor. The video controller supports:

o 640 pixel x 480 line VGA-compatible graphics resolution

o 640 pixel x 350 line EGA-compatible graphics resolution
o 320 pixel x 200 line CGA-compatible graphics resolution
o 1056 pixel x 400 line text mode (external monitor only)
o 720 pixel x 400 line text resolution (external monitor only)
o Up to 256 colors out of a 262,144 color palette

To maintain the high performance requirements of the COMPAQ LTE Lite

Personal Computer, the BIOS code for the VGC is copied into 16-bit RAM
during the boot procedure to provide faster video performance.

Serial/Parallel Interfaces

The COMPAQ LTE Lite Personal Computer includes a serial interface and a
parallel interface.

The serial interface provides a buffered, asynchronous port that is

compatible with the Electronic Industry Association (EIA) RS-232-C protocol
at standard baud rates up to 19200. This port, including a data FIFO
buffer, may be used to connect to a terminal, personal computer, external
modem, or any peripheral device with a compatible serial interface.

The parallel interface provides a port for connection to a printer. This

bidirectional port can operate as a standard parallel port, a PS/2 port, or
as a high-speed parallel port.

Enhanced Option Slot

The enhanced option slot allows the installation of an optional

communications device such as an enhanced modem or a second serial port.
The communications parameters of this interface are software-programmable.

2.5 SPECIFICATIONS

This section contains the environmental, electrical, and physical

specifications for the COMPAQ LTE Lite.

Table 2-1 lists the environmental specifications for a completely assembled

COMPAQ LTE Lite Personal Computer.

Table 2-2. COMPAQ LTE Lite Environmental Specifications

=======================================================
====================
Parameter Nonoperating Operating
---------------------------------------------------------------------------
Air Temperature -22oF to 140oF 50oF to 104oF
(-30oC to 60oC) (10oC to 40oC)

Shock 40 G for 11 ms 5 G for 11 ms

half-sine pulse half-sine pulse

Vibration 1 G for 5 - 500 Hz 0.15 G for 5 - 500 Hz

sinusoidal sinusoidal

Humidity 5% to 95% 10% to 90%

(noncondensing) (noncondensing)

Maximum Altitude 30,000 ft (9144 m) 10,000 ft (3048 m)

=======================================================
====================

Table 2-3 lists the electrical specifications of the COMPAQ LTE Lite.

Table 2-3. COMPAQ LTE Lite

Electrical Specifications
======================================
Parameter
--------------------------------------
Input Voltage 12 VDC

Power Consumption
Average 10.0 W
Peak 21.0 W
======================================

Tables 2-4 and 2-5 list the physical specifications of the COMPAQ LTE Lite
products.

Table 2-4. COMPAQ LTE Lite/20 and COMPAQ LTE Lite/25 Physical
Specifications (Closed)
=======================================================
=======
English Metric
--------------------------------------------------------------
Dimension
Height 1.75 in 4.45 cm
Width 11.0 in 27.9 cm
Depth 8.5 in 21.6 cm

Weight 6.01 lb 2.67 kg

=======================================================
=======

Table 2-5. COMPAQ LTE Lite/25E and COMPAQ Lite/25C Physical

Specifications (Closed)
=======================================================
=======
English Metric
--------------------------------------------------------------
Dimension
Height 2.0 in 5.08 cm
Width 11.0 in 27.9 cm
Depth 8.5 in 21.6 cm

Weight 6.5 lb 2.95 kg

=======================================================
=======

3.1 INTRODUCTION

This chapter describes the system processor (Figure 3-1), which includes
the elements listed below.

o Microprocessor [3.2]
o Math coprocessor [3.3]

ILLUSTRATION OF Figure 3-1. System Processor Block Diagram

3.2 MICROPROCESSOR

All models of the COMPAQ LTE Lite Family are based on the Intel 386SL
Microprocessor. The 386SL microprocessor contains all the functionality of
the 386SX microprocessor with additional functions and enhancements. The
386SL microprocessor uses a 32-bit internal architecture while interfacing
with external functions and subsystems on 16-bit data buses. The 386SL
includes a static CPU core, ISA bus control logic, a system memory
controller, special power management logic, and, in the 25-MHz version, a
cache memory controller. The 80386SL is compatible with software written
for the 8088/8086, the 80286, and the 80386DX.

The 80386SL is reset when internal (battery) or external power is applied

to the system board or when, if the system is already powered, the user
presses CTRL + ALT + DEL. After reset, the microprocessor addresses ROM for
instructions. The initial boot process in ROM checks the system RAM and ROM
for errors (checksums), then initializes the system.

Initializing or restarting the system loads the initialization and

configuration values into programmable devices. After initializing the
system, the microprocessor loads the operating system into memory either
from the diskette drive or from the fixed disk drive.

External Interfacing

The 80386SL uses three 16-bit data buses for external data transfers: a
cache memory/coprocessor bus, a memory bus, and a system bus. The cache
memory/coprocessor bus handles data transfers at processor speed between
the microprocessor and either the cache memory (on 25-MHz models) or the
math coprocessor (if installed). The cache memory is discussed in detail in
Chapter 4 "Memory." More information on the math coprocessor is included
later in this chapter.

The memory bus provides data transfers at processor speed between the
microprocessor and system memory. The 386SL includes an integrated memory
controller that performs address translation according to the
Lotus/Intel/Microsoft (LIM) Expanded Memory Specification (EMS) 4.0
standard. The system memory is discussed in detail in Chapter 4, "Memory."

The system bus handles data transfers between the 386SL microprocessor and
the peripheral subsystems. The system bus has the functionality of two
buses: the peripheral bus, where transactions occur at processor speed; and
the ISA expansion bus, which provides full support of ISA transactions at
8-MHz speed. In the COMPAQ LTE Lite, the system bus operates as a
peripheral bus during video operations and as an ISA expansion bus for all
other functions. Table 3-1 lists the signals that are shared by peripheral
and ISA operations on the system bus.

Table 3-1. Peripheral/ISA Ops System Bus Signals

=======================================================
====================
Signal Function
---------------------------------------------------------------------------
SA<19..0> System address signals

LA<23..17> Latchable address signals

SD<15..0> System data signals

SBHE- Bus high byte enable signal

=======================================================
====================

Table 3-2 shows control signals used by the system bus operating in
peripheral mode.

Table 3-2. Peripheral Ops (Only) System Bus Signals

=======================================================
====================
Signal Function
---------------------------------------------------------------------------
PSTART- P-bus start

PCMD- P-bus command

PRDY- P-bus ready

PMI/O- P-bus memory/I/O cycle

PW/R- P-bus write/read cycle

VGACS- VGA (video) chip select

FLSHDCS- Flash disk chip select

=======================================================
====================
All devices outside the 80386SL are addressed as either memory-mapped or
I/O-mapped devices. The PM/IO signal specifies whether a memory-mapped or
an I/O-mapped device or location is being addressed for both peripheral and
ISA modes.

For a complete list and description of system bus signals used for ISA
expansion bus operations, refer to Chapter 5, "ISA Expansion Bus."

Software Concepts

The 80386SL allows software compatibility by providing the same operating

modes as the 80286. The Real and Protected modes of the 80386SL are fully
compatible with 80286 instructions that use 8- and 16-bit operands. In
addition, the 80386SL extends register width as well as address and data
paths to 32 bits. This improves performance on large integer calculations,
data transfers, and large memory models. These additional functions are
transparent to applications not taking advantage of them.

When power is applied or a reset operation occurs, the 80386SL enters the
Real mode. The 80386SL then provides all the capabilities and limitations
of Real mode, including compatibility with the 8086 and the 80286. The Real
mode allows only one megabyte of physical memory to be addressed and does
not provide any memory protection features. Memory is addressed via the
segment registers with the traditional 64-Kbyte limitation on segment size.
The major distinction between the Real mode of the 80386SL and that of the
80286 microprocessor is that 32-bit operands can be used with the extended
instruction set of the 80386SL. This superset of the 80286 instruction set
allows operations, such as multiplication, to use 32-bit register or memory
operands.

The Protected mode offers features compatible with the 80286 and fully
supports the following 80286 features: memory protection, addressing via
segment selectors, and 16-bit instruction set. Protected mode also allows
for improved functions unique to the 80386 that are beyond the capability
of the 80286 segment sizes (that is, 4 gigabytes on the 80386 as compared
to 64 Kbytes on the 80286). The improved functions are memory paging, I/O
protection, Virtual 8086 mode, and Protected mode's full 32-bit extended
instruction set.

The improved functions allow implementation of much more powerful software

products. Many applications, such as artificial intelligence expert
systems, require a large linear address space and exceptional processor
performance to accommodate their size and complexity.

The 80386SL also offers the Virtual mode to provide significantly improved
compatibility with, and protection for, concurrent execution of Real mode
applications with Protected mode operating systems. The Virtual mode allows
applications written for 8088, 8086, or 80286 Real mode to be executed
within the privilege levels defined by Protected mode. In contrast, the
80286 does not allow for security in real mode applications because the
microprocessor must be in the Real mode to execute these applications.

The Virtual mode, in combination with memory paging, allows the Real mode
address space to be simulated anywhere in the physical address space of the
80386SL. In addition, the I/O protection features permit the operating
system to trap all or a selected set of I/O ports for device protection.

The COMPAQ Expanded Memory Manager (CEMM) enables the innovative use of
these features.

Speed Control

The COMPAQ LTE Lite Personal Computer implements an innovative feature that
simulates system speeds less than the (micro)processor speed. This feature
has been implemented to provide compatibility with a small number of
software products that contain programs dependent on certain system speeds.
Typically, these programs contain timing idiosyncrasies associated with the
diskette copy protection mechanisms. The processor speed can be slowed when
the program accesses the diskette drive to allow for compatibility with
these copy protection schemes.

The processor and system memory operate at processor (CPU) speed. Access to
the expansion bus and I/O devices always occurs at 8 MHz. The expansion bus
and I/O accesses are not affected by simulated changes in CPU operating
speed.

This simulated speed control is also useful for adjusting the COMPAQ LTE
Lite to handle action software games written for 8088-based personal
computers. Reduction of the system speed to simulate the system speed of an
8088-based personal computer allows these games to be played at a realistic
speed. Many games require the user to boot from the game diskette. The
COMPAQ LTE Lite accommodates this requirement by allowing the user to
restart the system, using CTRL + ALT + DEL, without affecting the selected
system speed. The system remains at the selected speed until a new speed
has been selected or a power-on reset occurs.

The COMPAQ LTE Lite system speed can be set to values that correspond to
the equivalent speeds of an 8088-based personal computer and 6- and 8-MHz
80286-based products. These values can be entered with the Mode command
(MODE SPEED=xx) from either Microsoft MS-DOS or MS OS/2 as published by
Compaq Computer Corporation, or can be used with the "Set System Speed"
BIOS function (CX=xx) to simulate the computing speed (that is, the
processor/memory system speed) of other personal computer products.
Table 3-3 lists the values that can be used to control CPU speed with the
"MODE SPEED=" command and the resulting CPU speeds.

Table 3-3. MODE SPEED Command Values

=======================================================
====================
MODE SPEED CPU Speed CPU Speed
---------------------------------------------------------------------------
Value 20 MHz Models 25 MHz Models
---------------------------------------------------------------------------
Auto * 20 MHz 25 MHz

High 20 MHz 25 MHz

Fast 10 MHz 12.5 MHz

Common 5 MHz 6.25 MHz

1-12 2.5 MHz 3.12 MHz

13-25 5 MHz 6.25 MHz

26-38 10 MHz 12.5 MHz

39-50 20 MHz 25 MHz

---------------------------------------------------------------------------
* See text below
=======================================================
====================

MODE SPEED=AUTO is typically used for accessing a diskette drive at a

slower speed because an application's software dictates it. In this mode,
the CPU operates at full processor speed except when accessing a diskette
drive, at which point the speed slows to a simulated 8 MHz until the
diskette drive motor shuts off; the speed then returns to 20 or 16 MHz.

MODE SPEED=HIGH is typically used to provide maximum performance where

an application is not speed sensitive. In this mode, the CPU operates
at processor speed at all times.

NOTE: In order to have the correct support, use the version of MODE that
comes on the User Programs diskette packaged with the computer.

Simulated CPU speed control is achieved by including special hardware on

the system board that uses extended refresh cycles to reduce the system bus
bandwidth. Since the CPU is in a HOLD state during refresh cycles, the
execution speed of programs is reduced as the length of the refresh cycles
is increased.

The 80286-based product equivalent speed values are listed for relative
reference to other speed values.

The lengthening of the refresh cycles, however, has been carefully

implemented so as not to increase the DMA latency period that is otherwise
present during refresh cycles of a normal length. A DMA request (for access
to the bus) that takes place during the extension of a refresh cycle is
immediately granted access to the bus, since the microprocessor is already
in a HOLD state.

Power Management Feature

In previous products, power management was controlled by interrupt (INT)

15. The 386SL microprocessor includes a new interrupt called the system
management interrupt (SMI). The SMI, which is non-maskable and has the
highest priority (even over the NMI), is the mechanism by which power
management functions such as hibernation are controlled in the COMPAQ LTE
Lite. The SMI is initiated by writing power management parameters to
configuration memory locations 72h, 73h, and 74h, then writing an SMI
function code to port 10h (refer to Appendix C, "Power Conservation," for a
detailed discussion on SMI-generating functions).
3.3 MATH COPROCESSOR

The 386-based COMPAQ LTE Lite includes a socket for the optional Intel
387SL math coprocessor. The 387SL math coprocessor provides floating point,
extended integer, and binary-coded decimal (BCD) data-type support. The
386SL microprocessor checks for the presence of the 387SL by sampling the
ERROR- input line after a reset. If a low is detected, the 386SL
microprocessor will be set to make use of the 387SL when applicable. A high
indicates to the 386SL that the math coprocessor is not installed.

The math coprocessor executes all numeric instructions as they are

encountered and responds to particular I/O addresses (8000F9h, 8000FFh)
that are generated by the 386SL microprocessor.

The ERROR- signal is connected to IRQ13 (INT 75h). The BIOS interrupt
handler for INT 75h routes this interrupt to INT 02h, which is the actual
routine for coprocessor exceptions. This method is used to provide
compatibility with 8088/8086 coprocessor exceptions. See Chapter 7, "BIOS,"
chapter for further information.

The 386SL provides a programmable idle clock signal to the 387SL math
coprocessor. When the 387SL is active, math coprocessing is performed at
processor (386SL) speed. The 386SL can be programmed to provide either no
idle clock signal at all or an idle clock of 1/16, 1/8, 1/4, 1/2, or at
processor frequency.

In 25-MHz 386SL-based models, the 387SL math coprocessor shares the address
and data bus used by the cache memory subsystem.

System compatibility with exception-handling for the 8087 coprocessor

exceptions is provided by an INT 02h (NMI). The numeric coprocessor BUSY-
signal is cleared by an output to port F0h.

Table 3-4 defines the port addresses used by the coprocessor on the system
board.

Table 3-4. Coprocessor I/O Map

=======================================================
====================
Port Address Bits Device
9876543210
---------------------------------------------------------------------------
F0h 00111X0XX0 Clear math processor busy

F1h 00111X0XX1 Reset math processor

F8h..FFh 0011111YYX 80387SL command ports

---------------------------------------------------------------------------
Legend: X = Don't care. The value of these bits does not affect the I/O
address decoding.
Y = Register dependent.
=======================================================
====================

4.1 INTRODUCTION
The COMPAQ LTE Lite Personal Computer contains a memory subsystem
(Figure 4-1) that includes the following:

o BIOS Flash ROM

o Configuration memory
o Cache memory (25-MHz models only)
o System memory

ILLUSTRATION OF Figure 4-1. Memory Subsystem Block Diagram

4.2 BIOS FLASH ROM

The Basic Input/Output System (BIOS) and video firmware are contained in a
single 128K x 8 Flash Read Only Memory (ROM). Flash ROM operates like
standard ROM, providing nonvolatile storage of data, but has the added
convenience of being easily reprogrammable. Without removing the ROM chip,
the BIOS can be updated with appropriate utility software that will write
the new BIOS firmware into the ROM.

The BIOS Flash ROM is accessed through the X-bus (which is off the system
bus) during the power-on self test (POST) routine (read cycle) and when the
BIOS is being updated (write cycle). Since system memory RAM provides
higher performance than the Flash ROM, the contents of the Flash ROM are
copied into system memory (between F0000h and FFFFFh) during POST. All
subsequent BIOS calls are serviced as system memory (RAM) accesses.

For a description of the BIOS firmware refer to Chapter 7, "BIOS."

4.3 CONFIGURATION MEMORY

The configuration memory contains real-time clock (RTC) data and data
pertaining to the configuration of the system. This CMOS-type memory along
with the RTC circuitry is kept nonvolatile when the system unit is turned
off by means of a dedicated lithium battery.

The configuration memory for the COMPAQ LTE Lite is contained within the
82360SL peripheral controller.

Table 4-1 lists the configuration memory locations. Configuration memory

locations are not accessed directly. Instead, all configuration memory
accesses are accomplished by writing the desired configuration memory
address with a ISA bus write cycle to I/O port 70h and then writing or
reading configuration memory data to or from I/O port 71h .

Table 4-1. Configuration Memory Locations

=======================================================
====================
Register Function
---------------------------------------------------------------------------
00h Seconds

01h Seconds Alarm

02h Minutes

03h Minutes Alarm

04h Hour

05h Hour Alarm

06h Day of Week

07h Day of Month

08h Month

09h Year

0Ah Status register A-Byte

0Bh Status register B-Byte

0Ch Status register C-Byte

0Dh Status register D-Byte

0Eh Diagnostic Status Byte

0Fh Reset Code Byte

10h Diskette Drive Type

11h Reserved

12h Fixed Disk Drive Type

13h Keyboard Options

14h Equipment Installed

15h,16h Base Memory Size

17h,18h Memory Amount

---------------------------------------------------------------------------
Register Function
---------------------------------------------------------------------------
19h Drive C Extended Fixed Disk Drive Value

1Ah Drive D Extended Fixed Disk Drive Value (not used)

1Bh Reserved

20h Reserved

21h Reserved
22h Reserved

23h Reserved

24h Fixed Disk Drive Timeout

25h Reserved

26h Reserved

27h External Drive Information (External Storage Module)

28h Internal Base Memory/Extended Memory Allocation

29h Peripheral Configuration

2Ah Reserved

2Bh System Inactivity Timeout/Power Conservation Power-Up

Condition

2Ch Screen Time-Out

2Dh Additional Flags

2Eh,2Fh Memory Checksum

30h,31h Extended Memory

32h Date, Century

33h System Information

34h through 3 Fh Reserved

72h through 73h System Management

=======================================================
====================

Time, Calendar, and Alarm Rules

The first ten bytes, 00h through 09h, hold time, calendar, and alarm
information; the contents may be in either binary or BCD format, but not a
mixture. For the format to be switched, all ten bytes must be
re-initialized in the new format.

These bytes are updated once a second, at which time alarm conditions are
also checked. Attempts to read any of the ten bytes during an update
result in undefined data output(s). Status register B-Byte, discussed
later in this section, defines the parameters. Before initializing the
internal registers, Bit <7> of Status register B should be set to "1" to
prevent updates during initialization. This bit can then be cleared to
permit regular updating.

Status and Configuration Bytes

The status and configuration bytes contain parameters that are stored in
configuration memory and used by the ROM BIOS to determine system
configuration during the boot sequence.

Status Register A -- Byte 0Ah

BIT FUNCTION
----------------
7 0 = All right to read device
1 = Time update in progress; device read not all right.

6..4 These bits specify the time base frequency. The default value
is 010 (32.768 KHz).

3..0 These bits specify the divider frequency for the clock. The
default value is 0110 (1.024 KHz).

Status Register B -- Byte 0Bh

BIT FUNCTION
----------------
7 0 = Normal operation (default)
1 = Disable time updating so that time can be set

6 0 = Interrupt disabled (default)

1 = Enable interrupt at frequency specified by Status register A

5 0 = Disable alarm interrupt (default)

1 = Enable alarm interrupt

4 0 = Enable End-of-Update interrupt (default)

1 = Disable End-of-Update interrupt

3 0 = Output disabled (default)

1 = Enables frequency output selected by Status register A

2 0 = Time and Date in BCD format (default)

1 = Time and Date in Binary format

1 0 = 12-hour mode
1 = 24-hour mode (default)

0 0 = No Daylight Savings Time (default)

1 = Daylight Savings Time selected

Status Register C -- Byte 0Ch (Read Only)

BIT FUNCTION
----------------
7 1 = Interrupt Output signal active

6 1 = Periodic Interrupt Flag

5 1 = Alarm Interrupt Flag

4 1 = End-of-Update Interrupt Flag

3..0 Reserved

Status Register D -- Byte 0Dh

BIT FUNCTION
----------------
7 0 = Real-Time Clock has lost power
1 = Real-Time Clock has not lost power

6..0 Reserved

Configuration Byte Register 0Eh -- Diagnostic Status Byte

The diagnostic status byte tells the system when there is a problem (time
invalid, faulty fixed disk drive controller, etc.) with the configuration
of the subsystems.

BIT FUNCTION
----------------
7 1 = Real-Time Clock has lost power

6 1 = CMOS Checksum invalid

5 1 = System initialization equipment check does not match the

equipment specified in the configuration memory.

4 1 = The amount of memory detected during the system initialization

is not the same as the amount specified in the configuration
memory.

3 1 = Fixed disk drive or controller failed power-on test

2 1 = Time not valid

1,0 Reserved

Configuration Byte Register 0Fh -- Reset Code Byte

The reset code tells the system what to do after the CPU is reset. The
reset code identifies the type of, or reason for, the reset. It also
provides a method of resetting the system without losing previously-stored
data or of returning the system to Real mode from Protected mode.

BIT FUNCTION
----------------
7..0 00h = Normal power-on reset
04h = Proceed to load DOS from fixed disk
05h = Jump to reset vector 0040:0067; initialize interrupt
controllers
09h = Block move return
0Ah = Jump to reset vector 0040:0067; do not initialize interrupt
controllers
Configuration Byte Register 10h -- Diskette Drive Type

This byte keeps track of drive types for two diskette drives including an
optional diskette drive installed in the External Storage Module or the
Desktop Expansion Base.

BIT FUNCTION
----------------
7..4 Primary diskette drive type:
0100 = 1.44-megabyte diskette drive only

3..0 Secondary diskette drive type:

0000 = No diskette drive
0001 = 360-Kbyte diskette drive
0010 = 1.2-megabyte diskette drive
0011 = Reserved
0100 = 1.44-megabyte diskette drive
0101 = Reserved
:
1111 = Reserved

Configuration Byte Register 12h -- Fixed Disk Drive Type

The COMPAQ LTE Lite system unit supports only one fixed disk drive, which
is designated the primary drive.

BIT FUNCTION
----------------
7..4 Primary fixed disk drive type:
0000 = No fixed disk drive type
0001 = Type 1
0010 = Type 2
0011 = Type 3
:
1110 = Type 14
1111 = Other type (see Configuration Byte 19h)

3..0 Reserved

Configuration Byte Register 13h -- Password/Network Server Mode

This byte contains the password and network server mode status.

BIT FUNCTION
----------------
7..2 Reserved
1 Password
1 = Exists
0 = not available

0 Network Server Mode

1 = Enabled
0 = Disabled
Configuration Byte Register 14h -- Equipment Installed

This byte tells the system the type of equipment installed in the unit.

BIT FUNCTION
----------------
7,6 Number of diskette drives installed:
00 = 1 drive
01 = 2 drives
10 = Reserved
11 = Reserved

5,4 Type of video display controller and operating mode:

00 = Reserved
01 = Color/Graphics, 40-column
10 = Color/Graphics, 80-column
11 = Monochrome/text

3,2 Reserved

1 0 = No coprocessor installed
1 = Coprocessor installed

0 0 = No diskette drives installed

1 = Diskette drive(s) installed

Configuration Byte Registers 15h and 16h -- Base Memory Size

Bytes 15h and 16h comprise a 16-bit value that specifies the base memory
size in increments of one Kbyte. The word is stored with the
least-significant byte at the lower address (in this case, 15h).

Table 4-2 defines valid sizes for the base memory.

Table 4-2. Valid Base Memory Size

=======================================================
====================
Byte 16h Byte 15h Memory Size (in Kbytes)
---------------------------------------------------------------------------
01h 00h 256

02h 00h 512

02h 80h 639

04h 00h 1024

08h 00h 2048

=======================================================
====================

Configuration Byte Registers 17h and 18h -- Memory Amount

Bytes 17h and 18h comprise a 16-bit value that specifies the extended
memory size in increments of one Kbyte (1024 bytes). The word is stored
with the least-significant byte at the lower address (in this case, 17h).

Table 4-3 defines the extended memory sizes for memory on all memory option
boards.

Table 4-3. Extended Memory Size

=======================================================
====================
Byte 18h Byte 17h Memory Size (in Kbytes)
---------------------------------------------------------------------------
02h 00h 512
04h 00h 1024
06h 00h 1536
: : :
20h 00h 8192
20h 80h 8320
=======================================================
====================

Configuration Byte Register 19h -- Drive C Type

This byte contains the type number. If the fixed disk drive is an extended
drive type (type 15 or greater), bits <7..4> of byte 12h contain 1111
(binary). If it is a type 59, then 59 (3Bh) is contained in this byte.
(Type 60 is also a valid drive for the COMPAQ LTE 386s/20.)

Configuration Byte Register 1Ah -- Reserved

Configuration Byte Register 27h -- Memory Allocation/Base Memory Size

Since the COMPAQ LTE 386s/20 system allows the user to have an additional
external diskette drive (installed in the optional Desktop Expansion Base
or External Storage Module) which may be configured as drive A or B, bits
<1,0> are used to keep track of this information. Bits <5..2> store
diskette drive type(s) from Configuration Byte register 10h. Bit <6> keeps
track of CPU speed.

BIT FUNCTION
----------------
7 Reserved
6 CPU speed
0 = Auto
1 = High
5..2 Configuration Byte register 10h save value

1 External drive select:

0 = Drive B
1 = Drive A
0 External drive state:
0 = External drive not installed
1 = External drive installed

Configuration Byte Register 28h -- Peripheral Configuration

Bit 7 defines the source of hardware interrupt IRQ12. Bits <6,5> hold the
Base Memory Size and indicate how much of base memory (640 Kbytes,
512 Kbytes, or 256 Kbytes) to enable. The system ROM writes out this amount
to the Memory Installed register (I/O port 1065h).

BIT FUNCTION
----------------
7 IRQ12 select:
0 = Pointing device (mouse)
1 = Expansion bus

6,5 Base Memory Size

00 = 640 Kbytes
01 = 512 Kbytes
10 = 256 Kbytes
11 = Illegal

4..0 Reserved

Configuration Byte Register 29h -- Peripheral Configuration

This register contains information about the desired configuration for the
system's peripheral devices. Included are the serial, modem, printer, and
fixed disk drive devices. The ROM writes the value from CMOS into the
Peripheral Configuration register (I/O port 0465h).

BIT FUNCTION
----------------
7 Printer Interrupt Select
0 - Printer = IRQ5
1 - Printer = IRQ7 (default)

6,5 Printer I/O Port Select

00 - Primary I/O port (default)
01 - Secondary I/O port
10 - Tertiary I/O port
11 - Disable I/O port

4 Internal Fixed Disk Drive Enable

0 - Disable internal fixed disk drive
1 - Enable internal fixed disk drive (default)

3 Serial/Modem Interrupt Select

0 = Serial = IRQ3; Modem = IRQ4
1 = Serial = IRQ4; Modem = IRQ3 (default)

2 Modem State
0 = OFF (default)
1 = ON

1 Serial State
0 = OFF
1 = ON (default)

0 Serial/Modem I/O Port Select

0 = Serial = COM1; Modem = COM2 (default)
1 = Serial = COM2; Modem = COM1

Configuration Byte Register 2Ah -- Fixed Disk Drive Timeout/Modem Status

This Power Conservation variable determines how much time, in 1-minute

multiples, before the fixed disk drive enters low power mode where power to
the motor is turned off.

The modem status bits facilitate dynamic configurability of the optional

modem in the COMPAQ LTE 386s/20 system. They are configurable through the
SETUP program.

This register is also used to determine the power-on state of the Power
Control register (I/O port 0865h), specifically for the fixed disk drive
and modem devices.

BIT FUNCTION
----------------
7 Reverse video
0 = White on black
1 = Black on white

6 Modem installed in system unit power-on state

0 - OFF (default)
1 - ON

5 Modem installed in system unit

0 - Not installed (default)
1 - Installed

4..0 Fixed disk drive timeout (minutes)

00000 - No timeout
00001 - 1 minute
00010 - 2 minutes
:
10101 - 21 minutes

Configuration Byte Register 2Bh -- Power Conservation Parameter

The first 5 bits, <4..0>, hold a Power Conservation parameter which

determines in 20-second increments how long a period of system inactivity
will elapse before the system will go into Standby. Bit <5>
enables/disables the run-time beep (configured with SETUP). The last 2
bits, <7, 6>, are for Power Conservation power-on condition and determine
how the system will be initialized for Power Conservation.

BIT FUNCTION
----------------
7,6 Power Conservation power-on condition
00 - PC AUTO (enable after 70 seconds)
01 - PC ON
10 - PC OFF

5 Run-Time Beep
0 = Enable 1 = Enable
4..0 System inactivity timeout (minutes)
00000 - No timeout
00001 - 1 minute
00010 - 2 minutes
:
10101 - 21 minutes

Configuration Byte Register 2Ch -- Screen Time-Out

The first 6 bits of this byte, <5..0>, hold a Power Conservation parameter,
which determines in 1-minute increments how long a period of keyboard
inactivity will elapse before the Backlit Display goes blank. Bit <6>
determines the Num Lock key status.

BIT FUNCTION
----------------
7 Reserved

6 NUM LOCK status

0 = Off 1 = On

5..0 Screen timeout value at power-on: (minutes)

000000 - No timeout
000001 - 1 minute
000010 - 2 minutes
:
111111 - 63 minutes

Configuration Byte Register 2Dh -- Additional Flags

This byte allows the configuration of special video features and disables
or enables keyclicking.

BIT FUNCTION
----------------
7..3 Reserved

2 0 = Video display controller not manufactured by Compaq installed

in Desktop Expansion Base
1 = COMPAQ Video Display Controller installed

1 0 = Disable keyclick
1 = Enable keyclick

0 0 = Monitor installed not dual-scan

1 = Dual-scan LCD installed

Configuration Byte Register 2Eh and 2Fh -- Memory Checksum

Value stored is the checksum for memory addresses 20h..2Dh.

Byte 2Eh = high byte of checksum

Byte 2Fh = low byte of checksum
Configuration Byte Registers 30h and 31h -- Extended Memory

Values indicate the amount of system memory in excess of 1 megabyte

detected at power-on. Bytes 17h and 18h are user defined. Bytes 30h and 31h
are tested by ROM and compared with 17h and 18h. The table below defines
the extended memory sizes.

=======================================================
====================
Byte 31h Byte 30h Memory Size
(in Kbytes)
---------------------------------------------------------------------------
02h 00h 512

04h 00h 1024

06h 00h 1536

08h 00h 2048

0Ah 00h 2560

0Ch 00h 3072

0Eh 00h 3584

10h 00h 4096

12h 00h 4608

14h 00h 5120

16h 00h 5632

18h 00h 6144

1Ah 00h 6656

1Ch 00h 7168

1Eh 00h 7680

=======================================================
====================

Configuration Byte Register 32h -- Date, Century

This is the century part of the current time and date encoded in BCD
(binary-coded decimal). The BIOS sets and reads this value.

Configuration Byte Register 33h -- System Information

BIT FUNCTION
----------------
7 1 = More than 1 megabyte of memory installed
0 = Less than 1 megabyte of memory installed
6 Used by SETUP procedures

5 Reserved

4 Coprocessor
1 = Installed
0 = Not installed

3 Run-Time Beep
1 = Disabled
0 = Enabled

2..0 Reserved

4.4 CACHE MEMORY

Cache memory is a relatively small amount of memory that provides higher

performance than normal system memory. Using fast Static RAM, cache memory
reads and writes can occur without the CPU having to insert wait states.
Since cache memory is smaller in size than system memory, a mechanism is
employed where only the most frequently used data is kept in the cache.

The cache memory subsystem of 25-MHz COMPAQ LTE Lite models consists of a
cache controller and 16- or 64-Kbytes of SRAM and provides zero-wait state
performance for most memory accesses. The cache controller is integrated
into the 386SL microprocessor and is programmed by BIOS at power-up to use
four-way set-associative mapping. Four-way set-associative mapping is the
most efficient caching scheme for most applications.

The cache memory uses the write-through mode of operation. In this mode of
operation, any data written into cache memory is also written into system
memory, ensuring that system memory always contains valid data.

Four-Way Set-Associative Mapping

For caching purposes, the system memory is organized into lines, blocks,
and pages. A line consists of two bytes and is the unit of transfer between
system memory and cache memory. These lines are grouped into blocks of 16
lines each. A 30-bit cache tag, which is used to determine the location,
validity, and frequency of use of data stored in the cache, is associated
with each block. The cache tags are stored in a 2-Kbyte RAM that is an
integrated part of the cache controller. In four-way set-associative
mapping, the cache tags are arranged into four sets that correspond to four
areas of the cache memory. Each area of cache memory can hold an amount of
data equal to one page of system memory data. The size of the cache memory
determines the size of a page of system memory.

Figure 4-2 shows the relationship between 16 kilobytes of cache memory and
4 megabytes system memory. The blocks of cache memory and system memory are
relative, i.e., locations in a block 0 of system memory will be mapped into
block 0 of area A, B, C, or D.

ILLUSTRATION OF Figure 4-2. 16-Kbyte Cache Memory/4-Megabyte System Memory

Relationship
Figure 4-3 shows the relationship between 64 kilobytes of cache memory and
four megabytes of system memory. In this configuration, a page of system
memory equals 512 blocks.

ILLUSTRATION OF Figure 4-3. 64-Kbyte Cache Memory/4-Megabyte System Memory

Relationship

Cache Flushing

Flushing the cache invalidates data held in the cache memory. The cache can
be flushed by disabling then re-enabling the cache, and by booting or
resetting the system. Following a cache flush, all subsequent memory
accesses will be cache misses until a particular location is accessed a
second time.

Non-Cacheable Addresses

Non-cacheable addresses are locations in system memory where write or read

accesses are not complemented with a cache memory update. To maintain cache
coherency for CPU-memory accesses, the areas of system memory used by such
functions as BIOS ROM copying, SM-RAM, and memory mapped I/O are marked as
non-cacheable.

Table 4-4. Non-Cacheable Addresses

========================================
Condition Address
----------------------------------------
SM-RAM enabled 30000h - 3FFFFh

BIOS/Video ROM B0000h - FFFFFh

========================================

All accesses to addresses beyond the installed extended memory go directly

to the Expansion bus. This allows adapters with dual-ported memory (for
example, multiport serial cards) to be placed above this address without
being cached.

Enabling/Disabling Cache Memory

The cache memory can be enabled or disabled by the following DOS commands.

o MODE MEM=ON This command enables cache memory.

o MODE MEM=OFF This command disables cache memory.

4.5 SYSTEM MEMORY

COMPAQ LTE Lite models come standard with two or four megabytes of 70-ns
enhanced-page Dynamic Random Access Memory (DRAM) as standard system
memory. The system memory controller is integrated into the 386SL
microprocessor. This controller supports LIM 4.0 EMS mapping and permits
traditional Direct Memory Access (DMA). The 82360SL provides local memory
refresh support and allows bus master control of memory.
Figure 4-4 shows the arrangement of the standard four megabytes of system
memory of 25 MHz COMPAQ LTE Lite models.

ILLUSTRATION OF Figure 4-4. 25-Mhz COMPAQ LTE Lite Models System Memory
Block Diagram

Figure 4-5 shows the arrangement of the standard two megabytes of system
memory of the COMPAQ LTE Lite/20.

ILLUSTRATION OF Figure 4-5. COMPAQ LTE Lite/20 System Memory Block Diagram

Memory Expansion

A dedicated internal expansion slot permits increasing system memory by

adding an optional 2-, 4-, or 8-, or 16-Megabyte * Memory Card for a total
of up to 20 megabytes depending on model.

* The 16-Megabyte Memory Card is not supported by the COMPAQ LTE Lite/20.

Memory Control

The 386SL microprocessor accesses data from system memory as bytes (8 bits)
or words (16 bits). When it accesses a word on an even boundary, the CPU
gives that word an even-numbered address and simultaneously reads from or
writes to, as appropriate, that address and the one above it.

Memory Refresh

Refresh is provided to prevent loss of data in DRAM devices. The memory

controller of the 386SL microprocessor performs a DRAM refresh when the
REFREQ signal is asserted by the 82360SL peripheral controller. Refresh is
usually initiated by the 82360SL but can also be initiated with the
REFRESH- signal sent from a bus master installed in the Desktop Expansion
Base to the 82360SL.

If an external bus master wants to control the bus for an extended period,
that bus master must perform the refresh or risk losing the contents of
dynamic memory. The external bus master performs the refresh by developing
its own refresh request timer and internal arbitration.

If a refresh is in progress when a DMA cycle is requested, the DMA cycle

runs without allowing the CPU to regain control of the bus. If a direct
memory cycle is in progress when a refresh is requested, the refresh cycle
runs without allowing the CPU to regain control of the bus. Refresh and
other DMA cycles are started on a first-come, first-serve basis after the
CPU releases the bus.
The standard DRAM used in COMPAQ LTE Lite Personal Computers feature low
power consumption and slow refresh times to provide longer battery usage.
The optional memory cards specifically designed for COMPAQ LTE Lite
Personal Computers also share the low power and slows refresh
characteristics. The refresh rates are dependent on the configuration of
the system and whether or not the system is in Standby. Table 4-5 shows the
refresh times for the various system configurations.

Table 4-5. DRAM Refresh Specifications

=======================================================
====================
Configuration Standard Memory Expansion
Refresh Rate Connector
Refresh
Rate
---------------------------------------------------------------------------
Stand-alone Unit -- Normal operation:
No expansion memory 124.8 usec N/A
70 nsec expansion memory 124.8 usec N/A
80 nsec expanded memory/16-MB memory card 15.6 usec N/A

Stand-alone unit -- Standby operation:

No expansion memory 124.8 usec N/A
70 nsec expansion memory 124.8 usec N/A
80 nsec expanded memory/16-MB memory card 15.6 usec N/A

Unit with Desktop Expansion Base:

No expansion memory 124.8 usec 15.6 usec
70 nsec expansion memory 124.8 usec 15.6 usec
80 nsec expanded memory/16-MB memory card 15.6 usec 15.6 usec
=======================================================
====================

Memory Map

The system memory is typically configured with 640 Kbytes of base memory
with the extended memory mapped as shown in Figure 4-6.

ILLUSTRATION OF Figure 4-6. System Memory Map with 640-Kbyte Base Memory

5.1 INTRODUCTION

This chapter describes the expansion capability of the COMPAQ LTE Lite as
provided through the 198-pin external interface connector on the back of
the system unit. This connector allows optional peripherals such as the
Desktop Expansion Base, External Storage Module, or an external keyboard
and mouse to be added to the system unit.

The 198-pin external interface connector, in addition to duplicating access

to communications and video interfaces, also allows access to the 8-/16-bit
Industry Standard Architecture (ISA) expansion bus through the Desktop
Expansion Base.
This chapter covers the following topics:

o ISA expansion bus [5.2]

o Expansion interface connector signal descriptions [5.3]

5.2 ISA EXPANSION BUS

The ISA expansion bus, which operates at 8-MHz, is intended primarily for
use by I/O devices. Accessing memory via the ISA expansion bus degrades the
performance of the COMPAQ LTE Lite. For best system performance, the
memory expansion slot, which operates at processor speed, should be used
for all memory expansion.

Logic contained within the 386SL and the 82360SL provide all control
functions of the ISA expansion bus, which exists as a shared function of
the system bus described in Chapter 3 "Processor." The ISA expansion bus
provides 8- and 16-bit data transfers with integrated peripherals as well
as expansion devices installed in the Desktop Expansion Base.

Expansion boards that do not strictly conform to ISA specifications may not
function properly. Boards most likely to fall into this category are bus
masters that are capable of gaining control of the ISA expansion bus. If an
external bus master is accessing internal memory and the SL chipset
deasserts BUSRDY (adds a wait state), the bus master should not sample the
system data (SD) lines when the BUSRDY signal is reasserted but should
sample the SD lines when the data is valid.

The 386SL is specified to have a maximum delay of 48 nsec from the

deassertion of BUSRDY until the data is valid on the SD lines. The data
should not be sampled until this delay is met along with any propagation
delays and external logic timing requirements. One method of achieving this
is by extending the deasserted BUSRDY signal to the external bus master
until the data is valid and then reasserting the BUSRDY signal. The timing
of the BUSRDY signal from an external device to the system unit should not
be altered.

For more information regarding ISA expansion operations and timing, refer
to the documentation listed in Chapter 1, "Introduction."

5.3 EXTERNAL INTERFACE CONNECTOR SIGNAL DESCRIPTIONS

Table 5-1 provides a description of the 198-pin external interface

connector signals. For a pinout of the 198-pin external options interface
connector, refer to Appendix B, "Connectors." The signal descriptions are
grouped according to function.

Table 5-1. External Interface Connector Signals

=======================================================
====================
Signal I/O Pin Description
Name
---------------------------------------------------------------------------
ISA Expansion Bus Signals
---------------------------------------------------------------------------
SA19 I/O 131 These bidirectional signals address
SA18 I/O 130 memory or I/O devices within the
SA17 I/O 129 system. They form the low-order
SA16 I/O 127 20 bits of the 24-bit address bus that
SA15 I/O 126 the system offers. These lines are
SA14 I/O 125 enabled onto the bus while BALE is
SA13 I/O 123 high and are latched when BALE goes
SA12 I/O 122 from a high to a low state. These
SA11 I/O 121 signals can be driven by an expansion
SA10 I/O 120 bus board acting as a bus master.
SA9 I/O 118
SA8 I/O 117
SA7 I/O 116
SA6 I/O 114
SA5 I/O 113
SA4 I/O 112
SA3 I/O 165
SA2 I/O 164
SA1 I/O 163
SA0 I/O 161
---------------------------------------------------------------------------
LA23 I/O 160 These signals (latchable address)
LA22 I/O 159 decode memory that must respond with
LA21 I/O 157 0 or 1 wait state or that is addressed
LA20 I/O 156 above 1 Mbyte. They are guaranteed to
LA19 I/O 155 be valid when BALE is high. They can
LA18 I/O 154 be driven by an expansion board acting
LA17 I/O 152 as a bus master.
---------------------------------------------------------------------------
SD15 I/O 78 These bidirectional signals are the
SD14 I/O 79 high 8 bits of the system data bus.
SD13 I/O 80 Also, 16-bit devices should use these
SD12 I/O 82 lines to transfer the high half of a
SD11 I/O 83 data word when the line SBHE- is low.
SD10 I/O 84 They can be driven by an expansion bus
SD9 I/O 86 board acting as a bus master. An
SD8 I/O 87 expansion card should have no more than
two Low power Schottky loads (0.8 mA
low, 400 uA high, 50 pF) on this bus.

---------------------------------------------------------------------------
Signal I/O Pin Description
Name
---------------------------------------------------------------------------
ISA Expansion Bus Signals
---------------------------------------------------------------------------
DAK0* O 33 These output signals (Dma
DAK1* O 32 AcKnowledge) indicate that a request
DAK2* O 31 for a DMA service from the DMA
DAK3* O 66 subsystem has been recognized. The
DAK5* O 65 acknowledge is indicated by a LOW on
DAK6* O 63 this line. Use this line with the
DAK7* O 62 IORC- or IOWC- line to decode the
desired DMA device. If used to signal
acceptance of a bus-master request,
this signal indicates when it is
legal to pull GRAB- low.
---------------------------------------------------------------------------
RESETDRV O 76 This signal (bus reset) is driven
active when the unit is powered up
and when the unit exits from a low
power suspended state (Standby or
sleep condition) When high, this
output signal indicates that the
terminal count of a DMA operation has
been reached. It should be decoded
with the appropriate DAKx line for
proper operation.
---------------------------------------------------------------------------
TC O 99 This input signal is used to signal
the CPU about parity or other serious
errors on expansion memory boards
plugged into the expansion bus.
---------------------------------------------------------------------------
IOCHCK* I 110 This signal should be driven low by
an open-collector output capable of
sinking 20 mA when an uncorrectable
system error occurs.
---------------------------------------------------------------------------
NOWS- I 143 This input signal (No Wait State)
informs the system that standard wait
states can be deleted for cycles when
this signal is made active. If a
16-bit memory device wants to prevent
the standard wait state then it must
pull the NOWS- line low (active)
before BCLK falls after the falling
edge of BALE. (Note that this is not
possible on 16-bit I/O cycles because
it is not known that an I/O cycle
exists until the required time.) If
an 8-bit device wants to prevent the
standard wait states then it must
pull the NOWS- line low (active)
within one BCLK time from the falling
edge of the command. The decode logic
to drive NOWS- should use the device
address and MRDC-, MWTC-, IORC- or
IOWC- as inputs. If less than the
four standard wait states normally
used on 8-bit bus cycles is desired,
then the NOWS- line can be used to
provide 1, 2, or 3 wait states by
delaying the activation of NOWS-. The
NOWS- line is sampled at
approximately the falling edge of
BCLK. It should be driven by an
open-collector device capable of
sinking 20 mA.

---------------------------------------------------------------------------
Signal I/O Pin Description
Name
---------------------------------------------------------------------------
ISA Expansion Bus Signals
---------------------------------------------------------------------------
M16- O 178 This input signal (memory is 16 bits)
notifies the system that the
addressed memory is capable of
transferring 16 bits of data at once.
When this line is made active during
a memory read or write, the standard,
1-wait-state memory cycle is run.
This line should be derived from the
LAxx address lines. Do NOT decode the
M16- line with any of the SAxx lines
or BALE for full compatibility with
COMPAQ products. The M16- line must
be correct before BALE goes inactive
to ensure that it is latched by the
system board latch. Pulling this line
low prevents the 16-bit to 8-bit bus
conversion logic from being
activated. It should be driven low by
an open-collector device capable of
sinking 20 mA.
---------------------------------------------------------------------------
GRAB- I 180 This input signal indicates that a
board-mounted bus master is
controlling the bus. A board pulls
this line low when the appropriate
DAKx line is made active, signaling
that a master request is granted. The
system address, data, and control
lines are floated, allowing the board
to begin controlling them one full
BCLK period after GRAB- becomes
active. At least one more full BCLK
period should be allowed after
putting a valid address on the bus
before activating any of the control
lines. On release, the control lines
should be driven inactive, then all
lines should be floated. After this,
the GRAB- and DRQx lines can be made
inactive. This line should be driven
by an open-collector device capable
of sinking 20 mA.
---------------------------------------------------------------------------
SBHE- I/O 181 This signal (byte high enable)
indicates, when low, that data is
being transferred on the high byte of
the data bus (SD15..8).
---------------------------------------------------------------------------
REFRESH- I/O 182 This signal indicates a refresh cycle
is in progress.

Keypad I 42 Numeric keypad data

KYBD CLK I/O 44 External keyboard clock line

KYBD DATA I/O 45 External keyboard data line

Mouse CLK I/O 46 Mouse clock line

G Data O 16 Green video data

B Data O 17 Blue video data

HS O 18 Horizontal sync

VS O 19 Vertical sync

GND - 48 Video ground

GND - 49 Video ground

GND - 50 Video ground

RI I 22 Ring indicate
TXD O 23 Transmit data

CTS I 24 Clear to send

RXD I 26 Receive data

RTS O 27 Ready to send

CD I 28 Carrier detect

DSR I 29 Data set ready

BUSY I 2 Printer busy

STB- O 8 Strobe

PE I 35 Out of paper (end)

ACK- I 36 Acknowledge

AUTOLF- O 101 Auto line feed

ERROR- I 102 Error

INIT- O 104 Initialize

SLCTIN- O 133 Select

D0 I/O 41 Data lines

D1 I/O 7

D2 I/O 40

D3 I/O 6

D4 I/O 38

D5 I/O 4

D6 I/O 37

D7 I/O 3

WRTDATA- O 72 Write data

STEP- O 74 Step signal

TRK0- I 75 Track 0

WRTGATE- O 105 Write gate

RDATA- I 106 Read data

BOOT I 134 This signal, when present during

POST, allows the external diskette
drive to be the system's boot
drive (A).

LWDENMD- I 135 Low density media in the external

diskette drive.

DIRIN- O 136 Direction select when stepping the

head.

INDEX- I 138 Index pulse.

DSKCHNG- I 139 The door to the diskette drive has

been opened.

HEADSEL O 140 Head select.

DSEL- O 166 Drive select.

LOWDEN- O 167 Low density select.

-- O 168 Reserved.

EXT-FPY- I 169 External diskette drive present.

DSEL4- O 170 Drive select 4 (tape).

MOTOR- O 172 Motor on.

=======================================================
====================

6.1 INTRODUCTION

This chapter describes the communications capabilities of the COMPAQ LTE

Lite. The following subjects are discussed:

o Serial port
o Parallel port
o Enhanced option slot

6.2 SERIAL PORT

The COMPAQ LTE Lite includes as standard one serial port for connection to
an asynchronous communications device. The serial port connector is located
on the back of the system unit and is duplicated on the back of the
optional Desktop Expansion Base. The serial port function is provided by
the 82360SL peripheral controller and a RS-232-C driver/receiver that
includes a low-power shut down feature.

The serial port is I/O-mapped at addresses 3F8h..3FFh when configured for

COM1 and 2F8h..2FFh when configured for COM2. The serial port may also be
disabled. For detailed programming information on the serial port refer to
the documentation listed in Chapter 1, "Introduction."

6.3 PARALLEL PORT

The COMPAQ LTE Lite includes one parallel port primarily for connection to
a printer. The parallel port, located on the back of the system unit and
duplicated on the optional Desktop Expansion Base, also supports PS2
operations and high-speed bidirectional data transfers with devices using a
compatible parallel interface. The parallel port can be mapped at addresses
3BCh..3BEh for LPT1, 378h..37Ah for LPT2, or 278h..27Ah for LPT3. The
parallel port function is contained completely within the 82360SL
peripheral controller. For detailed programming information, refer to the
documents listed in Chapter 1, "Introduction."

6.4 ENHANCED OPTION SLOT

The enhanced option slot provides the COMPAQ LTE Lite with internal
expansion of communications capabilities. The enhanced option slot is a
programmable interface that can be adapted to accommodate a variety of
peripherals such as modems, modem/faxes, second serial port modules, etc.

Configuration Registers

The enhanced option slot is controlled through the following I/O-mapped

registers:

o Peripheral Configuration Register (0465h)

o Option Slot Configuration Register (2865h)
o Option Slot Address Register (2C65h)
o Miscellaneous Options Register (3465h)

It should be noted that these registers control some functions unrelated to

the enhanced option slot. Also, there is a close working relationship
between registers in defining some configurations.

Peripheral Configuration Register (0465h)

The Peripheral Configuration Register defines the mapping of the enhanced

option slot interface. Bits <7>, <3>, and <1> are used in conjunction with
bits <3> and <2> of the Option Slot Configuration Register (refer to
Table 6-1) to determine the mapping of the Option Slot IRQ.
Read/Write I/O Address 0465h, Power Up Value = 00000010b

BIT FUNCTION
----------------
7 Slot IRQ Printer Interrupt Mapping
0 = SLOTIRQB mapped to IRQ7
1 = SLOTIRQB mapped to IRQ5

6..4 RESERVED

3 Option Slot IRQ Mapping

0 = SLOTIRQA mapped to IRQ4, SLOTIRQB to IRQ3 (default)
1 = SLOTIRQA mapped to IRQ3, SLOTIRQB to IRQ4

2 Option Slot Address Decode

0 = Enable COM decode and SLOT IRQA
1 = Disable COM decode and SLOT IRQA

1 Option Slot IRQB Mapping:

0 = Enable SLOT IRQB to map to IRQ3/4
1 = Disable IRQB if mapped to IRQB3/4

0 Option Slot I/O Address

0 = SLOT CS signal responds as COM2 (default)
1 = SLOT CS signal responds as COM1

Option Slot Configuration Register (2865h)

The Option Slot Configuration Register is used to configure the address

decode range length, the DMA channel (request/acknowledge) if required, as
well as the mapping of the interrupts for the enhanced option slot.
Bits <3> and <2> are used in conjunction with bits <7>, <3>, and <1> of the
Peripheral Configuration Register to determine interrupt mapping for the
Option slot (refer to Table 6-1).

Read/Write I/O Address 2865h, Power Up Value = 00000000b

BIT FUNCTION
----------------
7,6 RESERVED

5..3 SLOT IRQB (interrupt request B) mapping

000 = IRQ3 (default) 001 = IRQ4
010 = IRQ5 011 = IRQ7
100 = IRQ9 101 = N/A
110 = N/A 111 = N/A

5,4 DMA Mapping

00 = DMA disabled
01 = DRQ1, DAK1
10 = DRQ3, DAK3
11 = DRQ5, DAK5

3,2 Interrupt Mapping (Refer to Table 6-1)

1,0 Address Decode Range Length
00 = 8 bytes, address bit 3 compared
01 = 16 bytes, address bits 4 - 9 compared
10 = 32 bytes, address 5 - 9 compared
11 = 64 bytes, address bits 6 - 9 compared

Table 6-1. Enhanced Option Slot Addressing

=======================================================
====================
Peripheral Configuration Option Slot Configuration IRQB
Register Register
------------------------ ------------------------
Bit 7 Bit 3 Bit 1 Bit 3 Bit 2
---------------------------------------------------------------------------
0 0 0 0 0 Disabled
0 0 0 0 1 IRQ3
0 0 0 1 0 IRQ7
0 0 0 1 1 IRQ9
0 0 1 0 0 Disabled
0 0 1 0 1 Disabled
0 0 1 1 0 IRQ7
0 0 1 1 1 IRQ9
0 1 0 0 0 Disabled
0 1 0 0 1 IRQ4
0 1 0 1 0 IRQ7
0 1 0 1 1 IRQ9
0 1 1 0 0 Disabled
0 1 1 0 1 Disabled
0 1 1 1 0 IRQ7
0 1 1 1 1 IRQ9

=======================================================
====================
Peripheral Configuration Option Slot Configuration IRQB
Register Register
------------------------ ------------------------
Bit 7 Bit 3 Bit 1 Bit 3 Bit 2
---------------------------------------------------------------------------
1 0 0 0 0 Disabled
1 0 0 0 1 IRQ3
1 0 0 1 0 IRQ5
1 0 0 1 1 IRQ9
1 0 1 0 0 Disabled
1 0 1 0 1 Disabled
1 0 1 1 0 IRQ5
1 0 1 1 1 IRQ9
1 1 0 0 0 Disabled
1 1 0 0 1 IRQ4
1 1 0 1 0 IRQ5
1 1 0 1 1 IRQ9
1 1 1 0 0 Disabled
1 1 1 0 1 Disabled
1 1 1 1 0 IRQ5
1 1 1 1 1 IRQ9
=======================================================
====================

Option Slot Address Decode Register (2C65h)

The Option Slot Address Decode Register defines the base address to be used
when the enhanced option slot is used for a function other than COM1 or
COM2. The 10-line address bus (SA9..SA0) is programmable for address range
lengths of 8, 16, 32, or 64 bytes as defined by the Option Slot
Configuration Register. The Option Slot Address Decode Register further
defines address decoding by specifying the LAx bit(s) to be compared for
generating the SLOT CS- signal, which indicates that the enhanced option
slot logic has performed a valid I/O address decode.

Read/Write I/O Address 2C65h, Power Up Value = 00000000b

BIT FUNCTION
----------------
7 Programmable address decode enable
0 = Address determined by Peripheral Configuration Register
1 = Address determined by Option Slot Address and Option Slot
Configuration Registers

6..3 Starting address bits 9-6. These are compared to bits SA9..SA6 in a
64-byte decode range. SLOT-CS is generated if these and all other
bits compare

2 Starting address bit 5. This bit is compared with SA5 in an

8-, 16-, or 32-byte decode range. SLOT-CS is generated if these
and bits SA9..SA6 compare.

1 Starting address bit 4. This bit is compared with SA4 in an

8- or 16-byte decode range. SLOT-CS is generated if these and bits
SA9..SA5 compare.

0 Starting address bit 3. This bit compared with SA3 in an 8-byte

decode range. SLOT-CS is generated if these and bits SA9..SA4
compare.

Miscellaneous Options Register (4365h)

The Miscellaneous Options Register controls the SLOT ON signal to the

Option slot. This register also controls other functions unrelated to the
Options Slot. The state of bit <2> reflects the condition of the SLOT ON
signal. The SLOT ON signal can be used by a device connected to the Option
Slot to turn off power or enter a low power or "sleep" mode to conserve
battery power. The SLOT RST signal is asserted for 10 msec whenever the
SLOT ON signal is toggled. The other functions of this register are covered
in the appropriate chapters.

Read/Write I/O Address 3465h, Power Up Value = 00000100b

BIT FUNCTION
----------------
7..4 RESERVED
3 Force Disk Change
0 = Disk change clear enable
1 = Force disk change

length
---------------------------------------------------------------------------
x = Don't care
=======================================================
====================

Enhanced Option Slot Connector Signals

The enhanced option slot interface uses a 50-pin connector to transfer

signals to/from an optional modem, second serial port, or other I/O device.
Table 6-3 describes the connector signals, which in effect represent a
subset of the ISA expansion bus interface. The timing of the enhanced
option slot signals is identical to that of ISA expansion bus signals. The
I/O designation is with respect to the device installed in the enhanced
option slot.

Table 6-3. Enhanced Option Slot Signal Descriptions

=======================================================
====================
Pin I/O Signal Name Function
---------------------------------------------------------------------------
1 I GND Ground
26 I GND Ground
27 I GND Ground
---------------------------------------------------------------------------
2 I/O DB00 These bidirectional lines are used for
3 I/O DB01 all byte transfers with 8-bit devices.
4 I/O DB02 16-bit devices use these lines for
5 I/O DB03 transferring the low byte in a word
6 I/O DB04 transfer (XA0B low).
7 I/O DB05
8 I/O DB06
9 1/O DB07
---------------------------------------------------------------------------
29 I/O DB15 These bidirectional lines are used
30 I/O DB14 exclusively by 16-bit devices for
31 I/O DB13 transferring the high byte in a word
32 I/O DB12 transfer.
33 I/O DB11
34 I/O DB10
35 1/O DB09
36 1/O DB08
---------------------------------------------------------------------------
10 I SLOT CS- When active (low), indicates that the
option slot interface logic has
generated a valid I/O address decode.
---------------------------------------------------------------------------
11 I SIOWC- I/O write command (active low)
---------------------------------------------------------------------------
12 I SIORC- I/O read command (active low)
---------------------------------------------------------------------------
13 O SLOT IRQA Interrupt request for the option slot
interface. May be configured as IRQ3
or IRQ4.
---------------------------------------------------------------------------
14 I/O BUSRDY- This signal lengthens a bus signal from
its standard length when a controller
board cannot respond quickly enough.
BUSRDY- should be pulled low as soon as
a slow device is selected and should be
held low until the device has
responded. Bus cycles are lengthened by
an integral number of BCLK cycles. This
line should not be held low for more
than 2.5 us. It should be driven by an
open collector device capable of
sinking 20 mA.
---------------------------------------------------------------------------
15 I +5 VDC DC power for option slot interface
16 I +5 VDC device (350 mA total current load).
---------------------------------------------------------------------------
17 I SLOT RST Reset signal used to clear all
registers and control logic of the
option slot interface.
---------------------------------------------------------------------------
18 I SA0 These lines provide local address
19 I SA1 signals to the option slot interface
20 I SA2 device. The option slot interface logic
37 I SA3 can be programmed to decode I/O address
38 I SA4 range lengths of 8, 16, 32, and 64
39 I SA5 bytes.
40 I SA6
41 I SA7
42 I SA8
43 I SA9

---------------------------------------------------------------------------
Pin I/O Signal Name Function
---------------------------------------------------------------------------
21 I COMMCLK 1.8432 MHz clock, 50 percent duty
cycle. Not present when the computer
is in a Standby or sleep condition.
---------------------------------------------------------------------------
22 -- Reserved Not used
---------------------------------------------------------------------------
23 O WAKEUP- This signal, when low, brings the
system out of Standby.
---------------------------------------------------------------------------
24 I SLOT ON This signal can be used to control an
option slot device's low power (sleep)
mode capabilities.
---------------------------------------------------------------------------
25 O MSPKDRV Audio output to system speaker (5 volts
RMS maximum into 10K ohm load).
---------------------------------------------------------------------------
28 I DMA This signal, when active (high),
indicates a DMA cycle is in progress.
---------------------------------------------------------------------------
44 O SLOT DMA- This signal, when active (low),
indicates to the system that the option
slot interface device is capable of DMA
operations. It should be driven by an
open collector device capable of
sinking 20 mA.
---------------------------------------------------------------------------
45 I T-C When high, this signal indicates that
the terminal count of a DMA operation
has been reached.
---------------------------------------------------------------------------
46 O SLOT IRQB Interrupt request for option slot
interface devices using programmable
address decoding. This signal may be
programmed as IRQ3, IRQ4, IRQ5, IRQ7,
or IRQ9.
---------------------------------------------------------------------------
47 O I/O16- This signal, when low, notifies the
system that the addressed device is
capable of supporting 16-bit transfers.
It should be driven by an open
collector device capable of sinking
20 mA.
---------------------------------------------------------------------------
48 O SLOT DRQ DMA request. This signal may be
configured as DRQ1, DRQ3, or DRQ5.
---------------------------------------------------------------------------
49 O SLOT IOEN- I/O enable. This signal indicates, when
low, that the option slot device has a
valid I/O address decode.
---------------------------------------------------------------------------
50 I SLOT DAK DMA acknowledge. This signal indicates
to the option slot that the system has
recognized the SLOT DRQ.
=======================================================
====================

7.1 INTRODUCTION

The basic input/output system (BIOS) of a computer is the collection of

machine language programs contained in read-only memory (ROM) that controls
the most fundamental processes or functions of the system such as:

o Execution of power-on self-tests

o Initialization of the system
o Interaction with the display, diskette and hard drives, communications
devices, and other peripheral devices

In addition, the BIOS supports:

o Power Conservation Features

o Video Graphics Controller

Fundamentals of Interrupt Service Calls

BIOS functions are accessed by the processor interrupt (INT) instruction.

This is a software interrupt, or service call, requesting that a certain
function be performed. For example, when the processor encounters the
instruction INT 10h (video I/O), it invokes the program or routine in the
BIOS memory that controls the video functions.
Before the INT instruction can be used, the processor's registers must be
set up with the values assigned to the function desired. The formats for
the register values are described at each function. The values in the
register after the function call (INT) also depend upon the function. To
prevent major software problems, routines interfacing to higher level
language programs (such as BASIC, C, Pascal, or Prolog) that use service
calls, must be written so as to ensure that, when a function is complete,
the register values are returned to the pre-service call state.

When the processor is operating in Real mode, the system stores a software
interrupt memory location table in RAM, starting at address 0000:0000
(segment:offset). A vector is a pointer to another location. For example,
memory locations 40h..43h contain a vector to the video interrupt service
routine; when INT 10h (video I/O) is called, the processor looks to memory
locations 40h..43h for the address of that routine. In the Protected mode,
the vector table can begin anywhere in physical memory as defined by the
Interrupt Descriptor Table (IDT) base register in the processor.

Interrupts caused by hardware devices also have service routines in memory.

The vectors for these interrupts are included in the interrupt memory
location tables in this chapter.

Some interrupt calls have more than one function available, requiring some
method of specifying which function is desired. This information is
provided by loading the AH register with the number of the desired function
before the INT instruction is issued.

In some cases, more than one parameter (value) must be loaded into the
processor's registers before the INT instruction is issued. Before using a
software INT instruction, always ensure that all registers are properly
set.

All register contents, except for the AX register and any other register
specifically mentioned in the corresponding INT section, are preserved when
the interrupt service calls return to the calling program.

BIOS Initialization

When the processor is reset, execution begins at address FFFFFFF0h, which

is located in the system BIOS ROM. Processor reset always occurs when the
computer is turned on (a "cold boot"). It can also be initiated by holding
down the Ctrl + Alt + Delete keys (a "warm boot"). Finally, processor reset
can occur under program control, usually to resume program execution in
Real mode.

The BIOS senses an initial "power-on" condition when the system flag
(bit <2>) in the 8042 keyboard controller status port is "0." Subsequent
power-on functions performed by the BIOS consist of EISA expansion board
initialization, device initialization, diagnostic tests, configuration
sensing and verification, and bootstrapping from either the diskette drive
or a hard drive.

Normal Reset
Normal reset includes the following operations:

o Initialization of programmable devices

o Video display controller initialization

o BIOS stack (SS:SP) established

o EISA expansion board initialization

o Memory map initialization

o RAM test

o Cache test

o Real-time clock initialization

o Initialization and test of keyboard, diskette drive, and hard drive (and
their respective controllers)

o A20 gate disablement, enabling 20-bit address wrap around

o Option ROMs scanning

Before the system is bootstrapped, hardware interrupts IRQ1 (for the

keyboard) and IRQ9 (a chain to IRQ2) are also enabled. Control then
transfers to INT 19h, the system bootstrap.

Software Reset

Because the processor can be reset for a variety of software-related

reasons, a byte in the configuration memory (0Fh) has been set aside to
record a "reset code." This code is loaded immediately before the keyboard
controller is requested to issue a system reset command and is examined
afterwards to tell the BIOS what operation was in effect before the reset.
When a vector is needed for a return address or a pointer to a saved
environment, the reset vector at address 0040:0067 is used.

Several reset codes have been set aside for use when system software needs
to switch from Protected mode to Real mode. These are listed in Table 7-1.

Table 7-1. Reset Codes

=======================================================
====================
Code Function Action Reset Vector (0040:0067)
---------------------------------------------------------------------------
00h Normal reset Reserved

04h Reset with Reserved

Boot Request

05h Return EOI Return address (CS:IP)

09h Return from Pointer to stack frame (SS:SP)

Block Move (used internally by BIOS INT 15h, AH = 87h)

0Ah Return without EOI Return address (CS:IP)

=======================================================
====================

Other reset codes are reserved by the BIOS, but they should not be used. On
return to the destination environment, the stack segment (SS) and stack
pointer (SP) registers point to an area in BIOS RAM for all reset codes
except for code 09h, return from block move. This function uses the reset
vector at 0040:0067 as a save area for SS:SP, a stack frame pointer. The
stack frame stores the processor's registers in the following order,
beginning at offset +00h (top of stack): DS, ES, DI, SI, BP, SP, BX, DX,
CX, AX, IP, CS, and flags.

7.2 BIOS INTERRUPTS SUMMARY

This section summarizes the interrupt calls used for each system function
and the memory locations used by the BIOS for those functions.

Interrupts are classified into four categories according to their sources:

software (SW), central processing unit (CPU), hardware (HW), and pointer
(PTR).

o SW interrupts are issued by application programs or system software.

Interrupt service routines are provided by the BIOS ROM or other
user-supplied system software. These interrupts form a standardized
interface among applications programs, system software, and BIOS
firmware.

o CPU interrupts are initiated by the processor or coprocessor as the

result of a processing exception. For example, executing an invalid
opcode causes an INT 06h.

o HW interrupts are initiated by the processor's device signals on the

nonmaskable Interrupt (NMI) or Interrupt (INTR) pins. Signals on the INTR
pin are arbitrated by interrupt controllers. An interrupt-acknowledge
cycle by the processor requests the active interrupt controller to place
the actual interrupt number on the bus.

o PTR interrupts are not used to transfer program control; they are 4-byte
pointers in low-address memory named for the interrupt vector location
they occupy. These pointers typically point to video, diskette drive, or
hard drive controller parameters, character dot-pattern tables, or tables
of other pointers.

In the interrupt listings, each interrupt will include a header indicating

the hex number of the interrupt, its category, its function(s), and [in
brackets] the RAM location in which its vector is stored, as in the
following example:

INT 13h -- SW -- hard Drive I/O [0000:004C]

Subsets of an interrupt are introduced by a header indicating the hex

number, the input values, and the interrupt function, as in the following
example:

INT 13h, AH = 02h -- Read Sectors

Table 7-2 summarizes all the BIOS interrupts in ascending order by hex
number. Where two interrupts share a single address, both are listed at the
appropriate hex number. All the interrupts listed occupy 4 bytes.

Table 7-2. BIOS Interrupt Summary (all take 4 bytes)

=======================================================
====================
INT Type Function RAM Location
Address
---------------------------------------------------------------------------
00h CPU Divide by zero 0000:0000

01h CPU Debug exception (Single step) 0000:0004

02h HW Nonmaskable Interrupt (NMI) 0000:0008

03h CPU Software breakpoint 0000:000C

04h CPU Arithmetic overflow 0000:0010

05h SW Print screen 0000:0014

CPU Bound exceeded

06h CPU Invalid opcode 0000:0018

07h CPU Coprocessor not present 0000:001C

08h CPU Double fault error 0000:0020

HW IRQ0, Tick counter

09h CPU Coprocessor/486 FPU segment overrun 0000:0024

HW IRQ1, Keyboard

0Ah CPU Invalid TSS 0000:0028

HW Simulated IRQ2

0Bh CPU Segment not present 0000:002C

HW IRQ3, Comm, secondary

0Ch CPU Stack segment overflow 0000:0030

HW IRQ4, Comm, primary

0Dh CPU General protection 0000:0034

HW IRQ5 Reserved

---------------------------------------------------------------------------
INT Type Function RAM Location
Address
---------------------------------------------------------------------------
0Eh HW IRQ6, Diskette drive 0000:0038
0Fh HW IRQ7, Printer 0000:003C

10h SW Video I/O 0000:0040

11h SW Configuration 0000:0044

12h SW Base memory size 0000:0048

13h SW Diskette/hard drive I/O 0000:004C

14h SW Communications I/O 0000:0050

15h SW Miscellaneous BIOS Functions 0000:0054

16h SW Keyboard I/O, cache memory 0000:0058

17h SW Printer I/O 0000:005C

18h SW Boot Fail 0000:0060

19h SW Bootstrap 0000:0064

1Ah SW Tick counter/RTC 0000:0068

1Bh SW Control break service 0000:006C

1Ch SW Tick counter service 0000:0070

1Dh PTR Video controller board parameters 0000:0074

1Eh PTR Diskette drive parameter table 0000:0078

1Fh PTR External graphics character set 0000:007C

(Graphics Dot Table Vector)

41h PTR hard drive 1 parameters 0000:0104

43h PTR External graphics character set 0000:010C

(Graphics Dot Table Vector)

46h PTR hard drive 2 parameters 0000:0118

4Ah SW RTC alarm service 0000:0128

70h HW IRQ8, Real-time clock (RTC) 0000:01C0

71h HW IRQ9, (redirected to IRQ2) 0000:01C4

72h HW IRQ10, Reserved 0000:01C8

73h HW IRQ11, Reserved 0000:01CC

74h HW IRQ12, Pointing device 0000:01D0

75h HW IRQ13, Coprocessor error 0000:01D4

76h HW IRQ14, hard drive 0000:01D8

77h HW IRQ15, Power 0000:01DC

=======================================================
====================

In addition to using a section of RAM for the vector table, the system BIOS
uses another section for status information and buffers for data transfers.
Table 7-3 lists these locations.

Table 7-3. RAM Locations Used by the BIOS for Status Information and
Buffers
=======================================================
====================
Address Bytes Function
---------------------------------------------------------------------------
0040:0000 2 Base address of Comm Port 0 (COM1)

0040:0002 2 Base address of Comm Port 1 (COM2)

0040:0004 2 Base address of Comm Port 2

0040:0006 2 Base address of Comm Port 3

0040:0008 2 Base address of Printer Port 0 (LPT1)

0040:000A 2 Base address of Printer Port 1 (LPT2)

0040:000C 2 Base address of Printer Port 2 (LPT3)

0040:000E 2 Pointer to extended BIOS data area

0040:0010 2 Equipment status

0040:0012 1 Used by power-on diagnostics

0040:0013 2 Base memory size in Kbytes

0040:0015 1 Previous scan code

0040:0016 1 Keyclick loudness

0040:0017 2 Keyboard bit status

0040:0019 1 Accumulator for ALT key input

0040:001A 2 Keyboard buffer pointer -- head

0040:001C 2 Keyboard buffer pointer -- tail

---------------------------------------------------------------------------
Address Bytes Function
---------------------------------------------------------------------------
0040:001E 32 Keyboard type-ahead buffer -- 16 entries

0040:003E 1 Diskette drive status

0040:003F 1 Motor status

0040:0040 1 Motor off time-out counter

0040:0041 1 Diskette last operation status

0040:0042 7 Diskette drive controller status

0040:0049 1 Video mode

0040:004A 2 Number of columns on screen

0040:004C 2 Length of screen memory

0040:004E 2 Starting address for screen memory

0040:0050 16 Cursor save area for each page (8 entries)

0040:0060 2 Cursor mode (start and end scanlines)

0040:0062 1 Current page

0040:0063 2 Base address to active video adapter board

0040:0065 1 Current mode

0040:0066 1 Current color

0040:0067 4 Reset vector

0040:006B 1 Interrupt occurred flag

0040:006C 4 Timer ticks since midnight

0040:0070 1 Timer-rolled-over flag

---------------------------------------------------------------------------
Address Bytes Function
---------------------------------------------------------------------------
0040:0071 1 Break bit

0040:0072 2 Reset word

0040:0074 1 hard drive status of last operation

0040:0075 1 Number of hard drives

0040:0076 1 hard drive control byte

0040:0077 1 Reserved

0040:0078 1 Time-out for printer port 0 (LPT1)

0040:0079 1 Time-out for printer port 1 (LPT2)

0040:007A 1 Time-out for printer port 2 (LPT3)

0040:007B 1 Reserved

0040:007C 1 Time-out for Comm port 0 (COM1)

0040:007D 1 Time-out for Comm port 1 (COM2)

0040:007E 1 Time-out for Comm port 2

0040:007F 1 Time-out for Comm port 3

0040:0080 2 Keyboard buffer begin

0040:0082 2 Keyboard buffer end

0040:0084 7 Reserved

0040:008B 1 Last data rate selected

0040:008C 1 hard drive status

0040:008D 1 hard drive error

0040:008F 1 Diskette drive indicator

0040:0090 1 Drive 1(A) media state

0040:0091 1 Drive 2(B) media state

0040:0092 1 Drive 1(A) operation start state

0040:0093 1 Drive 2(B) operation start state

0040:0094 1 Drive 1(A) current track

0040:0095 1 Drive 2(B) current track

0040:0096 1 Enhanced keyboard shift status

0040:0097 1 Keyboard LED flags

0040:0098 4 Pointer to caller's wait flag

0040:009C 4 Wait count (32-bit)

0040:00A0 1 Wait active flag

0040:00A1 95 Reserved

0040:0100 1 Print screen status

=======================================================
====================

Functional Interrupt Summary

This chapter has categorized the BIOS interrupts according to the

subsystems they affect. The following describes functional aspects for the
interrupts involving the following areas:

o System
o Real-Time Clock (RTC)
o Processor
o Math Coprocessor
o Cache Memory
o Diskette Drive
o Hard Drive
o Keyboard
o Parallel Port
o Serial Port
o Video
o Miscellaneous

7.3 SYSTEM INTERRUPTS

The system interrupts provide a variety of services that apply to the

system in general. Table 7-4 lists the system interrupts.

Table 7-4. System Interrupts

11h SW 0000:0044 4 Equipment Configuration

12h SW 0000:0048 4 Base Memory Size

BIOS Extension; function

15h SW 0000:0054 4 determined by AH;

(refer to Table 7-5)

18h SW 0000:0060 4 Boot Fail

19h SW 0000:0064 4 Bootstrap

=======================================================
====================

INT 15h is used for a variety of BIOS functions, as summarized in

Table 7-5.

Table 7-5. INT 15h BIOS Extension Functions

=======================================================
====================
AH Function
---------------------------------------------------------------------------
4Fh Keyboard Scan Code Intercept

80h Device Open

81h Device Close

82h Program Terminate

83h Dispatch function determined by AL:

00h = Set event wait
01h = Cancel event wait

84h Joystick

85h SYS REQ Key Routine

86h Unconditional Wait

87h Move Block

88h Extended Memory Determination

89h Enter Protected mode

90h Device Wait

91h Device Post

C0h Return System Environment

C1h Return Extended BIOS Data Area Segment

C2h Auxiliary Input Interface function determined by AL:

00h = Enable/disable pointing device
01h = Reset pointing device
02h = Set pointing device
03h = Set pointing device resolution
04h = Read pointing device type
05h = Initialize pointing device interface
06h = Pointing device extended commands
07h = Device driver for call initialization
=======================================================
====================
Table 7-6 lists additional memory locations affected by system functions.

Table 7-6. Other Memory Locations Affected By System Functions

=======================================================
====================
Address Bytes Contents
---------------------------------------------------------------------------
0040:0010 2 Equipment Status

0040:0013 2 Base Memory Size in Kbytes

0040:0067 4 Reset Vector

0040:0072 2 Reset Word

0040:0098 4 Pointer to Caller's Wait Flag

0040:009C 4 Wait Count (32-bit)

0040:00A0 1 Wait Active Flag

=======================================================
====================

Extended System Interrupts

The following paragraphs describe BIOS extensions that provide additional

system functions.

INT 15h, AH = C1h -- Return Extended BIOS Data Area Segment

INT 15h, AH = C1h returns the segment of the extended BIOS data area in ES.

INPUT: AH = C1h

OUTPUT: ES = Extended BIOS data area segment

CF = 1, If error (no extended BIOS data area present)

INT 15h, AH = C2h, AL = 00h -- Enable/Disable Pointing Device

INT 15h, AH = C2h, AL = 00h will enable, or disable a pointing device.

INPUT: AH = C2h
AL = 00h
BH = 00h, Disable auxiliary pointing device
= 01h, Enable auxiliary pointing device

OUTPUT: AH = 00h, No error

= 01h, Invalid function call
= 02h, Invalid input
= 03h, Interface error
= 04h, Resend command error
= 05h, No far call installed error
BH = Device ID (00h for mouse)
CF = 0, Successful completion
= 1, Unsuccessful operation
INT 15h, AH = C2h, AL = 01h -- Reset Pointing Device

INT 15h, AH = C2h, AL = 05h is similar to INT 15h, AH = C2h, AL = 01h

except this call also sets the data packet size according to the value in
BH. After the call, the sample rate, scaling, and resolution are all set to
their default values (100 reports/sec, 4 counts/mm, and 1:1 scaling,
respectively), and the pointing device is disabled.

INPUT: AH = C2h
AL = 00h
BH = Data Packet Size
00h, Reserved
01h, 1 byte
02h, 2 bytes
03h, 3 bytes
04h, 4 bytes
05h, 5 bytes
06h, 6 bytes
07h, 7 bytes
08h, 8 bytes

OUTPUT: AH = 00h, No error

= 01h, Invalid function call
= 02h, Invalid input
= 03h, Interface error
= 04h, Resend command error
= 05h, No far call installed error
CF = 0, Successful completion
= 1, Unsuccessful operation

INT 15h, AH = C2h, AL = 06h -- Pointing Device Extended Commands

INT 15h, AH = C2h, AL = 06h returns the three-byte status from the pointing
device or will set the scaling factor, depending on the value passed in BH.

INPUT: AH = C2h
AL = 06h
BH = 00h, Return status
= 01h, Set 1:1 scaling factor
= 02h, Set 2:1 scaling factor

OUTPUT: AH = 00h, No error

= 01h, Invalid function call
= 02h, Invalid input
= 03h, Interface error
= 04h, Resend command error
= 05h, No far call installed error
BH = 00h, If the operation is successful
BL = Status byte 1 (refer to bit map )

BL BIT FUNCTION
----------------
7 Reserved

6 Mode
0 = Stream mode
1 = Remote mode

5 1 = Pointing device enabled

4 Scaling Factor
0 = 1:1 scaling
1 = 2:1 scaling

3 Reserved

2 1 = Left button pressed

1 Reserved

0 1 = Right button pressed

INT 15h, AH = C2h, AL = 07h -- Device Driver Far Call Initialization

INT 15h, AH = C2h, AL = 07h stores the location of the pointing device
driver in the extended BIOS data area.

INPUT: AH = C2h
AL = 07h
BX = Offset of device driver address
ES = Code segment of device driver address
OUTPUT: AH = 00h, No error
= 01h, Invalid function call
= 02h, Invalid input
= 03h, Interface error
= 04h, Resend command error
= 05h, No far call installed error
CF = 0, Successful completion
= 1, Unsuccessful operation

7.4 TICK COUNTER/REAL-TIME CLOCK INTERRUPTS

The Tick Counter/Real-Time Clock (RTC) Interrupts provide all time-keeping

functions in the BIOS. The Tick Counter/RTC Interrupts are actually two
separate services attached to two different hardware elements:

o The tick counter is one counter of the 8254 Programmable Interval Timer
(or equivalent), and is provided chiefly for compatibility with software
written for 8088/8086-based products.

o The real-time clock is part of the RTC and Configuration Memory device
which is powered by its own battery. The RTC provides battery backed-up
time-of-day information and alarm service in a binary-coded decimal (BCD)
format. The RTC maintains its function no matter what the power condition
of the computer itself.

During power-on, the BIOS uses the RTC to initialize the tick counter.
Thereafter, the tick counter maintains a 32-bit counter in the BIOS RAM
area that contains the number of ticks since midnight. Ticks arrive from
hardware interrupt IRQ0 and are vectored through INT 08h at a rate of
approximately 18.2 ticks per second (18.2 Hz). When the counter reaches
1573040 (24 hours), it rolls over to zero and sets a rolled-over flag in
BIOS RAM.

In addition to time keeping, the tick counter also decrements a countdown

timer variable in BIOS RAM, and when zero is reached, turns off the
diskette drive motors. A periodic interrupt to application software is
provided by the BIOS calling INT 1Ch every tick. The vector in INT 1Ch is
initialized at power-on to point to a dummy interrupt return.

RTC BIOS support provides an interface to the real-time clock device. This
device maintains the time of day and an alarm function in hardware. When
enabled, it also interrupts the processor on IRQ8 vectored through INT 70h
at a rate of 1024 interrupts per second (one every 976 us).

Three software services are driven by the RTC hardware interrupt to IRQ8:

o Event Wait (INT 15h, AH = 83h)

o Unconditional Wait (INT 15h, AH = 86h)
o RTC Alarm Service (INT 4Ah)

Table 7-7 lists the system interrupts used by the Tick Counter/Real-Time
Clock interrupts.

Table 7-7. Tick Counter and RTC Interrupts

1Ah SW 0000:0068 4 Tick Counter/RTC function

determined by AH:
00h = Read tick counter
01h = Reset tick counter
02h = Read RTC time
03h = Set RTC time
04h = Read RTC date
05h = Set RTC date
06h = Set RTC alarm
07h = Reset RTC alarm

1Ch SW 0000:0070 4 Tick Counter Service

4Ah SW 0000:0128 4 RTC Alarm Service

70h HW 0000:01C0 4 IRQ8, RTC Interrupt

=======================================================
====================

Table 7-8 lists additional memory locations used by the tick counter and
RTC functions.

Table 7-8. Other Memory Locations Affected By Tick Counter and RTC
Functions
=======================================================
====================
Address Bytes Contents
---------------------------------------------------------------------------
0040:0040 1 Motor off counter

0040:006B 1 Interrupt-Occurred Flag

0040:006C 4 Timer Ticks Since Midnight

0040:0070 1 Timer-Rolled-Over Flag

0040:0098 1 Pointer to Caller's Wait Flag

0040:009C 4 Wait Count (32-bit)

0040:00A0 1 Wait Active Flag

=======================================================
====================

7.5 PROCESSOR INTERRUPTS

The system processor has a number of predefined interrupts for notifying

system or application software of execution exceptions. These CPU-type
interrupts are categorized as processing, debug, and arithmetic interrupts.
Refer to the Intel Programmer's Reference manual for a detailed explanation
of the CPU-type interrupts. In addition, two software interrupts are used
to control the CPU speed. These are described in detail following the table
below.

Table 7-9 lists the memory locations used by the processor interrupts.

Table 7-9. Processor Interrupts

01h CPU 0000:0004 4 Debug Exception

03h CPU 0000:000C 4 SW Breakpoint

04h CPU 0000:0010 4 Arithmetic Overflow

05h CPU 0000:0014 4 Bound Exceeded

06h CPU 0000:0018 4 Invalid Opcode

08h CPU 0000:0020 4 Double-Fault Error

0Ah CPU 0000:0028 4 Invalid TSS

0Bh CPU 0000:002C 4 Segment Not Present

0Ch CPU 0000:0030 4 Stack Segment Overflow

0Dh CPU 0000:0034 4 General Protection

0Eh CPU 0000:0038 4 Page Fault

11h * CPU 0000:0044 4 Alignment Check

16h SW 0000:0058 4 CPU speed function determined

by AH:
F0h = Set CPU speed
F1h = Read current CPU speed
---------------------------------------------------------------------------
* 486-specific interrupt
=======================================================
====================

INT 16h, AH = F0h -- Set CPU Speed

INT 16h, AH = F0h changes the value of the Interval Timer 2, Counter 2 to
specify the simulated CPU speed.

INPUT: AH = F0h
AL = 00h Sets speed to the equivalent of a 286-based system at 6 MHz
(COMMON)
= 01h Sets speed to the equivalent of a 286-based system at 8 MHz
(FAST)
= 02h Sets speed to maximum speed (HIGH)
= 03h Toggles speed between AUTO and HIGH
= 08h Sets speed to switch between the 286 8-MHz equivalent
speed and maximum speed during diskette operations (AUTO)
= 09h Sets system speed to a value between 1 and 50 decimal. A
value of 1 is the slowest speed possible, and 50
approximates the maximum speed.

CX = Speed Value (1..50)

NOTE: CX contains the speed value only when AL contains 09h.

OUTPUT: None

INT 16h, AH = F1h -- Read Current CPU Speed

INT 16h, AH = F1h returns the current system speed.

INPUT: AH = F1h

OUTPUT: AL = 00h, if system speed is set to 6-MHz 286 speed equivalent

(COMMON)

= 01h, if system speed is set to 8-MHz 286 speed equivalent

(FAST)
= 02h, if system speed is set to maximum speed (HIGH)
= 08h Sets speed to switch between the 286 8-MHz equivalent
speed and maximum speed during diskette operations (AUTO)
= 09h, if system speed has been set by BIOS function
CX = Speed Value (01h..32h)

NOTE: CX contains the speed value only when AL contains 09h.

7.6 COPROCESSOR INTERRUPTS

The BIOS provides two areas of basic support for a math coprocessor, which
is also known as a floating point unit (FPU):

o BIOS checks for the presence of a coprocessor during the system

initialization process. When a coprocessor is present (which will always
be the case with the 486), the BIOS sets the appropriate bits in the
machine status word in the processor.

o The BIOS transfers INT 75h (IRQ13, FPU error) to INT 02h for
compatibility with software written for 8088/8086-based products. After
initialization, coprocessor interrupts INT 07h (FPU not present) and
INT 09h (FPU segment overrun) are normally supported by system software
operating systems and are not handled by the BIOS.

Table 7-10. Coprocessor Interrupts

09h CPU 0000:0024 4 Coprocessor/486-FPU segment overrun

10h CPU 0000:0040 4 Floating point error

75h HW 0000:01D4 4 IRQ13, Coprocessor/486-FPU error

=======================================================
====================

7.7 CACHE MEMORY INTERRUPTS

The cache memory subsystem uses software interrupt INT 16h, AH = F4h. It is
used to return the status of the cache controller and to enable or disable
the cache controller. The functions of the cache memory interrupts are
listed in Table 7-11 and described in the following paragraphs.

Table 7-11. Cache Memory Interrupts

=======================================================
====================
Interrupt Type Memory Bytes Function
Location
---------------------------------------------------------------------------
16h, AH = F4h SW 0000:0058 4 Determined by AL:
00h = Return cache controller
status
01h = Enable cache controller
02h = Disable cache controller
=======================================================
====================

INT 16h, AH = F4h, AL = 00h -- Return Cache Controller Status

INT 16h, AH = F4h, AL = 00h returns the cache controller status.

INPUT: AH = F4h
AL = 00h

OUTPUT: AH = E2h
AL = Cache controller status
00h = Cache controller not present
01h = Cache controller enabled
02h = Cache controller disabled

Other registers are preserved.

INT 16h, AH = F4h, AL = 01h -- Enable Cache Controller

INT 16h, AH = F4h, AL = 01h enables the cache controller.

INPUT: AH = F4h
AL = 01h
OUTPUT: AH = E2h
AL = 01h, Successful completion
= 00h, No Cache controller available

Other registers are preserved.

INT 16h, AH = F4h, AL = 02h -- Disable Cache Controller

INT 16h, AH = F4h, AL = 02h disables the cache controller.

INPUT: AH = F4h
AL = 02h

OUTPUT: AH = E2h
AL = 02h, Successful completion
= 00h, No Cache controller available

7.8 DISKETTE DRIVE INTERRUPTS

All communication between the user and the diskette drive is via a single
ROM call (INT 13h). When the system contains a hard drive, INT 13h
interrupts are vectored to INT 40h. The user can perform any of several
functions.

During a write operation, a head settle time of 15/20 ms (as appropriate)

is used if a diskette drive parameter table specifies a head settle time of
less than 15 ms for a 1.2-megabyte diskette drive, or less than 20 ms for a
360-Kbyte double-density diskette drive. In addition, a motor settle time
of one second is used for a write or format operation, and 625 ms for a
read or verify operation. To read or write to 48-TPI media, the software
must step the 96-TPI drive head twice between each 48-TPI track.

Table 7-12 lists the BIOS diskette drive interrupts and memory locations
used.

Table 7-12. Diskette Drive Interrupts

13h SW 0000:004C 4 Diskette I/O function determined

by AH:
00h = Reset diskette subsystem
01h = Read status of last
operation
02h = Read sectors
03h = Write sectors
04h = Verify sectors
05h = Format track
08h = Get drive parameters
15h = Get drive type
16h = Read diskette change line
status
17h = Set drive type for format
18h = Set media type for format

1Eh PTR 0000:0078 4 Diskette Drive Parameter Table

Vector

40h SW
0000:0100 4 Diskette I/O (refer to INT13h
above)
=======================================================
====================

Table 7-13 shows the memory locations that are affected by the diskette
drive functions.

Table 7-13. Memory Locations Used By Diskette Drive Functions

=======================================================
====================
Location Bytes Function
---------------------------------------------------------------------------
0040:003E 1 Drive recalibration status:
<7> = Interrupt occurred flag
<6> = Reserved
<3..0> = Drives 4..1 (respectively) need
recalibration if bit <3..0> = 1

0040:003F 1 Motor time-out

0040:0040 1 Time-out counter for drive motor turns off after

2 seconds of tick counts (37 ticks)

0040:0041 1 Diskette status

0040:0042 7 Drive controller status

0040:008B 1 Data rate status

<7,6> = Last data rate sent to Controller
00 = 500 Kb/s 10= 250 Kb/s
01 = 300 Kb/s 11= Reserved
<5,4> = Reserved
<3,2> = Data rate with which the operation started
<1> = Reserved
<0> = 1 = hard drive controller board installed
0 = Not installed

0040:008F 1 Drive information:

A B
-----------
Bits
<3> <7> = Reserved
<2> <6> = Multidata rate capability determined
<1> <5> = Multidata format capability
<0> <4> = 80-track capability

0040:0090 1 <7, 6> -- Data-transfer rate

00 = 500 Kb/s
01 = 300 Kb/s
10 = 250 Kb/s
11 = Reserved
<5> -- Double step required
<4> -- Diskette drive/diskette established
<3> -- Reserved
<2..0> -- Diskette drive/diskette
000 = 48-TPI/360-KB (NOTE 1)
001 = 48-TPI/1.2-MB (NOTE 1)
010 = 96-TPI/1.2-MB (NOTE 1)
011 = 48-TPI/360-KB (NOTE 2)
100 = 48-TPI/1.2-MB (NOTE 2)
101 = 96-TPI/1.2-MB (NOTE 2)
110 = Reserved
111 = Reserved

0040:0091 1 Drive 2 (B) Media state byte

0040:0092 1 Drive 1 (A) operation start state (the operation

start state is the starting media state when a
diskette drive operation begins)

0040:0093 1 Drive 2 (B) operation start state

0040:0094 1 Drive 1 (A) current track bytes

0040:0095 1 Drive 2 (B) current track bytes

---------------------------------------------------------------------------
NOTES: 1. Media has not been established
2. Media has been established
=======================================================
====================

The diskette drive BIOS uses INT 0Eh (IRQ6) and DMA channel 2 of the
system. There are six possible combinations of diskette drives and
diskettes that can be used together. The BIOS must be able to determine the
combination being used in order to supply the appropriate parameters. The
parameters for each combination are stored in a table referred to as the
Diskette Drive Parameter Table (DDPT) that is called with INT 1Eh.

The DDPT for each combination is shown in Table 7-14.

Table 7-14. Diskette Drive Parameter Table

=======================================================
====================
Description Diskette Drive/Diskette Combination *
of DDPT Byte 1 2 3 4 5 6
---------------------------------------------------------------------------
Step Rate (SRT)/
Head Unload Time (HUT) DFh DFh DFh DFh DFh AFh

Head Load Time/DMA 02h 02h 02h 02h 02h 02h

Motor OFF Time 25h 25h 25h 25h 25h 25h

Sector length 02h 02h 02h 02h 02h 02h

Sectors/track 09h 09h 0Fh 09h 09h 12h

Gap length, Read/Write 2Ah 2Ah 1Bh 2Ah 2Ah 1Bh

Data transfer length FFh FFh FFh FFh FFh FFh

Gap length, format 50h 50h 54h 50h 50h 6Ch

Fill character, format F6h F6h F6h F6h F6h F6h

Head-settle time 0Fh 0Fh 0Fh 0Fh 0Fh 0Fh

Motor-settle time 08h 08h 08h 08h 08h 08h

Maximum track value 27h 27h 4Fh 4Fh 4Fh 4Fh

Data transfer rate 80h 40h 00h 80h 80h 80h

---------------------------------------------------------------------------
* The six diskette drive/diskette combinations are:
1 = 360-Kbyte diskette in 360-Kbyte drive (5 1/4-inch)
2 = 360-Kbyte diskette in 1.2-megabyte drive (5 1/4-inch)
3 = 1.2-megabyte diskette in 1.2-megabyte drive (5 1/4-inch)
4 = 720-Kbyte diskette in 720-Kbyte drive (3 1/2-inch)
5 = 720-Kbyte diskette in 1.44-megabyte drive (3 1/2-inch)
6 = 1.44-megabyte diskette in 1.44-megabyte drive (3 1/2-inch)
=======================================================
====================

Common Operations

Determining Media

On entry to the diskette drive routines that access the diskette

(read/write/verify), a check is made of the media state for the target
diskette drive. If the media state is established, processing continues
normally. If the media state is not established, a process internal to the
BIOS determines the type of media installed.

Table 7-15 lists a description of the diskette drive settings.

Table 7-15. Diskette Drive Settings

==============================================
Drive Setting Description
----------------------------------------------
0 No drive present

1 5 1/4-in 360-KB

2 5 1/4-in 1.2-MB

3 3 1/2-in 720-KB
4 3 1/2-in 1.44-MB
==============================================

Diskette Change

DISKETTE CHANGE- is a status signal from the 720-Kbyte, 1.2-megabyte and

1.44-megabyte diskette drives that indicates when the drive latch has been
opened. This signal is not used on 360-Kbyte diskette drives.

Whenever an access of the diskette drive for read, write, verify, or format
is requested by a BIOS interrupt, the BIOS checks the DISKETTE CHANGE-
signal status. If the DISKETTE CHANGE- signal is active (door has been
opened), the BIOS checks to see whether the door is still open.

The media state for the drive (0040:0090 or 0040:0091) is set to

unestablished, 48-TPI media in a 1.2-megabyte diskette drive (61h),
whenever the drive door is opened. The system then determines the type of
media installed with the next diskette access.

Formatting a Diskette

To format a high-density (1.2- or 1.44-megabyte) diskette properly, a set

media type for format (INT 13h, AH = 18h) should be made first. This
function sets the media state for the diskette drive to "established." If
this function call is not made, the format of the diskette is based upon
the current media state (established or not) of the diskette drive.

To format a 3 1/2-inch diskette for 1.44 megabytes of capacity in a

1.44-megabyte diskette drive requires a high-density 3 1/2-inch diskette.
To format for 720 Kbytes of capacity requires a low-density 3 1/2-inch
diskette. High-density 3 1/2-inch diskettes cannot be formatted for
720 Kbytes of capacity in a 1.44-megabyte diskette drive.

7.9 HARD DRIVE INTERRUPTS

The hard drive BIOS supports two hard drives, Drive 1 (80h) and Drive 2
(81h). Use INT 13h, AH = 08h to determine their individual capacities, or
use the parameter tables pointed to by INT 41h and INT 46h. Do not use the
hard drive types stored in the CMOS configuration memory to determine the
capacities.

The hard drive Wait and POST functions are supported via INT 15h. The hard
drive Wait function call is AH = 90h with AL = 00h. The function call for
Power-On Self-Test (POST) is AH = 91h with AL = 00h. Wait is performed to
wait for a hard drive interrupt.

If an error occurs on a hard drive operation, reset (INT 13h, AH = 00h or

0Dh) the hard drive system before retrying the operation. The hard drive
controller will perform internal retries before returning an error.

To format a hard drive with more than eight heads, recalibrate (INT 13h,
AH = 11h) head 0, then format heads 0 through 7. Next, recalibrate head 8
and format heads 8 through 15.
When using the Read or Write functions, the most significant bit (MSB) of
the drive control byte (at offset +08h) of the hard drive parameter table
(at INT 41h or INT 46h) can be set to "1" to disable the hard drive
controller internal retry function.

These interrupts use the standard ISA interface. For greater performance
use the 32-bit bus master interface, if available.

Table 7-16 lists the BIOS hard drive interrupts.

Table 7-16. Hard Drive Interrupts

=======================================================
====================
Interrupt Type Location Bytes Function
---------------------------------------------------------------------------
INT 13h SW 0000:004C 4 Hard drive I/O function determined
by AH:
00h = Reset hard drive subsystem
01h = Read status of last operation
02h = Read sectors
03h = Write sectors
04h = Verify sectors
05h = Format track
08h = Get drive parameters
09h = Initialize hard drive
parameters
0Ah = Read long
0Bh = Write long
0Ch = Seek cylinder
0Dh = Alternate disk reset
10h = Test Drive Ready-
11h = Recalibrate drive
14h = Controller diagnostic
15h = Get drive type

INT 41h PTR 0000:0104 4 Hard drive 1 Parameter Table

INT 46h PTR 0000:0118 4 Hard drive 2 Parameter Table

INT 76h HW 0000:01D8 4 IRQ14, hard drive interrupt

=======================================================
====================

Table 7-17 shows the memory locations used by hard drive functions.

Table 7-17. Other Memory Locations Affected By Hard Drive Functions

0040:0075 1 Number of hard drives

0040:0076 1 Hard drive control byte

0040:0077 1 <0> = 0, no translation for drive 1
= 1, translate drive 1
<1> = 0, no translation for drive 2
= 1, translate drive 2

0040:008C 1 Additional hard drive status

0040:008D 1 Hard drive error status

0040:008E 1 Hard drive interrupt flag

=======================================================
====================

7.10 KEYBOARD INTERRUPTS

The BIOS generally controls all interactions with the keyboard. However,
the interrupts and memory locations used for the keyboard make it very easy
to change the keyboard functions.

Table 7-18 lists the BIOS keyboard interrupts and memory locations used.

Table 7-18. BIOS Keyboard Interrupts

INT 16h SW 0000:0058 4 Keyboard I/O determined by AH:

00h = Get key
01h = Check for key status
02h = Read shift status
03h = Set repeat key rate and delay
05h = Place scan code/character in
type-ahead buffer
10h = Get enhanced key from
type-ahead buffer
11h = Check for enhanced key in
buffer
12h = Get enhanced key status
F2h = Determine attached keyboard

INT 1Bh SW 0000:0066 4 CTRL-BREAK service

INT 74h HW 0000:01D0 4 IRQ12, Auxiliary input

=======================================================
====================

Table 7-19 shows other memory locations used by the keyboard functions.

Table 7-19. Other Memory Locations Affected By Keyboard Functions

0040:0016 1 Key click loudness

0040:0017 2 Keyboard bit status

0040:0019 1 Accumulator for ALT key input

0040:001A 2 Keyboard buffer pointer head

0040:001C 2 Keyboard buffer pointer tail

0040:001E 32 Keyboard type-ahead buffer (16 entries)

0040:0071 1 Break Bit (bit <7>)

0040:0080 2 Keyboard buffer begin

0040:0082 2 Keyboard buffer end

0040:0096 1 Enhanced shift status

0040:0097 1 Keyboard LED flags

=======================================================
====================

SYS REQ Key

The SYS REQ key is a special key. It is not encoded, nor is anything placed
in the keyboard queue when it is pressed.

Pressing the SYS REQ key invokes INT 15h with AH = 85h, AL = 00h (SYS REQ
Make code). Releasing the SYS REQ key invokes INT 15h with AH = 85h,
AL = 01h (SYS REQ Break code).

The SYS REQ key does not interact with any other key and is not repeating.
An application must trap INT 15h in order to make use of the SYS REQ key.

RAM location 0040:0018 stores the SYS REQ key status. If bit <2> in the
status byte at 0040:0018 is set, the SYS REQ key is currently held down.
The bit is cleared when the SYS REQ key is released.

Keyboard Indicators

The BIOS normally controls the state of the keyboard LED indicators. It
automatically changes the state of the LED indicators to reflect the
current status of CAPS LOCK, NUM LOCK, and SCROLL LOCK keyboard functions.

All communications to the keyboard occur through ports 60h and 64h of the
8042 keyboard controller.

To change the keyboard LED state, use the IN and OUT instructions of the
processor to:
1. Read port 64h to determine the input/output status of the 8042, making
sure the input buffer is empty.

2. Write the disable keyboard (ADh) command to port 64h to disable the
keyboard interface. Read the scan code from port 60h.

3. Wait until the 8042 input buffer is empty. Output EDh to the keyboard
assembly using port 60h. Wait until an ACK (the first of two ACK bytes)
is received from port 60h.

4. Write the LED data byte when the 8042 input buffer is empty. Wait until
the second ACK byte is received.

5. When the 8042 buffer is empty, write the enable keyboard (AEh) command
to the 8042 to reenable the keyboard interface.

Enhanced Keyboard

A RAM variable at 0040:0096 is used in conjunction with the Enhanced

Keyboard for state information.

The format of RAM location 0040:0096 (byte) is defined below:

BIT FUNCTION
----------------
7 Read ID command in progress

6 Last character received was ID byte

5 If Enhanced Keyboard installed, force NUM LOCK

4 Enhanced Keyboard installed

3 Right ALT key down

2 Right CTRL key down

1 Last code was E0h

0 Last code was E1h

A RAM variable at 0040:0097 reflects the state of the keyboard LED

indicators. The LED indicators are controlled by the keyboard BIOS through
the use of commands issued to the 8042 Keyboard Controller.

The information in 0040:0097 is compared with the mode bits in 0040:0017 to

determine whether the LED indicators are up-to-date.

The format of RAM location 0040:0097 (byte) is defined below:

BIT FUNCTION
----------------
7 Reserved

6 1 = 8042 command in progress

5 Reserved

4 1 = ACK reply received

3 Reserved

2 1 = CAPS LOCK LED ON

1 1 = NUM LOCK LED ON

0 1 = SCROLL LOCK LED ON

The status of the LED indicators are checked:

o Each time a keyboard hardware interrupt occurs.

o When the Get Key (INT 16h, AH = 00h or AH = 10h) function is invoked.
o When the Check For Key Available (INT 16h, AH = 01h or AH = 11h) function
is invoked.

The ability to adjust the volume of the key click is a BIOS feature unique
to COMPAQ personal computers. Two RAM locations are associated with the key
click as shown in Table 7-20.

Table 7-20. Memory Locations Used For Key Click Function

0040:0016 1 Key click loudness (0..127)

=======================================================
====================

Miscellaneous BIOS Keyboard Information

Immediately after placing a key in the keyboard queue, INT 15h is called
with AH = 91h, AL = 02h. (See "Device Wait" and "Device Post" under INT 15h
functions.)

Keys and key combinations that do not cause something to be placed in the
keyboard queue (such as simply pressing and releasing the Caps Lock key) do
not cause a Device Post. Pause (Ctrl + Num Lock) does not perform either a
Device Wait or a Device Post.

Decimal keyboard codes can be entered by holding down the Alt key, entering
the number on the numeric keypad, then releasing the Alt key. This feature
works regardless of the state of the Num Lock key. For example, to enter
the PI character, hold down the Alt key, type 227 on the numeric keypad,
then release the Alt key.

The Get Key function (INT 16h, AH = 00h or AH = 10h) executes a Device Wait
(INT 15h, AH = 90h, AL = 02h), if a key code is not currently available in
the keyboard queue.
The following key combinations do not place scan codes in the keyboard
type-ahead buffer:

o Increase key click loudness (Ctrl + Alt + Numeric Keypad "+")

o Decrease key click loudness (Ctrl + Alt + Numeric Keypad "-")

To indicate receive time-out errors, parity errors, and overrun errors, the
8042 places a scan code of FFh in its output buffer. The system beeps once
when it receives the FFh from the keyboard.

To indicate transmit time-out errors, the 8042 places a scan code of FEh in
its output buffer.

Interrupts remain enabled and execution is suspended if Ctrl + Num Lock is

input.

INT 16h, AH =F2h -- SW -- Determine Attached Keyboard

INT 16h, AH = F2h determines whether a 9- or an 11-bit keyboard is in use:

INPUT: AH = F2h

OUTPUT: AL = 00h

COMPAQ BIOS only supports an 11-bit keyboard. Therefore, AL will always be

00h.

INT 1Bh -- SW -- CTRL - BREAK Service

INT 1Bh is called from the ROM when the Ctrl + Break keys are pressed. INT
1Bh is provided to allow operating systems and user programs a way to exit
a program.

ROM ENTRY: Points to a dummy interrupt return

ROM ACTION: Control returns to the calling program

USE: The vector for this interrupt is normally used by the operating
system. It can be changed to point to a user-supplied routine.

7.11 SERIAL PORT INTERRUPTS

The interrupts for the serial port interface provide simplified

asynchronous communications for peripherals. Functions are provided for
initializing a serial port, transmitting characters, receiving characters,
and reading status.

Asynchronous communications are not hardware interrupt driven. There are

two device oriented interrupts, IRQ4 (INT 0Ch) for the primary port, and
IRQ3 (INT 0Bh) for the secondary port.

During power-on, the BIOS searches for asynchronous communication ports at

two standard port locations, 3F8h and 2F8h. When a serial port is found,
its base address is placed in the BIOS memory, beginning at 0040:0000.
Therefore, when programming a serial port, use the address extracted from
the table in BIOS memory rather than a hard coded address.

The BIOS provides a serial port time-out function, whose length is

programmable by the user. A 4-byte table in BIOS memory beginning at
0040:007C is reserved for setting the time-out values for each serial port.
These time-out values are initialized to 1 during power-on and can be set
to a maximum of 255. Each increment represents approximately 900 ms.

Table 7-21 lists the serial port interrupts.

Table 7-21. Serial Port Interrupts

INT 0Ch HW 0000:0030 4 IRQ4, Comm, Primary

INT 14h SW
0000:0050 4 Serial port I/O function
determined by AH:
00h = Initialize port
01h = Transmit character
02h = Receive character
03h = Sense communications
status
04h = Extended initialize
05h = Extended port control
=======================================================
====================

Table 7-22 lists additional memory locations affected by serial port

interrupts.

Table 7-22. Other Memory Locations Used By Serial Port Functions

0040:0002 2 Base Address of Comm Port 1

0040:0004 2 Base Address of Comm Port 2

0040:0006 2 Base Address of Comm Port 3

0040:007C 1 Time-out for Comm Port 0

0040:007D 1 Time-out for Comm Port 1

0040:007E 1 Time-out for Comm Port 2

0040:007F 1 Time-out for Comm Port 3

=======================================================
====================

7.12 PARALLEL PORT INTERRUPTS

The BIOS provides a simplified interface to the parallel printer port. BIOS
functions include initializing a printer, printing characters, and checking
the printer status.

Although printer operation is not interrupt driven, a Device Wait interrupt

(INT 15h, AH = 90h, AL = FEh) is supported internally. It is executed if
the printer is not ready when the Print Character function is called.
Printer interrupt IRQ7 (INT 0Fh) is available for systems software.

During power-on, the BIOS searches for parallel printer interfaces at three
standard port locations: 3BCh, 378h, and 278h. When an interface is found,
the BIOS places the printer port base address in BIOS memory, beginning at
0040:0008. Therefore, when programming a printer port, use the address
extracted from the table in BIOS memory, rather than a hard-coded address.

In addition to application software being able to directly call the Print

Screen function (INT 05h), it is invoked by the keyboard BIOS when the
Print Scrn key is pressed. INT 05h repeatedly invokes INT 17h for each
character. Characters in every position on the screen are sent to the
printer without suppressing trailing blanks. A flag in BIOS ROM at location
0040:0100 contains the print screen status.

BIOS provides a time-out function whose length is programmable by the user.

A 4-byte table in BIOS memory beginning at 0040:0078 is reserved for
setting the time-out values for each parallel printer port. At power-on
these time-out values are initialized to 20 and may be set from 1 to 255.
Each increment is approximately one second.

Table 7-23 lists the BIOS printer interrupts. For a detailed explanation of
each interrupt, refer to the Intel Programmer's Reference Manuals.

Table 7-23. Parallel Port Interrupts

INT 0Fh HW 0000:003C 4 IRQ7, Printer Interrupt

INT 17h SW
0000:005C 4 Printer I/O function
determined by AH:
00h = Print character
01h = Initialize printer
02h = Get printer status
=======================================================
====================

Table 7-24 lists additional memory locations used by parallel port

functions.

Table 7-24. Other Memory Locations Used By Parallel Port Functions

0040:000A 2 Base Address of Printer Port 1

0040:000C 2 Base Address of Printer Port 2

0040:0078 1 Time-out for Printer Port 0

0040:0079 1 Time-out for Printer Port 1

0040:007A 1 Time-out for Printer Port 2

0040:0100 1 Print Screen Status

=======================================================
====================

7.13 VIDEO INTERRUPTS

The BIOS video interrupts provide access to the video display controller
using software interrupt INT 10h. Many functions are provided, including:

o Initializing the display in one of several formats

o Reading from or writing to the screen memory
o Scrolling a window on the display

Two other interrupts, INT 1Dh and INT 1Fh contain pointers to tables. These
interrupts are provided for altering the CRT controller parameters and
providing an extension to the graphics mode dot table.

The BIOS can support either a color graphics display (using memory
addresses beginning at 0B8000h) or a monochrome text controller (using
memory addresses beginning at 0B0000h). Video graphics displays that use
memory beginning at A0000h are supported as well. Remember that only one
graphics controller can be supported at a time.

If the integrated VGA controller is disabled, the ROM-based video BIOS

functions are disabled as well. This is done to avoid conflict between the
system ROM and a video controller board containing its own BIOS ROM.

During power-on, the BIOS checks the configuration memory, and sets
bits <5, 4> byte (0040:0010), to determine the type of display used
initially. The initial display mode can be either:

o Color display in 40 x 25 or 80 x 25 character text mode (video BIOS

mode 3)

o monochrome display in 80 x 25 character text mode (video BIOS mode 7).

Use the Set Video mode command (INT 10h, AH = 00h) to initialize the video
display controller. Refer to the video chapter of this guide for a listing
of the video BIOS modes available.

Whether to use BIOS or to directly access the screen memory depends on how
much software portability or application performance is needed.

Table 7-25 lists the video interrupts.

Table 7-25. INT 10h Video BIOS Calls

=======================================================
====================
INT 10h Function
---------------------------------------------------------------------------
AH=00h Set Video mode

AH=01h Set Cursor Type

AH=02h Set Cursor Position

AH=03h Read Cursor Position

AH=04h Read Lightpen Position

AH=05h Select Active Display Page

AH=06h Scroll Active Page Up

AH=07h Scroll Active Page Down

AH=08h Read Attribute/Character at Current Cursor Position

AH=09h Write Attribute/Character at Current Cursor Position

AH=0Ah Write Character Only at Current Cursor Position

AH=0Bh Set Color Palette

AH=0Ch Write Pixel

AH=0Dh Read Pixel

AH=0Eh Write TTY Character

AH=0Fh Read Current Video State

---------------------------------------------------------------------------
INT 10h Function
---------------------------------------------------------------------------
AH=10h Set Palette registers
AL=00h Set Individual Attribute Controller register
AL=01h Set Overscan Color
AL=02h Set All Attribute Controller registers
AL=03h Program Blink/Intensity
AL=07h Read Individual Attribute Controller register
AL=08h Read Overscan
AL=09h Read All Attribute Controller registers and Overscan
AL=10h Set Individual RAM DAC Color register
AL=12h Set Block of RAM DAC Color registers
AL=13h
BL=00h Select Color Paging mode
BL=01h Select Color Page
AL=15h Read Individual RAM DAC Color register
AL=17h Read Block of RAM DAC Color registers
AL=1Ah Read Current Color Page
AL=1Bh Sum RAM DAC Color Values to Gray Shades

AH=11h Load Character Generator

AL=00h Load User Defined Character Set
AL=01h Load ROM 8 x 14 / 9 x 14 Character Set
AL=02h Load ROM 8 x 8 Double-Dot Character Set
AL=03h Set Block Specifier
AL=04h Load ROM 8 x 16 / 9 x 16 Character Set
AL=10h Load User Defined Text Character Set
AL=11h Load ROM 8 x 14 / 9 x 14 Character Set
AL=12h Load ROM 8 x 8 Double-Dot Character Set
AL=14h Load ROM 8 x 16 Character Set
AL=20h Load User 8 x 8 Character Set
AL=21h Load User Character Set
AL=22h Load ROM 8 x 14-Dot Character Set
AL=23h Load ROM 8 x 8 Double-Dot Character Set
AL=24h Load ROM 8 x 16 Character Set
AL=30h Return Font Information

AH=12h Alternate Select

AL=00h
BL=10h Return EGA Information
BL=20h Select Alternate Print Screen Routine
BL=30h Select Scan lines for Text mode
BL=31h Enable/Disable Default Palette Loading
BL=32h Enable/Disable Video
BL=33h Enable/Disable Summing to Gray Shades
BL=34h Enable/Disable Cursor Emulation
BL=36h Screen ON/OFF

AH=13h Write String

AH=1Ah Read/Write Video Type Code

AH=1Bh Get Functionality/Current Video Environment

AH=1Ch Save/Restore Video Environment

AH=BFh Video BIOS Extensions *

AL=03h Get Video Environment
AL=05h Enable/Disable Display
AL=0Ch Set DAC to 6-bit mode
AL=0Dh Set DAC to 8-bit mode
AL=0Eh Get DAC to 6-/8-bit mode
AL=0Fh Set high address map register value
AL=10h Get high address map register value
---------------------------------------------------------------------------
* The video BIOS extensions are unique to COMPAQ BIOS and are discussed
in more detail later in this section.
=======================================================
====================

Interrupts remain enabled and execution may be suspended if the Ctrl + Num
Lock keys are pressed. Functions and their related parameters are
individually described below.

When the system encounters the SW video interrupt, it jumps to the address
pointed to by the vector for that interrupt. Table 7-26 lists the memory
locations where these vectors reside.

Table 7-26. Memory Locations Used by Video Interrupts

0000:0074 4 INT 1Dh vector

0000:007C 4 INT 1Fh vector

0000:0108 4 INT 42h vector

0000:010C 4 INT 43h vector

0040:0049 1 Current video mode

0040:004A 2 Number of columns on screen

0040:004C 2 Length of screen memory (in bytes)

0040:004E 2 Start of screen memory

0040:0050 16 Cursor save area for each page (8 entries)

0040:0060 2 Cursor mode (start and end scanline)

0040:0062 1 Current page being displayed

0040:0063 2 Base address of active video interface board

0040:0065 1 Current mode

0040:0066 1 Current color

0040:0084 1 Number of screen rows - 1

0040:0085 2 Character height

=======================================================
====================
INT 1Dh and INT 1Fh contain pointers to tables. They are provided for
altering the CRT controller parameters and providing an extension to a
user-supplied graphics mode dot table.

INT 1Fh -- PTR -- Dot Table

INT 1Fh points to a user-supplied dot table used to generate and read 8 x
8-dot graphics characters in modes 4, 5, and 6. This table is needed only
for those characters within the range of 80h..FFh.

ROM ACTION: INT 1Fh is used exclusively by the INT 05h Print Screen and INT
10h Video I/O routines, and then only in the graphics modes for the
upper-128 character set.

INPUT: None

OUTPUT: None

USE: The user must set INT 1Fh to point to a supplied table as shown.

ILLUSTRATION OF 8 x 8 Dot Table for the Upper 128 Character Set

INT 42h -- SW -- Compatible Video I/O

This interrupt gives direct access to previously available INT 10h

functions. It saves the contents of the existing INT 10h vector during
system power-on initialization and vectors function calls outside of the
range 00h..13h and BFh to the system BIOS ROM. The alternate video adapter
(if installed) is initialized into a video mode using this vector.

INT 43h -- PTR -- Graphics Dot Table Vector

INT 43h points to the dot table used to generate and read dot graphics
characters. In 8 x 14- and 8 x 16-dot modes, it points to the table for all
characters. In the 8 x 8-dot modes, it points to the table for the
first-128 characters (00h..7Fh).

Alphanumeric characters are usually left-justified in the cell. Visible

dots are usually composed of two adjacent pixels ON. The top two (0, 1) and
bottom three (11, 12, 13) scanlines are usually blank, except for
ascenders, descenders, and special graphics characters.

Video BIOS Extensions

INT 10h, AH = BFh adds extensions to the video BIOS needed for sensing or
altering the hardware environment. These interrupts are unique to COMPAQ
personal computers.

INPUT: AH = BFh
AL = 00h = Turn External Display on
01h = Turn Internal Display on
03h = Get Video Environment
05h = Enable/Disable Video Display
0Ch = Set DAC to 6-bit mode
0Dh = Set DAC to 8-bit mode
0Eh = Get DAC 6-/8-bit mode
0Fh = Set High Address Map Register Value
10h = Get High Address Map Register Value
11h = Get Extended Environment
12h = Set Active Display

INT 10h, AH = BFh, AL = 00h -- Turn External Display On

INT 10h, AH = BFh, AL = 00h is used in portable systems to turn on an

external display. This function is unique to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 00h, Turn External Display On

OUTPUT: None

INT 10h, AH = BFh, AL = 01h -- Turn Internal Display On

INT 10h, AH = BFh, AL = 00h is used in portable systems to turn on the

internal display. This function is unique to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 01h, Turn Internal Display On

OUTPUT: None

INT 10h, AH = BFh, AL = 03h -- Get Video Environment

INT 10h, AH = BFh, AL = 03h returns the control mode, the active monitor
selection, and the internal and external display types of the currently
active video controller. This function is unique to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 03h = Get Video Environment
BX = 0000h (see NOTE)

NOTE: BX should be set to 0000h for full compatibility with previous video
BIOS.

OUTPUT: BH = Active Monitor

00h = External active
01h = Internal active
03h = Internal and external active
04h = Neither internal or external active
BL = Control mode
05h = EGA
06h = VGA
08h = LCD VGA
09h = Plasma VGA
0Ah = TFT VGA
CH = Reserved
CL = (see bit map below)

BIT FUNCTION
----------------
7 8-bit DAC mode available

6 640 x 480 with 256-color mode available

5 132-column support available

4 Bit BLT engine available

3..0 Reserved

DH = Internal monitor type

00h = None
04h = Plasma CGA
07h = 8-level monochrome LCD VGA
08h = 16-level monochrome plasma VGA
09h = 4-level monochrome LCD CGA
0Ah = 16-level monochrome LCD VGA
0Bh = Color TFT panel
DL = External monitor type
00h = None
01h = Dual-mode monochrome
02h = RGBI 16-color
03h = Enhanced 64-color
04h = Plasma
05h = VGC monochrome
06h = VGC color display in character format

INT 10h, AH = BFh, AL = 05h -- Enable/Disable Display

INT 10h, AH = BFh, AL = 05h turns the video display ON or OFF. This
function is unique to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 05h
BL = ON/OFF
00h = Video OFF
01h = Video ON

INT 10h, AH = BFh, AL = 0Ch -- Set DAC to 6-Bit Mode

INT 10h, AH = BFh, AL = 0Ch provides the ability to switch the Video DAC to
6-bit mode. This function is unique to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 0Ch Set DAC to 6-bit mode

INT 10h, AH = BFh, AL = 0Dh -- Set DAC to 8-Bit Mode

INT 10h, AH = BFh, AL = 0Dh provides the ability to switch the Video DAC to
8-bit mode. This function is unique to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 0Dh Set DAC to 8-bit mode
INT 10h, AH = BFh, AL = 0Eh -- Get DAC 6-/8-Bit Mode

INT 10h, AH = BFh, AL = 0Eh returns the current mode of the Video DAC. This
function is unique to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 0Dh Get DAC 6-/8-bit mode

OUTPUT: AL = 6-/8-bit mode

00h DAC currently in 6-bit mode
01h DAC currently in 8-bit mode

INT 10h, AH = BFh, AL = 0Fh -- Set High Address Map Register Value

INT 10h, AH = BFh, AL = 0Fh provides the ability to enable and locate the
high address map buffer. This function is unique to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 0Fh Set High Address Map Register Value
BX = 0000h Disable high address map
000nh Set high address map location to megabyte n.
FFFFh ROM configures high address map.

OUTPUT: AL = High address map (see bit map below)

AL BIT FUNCTION
----------------
7..4 Reserved

3..0 Current value of high address map. If <3..0> = 0 on return,

high address map is disabled.

INT 10h, AH = BFh, AL = 10h -- Get High Address Map Register Value

INT 10h, AH = BFh, AL = 10h provides the ability to determine the current
location of the high address map buffer. This function is unique to the
COMPAQ BIOS.

INPUT: AH = BFh
AL = 10h Get High Address Map Register

OUTPUT: BX = The current value of the high address map register

INT 10h, AH = BFh, AL = 11h -- Get Extended Environment

INT 10h, AH = BFh, AL = 11h describes feature supported by video

controller. This function is unique to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 11h Get Extended Environment

OUTPUT: AL = BFh call is supported

ES:DI = A pointer to COMPAQ string in the VGA ROM.
ES:SI = A pointer to a dword table in the ROM to indicate advanced
functionality of the COMPAQ VGC.
BL BIT FUNCTION
----------------
31..1 Reserved

0 Concurrent display supported

INT 10h, AH = BFh, AL = 12h -- New Active Monitor Control

INT 10h, AH = BFh, AL = 11h is used in portable systems for turning on the
internal display, external display, or both. This call is also used to
toggle the external or internal display on or off. This function is unique
to the COMPAQ BIOS.

INPUT: AH = BFh
AL = 11h Set Active Monitor
BH = Reserved
BL = See bit map below. Bit <7> is the command mode bit.
If bit <7> = 0, a 1 in bits <1,0> makes the corresponding display
active.
If bit <7> = 1, a 1 in bits <1,0> toggles the active state of the
corresponding display. Refer to bit map on below.

BL BIT FUNCTION
----------------
7 On/Off or toggle
1 = Toggles active state of corresponding display
0 = Makes corresponding display active

6..2 Reserved

1 Internal Monitor Control

0 External Monitor Control

7.14 MISCELLANEOUS INTERRUPTS

This section contains information on the unused hardware interrupts and

miscellaneous information locations in the BIOS ROM. Seven unused
interrupts, listed in Table 7-27, are available for use by optional
interface boards and user-written applications or system software.

Table 7-27. Miscellaneous Interrupts

=========================================
Interrupt Type Function
-----------------------------------------
INT 0Ah HW Simulated IRQ2

INT 0Dh HW IRQ5

INT 71h HW IRQ9

INT 72h HW IRQ10

INT 73h HW IRQ11

INT 74h HW IRQ12

INT 77h HW IRQ15

=========================================

When the system encounters one of these interrupts, it jumps to the address
pointed to by the vector for that interrupt. Table 7-28 lists the memory
locations where these vectors reside.

Table 7-28. Memory Locations Used by Miscellaneous Interrupts

0000:0034 4 INT 0Dh Vector

0000:01C4 4 INT 71h Vector

0000:01C8 4 INT 72h Vector

0000:01CC 4 INT 73h Vector

0000:01D0 4 INT 74h Vector

0000:01DC 4 INT 77h Vector

=======================================================
====================

INT 71h -- HW -- IRQ9

INT 71h receives the interrupts from IRQ9. On 8088/8086-based products, bus
pin B04 of the expansion bus is connected to IRQ2, which is vectored
through INT 0Ah. On COMPAQ 286-, 386-, and 486-based products, bus pin B04
is connected to IRQ9, which is vectored through INT 71h. For system
compatibility with 8088/8086-based products, interrupts vectored through
INT 71h are redirected by the BIOS to INT 0Ah.

ROM ENTRY: Points to IRQ9 handler

ROM ACTION: The IRQ9 handler points to the IRQ2 vector, which points to an
interrupt return.

USE: It is the responsibility of the operating system or the application

program to set up this vector for useful action.

INT 72h -- HW -- IRQ10

INT 72h receives the interrupts from IRQ10.

INT 72h is not processed by the BIOS other than to return control to the
calling program.
ROM ENTRY: Points to an interrupt return

ROM ACTION: None

USE: It is the responsibility of the operating system or the application

program to set up this vector for useful action.

INT 73h -- HW -- IRQ11

INT 73h receives the interrupts from IRQ11.

INT 73h is not processed by the BIOS, other than to return control to the
calling program.

ROM ENTRY: Points to an interrupt return

ROM ACTION: None

USE: It is the responsibility of the operating system or the application

program to set up this vector for useful action.

INT 74h -- HW -- IRQ12, Pointing Device Interrupt

INT 74h occurs each time a byte is received from the pointing device. INT
74h normally handles the pointing device interrupts from IRQ12.

ROM ENTRY: Points to ROM input device interrupt handler

ROM ACTION: The interrupt routine reads the pointing device from the 8042
registers, takes special action if required, notifies the 8042 that the
port has been read, clears the 8259A interrupt controller, and loads the
device data into the extended BIOS data area until the specific packet size
is built. The packet size is determined by INT 15h, AH = C2h. Once the
packet size is reached, INT 74h calls the device driver.

INPUT: Pointing device

OUTPUT: The packet is passed to a software-resident device driver via the

SP stack.

USE: The vector for this interrupt can be changed to select a user-supplied
input device handler.

INT 77h -- HW -- IRQ15

INT 77h receives the interrupts from IRQ15.

INT 77h is not processed by the BIOS other than to return control to the
calling program.

ROM ENTRY: Points to an interrupt return

ROM ACTION: None

USE: It is the responsibility of the operating system or the application
program to set up this vector for useful action.

7.15 SPECIAL ROM LOCATIONS

The ROM memory locations described in the following sections are supplied
in COMPAQ products.

Table 7-29 lists the special BIOS ROM locations.

Table 7-29. Special BIOS ROM Locations

=================================================
Address Bytes Function
-------------------------------------------------
F000:FFE4 1 Product family code

F000:FFE8 2 BIOS type code

F000:FFEA 6 Machine ID

F000:FFFE 1 Machine type code

=================================================

Product Family Code

The BIOS ROM contains a 1-byte product family code at address F000:FFE4.
The contents of this memory location is listed in Table 7-30.

BIOS Type Code

The BIOS type is identified by a 2-byte ASCII code at address F000:FFE8.

The contents of this memory location are listed in Table 7-30.

Machine ID

COMPAQ personal computers can be identified by a 6-byte string at address

F000:FFEA that contains "COMPAQ" in uppercase ASCII code.

Machine Type Code

The machine type is identified by a 1-byte code at address F000:FFFE. The

machine type code is provided for compatibility with 286-based software.
The contents of this memory location is listed in Table 7-30.

Table 7-30. Special BIOS ROM Codes

=======================================================
====================
COMPAQ Product Family Code BIOS Type Code Machine Type Code
---------------------------------------------------------------------------
LTE N N/A FE

LTE 286 N 01 FC

SLT 286 B 01 FC
DESKPRO 286 G 01 FC

DESKPRO 286e F 01 FC

DESKPRO 286N D 01 FC

LTE 386s/20 B1 03 FC

SLT 386s/20 B 03 FC

DESKPRO 386N D 03 FC

DESKPRO 386s/20N D 03 FC

DESKPRO 386s F 03 FC

DESKPRO 386s * R 03 FC

DESKPRO 386s/20 R 03 FC

PORTABLE 386 P 03 FC

DESKPRO 386 G 03 FC

DESKPRO 386/20 G 03 FC

DESKPRO 386/20e H 03 FC

DESKPRO 386/20e * H1 03 FC

DESKPRO 386/25 G 03 FC
---------------------------------------------------------------------------
* Models which support 256 colors
---------------------------------------------------------------------------
COMPAQ Product Family Code BIOS Type Code Machine Type Code
---------------------------------------------------------------------------
DESKPRO 386/25e H 03 FC

DESKPRO 386/25e * H1 03 FC

DESKPRO 386/33 L 03 FC

DESKPRO 386/33L E1 03 FC

DESKPRO 486/25 E 03 FC

DESKPRO 486/33L E1 03 FC

PORTABLE 486/33c E3 03 FC

DESKPRO 486/50L E1 03 FC

DESKPRO/M Family E2 03 FC

SYSTEMPRO E 03 FC
SYSTEMPRO/LT Family E2 03 FC
---------------------------------------------------------------------------
* Models which support 256 colors
=======================================================
====================

7.16 PROGRAMMING EXAMPLES FOR PROTECTED MODE OPERATING SYSTEMS

Compaq provides advanced hardware features that provide improved

performance and compatibility when using operating systems as published by
Compaq. A Protected mode operating system (such as MS OS/2 or UNIX) may
need additional codes to exploit fully these features that are specific to
COMPAQ products. Compaq has developed several code routines to help
software developers take full advantage of those COMPAQ personal computer
features available when using the 386 microprocessor in the 386 Protected
mode.

The following contains examples of routines that:

o Determine CPU type (8086, 8088, 286 or 386).

o Determine whether or not the machine is a COMPAQ product.
o Put the CPU in HIGHest speed mode.
o Unprotect the highest 128 Kbytes of RAM.
o Relocate VGA font vectors for COMPAQ VGA.
o Size and allocate system RAM in a UNIX environment.

NOTE: In order to ensure compatibility with future 386-based COMPAQ

products, access (reading or writing) to these registers must be done
via the ROM-BIOS software interrupt Block Move (INT 15h, AH = 87h).
The Block Move function in the BIOS recognizes access to the special
80C00000h location and takes the appropriate action to access the
system registers to perform the equivalent function in future COMPAQ
products.

;*************************************************************************
; The following routines are written in 386 assembly language. The code is
; assembled and linked using 386 Protected mode addressing. However, the
; code modules themselves are executed while the 386 CPU is in the 8086
; Real mode.
;
; These subroutines are provided to help programmers detect a COMPAQ
; personal computer. Under no circumstances should these routines be used
; to exclude the use of applications software on computer products
; manufactured by others.
;
;*************************************************************************

LISTING

; PUBLIC _cpuvendor
; _cpuvendor DW 0 ; Global reference for vendor, 1 == COMPAQ
; PUBLIC _cputype
_cputype DW 0 ; Global reference for CPU, 86H, 286H, 386H
; COMPAQ EQU 1
; OTHER EQU 0
;*************************************************************************

; MAIN ROUTINE
;
; Real mode initialization for operating system start-up. Must be called
; after boot but before transition to Protected mode. This routine
; performs specific initialization for COMPAQ personal computers only
;
; Other systems may also require specific initialization procedures.
; Determine CPU type and update _cputype flag.
; Determine whether or not vendor is Compaq and update _cpuvendor
; Use those flags to perform COMPAQ and/or 386-specific initialization
; If (cpuvendor == Compaq){
; hi_speed( );
; if(cpu_type == 0x386) {
; egavec( ) ; /* re-init VGA font vectors */
; romoff( ) ; /* unprotect highest 128K 32-bit RAM */
; }
;}
;*************************************************************************
;
; PUBLIC oemreal
oemreal proc near
call cpu_type ; Determine CPU, ax=type
mov _cputype],ax ; Update flag
call cpu_vendor ; Determine machine vendor
mov [ _cpuvendor],ax ; Update flag
cmp ax,COMPAQ ; Q: Is machine a COMPAQ?
jnz not386 ; N: Don't attempt high speed or
; high RAM
call hi_speed ; Y: Set speed to highest
; possible
mov ax,[ _cputype] ; Get flag
cmp ax,0386h ; Q: Is machine a 386?
jnz not386 ; N: Don't attempt to enable
; high RAM
call egavec ; Y: Fix ROM pointers for VGA
call romoff ; Y: Unprotect highest memory
; not 386:
; Other OS-specific Real mode
; init code goes here
ret ; Real mode init completed
oemreal endp

;*************************************************************************
; ROUTINE TO DETERMINE WHETHER OR NOT MACHINE IS A COMPAQ PRODUCT
; cpu_vendor
; Determines whether or not Compaq is CPU vendor by looking at ROM
; Must be executed in Real mode
; Pointer to COMPAQ string must be derived at runtime. Although the
; assembler uses Protected mode addressing, this code runs in Real mode.
; AX = CPU vendor value
; 0 = Indeterminate (not manufactured by Compaq)
; 1 = COMPAQ
;*************************************************************************

PUBLIC cpu_vendor
cmpqstr DB `COMPAQ'
pBegin cpu_vendor near

push ds ; Protect used registers

push es ;
push si ;
push di ;
push cx ;
cld ; Auto increment
mov ax,0F000h ; Point to ROM string
mov es,ax ;
mov di,0FFEAh ;
mov ax,cs ; Point to compare string
mov ds,ax
mov si, offset OEMSUP_TEXT:cmpqstr
mov cx,6 ; Length of COMPAQ string
repe cmpsb ; String compare

mov ax, OTHER ; Return status if not manufactured

; by Compaq
jnz nomatch ; String did not match
mov ax,COMPAQ ; It is a COMPAQ
nomatch:
pop cx ;
pop di ; Restore used registers
pop si ;
pop es ;
pop ds ;
ret ; *** RETURN ***
pEnd cpu_vendor

;*************************************************************************
; ROUTINE TO DISABLE ROM REPLACEMENT
;
; Disable ROM Replacement and make high memory 0FE0000h to FFFFFFh
; writable. Use the ROM BIOS Move Block INT 15h (see GDT format below)
; to write 0FFh to the memory-mapped control register at 80C00000h.
; This is the simplest way to get a 32-bit GDT in 286 Protected mode.
; (Protected mode 286 GDTs are only 24-bit.)
;
; The following routine enables and disables gate A20. Therefore, the
; operating system must enable gate A20 after completion of the routine.
;
; Must be called from Real mode
;
; Move Block Calling Arguments
; INPUT: None
; OUTPUT: AH = 0, If operation successful
; 1, If parity error occurred
; 2, If exception error occurred
; 3, If gate A20 failed
; move_block - Move (copy) a block of data to or from anywhere in physical
; or from extended memory (beyond 1 MB) because Real mode
; addressing can address only the first MB of RAM.
; ENTRY: CX = number of words to move (max 8000h)
; ES:SI = Pointer to descriptor table (refer to following diagram)
; EXIT: AH = 00, If OK
; 01, If parity error
; 02, If exception error
; 03, If gate address bit A<20> fails
; Flags are unaffected
; USED: AX
; NOTE: The Block Move is performed with interrupts disabled.
;
;
; GDT
; ES:SI --> +---------------------------------+
; | Dummy descriptor | GDT (0)
; +---------------------------------+
; | GDT descriptor | GDT (1)
; +---------------------------------+
; | Source segment descriptor | GDT (2)
; +---------------------------------+
; | Target segment descriptor | GDT (3)
; +---------------------------------+
; | BIOS CS segment descriptor | GDT (4)
; +---------------------------------+
; | BIOS SS segment descriptor | GDT (5)
; +---------------------------------+
; Entries 0, 1, 4, and 5 should all be initialized by the caller to
; 8 bytes of 0 each. Entries 2 and 3 must be valid descriptors
; containing the appropriate base addresses, limit values, and access
; rights.
;
;*************************************************************************

; Definition of a descriptor
;
desc struc
limit dw 0 ; Offset of last byte in segment
base_low dw 0 ; Low 16 bits of 24-bit address
base_high db 0 ; High 8 bits of 24-bit address
rights db 0 ; Access rights byte
ext_lim db 0 ; 386 limit <19..16>
ext_base db 0 ; 386 extended base
desc ends
;
; Define fixed GDT selector values for Block Move routine
;
ROMDUM_SEL equ 0 * size desc ; GDT(0) = Dummy selector

ROMGDT_SEL equ 1 * size desc ; GDT(1) = GDT segment selector

ROMSRC_SEL equ 2 * size desc ; GDT(2) = Source segment selector
ROMDST_SEL equ 3 * size desc ; GDT(3) = Target selector
ROMBIOS_CS_SEL equ 4 * size desc ; GDT(4) = BIOS CS segment selector
ROMBIOS_SS_SEL equ 5 * size desc ; GDT(5) = BIOS SS segment selector
;
; Various access rights
;
DS_ACCESS equ 92h ; Expand up, level 0, writable
CS_ACCESS equ 9Ah ;
MAXSEG equ 0FFFFh ; 64K segment

rploff label WORD

DW 0FFFFh ; Disable ROM replace command

PUBLIC romoff ; Disable ROM replacement

romoff proc near

push bp ; Protect used registers
push es ;
push si ;
push di ;
push cx ;
cld ; Auto increment

; Allocate a GDT on the stack;

sub sp,size desc * 6 ; 6 entries in Block Move GDT
mov bp,sp ; Get base to it
mov ax,ss ; Get segment address of GDT
mov es,ax ; ... into ES
mov si,bp ; ES:SI = GDT
mov di,bp ; ES:DI = GDT
xor ax,ax ; AX = 0
mov cx,size desc * 6 ; Number of bytes to clear
rep stosb ; Clear 6 GDT entries

; Fill in the source descriptor in the GDT

;
lea di,[bp+ROMSRC_SEL] ; DI = address of SRC descriptor
mov ax,cs ; Compute base low of IOCTRL
shl ax,4 ;
add ax,offset rploff
mov es:[di].base_low,ax ; Copy from address of local 0FFh
mov ax,offset rploff ;
shr ax,4 ;
mov cx,cs ; Get segment address
add ax,cx ;
shr ax,12 ;
mov es:[di].base_high,al ; Set base high in descriptor
mov es:[di].limit,MAXSEG ; Set limit
mov es:[di].rights,CS_ACCESS ; Set access rights

; Fill in the destination descriptor in the GDT

;
lea di,[bp+ROMDST_SEL] ; DI = address of DST
; descriptor
mov es:[di].base_low,0 ;
mov es:[di].base_high,0C0h ; Copy to 80C00000h
mov es:[di].ext_base,80h ;
mov es:[di].limit,MAXSEG ;
mov es:[di].rights,DS_ACCESS ;
;
; Set the I/O control byte by performing a Block Move of '
; 1 word.

mov ah,87h ; Block Move opcode

mov cx,1 ; Move 1 word
int 15h ; Write to the I/O control
; byte
add sp,size desc * 6 ; De-allocate GDT on stack
pop cx ;
pop di ; Restore used registers
pop si ;
pop es ;
pop bp ;
ret ; *** RETURN ***
endp romoff

;*************************************************************************
;
; ROUTINE TO RELOCATE VGA FONT VECTORS
;
; egavec
;
; This code relocates VGA vectors at 0440:00xxh for the COMPAQ VGA.
; Normally, the ROM BIOS copies the VGA ROM to 32-bit RAM at FE0000h,
; then (using special hardware) remaps this RAM to 0E0000h. Thus, we have
; fast 32-bit RAM in an unused ROM location to speed up VGA ROM calls.
;
; Because that high memory is allocated for use as operating system RAM,
; the VGA font vector must point back to the real VGA ROM at 0C0000h.
;
;*************************************************************************

; PUBLIC egavec
VGA_VIDEO_IO equ 10h
VGA_DOT_VEC equ 1Fh
VGA_FONT_VEC equ 43h
VGA_SEGMENT equ 0C000h

pBegin egavec near

mov ax,0 ; Page 0 in es
mov es,ax
mov si,(VGA_VIDEO_IO*4)+2 ; INT 10h, segment
mov es:[si],VGA_SEGMENT ; Point it back to ROM
mov si,(VGA_DOT_VEC*4)+2 ; INT 1Fh, segment
mov es:[si],VGA_SEGMENT ; Point it back to ROM
mov si,(VGA_FONT_VEC*4)+2 ; INT 43h, segment
mov es:[si],VGA_SEGMENT ; Point it back to ROM
ret ; *** RETURN ***
pEnd egavec

;*************************************************************************
; PROTECTED MODE INITIALIZATION CODE SAMPLE
;
; The following memory-sizing code finds the highest RAM at 0XFA0000 to
; 0XFFFFFF on COMPAQ DESKPRO
; Personal Computers. This module is written in C and should be called
; during Protected mode initialization.
;
; The "ROMOFF" routine in Real mode initialization has removed write
; protection on the highest 128 Kbytes of 32-bit RAM (used as a ROM copy)
; before this code executes.
;
; Highest memory grows from the top (0XFFFFFF) downward; low memory
; grows from the bottom upward with a break occurring from 640 Kbytes to
; 1 megabyte. COMPAQ Personal Computers always have a minimum of 384 Kbytes
; of memory at 0XFA0000 to 0XFFFFFF. Other configuration ranges are:
;
; 16 MB 0XFFFFFF
; 128 KB (ROM/RAM) 0XFE0000
; 256 KB 0XFA0000
; 128 KB 0XF80000
; 256 KB 0XF40000
; 14 MB .... 0XE00000
; 1 MB 13 MB RAM 0X100000
; 640 KB ROM/VIDEO 0X0A0000
; 640 KB 0X000000
;
; NOTE: This code assumes that a bug in freerange ( ) causes it to look
; 512 bytes beyond the highest address given. The bug manifests
; itself only at the 16-Megabyte address boundary, hence the search
; recognizes 0XFFFDFF, rather than 0XFFFFFF, as the highest address.
; If freerange ( ) is altered, then the calling arguments presented
; here should also be altered.
;
; Debug printf's should be removed for production code.
; atoml macro divides by 512
;
; freerange (start, length); Verifies existence of RAM and adds
; it to the system freelist
;*************************************************************************

extern int cputype; /* Declared and initialized in Real mode */

short
freemem(fpage)
short fpage;
{
register short npages, pages;
extern char extmem;
/* first 640K */
pages = freerange(fpage, *atoml(0x09FFFF));
npages = pages;
printf("Kbytes at 000000 = %d \ n", pages / 2);
/* Normal 286 extended RAM from 1 MB to 16 MB */
/* On a 286, search all the way to 16 MB. On a 386, */
/* search only to the beginning of COMPAQ high memory */
/* at 0xf40000 */
pages = freerange (*atoml(0x100000),
*atoml ((cputype==0x386)? 0xF3FFFF : 0xFFFDFF));
npages += pages;
printf("Kbytes at 0x100000 = %d \ n", pages / 2);
/* Look for highest RAM. Because memory is */
/* contiguous from the first address to 0xFFFFFF, quit the search */
/* after the first block is found. This action minimizes available */
/* memory fragments. */

pages = 0;
while (cputype == 0x386)
{
pages = freerange(*atoml(0xF40000), *atoml(0xFFFDFF));
if (pages)
{
printf("Kbytes at 0xF40000 = %d \ n", pages / 2);
break;
}
pages = freerange(*atoml(0xF80000), *atoml(0xFFFDFF));
if (pages)
{
printf("Kbytes at 0xF80000 = %d \ n", pages / 2);
break;
}
pages = freerange(*atoml(0xFA0000), *atoml(0xFFFDFF));
if (pages)
{
printf("Kbytes at 0xFA0000 = %d \ n", pages / 2);
break;
}
pages = freerange(*atoml(0xFE0000), *atoml(0xFFFDFF));
if (pages)
{
printf("Kbytes at 0xFE0000 = %d \ n", pages / 2);
}
break;
}
npages += pages;
printf("Total Kbytes = %d \ n", npages / 2);
return (npages);
}

8.1 INTRODUCTION

The video subsystem on COMPAQ LTE Lite products consists of a VGA

controller (VGC) and a liquid crystal display (LCD). The COMPAQ LTE Lite
Family uses the following types of LCD screens:

o Edgelit monochrome display

o Backlit active matrix black and white VGA display using thin-film
transistor (TFT) technology

o Backlit active matrix color VGA display using thin-film transistor (TFT)
technology
This chapter provides information on the following topics. The bracketed
numbers indicate the section in which each topic is discussed:

o Liquid Crystal Display [8.2]

o Video Graphics Controller [8.3]
o Display Modes [8.4]
o Register Programming [8.5]
o Mode-Specific Register Values [8.6]

The VGC drives the internal LCD and supports simultaneous operation of an
optional external VGA monitor that can be connected to the back of the
system unit. The LCD is toggled on and off by the Ctrl + Alt + > command.
The external monitor is toggled on and off by the Ctrl + Alt + < command.

The video subsystem for the COMPAQ LTE Lite/20, COMPAQ LTE Lite/25, and
COMPAQ LTE Lite/25e supports MDA, CGA, EGA, and VGA modes in up to 64
shades of gray. Up to 256-color VGA and Accelerated VGA modes are also
supported with an external VGA monitor attached.

The video subsystem on the COMPAQ LTE Lite/25C supports MDA, CGA, EGA, VGA,
and Advanced VGA modes with up to 256 colors. Accelerated VGA modes are
also supported with an external VGA monitor attached.

Figure 8-1 presents a block diagram of the COMPAQ LTE Lite video subsystem.
The video graphics controller (VGC) components include the video ASIC,
video memory, video DAC, and video BIOS. The video subsystem interfaces
with the rest of the system over the system bus, which, for video
operations, uses peripheral bus cycles at processor speed. Most of the
functionality of the VGC is contained in the video ASIC, which operates
according to instructions received from the video BIOS ROM.

Although not considered a part of the video subsystem, the BIOS provides a
power-on diagnostic test of the VGC as well as the firmware needed to
initialize the VGC for the different video BIOS modes. Refer to Chapter 7,
"BIOS," for information on the video BIOS calls.

The COMPAQ LTE Lite/20 and COMPAQ LTE Lite/25 include 256 Kbytes of video
memory and use a monochrome edgelit LCD that supports VGA text and graphics
modes in up to 64 shades of gray (high or low resolution respectively).

The COMPAQ LTE Lite/25e contains 512 Kbytes of video memory and an active
matrix black and white LCD to provide high contrast gray scaling in up to
64 shades of gray.

The COMPAQ LTE Lite/25C contain 512 Kbytes of video memory and an active
matrix LCD to provide simultaneous 256-color support in 640 x 480
resolution.

ILLUSTRATION OF Figure 8-1. COMPAQ LTE Lite Video Subsystem Block Diagram

8.2 LIQUID CRYSTAL DISPLAY (LCD)

Liquid Crystal Technology

Liquid crystal technology is based on the polarized molecular activity that
occurs when an electric current passes through electrode strips or
crystals. When a voltage is placed across a liquid crystal cell, the
crystal twists and aligns the light with a top polarizer allowing light to
pass through. The crystals are separated by spacer particles enclosed with
them.

The 640 x 480 display panel is functionally a single physical entity

illuminated by fluorescent tubes. The panel is scanned in two halves of
640 x 240 pixels each (see Figure 8-2).

ILLUSTRATION OF Figure 8-2. Basic LCD Line/Column Scanning Configuration

The dual scanning of the LCD occurs in parallel. Data is applied as two
4-bit packages and displayed two lines at a time (i.e., lines 1 and 241 are
scanned simultaneously, followed by lines 2 and 242).

Unlike a CRT, the number of lines and columns of the LCD cannot be varied.
Selection of an operating mode utilizing less than the full 480 lines will
result in unused lines. During normal operating mode, the panel divides any
unused lines evenly between the top and bottom of the panel so that the
active display is always centered vertically. The scanning rate is always
constant because the display scan goes through all 480 lines on each frame
regardless of the number of active lines. This means that graphics modes
using 360 or 720-pixel wide resolution are not support by the LCD (but will
be displayed on a connected external monitor).

Since the horizontal dot count is fixed at 640, 9-dot text modes are
displayed in 8-dot format. The display has an 8-bit wide character cell
instead of the normal 9-bit cell for a VGA monitor. In text mode, the ROM
alters certain characters to permit their display in this format without
distortion. For more information, see "Text Attribute Implementation" in
this chapter and in the BIOS chapter.

The aspect ratio of the LCD display is fixed at 1:1. The resulting "square
pixels" have an effect on images appearing on the screen. The 640 x 480
modes will appear normal.

The 640 x 400 and 640 x 350 modes may appear to be flattened vertically
which can cause a change in the appearance of the shapes on the screen. The
modes will have their images centered on the screen.

The 360- and 720-pixel wide graphics modes and 132-column text modes are
not compatible with this active matrix LCD (but will be displayed on a
connected external VGA color monitor).

The LCD assembly consists of the following components:

o Display panel with data connector, backlight power cable, and one or two
fluorescent tubes

o Backlight inverter board with contrast and/or brightness control, and

associated circuitry to produce the required voltages for the LCD and
backlight.
>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> WARNING
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

Be aware that voltages as great as 350 volts are present on the power
connectors and Backlight Inverter Board when the unit is on.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<
<<<<<<<<<<<<<<<<<<<<

NOTE: Any disassembly of the LCD assembly can affect performance and will
void your warranty for this component.

Passive Matrix Monochrome LCD

The COMPAQ LTE Lite/20 and COMPAQ LTE Lite/25 use an edgelit passive matrix
monochrome LCD that provides VGA support in the following resolutions:

o 640 x 480 in 16 shades of gray

o 320 x 200 in 32 shades of gray
o 320 x 200 in 64 shades of gray

This 9.5 inch (diagonal) LCD features compensated super-twist technology

with a film-compensated LCD layer that enhances contrast. A single
cold-cathode fluorescent tube provides edgelighting for the display.

Active Matrix LCD

The COMPAQ LTE Lite/25e and COMPAQ LTE Lite/25C feature an active matrix
LCD that uses Amorphous Silicon thin film transistor (TFT) technology that
provides higher contrast and a sharper image. The active matrix LCD is
backlit with hot cathode fluorescent tubes to enhance brightness.

Active Matrix Black and White LCD

The COMPAQ LTE Lite/25e uses an active matrix black and white LCD featuring
TFT technology for a truer black and white effect and wider viewing angle.
This 9.5-inch (diagonal) LCD supports the following Advanced VGA and VGA
modes:

o 640 x 480 in 16 shades of gray

o 320 x 200 in 32 shades of gray
o 320 x 200 in 64 shades of gray

Active Matrix Color LCD

The COMPAQ LTE Lite/25C uses an active matrix color LCD featuring TFT
technology. This LCD supports the following Advanced VGA and VGA modes:

o 640 x 480 resolution in 256 colors

o 640 x 480 resolution in 16 colors
o 320 x 200 resolution in 256 colors
o 640 x 480 resolution in 16 colors

The 8.4-inch (diagonal) display panel contains 1920 (640 x 3 colors)

columns by 480 rows of pixels. Each square pixel has three colors and each
color uses a TFT as an active device. The pixel color order is repetitive
by columns, and data is loaded 3-bits/color, or 9-bits/pixel. Figure 8-3
shows the color LCD configuration.

ILLUSTRATION OF Figure 8-3. Active Matrix Color LCD Configuration

8.3 VIDEO GRAPHICS CONTROLLER (VGC)

As shown in Figure 8-1, the VGC consists of the video ASIC, video memory,
and video DAC.

Video ASIC

The video ASIC contains most of the functionality of the VGC. A block
diagram of the video ASIC is shown in Figure 8-4. The following paragraphs
describe the key functions of the video ASIC.

Bus Interface -- The Bus Interface handles all interaction between the
system bus and the video subsystem. Once permission has been granted by the
Sequencer, address and data information is passed to the appropriate Video
ASIC function.

Sequencer -- The Sequencer takes the output of the master clock and
generates timing, address and control signals used by other video subsystem
functions.

BitBLT Engine -- The Bit Block Transfer (BitBLT) engine provides hardware
support for moving blocks of data in video memory.

CRT Controller -- The CRT controller generates horizontal and vertical

blanking and synchronization signals. Memory address sequencing and CRT
timing signals are programmable for different BIOS modes.

Attribute Controller -- Data from video memory is processed to decode

blinking, highlighting, and reverse video and are then added to the video
stream. A 16-of-64 color palette is also included for compatibility with
software written for the EGA standard.

LCD Controller -- The LCD controller processes video data for display on
the LCD screen and provides power sequencer and screen save functions. In
the COMPAQ LTE Lite/20, COMPAQ LTE Lite/25, and COMPAQ LTE Lite/25e, the
LCD controller also provides the color-to-gray scale conversions. In the
COMPAQ LTE Lite/25C, the LCD controller provides RAMDAC and TFT processor
functions.

ILLUSTRATION OF Figure 8-4. Video ASIC Block Diagram

LCD Controller, Monochrome Operation

Colors written to the palette of the video DAC are translated by the LCD
interface logic to the nearest shades of gray. Software can reduce the
chance of different colors resulting in the same shade of gray by changing
values in the red, green, and blue (RGB) weighting registers (refer to the
Register Programming section).

LCD Controller, Color Operation

The color LCD controller supports the 512-color TFT panel. Two functions
unique for color support are provided: the RAMDAC function and the TFT
processor function.

RAMDAC Function

The RAMDAC function provides a 256 x 18-color palette and the control logic
that allows it to emulate the palette functions of the video DAC chip (that
supports the external VGA monitor). Normally the LCD controller RAMDAC
shadows video DAC writes. However, if the RAMDAC Emulation bit in the DAC
Control register is active, then the LCD controller RAMDAC takes over all
of the external RAMDAC's palette functionality.

TFT Processor Function

The TFT Processor function takes the 18-bit palette color from the palette
RAM and produces 9 bits of color data (3 bits of red, green, and blue) for
the TFT panel. Normally this would produce 512 colors. However, the VGC
circuitry is able to display 4096 colors in high resolution mode and 256K
colors in low resolution mode by using frame rate modulation.

In low resolution mode, these 16 color levels are further expanded to

produce 64 color levels for each primary color and thus 256K total colors.

The TFT Modulation bit in the DAC Control register, TFTMOD, provides a way
to turn off the frame rate modulation associated with the COL1_2 bit. If
this bit is active then there is no modulation in high resolution mode and
only 512 colors can be displayed. In low resolution mode only the half tone
signals (HT1OF4, HT1OF2, and HT3OF4) are used and 32 colors are produced
for red, green, and blue resulting in 32768 total colors.

The Round and Resolve bits in the DAC Control register operate on different
portions of the three 6-bit palette colors depending on whether the TFT
processor is in high or low resolution mode and whether the TFT Modulation
bit is active. If the VGC is in high resolution mode and the TFT Modulation
bit is inactive then frame rate modulation is disabled and the upper 3 bits
<5..3> of each color are sent unmodified to the panel. In this case,
bit <2> is used for rounding and bits <2..0> are used for resolving.

If the VGC is in high resolution mode and the TFT Modulation bit is active,
then bit <2> is used for frame rate modulation. In this case rounding is
based on bit <1> and resolving on bits <1> and <0>. If the VGC is in low
resolution mode and the TFT modulation bit is inactive then bits <2> and
<1> are used to select the alternating signals. Both rounding and resolving
use bit <0> in this case. If the VGC is in low resolution mode and the TFT
Modulation bit is active then bit <2> is used for frame rate modulation and
bits <1> and <0> are used to select the alternating signals. Round and
resolve have no effect in this case since all of the bits are being used.

Video Memory
A block diagram of video memory of the video system is shown in Figure 8-5.
The video memory is arranged into four RAM planes.

In text modes, planes 0, 1, and 2 hold characters, attributes, and fonts

respectively. Plane three is not used in text modes. In multiplane graphics
modes, planes can be addressed in parallel with each plane supplying a
pixel's color bit. In packed pixel graphics modes, a pixel's bits are
contained within a single byte.

The COMPAQ LTE Lite/20 and /25 include 256 Kbytes of video memory. The
COMPAQ LTE Lite/25e and COMPAQ LTE Lite/25C feature 512 Kbytes of video
memory that allows for 256 colors to be displayed simultaneously in 640 x
480 resolution on an optional external monitor. The COMPAQ LTE Lite/25C can
also display 256 colors on its color LCD.

Video Memory Mapping

The frame buffer can be accessed through traditional DOS video space or
through the High Address Map. The DOS video space (two areas known as DOS
apertures) is always enabled and the High Address Map is enabled if there
is room in the extended memory address space.

DOS Apertures

DOS allocates 128 Kbytes of address space (A000: to BFFF) to applications

for video memory access. However, for extended modes of operation, the size
of video memory is larger than 128 Kbytes. Therefore, video memory pages
must be used to map sections of video memory into the DOS apertures. Two
sizes of DOS apertures can be mapped: 32 Kbytes for mapping 64 KB of video
memory (Figure 8-6) and 64 Kbytes for mapping 128 KB of video memory
(Figure 8-7).

ILLUSTRATION OF Figure 8-5. Video Memory Block Diagram

ILLUSTRATION OF Figure 8-6. DOS 32K Apertures Mapping

ILLUSTRATION OF Figure 8-7. DOS 64K Apertures Mapping

High Address Map

The video memory can be accessed as one full frame buffer (up to 1
megabyte) at addresses above 1 megabyte. The High Address Map Register
(3CF.48 - 049h) specifies the CPU physical address corresponding to the
start of the video memory and may be read by software to determine the
location of video memory. Mapping is disabled when this register is
programmed with zeros. It is enabled when programmed with a non-zero
value. If the High Address Map is enabled, for every CPU memory read/write,
address bits 20 to 23 of the CPU are compared against the least-significant
four bits of the High Address Map Register. If they match, the frame buffer
is selected with the low 20 CPU address lines.

NOTE: Both the DOS Aperture and the High Address Map have the same view as
selected by bit 1 of the Control Register 0. Figure 8-8, High Address
Mapping, illustrates this mapping scheme.
In ISA-based systems, High Address Map is disabled. Software must query the
system for memory availability and set the High Address Map as desired. A
BIOS call is provided to support this query.

The High Address Map Register is reset to "0" when the sequencer is reset,
thus destroying any value stored. Before resetting the sequencer, the high
address must be saved and then later restored.

NOTE: A BIOS Mode switch always results in a Sequencer reset operation;

hence, the High Address Map Register must be saved before a BIOS Mode
switch and restored after the mode switch.

ILLUSTRATION OF Figure 8-8. High Address Mapping

Video DAC

A block diagram of the Video Digital/Analog Converter (DAC) is shown in

Figure 8-9. The Video DAC converts digital video data into analog signals
used by an external monitor. The Video DAC also provides the pixel port
multiplexing and color look-up table (palette) functions that supports the
packed-pixel modes.

Color Lookup Table (Palette RAM) -- Color bits from the attribute
controller provide a selection of 256 from a palette of 16,777,216 colors.
Each of the 256 locations in the palette RAM defines a color derived from 8
bits of red, green, and blue. If fewer than 256 colors are needed, the
palette can be subdivided into four palettes (for 64 colors) or even 16
palettes (for 16 colors). There are 6- and 8-bit modes for 218 or 224
palettes.

Digital/Analog Converter (DAC) -- The DAC components provide analog video

data for an external CRT monitor. Each set of eight outputs from the color
palette RAM is applied to one of three D/A converters. Digital codes from
00000000b to 11111111b (0h to FFh) correspond to an output voltage between
0.00 and 0.70 volts. A given primary color's intensity is directly
proportional to this output voltage (Table 8-1).

Table 8-1. Voltage Output from the Video Digital-to-Analog Converters

=======================================================
====================
Color Lookup Percent Video DAC
Table Contents Output (Volts)
---------------------------------------------------------------------------
00000000 0 0.00

00111100 25 0.17

01010100 33 0.23

01111100 50 0.34

10101000 67 0.46

10111100 75 0.52
11111111 100 0.70
=======================================================
====================

Monitor Configuration Sensor -- This logic uses a set of three

fixed-threshold voltage comparators that provide built-in test capability
and determines whether a monochrome or color CRT is attached by sensing the
load on the DAC outputs.

ILLUSTRATION OF Figure 8-9. Video DAC Block Diagram

8.4 DISPLAY MODES

The video graphics system provides one of two types of displays: text or
graphics. The video graphics system can be configured a number of ways
depending on the type of display desired and the operating and specific
BIOS mode selected.

Text Configurations

The text display uses a multiplane configuration where a character, its

attributes, and fonts are stored in the separate memory planes. Table 8-2
lists the text configurations provided by the video system. Note that the
text configurations for CGA/MDA, EGA, and VGA share common video BIOS modes
that result in the same format but provide different pixel resolutions.

NOTE: The LCD screen does not support 132-column text modes. An external
VGA monitor must be used to view 132-column text modes. In such a
configuration, the LCD will be blanked.

Table 8-2. Text Configuration Display Modes

=======================================================
====================
Software Video Format Pixel Number
Interface BIOS Resolution of
Mode Colors
---------------------------------------------------------------------------
CGA, EGA *, VGA *, 0 40 x 25 Text 320 x 200 16
Accelerated VGA #, 1 40 x 25 Text 320 x 200 16
Advanced VGA # 2 80 x 25 Text 640 x 200 16
3 80 x 25 Text 640 x 200 16
---------------------------------------------------------------------------
MDA 7 80 x 25 Text 720 x 350 Monochrome
---------------------------------------------------------------------------
EGA *, VGA *, 0 40 x 25 Text 320 x 350 16
Accelerated VGA #, 1 40 x 25 Text 320 x 350 16
Advanced VGA # 2 80 x 25 Text 640 x 350 16
3 80 x 25 Text 640 x 350 16
---------------------------------------------------------------------------
VGA *, 0 40 x 25 Text 360 x 400 16
Accelerated VGA #, 1 40 x 25 Text 360 x 400 16
Advanced VGA # 2 80 x 25 Text 720 x 400 16
3 80 x 25 Text 720 x 400 16
7 80 x 25 Text 720 x 400 Monochrome
---------------------------------------------------------------------------
Accelerated VGA #, 18 132 x 43 1056 x 350 Monochrome
Advanced VGA # 19 132 x 25 1056 x 400 Monochrome
1A 132 x 28 1056 x 400 Monochrome
1B 132 x 50 1056 x 400 Monochrome
1C 132 x 60 1056 x 480 Monochrome
22 132 x 43 1056 x 350 16
23 132 x 25 1056 x 400 16
24 132 x 28 1056 x 400 16
27 132 x 50 1056 x 400 16
28 132 x 60 1056 x 480 16
---------------------------------------------------------------------------
* Configurations that share common BIOS modes but provide different
resolutions
# Displayed on optional external VGA monitor only
=======================================================
====================

Graphics Configurations

The video system can operate in either of two fundamental graphics

configurations: Multiplane or Packed Pixel. Table 8-3 shows the graphics
configurations supported by the VGC.

Table 8-3. Graphics Configuration Display Modes

=======================================================
====================
Software Video Mapping Pixel Number
Interface BIOS Architecture Resolution of
Mode Colors
---------------------------------------------------------------------------
CGA 4 Packed Pixel -- 2 bits 320 x 200 4
5 Packed Pixel -- 2 bits 320 x 200 4
6 Packed Pixel -- 1 bit 640 x 200 2
---------------------------------------------------------------------------
CGA, EGA D Multiplane 320 x 200 16
E Multiplane 640 x 200 16
F Multiplane 640 x 350 Monochrome
10 Multiplane 640 x 350 16
---------------------------------------------------------------------------
CGA, EGA, 11 Multiplane 640 x 480 2
VGA 12 Multiplane 640 x 480 16
13 Packed Pixel -- 8 bits 320 x 200 256
---------------------------------------------------------------------------
CGA, EGA, VGA, 29 * Multiplane 800 x 600 16
Advanced VGA 2E # Packed Pixel -- 8 bits 640 x 480 256
---------------------------------------------------------------------------
* Displayed on optional external monitor only
# COMPAQ LTE Lite/25C only
=======================================================
====================

BIOS Modes D, E, F, and 10 are provided for compatibility with the EGA
standard. BIOS Modes 11 and 12 provide the highest LCD graphics resolution,
640 x 480.

Pixel data for both graphics configurations is physically stored in video

memory in a packed-pixel format. However, the graphics controller permits
the video memory to be "viewed" in either a packed-pixel or multiplane
organization. The packed-pixel view permits access to video memory the same
way the data is stored internally. The multiplane view enables the video
memory to be viewed in a planar organization (bit-plane basis) with the VGC
performing the required cycles to write/read the appropriate bits in video
memory (all transparent to the programmer).

Multiplane Configuration

The Multiplane configuration allows fast manipulation of graphical screen

images. This is done by an architecture that places the four video memory
planes in parallel with hardware that allows selective manipulation of up
to eight pixels at a time.

In the Multiplane configuration, each plane supplies one bit of the code
that selects a color from the palette (Figure 8-10). When all four planes
are used, 16 (24) colors are possible for each pixel. Four write modes and
two read modes are employed in multiplane configurations, as listed in
Table 8-4.

ILLUSTRATION OF Figure 8-10. Multiplane Configuration

Table 8-4. Summary of Modes Used in Multiplane Configuration

=======================================================
====================
Mode Description
---------------------------------------------------------------------------
Write Mode 0 Write Mode 0 allows bit manipulation of data going from
the system to memory. This mode writes individual
pixels to the screen.

Write Mode 1 Write Mode 1 allows copying a byte from one screen
location to several (or all) other screen locations.
Data comes from the Read Data Latch, in the read logic
in the graphics controller, rather than from the
system.

Write Mode 2 Write Mode 2 is used to fill selectively an area of the

screen with a particular color. Each bit in the data
byte from the system is expanded to eight bits in each
plane. Each bit loads one byte in each of the four
planes.

Write Mode 3 Write Mode 3 allows bit manipulation (for example,

ANDing or ORing) of data going from the system memory
to video memory. This mode writes individual pixels to
the screen.

Read Mode 0 Read Mode 0 is a normal read mode. It allows any one of
the four planes to be read back to the system. Each
byte in the plane is read directly to the system
without processing.

Read Mode 0 is selected by the graphics controller mode

register (refer to "Graphics Controller Registers"
section). The plane to be read is selected by entering
the appropriate code in the Read Plane Select register.
When a read cycle occurs, all four planes are read and
their data latched, but only the data from the
designated plane is used. For all four planes to be
read, this sequence must occur four times.

Read Mode 1 Read Mode 1 provides hardware assistance in searching

the screen for pixels of a given color. Read Mode 1
allows software to determine which pixels match a given
color.
=======================================================
====================

NOTE: Video BIOS uses only Write Mode 0 and Read Mode 0. If software needs
to change modes, the Graphics Controller Mode register must be
changed. (See "Graphics Controller Registers.")

Packed Pixel Configuration

The Packed Pixel configuration allows the CPU to have direct access to all
the bits that control a pixel. Depending on the BIOS mode, each pixel is
controlled by 1, 2, or 8 bits. Accordingly, each byte of video memory can
control one, four, or eight pixel(s).

Packed pixel operation allows the programmer to access video data as it is

physically stored. BIOS Modes 2Eh and 13 provide the most colors of any
BIOS mode supported by the VGC. BIOS Modes 4, 5, and 6 are provided for
compatibility with the CGA standard.

The Packed Pixel configuration incorporates three different display

formats:

1. 256-colors, BIOS Modes 2Eh (COMPAQ LTE Lite/25C only) and 13 @ 8 bits
per pixel

2. 320 x 200, 4 colors, BIOS Modes 4 and 5 @ 2 bits per pixel

3. 640 x 200, 2 colors, BIOS Mode 6 @ 1 bit per pixel

In the packed-pixel view, the first byte of video memory (A000:0)

represents the first pixel of the display (Figure 8-11). (Note that in the
256-color mode, eight bits are required to represent a single pixel.) The
second byte (A000:1) represents the second pixel of the display and so on.

ILLUSTRATION OF Figure 8-11. Packed Pixel Configuration (8 Bits Per Pixel)

Planar View

The planar view of the video memory enables the programmer to access bit
planes of the pixel data for read and write operations. Note that although
the pixel data is accessed as bit planes, it is still stored in video
memory in a packed-pixel format. In addition, two other write modes permit
the modification of eight pixels for each byte transferred. These two write
modes are referred to as "color-expand write modes" since each bit of data
written to the graphics controller is "expanded" into one pixel of data in
the frame buffer. This is useful in graphic rendering operations where one
byte of data can modify eight pixels on the screen; whereas the
packed-pixel view would require eight bytes to modify the same eight
pixels. During these write operations, back-end circuitry performs the
required operations to write/read the appropriate bits in video memory.
This operation is performed transparent to the programmer.

In planar view, the first byte of video memory (A000:0) corresponds to the
first eight pixels of the display. The second byte corresponds to the next
consecutive eight pixels and so on. The most significant bit of the byte is
the left-most pixel on the display.

There is one read mode and three write modes for this view. They are
referred to as Planar Read Mode, Planar Write Mode, Foreground/Background
Color-Expand Write Mode, and Foreground/Transparent Color-Expand Write
Mode.

Planar Read Mode

The Read Control Register (3CF.41h) specifies the "color bit plane" to be
read. Since data in physical memory is packed, a byte read at "color plane
n" means extracting bit n from eight consecutive 8-bit pixels. For an
example of this read mode, refer to Figure 8-12, Planar Read Mode.

ILLUSTRATION OF Figure 8-12a. Planar Read Mode (Part 1 of 2)

ILLUSTRATION OF Figure 8-12b. Planar Read Mode (Part 2 of 2)

Write Modes

The planar view for BIOS Mode 2Eh includes three write modes. These modes
are selected with bits <3, 2> of Control Register 0.

Writes to individual pixels are selected through the Pixel Write Mask
Register (3C5.02h). This register is the VGA Sequencer Write Plane Mask
extended to eight bits. Bit 7 affects the leftmost pixel on the screen (CPU
data bit 7). It is still a 4-bit register in VGA standard modes for
compatibility reasons.

Planar Write Mode

The Color Plane Write Mask Register (3CF.08h) specifies which color bit
planes are to be written (this is the VGA Bit Mask register). Bits with the
value of 1 in the write mask allow writes; bits with the value of 0
preserve the contents of the corresponding bit planes. Figure 8-13 (Planar
Write Mode Byte Write) and Figure 8-14 (Planar Write Mode Word Write)
illustrate this write mode.

ILLUSTRATION OF Figure 8-13. Planar Write Mode Byte Write

ILLUSTRATION OF Figure 8-14a. Planar Write Mode Word Write (Part 1 of 2)

ILLUSTRATION OF Figure 8-14b. Planar Write Mode Word Write (Part 2 of 2)

Foreground/Background Color-Expand Write Mode An 8-bit value is expanded

such that bits with the value of 1 select the 8-bit Foreground Color
Register and bits with the value of 0 select the 8-bit Background Color
Register to write to the corresponding 8-bit pixels. See Figure 8-15
(Foreground/Background Color-Expand Write Mode Byte Write) and Figure 8-16
(Foreground/Background Color-Expand Write Mode Word Write) for an example.
The hardware architecture for this configuration is depicted in
Figure 8-17, Foreground/Background Color-Expand Write Mode Block Diagram.

ILLUSTRATION OF Figure 8-15. Foreground/Background Color-Expand Write Mode

Byte Write

ILLUSTRATION OF Figure 8-16a. Foreground/Background Color-Expand Write Mode

Word Write (Part 1 of 2)

ILLUSTRATION OF Figure 8-16b. Foreground/Background Color-Expand Write Mode

Word Write (Part 2 of 2)

ILLUSTRATION OF Figure 8-17a. Foreground/Background Color-Expand Write Mode

Block Diagram (Part 1 of 4)

ILLUSTRATION OF Figure 8-17b. Foreground/Background Color-Expand Write Mode

Block Diagram (Part 2 of 4)

ILLUSTRATION OF Figure 8-17c. Foreground/Background Color-Expand Write Mode

Block Diagram (Part 3 of 4)

ILLUSTRATION OF Figure 8-17d. Foreground/Background Color-Expand Write Mode

Block Diagram (Part 4 of 4)

Foreground/Transparent Color-Expand Write Mode An 8-bit value is expanded

such that bits with the value of 1 select the 8-bit foreground color and
bits with the value of 0 disable writes to the corresponding 8-bit pixels.
This write mode is similar to a foreground/background color expand write
except that the physical memory plane corresponding to the pixel masked is
write inhibited. Figure 8-18 (Foreground/Transparent Write Mode Byte Write)
and Figure 8-19 (Foreground/Transparent Write Mode Word Write) illustrate
this write mode. The hardware architecture for this configuration is
depicted in Figure 8-20, Foreground/Transparent Write Mode Block Diagram.

ILLUSTRATION OF Figure 8-18. Foreground/Transparent Write Mode Byte Write

ILLUSTRATION OF Figure 8-19a. Foreground/Transparent Write Mode Word Write

(Part 1 of 2)

ILLUSTRATION OF Figure 8-19b. Foreground/Transparent Write Mode Word Write

(Part 2 of 2)

ILLUSTRATION OF Figure 8-20a. Foreground/Transparent Write Mode Block

Diagram (Part 1 of 4)

ILLUSTRATION OF Figure 8-20b. Foreground/Transparent Write Mode Block

Diagram (Part 2 of 4)

ILLUSTRATION OF Figure 8-20c. Foreground/Transparent Write Mode Block

Diagram (Part 3 of 4)

ILLUSTRATION OF Figure 8-20d. Foreground/Transparent Write Mode Block

Diagram (Part 4 of 4)

8.5 REGISTER PROGRAMMING

This section provides information needed to program the following VGC

registers:

o Control and Status Registers

o Sequencer Registers
o Graphics Controller Registers
o CRT Controller Registers
o Attribute Controller Registers
o Video DAC Registers
o Bit Block Transfer (BitBLT) Registers
o COMPAQ Personal Computer-specific registers

At the end of this section are tables presenting mode-specific register

values.

Control and Status Registers

Table 8-5 lists the Control and Status registers and their addresses.
Table 8-5. Control and Status Registers
=======================================================
====================
Address Register Read/Write
---------------------------------------------------------------------------
102h Option Select R/W

3C2h Input Status 0 R

3C2h Miscellaneous Output W

3xAh Input Status 1 R

3xAh Feature Control W

3CAh Feature Control R

3CCh Miscellaneous Output R

3CF.0Bh Compaq Configuration R/W

3CF.0Ch Version Number R

3CF.0Fh Environment Register 0 R

3CF.10h BitBLT Configuration R/W

3CF.40h Control Register 0 R/W

3CF.45h Page Register 0 R/W

3CF.46h Page Register 1 R/W

3CF.48 - 49h High Address Map R/W

46E8h Video Enable R/W

=======================================================
====================

Option Select, Port 102h, Read/Write

Only bit <0> of port 102h is used for Card Enable. Read/write access to
this register is allowed only when the setup bit <4> of the Video Enable
Register (46E8h) is asserted.

BIT FUNCTION
----------------
7..1 Reserved

0 0 = Disabled
The VGC does not respond to commands, data, or addresses on the
data bus.
1 = Enabled
The VGC responds to commands issued to VGC valid addresses.
Input Status 0, Port 3C2h, Read Only

This register contains the status of the analog comparator and of the
Vertical Retrace Interrupt.

BIT FUNCTION
----------------
7 Vertical Retrace Interrupt (IRQ9) status
0 = Interrupt cleared
1 = Interrupt pending

6,5 Reserved

4 Status of analog comparator (monitor sense)

0 = One or more RGB analog output(s) is above 0.35V
1 = All RGB analog outputs are below 0.35V

3..0 Reserved

Bit <4> is "0" whenever an R, G, or B video DAC output exceeds

approximately 0.35 volt.

Miscellaneous Output, Port 3C2h, Write Only (Read at 3CCh)

This register controls miscellaneous functions of the VGC circuitry.

BIT FUNCTION
----------------
7 Vertical Sync Polarity
0 = (+)
1 = (-)

6 Horizontal Sync Polarity

0 = (+)
1 = (-)

5 Page Select Bit in odd/even mode

0 = Low page (for diagnostic use)
1 = High page (for diagnostic use)

4 Reserved

3,2 Master Clock Frequency

00 = 25.175 MHz (640 or 320 pixels wide format)
01 = 28.322 MHz (720 or 360 pixels wide format)
10 = 41.538 MHz clock for 132-column modes
11 = Reserved

1 CPU access to video memory

0 = Disabled
1 = Enabled

0 I/O Base Address

0 = 3Bxh, monochrome display
1 = 3Dxh, color display

Input Status 1, Port 3xAh, Read Only

This register contains the status of various video signals.

The Display Enable signal bit indicates active display times. This signal
combines the horizontal and vertical sync and other blanking periods.

Bits <5, 4> of the Color Plane Enable register select which two of the
eight Color Lookup Table address bits will appear on bits <5, 4> of Input
Status 1 register.

=============================================
Color Plane Input Status 1
Enable Register Register
---------------------------------------------
Bits <5> <4> <5> <4>

0 0 P2 P0

0 1 P5 P4

1 0 P3 P1

1 1 P7 P6
=============================================

BIT FUNCTION
----------------
7,6 Reserved

5 R/B Multiplexed Video Bits MUX (See NOTE)

00 = P2 -- Primary Red (R)
01 = P5 -- Secondary Red (r)
10 = P3 -- Secondary Blue (b)
11 = P7
0 = Inactive
1 = Active

4 G/B Multiplexed Video Bits MUX (See NOTE)

00 = P0 -- Primary Blue (B)
01 = P4 -- Secondary Green (g)
10 = P1 -- Primary Green (G)
11 = P6
0 = Inactive
1 = Active

3 Vertical Sync Pulse (Interrupt IRQ9 control is available through

bits <4, 5> of Vertical Retrace End register)
0 = Inactive
1 = Vertical Retrace Interval

2,1 Reserved
0 Display Enable (Real-time status of inverted Display Enable)
0 = Video active
1 = Video blanked

NOTE: MUX = Bits <5, 4> of the Color Plane Enable register in the attribute
controller. The colors listed are for EGA modes only.

Feature Control, Port 3xAh, Write (Read at 3CAh)

This register specifies the state of the FC0 and FC1 signals.

BIT FUNCTION
----------------
7..0 Reserved

Compaq Configuration, Port 3CFh, Index 0Bh, Read/Write

The Compaq Configuration Register is used to enable the VGA for proper
operation depending on the environment and other configuration purposes.
This register is initialized to 00h and write-protected (locked) on
power-up. To write to these bits, Register 03CF.0F must be loaded with the
value 05h. This register will read 0Fh when locked.

BIT FUNCTION
----------------
7..4 For READ: Return power-up jumper configuration for bits 7..4.
For WRITE: Bits 5..7: Reserved
Bit 4 = 1: Enable 0 wait state signal for I/O and memory
if applicable.
Bit 4 = 0: Disable 0 wait state signal.

3 Spare (not used)

2 Video Memory Bus Configuration

1 = 16-bit video memory cycles
0 = 8-bit video memory cycles

1 BIOS Bus Configuration

1 = 16-bit BIOS memory cycles
0 = 8-bit BIOS memory cycles

0 BIOS Disable
1 = Disabled
0 = Enabled

Version Number, Port 3CFh, Index 0Ch, Read Only

This register is provided as a read only register to provide BIOS with a

way of determining the current version of the silicon. Note that the
version number in this register may not correspond to the part dash number.
This is because the register version number will only be incremented if the
previous version was released to production. Read only when unlocked.

BIT FUNCTION
----------------
7..3 Project number
00011 = Accelerated VGA
00101 = Advanced VGA

2..0 Version number of current silicon

001 = First production release

Environment Register 0, Port 3CFh, Index 0Fh, Read Only

The environment status bits <7..4> are read-only at 03CF.0F. These status
bits are loaded at power-on to identify the VGA board level configuration
and installation, and are used by the POST software to configure the VGA
for 8- or 16-bit operation. These configuration bits are read protected and
may only be read when the lock register 03CF.0F (bits <3, 2>) is loaded
with the value 05h. Otherwise, this register will read back as 0Fh for
compatibility.

BIT FUNCTION
----------------
7 Installed ROM BIOS Size (Read only)
1 = 8-bit
0 = 16-bit

6 Installed Video Bus Size (Read only)

1 = 8-bit
0 = 16-bit

5 Installed Slot Type (Read only)

1 = 16-bit
0 = 8-bit

4 Installed Bus Configuration (Read only)

Reserved. Must be 0

3,2 Lock Register (Read/Write)

Unlock = 05

BitBLT Configuration, Port 03CF, Index 10h, Read/Write

This register is Read/Write when unlocked.

BIT FUNCTION
----------------
7 TRI-STATE (TS)
This bit, when "1", tri-states all video memory data, address, and
control lines.

6 RESET BLT (RBLT)

This bit, when toggled from "0" to "1" to "0", resets the BLT
Engine State Machine and all BLT registers into a normal VGA
configuration.

5 Accelerated VGA = Reserved

Advanced VGA = IRQ9 Disable
1 = Tri-stated
0 = Enabled

4 Accelerated VGA = Reserved

Advanced VGA = IRQ Polarity
1 = Active low
0 = Active high

3 BitBLT ENABLE (BBEN)

This bit, when "1", enables the address decode and extended Raster
Ops of all BLT registers. When "0", they are not decoded.

2 BitBLT ADDRESS SELECT (BBAS)

This bit, when "1", assigns BitBLT registers 23C0h - 23CFh to
43C0h - 43CFh and 33C0h - 33CFh to 53C0h - 53CFh.

1 BUS CLOCK DISABLE (BCD)

When this bit is set to "1", the bus clock synchronization of
BUSRDY is disabled.

0 FIFO PRIORITY (FFP)

When this bit is set to "0", the FIFO priority is the same as the
COMPAQ VGC. When this bit is set to a "1", the FIFO priority is
such that more of the screen refresh accesses are forced to be page
mode.

Control Register 0, Port 3CF, Index 40h, Read/Write

This is an 8-bit read/write control register. It is cleared on power-up.

BIT FUNCTION
----------------
7 Reserved

6 Reserved. Must write zeros.

5,4 Select function for the triple-function pin

00 = Strobe for the clock synthesizer
01 = Display enable output
10 = Reserved
11 = Reserved

3,2 Select write mode

00 = Select planar write mode
01 = Select color-expand write mode
10 = Select transparent write mode
11 = Reserved

1 View enable
1 = Enable planar view (color-expand write modes)
0 = Enable packed pixel view

This bit affects both DOS video space and high address map. Packed
pixel mode must be enabled for BitBLTs, except for CPU-to-Screen
BitBLTs where planar view must be enabled. Page Register 0 and Page
Register 1 must be set and restored when switching between packed
pixel and planar modes.

0 Extended color mode enable

1 = Extended 256-color mode enabled
0 = Extended 256-color mode disabled

This bit is cleared when the sequencer is reset to be compatible

with standard VGA.

Page Register 0, Port 3CF, Index 45h, Read/Write

This is an 8-bit read/write control register. It defines where the first

32K/64K page aperture is mapped in video memory (to a 4K resolution). This
register is selected to add to the CPU address when A15 = 0 (and
3CF.06<3,2> = 01) or when A16 = 0 (and 3CF.06<3,2> = 00). This register is
also selected when 3CF.06<3,2> = 1x to allow CPU access to extra memory
available in standard VGA modes. It is cleared when the sequencer is reset
to be compatible with normal VGA modes. Note that Page Register 0 must be
set and restored when switching between packed pixel and planar modes.

Page Register 1, Port 3CF, Index 46h, Read/Write

This is an 8-bit read/write register. It defines where the second 32K/64K

page aperture is mapped into video memory (to a 4K resolution). This
register is selected to add to CPU address when A15 = 1 (3CF.06<3,2> = 01)
or when A16 = 1 (and 3CF.06<3,2> = 00). It is cleared when the sequencer is
reset to be compatible with normal VGA. Note that Page Register 1 must be
set and restored when switching between packed pixel and planar modes.

High Address Map Register, Port 3CF, Index 48 - 49h, Read/Write

This 16-bit register is divided into two 8-bit read/write registers. The
low byte is at index 48h and the high byte is at index 49h. It specifies
where the frame buffer is mapped in CPU address space.

BIT FUNCTION
----------------
15..4 Reserved (Write "0" to these bits)

3..0 Selects which 1 MB page to map. CPU address lines <23..20>

must match these four bits to qualify for the video memory access.
A "0" in this register indicates that the high map is disabled. A
value of "0Fh" is invalid.

Video Enable, Port 46E8h, Read/Write

Video Enable is mapped to port 46E8, bit <3>.

BIT FUNCTION
----------------
7..5 Reserved

4 0 = Enables normal operation

1 = SETUP -- disables normal memory and I/O cycles and enables
read/write to port 0102h. When SETUP is not asserted, the VGC
ignores address 0102h and allows normal operation.

3 1 = VGC enabled for memory and I/O

0 = VGC disabled for memory and I/O

2..0 Reserved

Sequencer Registers

Table 8-6 lists the Sequencer registers, their addresses, and their
indexes.

Table 8-6. Sequencer Registers

=======================================================
====================
Address Register Read/Write
---------------------------------------------------------------------------
3C4h Index R/W

3C5h Data R/W

00h Reset R/W

01h Clocking Mode R/W

02h Write Plane Mask R/W

03h Character Font Select R/W

04h Memory Mode R/W

=======================================================
====================

The sequencer uses two I/O (port) addresses for register access. Port 3C4h
is the Sequencer Index register. Port 3C5h interacts with one of five
Sequencer registers pointed to by the Sequencer Index register.

Sequencer Index, Port 3C4h, Read/Write

This register points to one of five Sequencer registers.

BIT FUNCTION
----------------
7..3 Reserved

2..0 Index
000 = Reset
001 = Clocking Mode
010 = Write Plane Mask
011 = Character Font Select
100 = Memory Mode

Sequencer Reset, Port 3C5h, Index 00h, Read/Write

This register resets the sequencer.

BIT FUNCTION
----------------
7..2 Reserved

1 0 = Synchronous reset (halt)

1 = Allow sequencer to run

0 0 = Asynchronous reset (halt)

1 = Allow sequencer to run

In a synchronous reset, the sequencer waits until a synchronized point at

which it can halt without any possibility of data loss. The sequencer must
be "0" before changing bit <3> or <0> of the Clock Mode register or bit <3>
or <2> of the Miscellaneous Output register.

In an asynchronous reset, the sequencer immediately locks all the registers

and counters. Stopping with this bit can cause data loss in the video RAM.

Bits <0> and <1> must both be set to "1" for the sequencer to run.

Sequencer Clocking Mode, Port 3C5h, Index 01h, Read/Write

This register specifies clock rates for various sequencer functions.

To change the contents of the Sequencer Clocking Mode register, halt the
sequencer synchronously, make the change, then restart the sequencer.

BIT FUNCTION
----------------
7,6 Reserved

5 0 = Normal screen operation

1 = Turn off video screen and give all memory access to processor
(Sync pulses maintained)

4 0 = Video serializers loaded every character clock

1 = Video serializers loaded every 4th clock (useful when 32 bits
are chained in the Shift register)

3 0 = Normal dot clock

1 = Dot clock = Master clock divided by two (320- and 360-pixel
modes)

2 0 = Video serializer reloads every character clock

1 = Video serializer reloads every other character clock (used when
16-bit memory chaining is enabled)

1 Reserved

0 0 = 9-dot character clock (Modes 7 and n+ only)

1 = 8-dot character clock

The dot clock bit (bit <3>) generates the 320-/360-dot modes by halving the
master clock input.
Sequencer Write Plane Mask, Port 3C5h, Index 02h, Read/Write

This Text and Multiplane Graphics Configuration register specifies which

planes of video memory are disabled.

BIT FUNCTION
----------------
7..4 VGA: Reserved (all modes except as noted below)
Mode 2Eh: Extension for 256-color packed pixel modes

3 0 = CPU cannot write to plane 3

1 = CPU can write to plane 3

2 0 = CPU cannot write to plane 2

1 = CPU can write to plane 2

1 0 = CPU cannot write to plane 1

1 = CPU can write to plane 1

0 0 = CPU cannot write to plane 0

1 = CPU can write to plane 0

When odd/even modes (16-bit chaining) are selected, planes 0 and 1 should
have the same value, and planes 2 and 3 should have the same Plane Mask
values. For 32-bit chaining mode, the value of this register should be 0Fh.

For packed pixel graphics configurations, this register behaves as a pixel

mask and can be referred to as the Pixel Write Mask Register. It is
extended to eight bits for 256-color mode and is used as a pixel mask in
color-expand write modes for fast character drawing. In normal VGA modes,
the upper four bits return "0" on reads for compatibility.

Sequencer Character Font Select, Port 3C5h, Index 03h, Read/Write

This register specifies which two fonts are used at any one time as the
source of the dot patterns for the character generator. In Text mode,
plane 2 is divided into eight 8-Kbyte banks. Each bank contains one
256-character font.

This register also specifies which 8-Kbyte bank of video memory is the
source of the dot patterns for the character generator.

=======================================================
====================
MAP A MAP B
---------------------------------------------------------------------------
Bit Bit
3 2 5 1 0 4
---------------------------------------------------------------------------
0 0 0 1st 8 KB Map 0 0 0 1st 8 KB Map
0 0 1 2nd 8 KB Map 0 0 1 2nd 8 KB Map
0 1 0 3rd 8 KB Map 0 1 0 3rd 8 KB Map
0 1 1 4th 8 KB Map 0 1 1 4th 8 KB Map
1 0 0 5th 8 KB Map 1 0 0 5th 8 KB Map
1 0 1 6th 8 KB Map 1 0 1 6th 8 KB Map
1 1 0 7th 8 KB Map 1 1 0 7th 8 KB Map
1 1 1 8th 8 KB Map 1 1 1 8th 8 KB Map
=======================================================
====================

BIT FUNCTION
----------------
7,6 Reserved

5 Font Map A select. Extension for bits <3, 2>

0 = 1st, 3rd, 5th or 7th map
1 = 2nd, 4th, 6th or 8th map

4 Font map B select. Extension for bits <1, 0>

0 = 1st, 3rd, 5th or 7th map
1 = 2nd, 4th, 6th or 8th map

3,2 Font Map A select. Bits <3, 2> specify which 8-Kbyte bank
to use when the text-attribute byte, bit <3> = 1
00 = 1st or 2nd 8-Kbyte Map
01 = 3rd or 4th 8-Kbyte Map
10 = 5th or 6th 8-Kbyte Map
11 = 7th or 8th 8-Kbyte Map

1,0 Font Map B select. Bits <1, 0> specify which 8-Kbyte bank
to use when the text-attribute byte, bit <3> = 0
00 = 1st or 2nd 8-Kbyte Map
01 = 3rd or 4th 8-Kbyte Map
10 = 5th or 6th 8-Kbyte Map
11 = 7th or 8th 8-Kbyte Map

Bit <3> of the text-attribute byte specifies whether the text (foreground)
is in highlight or whether an alternate character font (shown above) is
used. To allow bit <3> of the text-attribute byte to select dual-character
sets, set Map A not equal to Map B.

For consistent colors to be maintained when alternate fonts are used,

either some palette registers for the intensified colors 10..15 must be
reloaded for non-intensified colors, or the contents of the Color Plane
Enable register must be changed to ignore plane 3.

Bit <5> character map selects low bit A (extension for bits <3, 2>).
Bit <4> character map selects low bit B (extension for bits <1, 0>).

Sequencer Memory Mode, Port 3C5h, Index 04h, Read/Write

This register controls CPU access to the video memory and enables the
Character Font Select function, allowing dual-character sets.

BIT FUNCTION
----------------
7..4 Reserved

3 Chain 4
0 = Enables normal operation
1 = Two address LSBs select the map to be addressed. This bit
controls the map selected in the graphics subsystem during CPU
reads

2 0 = Even-numbered CPU addresses access planes 0 and 2

Odd-numbered CPU addresses access planes 1 and 3
1 = CPU addresses access data sequentially in the planes

1 Extended Memory
0 = CPU address bits A <15,14> are ignored. All video memory
accesses are forced to the first 16 Kbytes of display memory
1 = Access is allowed to all 64 Kbytes of display memory

0 Reserved -- Read only

Bit <2> (odd/even bit) controls only the CPU write accesses. CPU read
accesses are controlled by the odd/even bit in the Graphics Controller Mode
register.

Bit <3> controls the map selected in the graphics subsystem during CPU
reads.

Graphics Controller Registers

Table 8-7 lists the Graphics Controller registers, their addresses, and
their indexes.

Table 8-7. Graphics Controller Registers

=======================================================
====================
Address Register Read/Write
---------------------------------------------------------------------------
3CEh Index R/W

3CFh Data R/W

00h Data Set/Reset R/W

01h Enable Bit Set/Reset R/W

02h Color Compare R/W

03h Data Rotate R/W

04h Read Plane Select R/W

05h Mode R/W

06h Miscellaneous R/W

07h Color Don't Care R/W

08h Bit Mask R/W

41h Read Control R/W

43h Foreground Color R/W

44h Background Color R/W

33C2h Raster Operation 3 R/W

33C3h Raster Operation 2 R/W

33C4h Raster Operation 1 R/W

33C5h Raster Operation 0 R/W

33C7h Raster Operation A W

=======================================================
====================

Graphics Controller Index, Port 3CEh, Read/Write

Port 3CEh serves as the Index register for both graphics controllers.

BIT FUNCTION
----------------
7..0 Index:
00h = Data Set/Reset
01h = Enable Bit Set/Reset
02h = Color Compare
03h = Data Rotate
04h = Read Plane Select
05h = Mode
06h = Miscellaneous
07h = Color Don't Care
08h = Bit Mask
41h = Read Control
43h = Foreground Color
44h = Background Color

Graphics Controller Data Set/Reset, Port 3CFh, Index 00h, Read/Write

This register stores a bit pattern to write to video memory when in

Multiplane Graphics Configuration Write Mode 0 (see the Graphics Controller
Mode register). Values are written to each plane unless access to that
plane is disabled.

BIT FUNCTION
----------------
7..4 Reserved

3 Data Bit in Plane 3

0 = Reset
1 = Set

2 Data Bit in Plane 2

0 = Reset
1 = Set

1 Data Bit in Plane 1

0 = Reset
1 = Set
0 Data Bit in Plane 0
0 = Reset
1 = Set

The logic operation selected by the Graphics Controller Data Rotate

register is also applied to the output of the Data Set/Reset register. In
Write Mode 0, output from this register is not written to a plane, unless
that plane is enabled in the Sequencer Write Plane Mask register and the
Graphics Controller Enable Bit Set/Reset register. In Write Mode 3, the
Enable Bit Set/Reset register is ignored.

Graphics Controller Enable Bit Set/Reset, Port 3CFh, Index 01h, Read/Write

This register enables or disables the Bit Set/Reset function on a

plane-by-plane basis. When the Bit Set/Reset function is disabled, CPU data
is written to video memory. When the Bit Set/Reset function is enabled, the
value in the Data Set/Reset register is written to video memory.

This register contains a 4-bit plane pattern (color definition), that is

used during a color comparison (Read Mode 1). In Multiplane Graphics
Configuration Read Mode 1, normal reads cause a color comparison between
the contents of this register and the video memory addressed by the read.
Each pixel (dot) color in the byte read is compared to the color value, and
a "1" is returned in the corresponding bit position if the colors match. A
"0" is returned when a match does not occur in the corresponding bit
position.

BIT FUNCTION
----------------
7..4 Reserved

3..0 These four bits define the color to compare with the colors in
video memory.

Read Mode 1 must be in effect for the Graphics Controller Color Compare
register to be used. The color compare feature in Read Mode 1 is not
affected by the Graphics Controller Read Plane Select register; however, it
is affected by the Graphics Controller Color Don't Care register.

Graphics Controller Data Rotate, Port 3CFh, Index 03h, Read/Write

This register specifies the number of bits to rotate data and/or the type
of logic operation to perform on data during a CPU write to video memory.

BIT FUNCTION
----------------
7..5 Reserved

4,3 These bits determine the type of logic operation to apply

between the CPU or Data Set/Reset register output before the data
is written to video memory.
00 = Source data unmodified
01 = Source data ANDed with latch data
10 = Source data ORed with latch data
11 = Source data XORed with latch data

2..0 These bits specify the number of bits to rotate data. Data is
rotated to the right.

Data rotation is performed before the logic operation and is done only in
Multiplane Graphics Configuration Write Mode 0. When the data source is
latched data, the logic operation is not applied and latch data is
unmodified.

Graphics Controller Read Plane Select, Port 3CFh, Index 04h, Read/Write

This register determines the bit plane read. This determination occurs by
loading a value into bits <1, 0>, depending on the input conditions (CPU
address line A0 and Graphics Controller mode register odd/even bit <4>).
This register and these input conditions are valid in Read Mode 0 only,
unless bit <3> of Sequencer Memory mode = 1 (chain 4 bits).

BIT FUNCTION
----------------
7..2 Reserved

1,0 Input Conditions

=======================================================
============
Address Result
Plane Chain Line Odd/ (Plane
Select 4 A0 Even Read)
-------------------------------------------------------------------
00 0 XX 0 0
01 0 XX 0 1
10 0 XX 0 2
11 0 XX 0 3
00 0 X0 1 0
01 0 X0 1 0
10 0 X0 1 2
11 0 X0 1 2
00 0 X1 1 1
01 0 X1 1 1
10 0 X1 1 3
11 0 X1 1 3
XX 1 00 X 0
XX 1 01 X 1
XX 1 10 X 2
XX 1 11 X 3
-------------------------------------------------------------------
Legend: X = Don't care

=======================================================
============

Graphics Controller Mode, Port 3CFh, Index 05h, Read/Write

This register defines the current operating modes for the VGC.

BIT FUNCTION
----------------
7 Reserved

6 256-Color Mode
0 = Bit <5> controls shift register loading
1 = Shift registers loaded in 256-color format (8 shift registers x
4 bits)

5 0 = Video output data is serialized and sent to the attribute

controller
1 = Video output data is serialized with even-numbered bits from
even-numbered planes and odd-numbered bits from odd-numbered
planes (Modes 4 and 5 only).

4 Odd/Even Bit
0 = CPU reads data sequentially from the planes
1 = Even CPU addresses access planes 0 and 2. Odd CPU addresses
access planes 1 and 3. Normally, this value is the same as
bit <2> of the Sequencer Memory Mode register.

3 0 = Read Mode 0. The CPU reads the memory plane selected by

the Graphics Controller Read Plane Select register, unless
bit <3> (Chain 4) of the Sequencer Memory Mode register = 1.
1 = Read Mode 1. The CPU reads the results of the comparison
between the Video memory byte and the Graphics Controller Color
Compare register.

2 Reserved

1,0 00 = Write Mode 0. CPU or Data Set/Reset register output is written

to video memory.
01 = Write Mode 1. Latch data is written to video memory.
10 = Write Mode 2. Plane n is filled with data bit <n>.
11 = Write Mode 3. The addressed byte in each plane is filled with
the value of the corresponding bits of the Set/Reset register.
The Enable Set/Reset register has no effect. Rotated CPU data
is ANDed with Bit Mask register.

In Write Modes 0 and 3, the rotate count from the Graphics Controller Data
Rotate register is applied to the CPU data.

The logic function specified in the Data Rotate register is applied to the
data and latches in all write modes except Write Mode 1, in which data is
not affected.

Except in Mode 3, bits not selected by the Graphics Controller Bit Mask
register receive their value from the latches. The latches are loaded when
the CPU performs a video memory read operation.

Setting bit <5> to "1," facilitates the bit packing required by BIOS
Modes 4 and 5 (320 x 200).

Graphics Controller Miscellaneous, Port 3CFh, Index 06h, Read/Write

This register defines some miscellaneous functions of the graphics

controller.

BIT FUNCTION
----------------
7..4 Reserved

3,2 Video RAM address mapping

Starting Memory
Address Size (KB)
--------------------------
00 = A0000h 128
01 = A0000h 64
10 = B0000h 32
11 = B8000h 32

1 0 = CPU address A0 is used as video memory address bit <0>

1 = CPU address A0 is replaced by a higher CPU bit or the page
select bit (bit <5>) from the Control and Status Miscellaneous
Output register.

0 0 = Text mode enabled

1 = Graphics mode enabled

If the video display controller is mapped at A0000h and the video memory
size is 128 Kbytes, no other video display controller board can be in the
system because video memory conflict occurs.

Graphics Controller Color Don't Care, Port 3CFh, Index 07h, Read/Write

This register specifies which planes are ignored during a color comparison
between the Graphics Controller Color Compare register and the value in
video memory. When a plane is ignored, the comparison result is always a
match for that plane.

This register is used only when the graphics controller is in Read Mode 1.

BIT FUNCTION
----------------
7..4 Reserved

3 0 = Plane 3 is ignored
1 = Plane 3 is included in the comparison

2 0 = Plane 2 is ignored
1 = Plane 2 is included in the comparison

1 0 = Plane 1 is ignored
1 = Plane 1 is included in the comparison

0 0 = Plane 0 is ignored
1 = Plane 0 is included in the comparison

Graphics Controller Bit Mask, Port 3CFh, Index 08h, Read/Write

This register contains a mask pattern that determines whether CPU data or
graphics controller latch data is written to video memory.

Any bit rotations or logic operations occur before the masking operation
and before the write to video memory takes place.

Bits set to "0" in this register cause the corresponding graphics

controller latch bit to be written to video memory. This is equivalent to
leaving the bit unchanged. Bits set to "1" in this register allow the
results of the write mode operation (see Graphics mode register, R05) to be
written to memory.

In 256-color packed pixel graphic configurations (mode 2Eh), this register

behaves as a color bit plane mask register and can also be referred to as
the Color Plane Write Mask Register. Each bit corresponds to a color bit
plane in planar view mode. Bits with a value of "1" enable writes; bits
with a value of "0" disable writes to that bit plane.

In Mode 12, the programmer may need to mask certain planes with the VGA bit
mask. It is necessary to set the appropriate bits in the VGA bit mask,
perform a CPU read to load the read latches with video memory data, and
then perform the CPU write. The VGA bit mask then selects between data in
the read latches and CPU data.

However, in Mode 2Eh the CPU read is automatically performed by the

hardware whenever the VGA bit mask is not FFh.

Graphics Controller Read Control, Port 3CFh, Index 41h, Read/Write

This is an 8-bit read/write register.

BIT FUNCTION
----------------
7..3 Reserved

2..0 Selects one of eight bit planes for planar read:

000 = Plane 0
001 = Plane 1
:
111 = Plane 7

Graphics Controller Foreground Color, Port 3CFh, Index 43h, Read/Write

This 8-bit register is used in color-expand write and transparent write

modes. The pixel is written with the content of this register if the
corresponding bit of the CPU data is "1".

Graphics Controller Background Color, Port 3CFh, Index 44h, Read/Write

This 8-bit register is used in color-expand write mode. The pixel is

written with the content of this register when the corresponding bit of the
CPU data is "0".

Raster Operation 3, Port 33C2h, Read/Write

This register specifies the two-operand raster operation for combining

source pixels with destination pixels of plane 3. There is a separate ROP
register for each plane.

BIT FUNCTION
----------------
7..4 Reserved

3 RB3

2 RB2

1 RB1

0 RB0

Table 8-8 shows the result of each operation:

Table 8-8. Raster Operations

==============================================
Raster Operation Register
RRRR
BBBB
3210
----------------------------------------------
0000 0
0001 ! (D+S)
0010 D* ! S
0011 !S
0100 ! D *S
0101 !D
0110 D XOR S
0111 ! (D*S)
1000 D*S
1001 D XNOR S
1010 D
1011 ! D +S
1100 S
1101 ! D +S
1110 D+S
1111 1
----------------------------------------------
Legend: D = Destination (Read Latch)
S = Source (R/L)
! = Not
* = And
+ = Or
==============================================

Raster Operation 2, Port 33C3h, Read/Write

This register specifies the two-operand ROP for combining source pixels
with destination pixels of plane 2. The result of the ROP is the same as
ROP3.

BIT FUNCTION
----------------
7..4 Reserved

3 RB3

2 RB2

1 RB1

0 RB0

The CRT controller is a powerful, programmable, large-scale integrated

circuit, which generates the majority of the signals required to produce a
video display. The programmability of the CRT controller allows it to
operate with a variety of monitors and in different operating modes.

The CRT controller contains internal working registers and counters that
are not accessible by the CPU. The values in the CRT controller's counters
are continually compared with the values written to the indexed registers.
When the counter value matches the value of the indexed register, a signal
or process begins or ends.

Most of the CRT controller registers control the placement of the display
on the screen: centering, number of characters, scanlines, amount of
blanking, and so on.

Some register descriptions give the register contents in terms of a

variable value n. For some registers, you are instructed to subtract a
constant value from the value for n and place the resulting value in the
register. This process is required for proper operation of the CRT
controller.

Table 8-9 lists the CRT Controller registers, their addresses, and their
indexes.

Table 8-9. CRT Controller Registers

=======================================================
====================
Address Register Read/Write
---------------------------------------------------------------------------
3x4h Index R/W

3x5h Data R/W

00h Horizontal Total R/W

01h Horizontal Display End R/W

02h Start Horizontal Blank R/W

03h End Horizontal Blank R/W

04h Start Horizontal Sync (retrace) R/W

05h End Horizontal Sync (retrace) R/W

06h Vertical Total R/W

07h Overflow R/W

08h Preset Row Scan R/W

09h Maximum Scanline R/W

0Ah Cursor Start R/W

0Bh Cursor End R/W

0Ch Start Address High R/W

0Dh Start Address Low R/W

0Eh Cursor Location High R/W

0Fh Cursor Location Low R/W

10h Vertical Sync Start R/W

11h Vertical Sync End R/W

12h Vertical Display End R/W

13h Offset R/W

14h Underline Location R/W

15h Start Vertical Blank R/W

16h End Vertical Blank R/W

17h Mode R/W

18h Line Compare R/W

3CF.42h Overflow Register 1 R/W

=======================================================
====================

CRT Controller Index, Port 3x4h, Read/Write

This register serves as a pointer to the CRT controller's internal

registers. The Index register can be addressed as port 3B4h for the
monochrome mode and as port 3D4h for the color/graphics modes.

BIT FUNCTION
----------------
7,6 Reserved

5 0 (Test bit for IC testing; writable)

4..0 Value indicates destination register of next CRT controller access

The values for bits <4..0> and their associated functions are shown in
Table 8-10.

Table 8-10. CRT Controller Indexes

=======================================================
====================
Index Bits Read/Write Register Function
43210
---------------------------------------------------------------------------
00h 00000 R/W Horizontal Total

01h 00001 R/W Horizontal Display End

02h 00010 R/W Start Horizontal Blank

03h 00011 R/W End Horizontal Blank

04h 00100 R/W Start Horizontal Sync

05h 00101 R/W End Horizontal Sync

06h 00110 R/W Vertical Total

07h 00111 R/W Overflow

08h 01000 R/W Preset Row Scan

09h 01001 R/W Maximum Scanline

---------------------------------------------------------------------------
Index Bits Read/Write Register Function
43210
---------------------------------------------------------------------------
0Ah 01010 R/W Cursor Start

0Bh 01011 R/W Cursor End

0Ch 01100 R/W Start Address High (MSB)

0Dh 01101 R/W Start Address Low (LSB)

0Eh 01110 R/W Cursor Location High (MSB)

0Fh 01111 R/W Cursor Location Low (LSB)

10h 10000 R/W Vertical Sync Start

11h 10001 R/W Vertical Sync End

12h 10010 R/W Vertical Display End

13h 10011 R/W Offset

14h 10100 R/W Underline Location

15h 10101 R/W Start Vertical Blank

16h 10110 R/W End Vertical Blank

17h 10111 R/W Mode Control

18h 11000 R/W Line Compare

---------------------------------------------------------------------------
NOTE: Indexes 19h - 27h may return random values; 28h - 3Fh are always
read back as FFh.
=======================================================
====================

CRT Controller Horizontal Total, Port 3x5h, Index 00h, Read/Write

This register defines the total number of character times in a horizontal

scan interval, including the retrace period. If n is the total number of
character times, the contents of this register should be n - 5.
BIT FUNCTION
----------------
7..0 Total number of character times, (n) minus 5

CRT Controller Horizontal Display End, Port 3x5h, Index 01h, Read/Write

This register determines the duration of the Horizontal Display Enable

signal as the total number of displayed characters. If n is the total
number of character times, the contents of this register should be n - 1.

BIT FUNCTION
----------------
7..0 Total number of character times, (n) minus 1

CRT Controller Start Horizontal Blank, Port 3x5h, Index 02h, Read/Write

This register specifies, in character times, the point where horizontal

blanking begins.

BIT FUNCTION
----------------
7..0 Horizontal blanking begins when these bits equal the value in the
internal horizontal-character counter.

CRT Controller End Horizontal Blank, Port 3x5h, Index 03h, Read/Write

This register specifies, in character times, when horizontal blanking ends;

it also specifies a skew amount for the Display Enable (DE) signal.

BIT FUNCTION
----------------
7 1 (Test bit for IC testing; writable)

6,5 Skew of the DE signal, in character times

00 = 0
01 = 1
10 = 2
11 = 3

4..0 Horizontal blanking ends when these five bits equal the last five
bits of the horizontal-character counter.

The maximum blanking signal width (difference between blank start and end)
is 31 character times.

CRT Controller Start Horizontal Sync, Port 3x5h, Index 04h, Read/Write

This register specifies, in character times, the starting point for the
horizontal sync period. This register centers the display horizontally by
changing the horizontal sync position.

BIT FUNCTION
----------------
7..0 Horizontal sync period begins when these bits equal the value in
the internal horizontal-character counter.
CRT Controller End Horizontal Sync, Port 3x5h, Index 05h, Read/Write

This register specifies, in character times, the point where the horizontal
sync period ends, and a skew amount for the horizontal sync signal.

BIT FUNCTION
----------------
7 Bit <5> of End Horizontal Blank (other five bits in R03)

6,5 Horizontal sync delay

00 = 0
01 = 1
10 = 2
11 = 3

4..0 The horizontal sync period ends when these five bits equal the
last five bits of the horizontal-character counter.

CRT Controller Vertical Total, Port 3x5h, Index 06h, Read/Write

This register contains the eight least-significant bits of the 10-bit total
number of horizontal scans in a vertical interval (display plus retrace).
Bits <8, 9> are defined in the CRT Controller Overflow register. The value
loaded into this register is n - 2, where n is the total number of
horizontal scanlines.

BIT FUNCTION
----------------
7..0 Eight least-significant bits of total vertical scanline counter

CRT Controller Overflow, Port 3x5h, Index 07h, Read/Write

This register contains bit <8>, or bit <8> and bit <9>, the
most-significant bits of other CRT Controller registers.

BIT FUNCTION
----------------
7 Bit <9> of the Start Vertical Sync register R10

6 Bit <9> of the End Vertical Display register R12

5 Bit <9> of the Vertical Total register R06

4 Bit <8> of the Line Compare register R18

Bit <9> located in Max. Scanline register R09

3 Bit <8> of the Start Vertical Blank register R15

Bit <9> located in Max. Scanline register R09

2 Bit <8> of the Start Vertical Sync register R10

1 Bit <8> of the End Vertical Display register R12

0 Bit <8> of the Vertical Total register R06

CRT Controller Preset Row Scan, Port 3x5h, Index 08h, Read/Write

This register specifies the first displayed scanline after a vertical

retrace.

BIT FUNCTION
----------------
7 Reserved

6,5 Byte Panning Control

4..0 The scanline counter is loaded with this value when Display Enable
becomes active.

This register can be used to implement smooth pixel scrolling in the

vertical direction. The maximum preset row scan is limited to 31 pixels
(five bits). This value should not exceed the maximum scanline value, or
unpredictable results may occur.

NOTE: The value in the Preset Row Scan register is latched in the CRT
controller at the start of vertical retrace. Therefore, this register
should be updated by software prior to the start of the vertical
retrace period.

In multiple shift modes, the Byte Panning Control bits are extensions of
pixel panning functions. This allows panning across the width of the video
in larger increments.

CRT Controller Maximum Scanline, Port 3x5h, Index 09h, Read/Write

This register defines the number of scanlines per character. If n equals

the number of scanlines per character, load this register with n - 1.

BIT FUNCTION
----------------
7 Line double bit for 200 - 400 line conversions
0 = Normal, HS = Row scanline counter clock
1 = Line double, row scan count clock = HS/2

6 Bit <9> of the Line Compare register R18

Bit <8> located in Overflow register R07

5 Bit <9> of the Start Vertical Blank register R15

Bit <8> located in Overflow register R07

4..0 Number of scanlines per character n minus 1

Character height is limited to 32 scanlines.

CRT Controller Cursor Start, Port 3x5h, Index 0Ah, Read/Write

This register defines the starting scanline for the cursor. If the starting
scanline exceeds the maximum scanline, the cursor is invisible.
BIT FUNCTION
----------------
7,6 Reserved

5 Cursor Enable
1 = Cursor OFF
0 = Cursor ON

4..0 To start on scanline n, set to n - 1

If starting after the end, no cursor is generated.

CRT Controller Cursor End, Port 3x5h, Index 0Bh, Read/Write

This register specifies the last scanline for the cursor and a skew amount
for the cursor signal. If n equals the ending scanline value for the
cursor, load bits <4..0> of the Cursor End register with n + 1. When n + 1
exceeds the maximum scanline (as defined in the Maximum Scanline register),
and the starting scanline value is non-zero, load bits <4..0> with zero.

BIT FUNCTION
----------------
7 Reserved

6,5 Skew of the cursor signal, in character times

00 = 0
01 = 1
10 = 2
11 = 3

4..0 The cursor ends when these five bits equal the n character scanline
counter.

CRT Controller Start Address High, Port 3x5h, Index 0Ch, Read/Write

This register specifies the eight most significant bits of the 16-bit
starting address of displayed video memory. The eight least significant
bits are stored in the Start Address Low register, Index 0Dh (see NOTE).

BIT FUNCTION
----------------
7..0 Most significant byte of video memory start address

NOTE: The values in the Start Address High and Start Address Low registers
are latched in the CRT controller at the end of vertical retrace.
Therefore, these registers should be updated by software prior to the
end of the vertical retrace period.

CRT Controller Start Address Low, Port 3x5h, Index 0Dh, Read/Write

This register specifies the eight least significant bits of the 16-bit
starting address of displayed video memory. The eight most significant bits
are stored in the Start Address High register, Index 0Ch (see NOTE).

BIT FUNCTION
----------------
7..0 Least significant byte of video memory start address

CRT Controller Cursor Location High, Port 3x5h, Index 0Eh, Read/Write

This register defines the eight most significant bits of the 16-bit video
memory address for the cursor. The eight least significant bits of this
register are in the Cursor Location Low register, Index 0Fh.

BIT FUNCTION
----------------
7..0 Most significant byte of the cursor video memory address

CRT Controller Cursor Location Low, Port 3x5h, Index 0Fh, Read/Write

This register defines the eight least significant bits of the 16-bit video
memory address for the cursor. The eight most significant bits of this
register are in the Cursor Location High register, Index 0Eh.

BIT FUNCTION
----------------
7..0 Least significant byte of the cursor video memory address

CRT Controller Vertical Sync Start, Port 3x5h, Index 10h, Read/Write

This register contains the eight least significant bits of the 10-bit value
that specifies the starting scanline for the vertical sync period.

This value can be used to center the screen vertically by changing the
vertical sync position. Bits <8> and <9> of this value are located in the
Overflow register R07.

BIT FUNCTION
----------------
7..0 The vertical sync period begins when the 10-bit Vertical Sync start
address bits equal the last 10 bits of the scanline counter.

CRT Controller Vertical Sync End, Port 3x5h, Index 11h, Read/Write

This register contains the 4-bit value that specifies the ending scanline
for the vertical sync period.

Vertical interrupts occur at the start of the vertical-blanking period, not

the start of the vertical-sync period. Vertical interrupts do not actually
occur, but a status bit is available in Status 0 register, to indicate a
vertical sync has occurred.

BIT FUNCTION
----------------
7 Protect R00 through R07
0 = Enable write access to R0 through R7
1 = Write protect R0 through R7

Special Case: R7 bit <4> overflow of line compare R18 is not

protected

6 Select 5 Refresh Cycles

0 = 3 cycles (Normal VGA) per scanline
1 = 5 cycles per scanline

Reset to normal VGA by BIOS during mode set or by power reset

5 0 = Vertical interrupt enabled

1 = Vertical interrupt disabled

4 0 = Resets the CRT controller interrupt bit in Status 0 register

1 = Normal condition; interrupts can occur if enabled in bit <5>

3..0 The vertical sync period ends when this 4-bit value equals the four
LSBs of the scanline counter after VS has started.

When bits <4> and <5> are being changed, the other bits should not be
changed.

CRT Controller Vertical Display End, Port 3x5h, Index 12h, Read/Write

This register contains the eight least significant bits of the 10-bit value
that specifies the total number of displayed scanlines. If n equals the
total number of displayed scanlines, load this register with n - 1.

Bits <8> and <9> are stored in the Overflow register.

BIT FUNCTION
----------------
7..0 Eight least significant bits of 10-bit value

CRT Controller Offset, Port 3x5h, Index 13h, Read/Write

This register defines the logical line width or logical window size. The
starting memory address for the next displayable row, character, or
scanline is greater than the current row address by this amount. The value
is in words or double-words (dword), based on the CRT clocking mode. This
register is used in conjunction with the Horizontal Panning registers to
provide smooth panning.

BIT FUNCTION
----------------
7..0 Value specifies logical window width

CRT Controller Underline Location, Port 3x5h, Index 14h, Read/Write

This register specifies which character scanline is used for underlining,

which is active in all text modes. When the character scanline specified
for underlining is set to a value greater than the maximum scanline, no
underline occurs.
BIT FUNCTION
----------------
7 Reserved

6 Double-word mode
0 = Addressing controlled by bit <6> of R17
1 = Memory addresses or double-word addresses, causes address to be
divided by four, and overrides bit <6> of R17

5 Count by four
0 = Memory address counter is clocked by character clock
1 = Memory address counter is clocked by character clock/4.
Use only when double-word address is used.

4..0 Value specifies which character scanline is used for the underline.

CRT Controller Start Vertical Blank, Port 3x5h, Index 15h, Read/Write

This register contains the eight least significant bits of the 10-bit Start
Vertical Blank value. Bit <8> is stored in the Overflow register. Vertical
blanking begins when the 10-bit value is one less than the last 10 bits of
the scanline counter. Bit <9> is located in the Maximum Scanline register
(Port 3x5h, Index 09h).

BIT FUNCTION
----------------
7..0 Eight least significant bits of 10-bit Start Vertical Blank value.
It is loaded with n - 1, where n is the Start Vertical Blank value.

CRT Controller End Vertical Blank, Port 3x5h, Index 16h, Read/Write

This register specifies the ending scanline of the vertical blanking

period.

BIT FUNCTION
----------------
7..0 The vertical blanking period ends when these bits coincide with the
eight least significant bits of the scanline counter.

CRT Controller Mode Control, Port 3x5h, Index 17h, Read/Write

This register defines various CRT controller operating modes.

BIT FUNCTION
----------------
7 0 = Horizontal and vertical syncs are disabled
1 = Horizontal and vertical syncs are enabled

6 Word/byte mode select controls the memory addressing mode

0 = Selects word mode, shifts all memory addresses up by one and
replaces bit <0> with MSB
1 = Selects byte addressing mode and addressing is passed through;
this bit has control only when bit <6> of R14 = "0"
5 Address wrap controls address bit <0> in word mode
0 = Selects address bit <13> as LSB (if not in word mode, MA0
through MSB)
1 = Selects address bit <15> as LSB

4 Reserved

3 0 = Display memory address increments once per character clock

pulse
1 = Display memory address increments after every other character
clock pulse; used to create byte or word refresh address

2 0 = Vertical timing counter increments once per horizontal sync

pulse (normal)
1 = Vertical timing counter increments after every other horizontal
sync pulse; Vertical Counter has 1024 scanline capability
(10 bits in Vertical total); this bit allows up to 2048
scanlines

1 0 = Substitute address bit <1> for bit <14> during active display
cycles
1 = No substitution

0 0 = Substitute address bit <0> for bit <13> during active display
cycles
1 = No substitution

CRT Controller Line Compare, Port 3x5h, Index 18h, Read/Write

This register contains the eight least-significant bits of a 10-bit value

that specifies a scanline count where the video memory address is to be
reset to zero. This register generates horizontally split screens (windows)
on the display.

For normal non-split display, this 10-bit value should be set to its
maximum (3FFh). Bit <8> of this register is located in the Overflow
register. Bit <9> is in the Maximum Scanline register, (Port 3x5h,
Index 09h).

BIT FUNCTION
----------------
7..0 Eight least significant bits of the 10-bit scanline compare value

CRT Controller Overflow Register 1, Port 3CFh, Index 42h, Read/Write

This 8-bit register extends the CRTC offset and CRTC start address VGA
registers so that up to 1 megabyte of video memory can be addressed. The
bits are defined as shown below.

BIT FUNCTION
----------------
7..4 Reserved

3,2 Extended bits 17-16 of the CRTC Start Address Register. Allows
paging through the entire frame buffer. Cleared by resetting the
Sequencer to be compatible with standard VGA modes.

1,0 Extended bits 9-8 of the CRTC Offset Register. Allows the line
pitch to be set to 1024 bytes. Cleared by resetting the Sequencer
to be compatible with standard VGA modes.

Attribute Controller Registers

The Attribute Controller Index and Data registers are accessed through a
single port, 3C0h. An internal latch in the attribute controller determines
whether the Index register or the Data register is being accessed. Accesses
to this port alternate on output to 3C0h between the Index and Data
registers. Before accessing port 3C0h, reset the internal latch to a known
state by reading port 3xAh (Input Status 1 register). The first write to
the attribute controller is to the Index register.

NOTE: Reads from port 3C1h do not toggle the latch to point back to the
Index register for the next write. Therefore, the sequence for
reading attribute controller registers sequentially is as follows:

Read 3xAh: reset the latch

Write 3C0h: load the Index register, toggle the latch
Read 3C1h: read the data
Read 3xAh: reset
Write 3C0h: load.....
: read.....
etc....

Table 8-11 lists the Attribute Controller registers, their addresses and
their indexes. The data register value can be read from port 3C1h.

Table 8-11. Attribute Controller Registers

====================================================
Address Register Read/Write
----------------------------------------------------
3C0h Index R/W

3C0h Data W

00h Palette 0 W

01h Palette 1 W

02h Palette 2 W

03h Palette 3 W

04h Palette 4 W

05h Palette 5 W

06h Palette 6 W

07h Palette 7 W
08h Palette 8 W

09h Palette 9 W

0Ah Palette 10 W

0Bh Palette 11 W

0Ch Palette 12 W

0Dh Palette 13 W

0Eh Palette 14 W

0Fh Palette 15 W

10h Mode Control W

11h Overscan Color W

12h Color Plane Enable W

13h Horizontal Pixel Panning W

14h Color Select W

====================================================

Attribute Controller Index, Port 3C0h, Read/Write

This is an Index register that points to other Attribute Controller

registers.

If the Palette registers are accessed by the system, all the color outputs
go to zero, thereby blanking the display.

BIT FUNCTION
----------------
7,6 00 Reserved

5 0 = CPU has access to the Palette registers (Video OFF).

1 = Attribute controller has access to the Palette registers (Video
ON). (This bit should only be changed during retrace time. If
this bit is a "1," the Palette registers cannot be read.)

4..0 Value points to destination Attribute Controller Registers

Index Value Register Function

--------------------------------------
00h Palette 0
. .
. .
0Fh Palette 15
10h Mode Control
11h Overscan Color
12h Color Plane Enable
13h Horizontal Pixel Panning
14h Color Select
15h..1Fh Reserved

Video can be switched to OVERSCAN colors by manipulating bit <5>.

Attribute Controller Palette 0..15, Port 3C0h, Index 00h..0Fh, Write Only
(Read at 3C1h)

This palette is included for compatibility with software written for the
EGA and its monitors. For full-range control of colors, alter the Color
Select register and Color Lookup Table.

Sixteen 6-bit registers compose the color palette. Each register specifies
which color (or monochrome intensity) is to be displayed for a given
attribute or color code. Depending on the operating mode, the Palette
register bits can specify one of 64 colors in an enhanced color (RrGgBb)
mode, one of 16 colors in an RGBI color mode, or one of three intensities
in a monochrome mode.

The Palette registers should be modified only during blanking periods to

avoid video noise, or "glitches" in the display.

BIT FUNCTION
----------------
7,6 P6/P7 Reserved
EGA Operating Mode
-----------------------------------------------
Enhanced RGBI Monochrome
Color Color
-----------------------------------------------
5 Secondary Red P5 0 0

4 Secondary Green P4 Intensity Intensity

3 Secondary Blue P3 0 Video

2 Primary Red P2 Red 0

1 Primary Green P1 Green 0

0 Primary Blue P0 Blue 0

Attribute Controller Mode Control, Port 3C0h, Index 10h, Read/Write

This register defines various attribute controller operating modes.

In the text modes, the intensity/blink select bit changes the meaning of
bit <7> of the character-attribute byte, so that bit <7> is either the
background intensity bit or the blink bit.

In the graphics modes, the intensity/blink select bit changes the meaning
of bit <3>, so that it is either part of the color information or the blink
bit.
The blink rate is fixed at 32 vertical periods.

BIT FUNCTION
----------------
7 P4, P5 Select
0 = Palette
1 = Color Select register, R14h, bits <0> and <1>

6 Pixel Width
0 = All modes except mode 13
1 = Mode 13; eight bits to VDAC for 256-color mode

5 Pixel Panning Compatibility

0 = Line compare has no effect on Pixel Panning
1 = Successful line compare causes Pixel Panning to terminate until
next vertical sync

4 Reserved, Read only

3 Intensity/Blink Bit
In the Text mode (background)
0 = Intensity attribute selected
1 = Blink attribute selected

In the Graphics mode

0 = Color attribute selected
1 = Blink attribute selected

2 In the 9-dot mode

0 = 9th dot matches background
1 = 9th dot is duplicate of 8th dot for ASCII codes C0h..DFh

1 0 = Attribute byte interpreted as color attributes

1 = Attribute byte interpreted as monochrome attributes

0 0 = Attribute controller treats data as text

1 = Attribute controller treats data as graphics

Attribute Controller Overscan Color, Port 3C0h, Index 11h, Write Only (Read
at 3C1h)

This register defines a border or overscan color by selecting one of the

256-color Lookup Table registers that contain the R, G, and B values for
that color.

This feature is not supported in 40-column text or 320-pixel Graphics

modes, except Mode 13.

BIT FUNCTION
----------------
7..0 Color code (00h..FFh)

Attribute Controller Color Plane Enable, Port 3C0h, Index 12h, Write Only
(Read at 3C1h)
This register controls access to the color planes and selects which color
planes are read from Input Status 1 register.

If bit <4> of this register is set, all six color outputs are high
impedance (all white video); however, the values gated to Input Status 1
register will be correct, because they are gated before the high-impedance
buffers.

The values loaded into Input Status 1 register are gated after the blanking
logic; during a blanking period the gated values are blanked (reset to
zero) also.

BIT FUNCTION
----------------
7,6 Reserved

This register specifies the number of pixels by which the display is to be

shifted to the left in any display mode. This is not a wraparound shift. In
the 256-color mode, maximum shift is three pixels.

BIT FUNCTION
----------------
7..4 Reserved
3..0 Values range from 0 to 7 for 8-dot display modes and from 0 to 8
for 9-dot modes.

8-Dot 9-Dot
Mode Mode Mode 13
--------------------------------
Pixels Pixels Pixels
Value Shifted Shifted Shifted
0 0 1 0
1 1 2 -
2 2 3 1
3 3 4 -
4 4 5 2
5 5 6 -
6 6 7 3
7 7 8 -
8 - 0 -

The Horizontal Pixel Panning register should be updated only during the
vertical retrace period.

Attribute Controller Color Select, Port 3C0h, Index 14h, Write Only (Read
at 3C1h)

This register allows rapid color switching by applying additional color

selection bits to the VDAC.

BIT FUNCTION
----------------
7..4 Reserved

3, 2 P7, P6
These are the two high-order bits to the VDAC (P6, P7) except in
Mode 13. They allow switching between four sets of palettes.

1 P5 substitute
Refer to bit <7> of the Attribute Mode Control register. They (P4
and P5) allow rapid color switching.

0 P4 substitute

In all modes except 13, there are two high-order bits (P6, P7) to the VDAC.
These bits allow four sets of palettes.

Bits <0> and <1> substitute for P4 and P5 (see Attribute Mode Control
register R10h, bit <7>). They allow rapid color switching, especially with
16-color CGA applications.

Video DAC Registers

The Video DAC provides analog RGB signal capability, allowing up to 224
possible color combinations to be displayed on an analog RGB monitor. The
Video DAC registers provide three functions to be performed on the Video
DAC palette: reading the palette, writing to the palette, and masking the
palette. Table 8-14 lists the VDAC registers and their addresses.

Table 8-12. Video DAC Registers

=======================================================
====================
Address Register Read/Write
---------------------------------------------------------------------------
3C6h Pixel Mask R/W

3C7h VDAC State R

3C7h Pixel Address (Read Mode) W

3C8h Pixel Address (Write Mode) R/W

3C9h Pixel Data R/W

83C6h DAC Command Register 0 R/W

=======================================================
====================

The Video DAC State register (3C7h Read) is not a function of the video DAC
chip; it is an extra function provided by the VGC circuitry.

For compatibility with EGA modes, the first 16-palette map locations
produce EGA-compatible colors. The next 16-palette map locations produce 16
evenly spaced gray shades. The rest of the palette is loaded with colors
based on a hue-saturation-intensity model which provides a wide range of
generic color sets.

Writes to video DAC at 3C8h indicate that a write sequence will occur,
consisting of three successive writes at 3C9h: six (or 8) LSBs of red, then
of green, then of blue. Video DAC then transfers 18 (or 24) bits to a
location in the palette pointed to by the Address register. The Address
register auto-incrementing can repeat if desired.

Writes to video DAC at 3C7h indicate that a read sequence will occur,
consisting of three successive reads at 3C9h: six (or 8) LSBs of red, then
of green, then of blue. Video DAC then transfers 18 (or 24) bits to a
temporary Read register pointed to by the Address register. The Address
register auto-incrementing can repeat if desired.

Read at 3C7h

Bits <0> and <1> = 0 (DAC in read mode)

Bits <0> and <1> = 1 (DAC in write mode)

Reading at 3C8h or 3C7h has no effect on video DAC operations and may occur
at any time.

Normal Video Palette Accessing

The unit may first need to be disabled, in case any concurrently running
programs change the state of the video DAC.
1. Disable interrupts
2. Set 6- or 8-bit DAC Mode
3. Address --> Address register at 3C8h
4. Read or write 3 bytes of data at 3C9h
5. Repeat process as desired
6. Enable interrupts

When writing to the Palette registers, it is recommended that you wait for
assertion BLANK to DAC retrace interval (Input Status 1 register) or screen
off bit (Sequencer Clock Mode R01). Note that BIOS provides Read/Write
interfaces to the video DAC. Writing to Mask registers may cause corruption
of palette data.

External Palette (in Video DAC)

The first 16 locations are compatible with the other modes (that is, are
not changed). The second 16 locations are 16 evenly spaced gray shades. The
next 216 locations are loaded based on a hue-saturation-intensity model,
which provides a wide-range generic color set.

Video DAC Pixel Mask, Port 3C6h, Read/Write

The Pixel Mask register is used to mask selected bits of the Pixel Address
value applied to the Pixel Address input. A "0" in any bit of the Mask
register will mask the respective address bit to a zero, while a "1" will
leave the bit unaltered. This register does not affect the Pixel Address
generated by the microprocessor interface when the Lookup Table is being
accessed.

BIT FUNCTION
----------------
7..0 Pixel Address Mask
0 = Address bit masked to 0
1 = Address bit unaltered

Video DAC State, Port 3C7h, Read

The Video DAC State register is an extension of the Video DAC feature. It
provides status information on the current Video DAC read or write state.

BIT FUNCTION
----------------
7..2 Reserved

1,0 State Status

00 = Currently in Write mode
11 = Currently in Read mode

Video DAC Pixel Address (Read Mode), Port 3C7h, Write

Writing to the Video DAC Pixel Address (Read mode) will initiate a read
cycle from the address value written. The next three read operations from
the Video DAC Data register will contain the 18-bit (or 24-bit) data from
the Color Palette. (Refer to the Video DAC Data register for details.)
After the three data bytes are read, the palette address will increment,
and the next three bytes of palette data can be read.

BIT FUNCTION
----------------
7..0 Palette address where data is to be read

Video DAC Pixel Address (Write Mode), Port 3C8h, Read/Write

Writing to the Video DAC Pixel Address (Write mode) will initiate a write
cycle to the address value written. The next three write operations to the
Video DAC Data register will contain the 18-bit (or 24-bit) data to the
Color Palette. (Refer to the Video DAC Data register for details.) After
the three data bytes are written, the palette address will increment, and
the next three bytes of palette data can be written.

Reading this register will provide the current palette address being read
from or written to.

BIT FUNCTION
----------------
7..0 Palette address where data is to be written

Video DAC Pixel Data, Port 3C9h, Read/Write

The Video DAC Pixel Data register is used to read or write 18 (or 24) bits
of palette data, depending on the mode of operation. The mode of operation
is determined by a previous write to the Read Mode Pixel Address or the
Write Mode Pixel Address. Data access to and from this register is in
groups of three bytes. The first byte contains the value for the red
signal, the second byte for the green signal, and the third byte for the
blue signal. Only the six least-significant bits (in 6-bit DAC mode)
contain data for each byte access. In 8-bit DAC mode, all 8 bits are used
for pixel data.

BIT FUNCTION
----------------
7,6 Reserved

5..0 Palette Data

First of the sequence = Red data
Second of the sequence = Green data
Third of the sequence = Blue data

DAC Command Register 0, Port 83C6h, Read/Write

The Video DAC Command Register at address 83C6h is used to select 6-/8-bit
mode. The appropriate settings are indicated below.

BIT FUNCTION
----------------
7..2 Reserved

1 6-/8-bit mode select:

0 = 6-bit color mode (218 Palette)
1 = 8-bit color mode (224 Palette)

0 Reserved

In switching between 6-bit and 8-bit modes, the Video DAC Command Register
must be read first, bit 1 modified as desired, and then the new register
contents written back to the register. This preserves the other bit
settings of the Command Register. Switching to VGA modes other than
mode 2Eh (through BIOS) causes this bit to be reset to 0.

Bit Block Transfer Registers

Table 8-13 summarizes the Bit Block Transfer Registers.

Table 8-13. Bit Block Transfer Registers

23C2h Bitmap Width (8-Bit) Register R/W

23C4,5h Bitmap Height (10-Bit) Register R/W

23C8,9h Bitmap Height Working 10-Bit Register R

23CA,Bh Bitmap Pitch (16-Bit) Register R/W

23CC,Dh Bitmap Destination Off (16-Bit) Register R/W

33C0h BLT Start Mask (8-Bit) Register R/W

33C1h BLT End Mask (8-Bit) Register R/W

33C8h BLT Rotation (3-Bit) Register R/W

33C9h BLT Skew Mask (8-Bit) Register R/W

33CAh Plane 0 (8-Bit) Register R/W

33CBh Plane 1 (8-Bit) Register R/W

33CCh Plane 2 (8-Bit) Register R/W

33CDh Plane 3 (8-Bit) Register R/W

33CEh BLT Command 0 (8-Bit) Register R/W

33CFh BLT Command 1 (8-Bit) Register R/W

=======================================================
====================

BitBLT Register Definitions

BLT Source Address, Port 23C0,1h, Read/Write

This is the low 16 bits of the dword address of the beginning of the source
bitmap. The high order 2 bits are in BitBLT Height Register bits[15,14].

For Mode 12: This register contains the byte address for the beginning of
the source bitmap.

NOTE: This register is modified by the execution of a screen to screen

copy.

BIT FUNCTION
----------------
15..0 Address of source bitmap

Bitmap Width, Port 23C2h, Read/Write

This register contains the bitmap width in number of dwords.

For Mode 12: This register contains the width of the bitmap, in bytes,
along a scan line.

NOTE: This register is not modified by the execution of any BitBLT

operation.

BIT FUNCTION
----------------
15..0 Destination bitmap width

Bitmap Height, Port 23C4,5h, Read/Write

This is the height, in scan lines, of both the source and destination
bitmap. For Mode 2Eh, the six most significant bits are the high bits of
the source address, destination address, and bitmap pitch, respectively.

NOTE: This register is not modified by the execution of a screen-to-screen

copy.

BIT FUNCTION
----------------
15,14 Mode 2Eh: Bit 16, 17 of BitBLT source address
Mode 12: Reserved

13,12 Mode 2Eh: Bit 16, 17 of BitBLT destination offset

Mode 12: Reserved

11,10 Mode 2Eh: Bit 16, 17 of Bitmap pitch

Mode 12: Reserved

9..0 Mode 2Eh

Bitmap Height Working, Port 23C8,9h, Read Only

This register contains the number of scanlines remaining in the current

BLT.
BIT FUNCTION
----------------
15..10 Reserved

9..0 Number of scanlines in BLT

Bitmap Pitch, Port 23CA,Bh, Read/Write

This is the low 16 bits of the bitmap pitch in dwords (dword-aligned). The
high order 2 bits are in BitBLT Height Register bits[11,10]. The bitmap
pitch is equal to the number of dwords from the beginning of one scan line
to the beginning of the next scan line. This pitch can be programmed to
cause the address to wrap, which effectively causes the direction of the
BLT to go up the screen instead of down.

This is a twos complement value. Negative values cause the BLT direction to
proceed up the screen.

This register contains the bitmap pitch in bytes for Mode 12. The value is
represented within the full 16 bits of the register.

NOTE: This register is not modified by the execution of a screen-to-screen

copy.

BIT FUNCTION
----------------
15..0 Bitmap pitch

Bitmap Destination Off, Port 23CC,Dh, Read/Write

This is the low 16 bits of the 18-bit twos complement destination offset
value. This register is programmed with the number of dwords from the
dword-aligned source start byte address to the dword-aligned destination
start byte address. The high order 2 bits are in BitBLT Height Register
bits [13,12].

For Mode 12: This register contains the byte offset from the beginning of
the source address to the destination bitmap.

NOTE: This register is not modified by the execution of a screen-to-screen

copy.

BIT FUNCTION
----------------
15..0 Offset to destination bitmap

BLT Start Mask, Port 33C0h, Read/Write

The four least significant bits serve as a byte mask for the first dword of
the BitBLT transferred.

For Mode 12: Pixel mask for first byte transferred. Only those specified
pixels are modified in the first destination byte written for each scan
line.
BIT FUNCTION
----------------
7..0 Mode 12:
Pixel mask for first byte
1 = Byte in destination modified
0 = Byte in destination unmodified

7..4 Mode 2Eh: Reserved

3..0 Mode 2Eh: Byte mask for first double word.

1 = Byte in destination modified
0 = Byte in destination unmodified

BLT End Mask, Port 33C1h, Read/Write

The four least significant bits serve as a byte mask for the last dword of
the BitBLT transferred.

For Mode 12: Pixel mask for last byte transferred. Only those specified
pixels are modified in the last destination byte written for each scan
line.

BIT FUNCTION
----------------
7..0 Mode 12
Pixel mask for last byte
1 = Bits in destination modified
0 = Bits in destination unmodified

7..4 Mode 2Eh: Reserved

3..0 Mode 2Eh: Byte mask for last double word.

1 = Byte in destination modified
0 = Byte in destination unmodified

BLT Rotation, (3-Bit) Port 33C8h, Read/Write

This register provides phase alignment between the byte address of the
source and the byte address of the destination. For both Modes 2Eh and 12,
these three bits are the same bits as the least-significant bits located in
the current VGA register 3CF.03. This is programmed with a value of:

4 - ((source byte start address - dest byte start address)&3)

For Mode 12: Phase alignment between the bit address of the source and the
bit address of the destination, modulo 8. The value of this register is
equal to (8 - ((SRCX-DESX)&7))&7.

BLT Skew Mask, (8-Bit) Port 33C9h, Read/Write

The four least significant bits select current or previous source data. A
"0" selects a current byte; a "1" selects a previous byte (of the four
current bytes and four previous bytes source read).
For Mode 12: This register does a bit-by-bit select between the current and
previous source data. A "0" selects current data, while a "1" selects
previous data.

Plane (PReg0, PReg1, PReg2, PReg3) Registers, Ports 33CAh, 33CBh, 33CCh,
33CDh, Read/Write

There are two sets of PReg0, PReg1, PReg2, PReg3. One is the primary set
and the other is the secondary set. The two sets are located at 33CA, 33CB,
33CC, 33CD. Writing to these I/O locations results in the secondary set
being loaded with previous values of the primary set and the primary set
being loaded with the values programmed (providing that the source MUX
selection SMX[3..0] is programmed with zeros).

Only the primary set is accessed directly by the CPU. During the BitBLT
process, the BLT engine alternately selects these two sets for pattern fill
BLTs. The primary set is selected for the first memory transfer of a scan
line. This way, a full eight 8-bit pixel pattern can be implemented using
the BitBLT engine. Note that the secondary set is physically the same as
the previous source data latches. (See the advanced VGC BitBLT engine block
diagram for details.) As a result, their contents are destroyed after a
screen-to-screen BLT.

For Mode 12: These registers are used to store the source data for Plane n
during screen-to-screen copies. During block fills, this register is loaded
with the pattern that is block transferred to Plane n.

BLT Command 0, Port 33CEh, Read/Write

This register contains part of the control codes for the current engine
operation.

BIT FUNCTION
----------------
7 Reserved. Must write zeros.

6 HORIZONTAL DIRECTION (HDIR)

When set to a "1", the BLT engine decrements to the next address,
effectively blocking transferring from right to left and up,
instead of left to right and down.

5 BYTE SWAP (BSW)

When set to a "1", both reads and writes from the CPU are byte
swapped.

4 SKIP DESTINATION (SKD)

When set to a "1", tells the BLT engine that the destination bytes
are not needed except for the fringe areas. This would normally be
set for any operation that does not require any ROP function with
the destination (ROP = 1100).

3 SKIP SOURCE (SKS)

When set to a "1", tells the BLT engine that the source byte(s) are
not needed. This would normally be used for a pattern fill.
2 SKIP LAST (SKL)
When set to a "1" tells the BLT engine that the last source read is
not needed. Conversely, a "0" means the last source byte is needed.

1 PRELOAD (PL)
When set to a "1" tells the BLT engine that it should read two
source bytes before doing a destination write. When set to a "0",
only one source read is needed before a destination write can
begin.

0 START/STOP (SS)
When programmed to a "1", this causes the currently defined BLT to
start. This bit is also the status of the current operation. It
will be reset by the control engine back to a "0" when the current
operation is finished. Programming this bit to a "0" will cause the
BLT engine to halt at the next scanline, with this bit going to a
"0" when that state has been reached.

BLT Command 1, Port 33CFh, Read/Write

This register contains part of the control codes for the current engine
data path configuration.

BIT FUNCTION
----------------
7,6 Reserved. Must write zeros.

5 DISABLE SET/RESET REGISTERS (DSR)

A one in this bit disables the Set/Reset logic of the current VGA
Enable Set/Reset and Set/Reset registers.

4 RASTER OPERATION ENABLE (ROPE)

A zero selects normal VGA source modification (Pass-Through, AND,
OR, XOR). A one selects the ROP as described in the Raster
Operations register.

3..0 SOURCE MULTIPLEXER SELECT BITS (SMX)

The source data for each plane can come from several sources: from
any of the four Source Latches, the output of the Color Compare
Logic, or from the CPU. The source is selected according to the
table below.

Table 8-14. Source Data Selection

=======================================================
====================
SMX3 SMX2 SMX1 SMX0 Source Destination Plane
BIT BIT BIT BIT 3 2 1 0
---------------------------------------------------------------------------
0 x x x Src Latch 3 2 1 0
1 0 0 0 Src Latch 0 0 0 0
1 0 0 1 Src Latch 1 1 1 1
1 0 1 0 Src Latch 2 2 2 2
1 0 1 1 Src Latch 3 3 3 3
1 1 x 0 Color Compare CC CC CC CC
1 1 x 1 CPU Latch CP CP CP CP
---------------------------------------------------------------------------
Legend: x = Don't Care
CC = Color Compare Result
CP = CPU Data
=======================================================
====================

COMPAQ-Specific Registers

This section describes video-related I/O mapped registers that are specific
to the COMPAQ LTE Lite Family.

Table 8-15. COMPAQ-Specific Registers

03C6h Graphics Index Register R

03CF.09h Gray Scale RAM Address Reg. W

03CF.0Ah Gray Scale RAM Data Reg. R/W

83C6h RAMDAC Command Register R/W

=======================================================
====================

Screen Save Timeout Register, Port 0x27C6, Read/Write

The Screen Save Timeout register is an 8-bit register that controls how
long AVG circuitry will wait in the absence of system activity before
blanking the CRT or powering down the panels. The Timeout Occurred bit goes
active (1) if an event does not happen in time.

BIT FUNCTION
----------------
7 Timeout occurred (read only)

6 Reserved (1)

5..0 Timeout in minutes:

000000 = Disabled
000001 = 1 minute
000010 = 2 minutes
.
.
111111 = 63 minutes

AVG circuitry Mode Register, Port 0x03CF:80, Read/Write

This 7-bit register controls the type of panel/CRT combination that AVG
circuitry will use to display video. It should be written at system
configuration time to identify the panel type and mode of operation.
BIT FUNCTION
----------------
6 Eliminate 7<->5

5,4 Modulation

3,2 Panel Type:

00 = Reserved
01 = Monochrome LCD
10 = Black and white TFT LCD
11 = Color TFT LCD

1 LCD Power On:

0 = LCD is not powered
1 = LCD is powered

0 Panel Active:
0 = CRT display only
1 = LCD and/or CRT

DAC Control Register, Port 03CF.81, Read/Write

This 8-bit register controls certain functions in the gray scale

conversion, the AVG circuitry palette RAM and the TFT modulation logic.

BIT FUNCTION
----------------
7 Color Round:
0 = Not to round (default)
1 = Output of the gray scale logic and input to the TFT processor
are rounded toward positive infinity instead of being
truncated.

6 Color Resolve:
0 = Not to resolve (default)
1 = Slightly non-zero output of the palette that normally would be
truncated to produce black is mapped instead to produce the
lowest color value.

5 Palette Coherency:
0 = Coherency disabled
1 = Palette RAM maintains coherency with external RAMDAC palette.

4,3 Reserved

2 TFT Modulation:
0 = Modulation disabled
1 = Modulation enabled (default)

1 RAMDAC Emulation:
0 = No emulation (default)
1 = All RAMDAC palette writes and reads are performed to and from
palette RAM and external RAMDAC signals VWR and VRD are
inhibited.
AVG circuitry Miscellaneous Register, Port 03CF.8D, Read/Write

BIT FUNCTION
----------------
7 Panel Powerdown/Screen Blank
0 = No powerdown or blanking
1 = CRT is blanked, (panel drivers are turned off, signal OF5 is
active, and signal 26V (enable) is inactive. (default)

6 Enable Power Sequence

0 = Power sequencing of video ASIC is enabled (default)
1 = Power sequencing is disabled

5 Reserved

4 Panel Driver
0 = Drivers are off during blanking (default)
1 = Drivers are on during blanking

3..0 Reserved

RAMDAC Command Register, Port 83C6, Read/Write

BIT FUNCTION
----------------
7 Reserved

6 Clock Enable
0 = Normal operation
1 = Inhibit clocking

5 Setup Select
0 = Setup pedestal is 0 IRE
1 = Setup pedestal is 7.5 IRE

4 Blue Sync
0 = Disabled
1 = Enabled

3 Green Sync
0 = Disabled
1 = Enabled

2 Red Sync
0 = Disabled
1 = Enabled

1 6-Bit/8-Bit
0 = 6-bit
1 = 8-bit

0 Sleep Enable
0 = Normal operation
1 = Sleep mode
NOTE: A zero must be written to bit 7 when writing to this register to
ensure proper operation. This register is not initialized during the
RAMDAC powerup and is undefined until the first write access.

8.6 MODE-SPECIFIC REGISTER VALUES

This section contains tables showing the specific values written by the
BIOS to the registers for each of the BIOS modes. These values are provided
for reference for the systems developer, who needs working examples of
register programming. For proper operation, be sure that the environment is
understood (that is, know the types of monitors connected to the controller
and the timing that each display requires) before changing any of the
default parameters in the registers.

If the applications software is operating in a single-tasking operating

system environment, it is strongly recommended that operating modes be set
by making calls to BIOS INT 10h using AH = 00h (Set Mode). Adopting this
practice lessens the dependence of the software on the particular type of
video controller installed and monitor(s) attached.

Table 8-16 and Table 8-17 show the initial register values for the BIOS
modes. Table 8-17 shows the values specific to the 132-column modes. Cursor
positions and other read only register values are not shown.

Table 8-16. Initial Register Values (in Hexadecimal Notation) - Control

and Status Registers
=======================================================
====================
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
=======================================================
====================
Control and Status Registers (Part 1 of 2):

Miscellaneous
Output 3C2h -- W 63 63 63 63 63 63 63 A6 63 63 63 63 63 63 63

Feature
Control 3xAh -- W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP

Input
Status 0 3C2h -- R NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

Input
Status 1 3xAh -- R NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

Video Subsystem
Enable 46E8h -- R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP

COMPAQ
Config. 3CF 0B R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP

Environment
Status 3CF 0F R/W 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
Control and Status Registers (Part 2 of 2):

Miscellaneous
Output 3C2h -- W A2 A7 A2 63 63 63 A3 A3 63 63 63 67 E3 63 E3

Feature
Control 3xAh -- W NP NP NP NP NP NP NP NP NP NP NP NP NP NP 00

Input
Status 0 3C2h -- R NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

Input
Status 1 3xAh -- R NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

Video Subsystem
Enable 46E8h -- R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP

COMPAQ
Config. 3CF 0B R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP

Environment
Status 3CF 0F R/W 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 05
---------------------------------------------------------------------------
Legend:
NP - This register is not programmed during the setting of a BIOS mode.
This register is set during the POST process and is never programmed
by the BIOS again.
NA - This is a read only type register that is not and cannot be programmed
at any time since it is read only.
3xAh - This is the feature control port/input status one register address
which is dependent on the mode of the adapter. The following shows
the possible address values and the corresponding modes:
3BA - If the adapter is in the monochrome mode.
3DA - If the adapter is in the color/graphics mode.
=======================================================
====================

Table 8-16 (continued). Initial Register Values (in Hexadecimal Notation)

- Sequencer Registers
=======================================================
====================
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
=======================================================
====================
Sequencer Registers (Part 1 of 2):

Sequencer
Index 3C4h -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX
Reset 3C5h 00h R/W 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03

Clocking
Mode 3C5h 01h R/W 09 09 01 01 09 09 01 00 01 01 01 01 01 09 01

Map Mask 3C5h 02h R/W 03 03 03 03 03 03 01 03 03 03 03 03 03 0F 0F

Character Map
Select 3C5h 03h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Memory
Mode 3C5h 04h R/W 02 02 02 02 02 02 06 02 02 02 02 02 02 06 06
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
Sequencer Registers (Part 2 of 2):

Sequencer
Index 3C4h -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

Reset 3C5h 00h R/W 03 03 03 03 03 03 03 03 03 03 03 03 03 03 03

Clocking
Mode 3C5h 01h R/W 05 05 01 01 09 09 01 01 09 00 00 00 01 01 01

Map Mask 3C5h 02h R/W 0F 0F 0F 0F 03 03 03 03 03 03 03 03 0F 0F FF

Character Map
Select 3C5h 03h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Memory
Mode 3C5h 04h R/W 06 06 06 06 02 02 02 02 02 02 02 02 06 0E 0E
---------------------------------------------------------------------------
Legend:
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
=======================================================
====================

Table 8-16 (continued). Initial Register Values (In Hexadecimal Notation)

- CRT Controller Registers
=======================================================
====================
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
=======================================================
====================
CRT Controller Registers (Part 1 of 2):

CRTC Index 3x4h -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

Horizontal
Total 3x5h 00h R/W 2D 2D 5F 5F 2D 2D 5F 5F 5F 5F 5F 5F 5F 2D 5F

Horizontal Display
End 3x5h 01h R/W 27 27 4F 4F 27 27 4F 4F 4F 4F 4F 4F 4F 27 4F

Start Horizontal
Blanking 3x5h 02h R/W 28 28 50 50 28 28 50 50 50 50 50 50 50 28 50

End Horizontal
Blanking 3x5h 03h R/W 90 90 82 82 90 90 82 82 82 82 82 82 82 90 82

Start Horizontal
Retrace 3x5h 04h R/W 2B 2B 55 55 2B 2B 54 55 55 55 55 55 55 2B 54

End Horizontal
Retrace 3x5h 05h R/W A0 A0 81 81 80 80 80 81 81 81 81 81 81 80 80

Vertical
Total 3x5h 06h R/W BF BF BF BF BF BF BF BF BF BF BF BF BF BF BF

Overflow 3x5h 07h R/W 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F

Preset
Row Scan 3x5h 08h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
---------------------------------------------------------------------------
Maximum
Scanline 3x5h 09h R/W C7 C7 C7 C7 C1 C1 C1 4D C7 C7 C7 C7 C7 C0 C0

Cursor
Start 3x5h 0Ah R/W 06 06 06 06 00 00 00 0B 06 06 06 06 06 00 00

Cursor End 3x5h 0Bh R/W 07 07 07 07 00 00 00 0C 07 07 07 07 07 00 07

Start Address
High 3x5h 0Ch R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Start Address
Low 3x5h 0Dh R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Cursor Location
High 3x5h 0Eh R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Cursor Location
Low 3x5h 0Fh R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Start Vertical
Retrace 3x5h 10h R/W 9C 9C 9C 9C 9C 9C 9C 83 9C 9C 9C 9C 9C 9C 9C
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
---------------------------------------------------------------------------
End Vertical
Retrace 3x5h 11h R/W 8E 8E 8E 8E 8E 8E 8E 85 8E 8E 8E 8E 8E 8E 8E

Vertical Display
End 3x5h 12h R/W 8F 8F 8F 8F 8F 8F 8F 5D 8F 8F 8F 8F 8F 8F 8F

Offset 3x5h 13h R/W 14 14 28 28 14 14 28 28 28 28 28 28 28 14 28

Underline
Location 3x5h 14h R/W 1F 1F 1F 1F 00 00 00 0D 1F 1F 1F 1F 1F 00 00

Start Vertical
Blanking 3x5h 15h R/W 96 96 96 96 96 96 96 63 96 96 96 96 96 96 96

End Vertical
Blanking 3x5h 16h R/W B9 B9 B9 B9 B9 B9 B9 BA B9 B9 B9 B9 B9 B9 B9

Mode
Control 3x5h 17h R/W A3 A3 A3 A3 A2 A2 C2 A3 A3 A3 A3 A3 A3 E3 E3

Line
Compare 3x5h 18h R/W FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
---------------------------------------------------------------------------
Legend:
3x4h - This is the CRT controller index register address which is dependent
on the mode of the adapter. The following shows the possible
address values and corresponding mode:
3B4 - If the adapter is in the monochrome mode.
3D4 - If the adapter is in the color/graphics mode.
3x5h - This is the CRT controller data register address which is dependent
on the mode of the adapter. The following shows the possible
address values and corresponding mode:
3B5 - If the adapter is in the monochrome mode.
3D5 - If the adapter is in the color/graphics mode.
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
CRT Controller Registers (Part 2 of 2):

CRTC Index 3x4h -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

Horizontal
Total 3x5h 00h R/W 5F 5F 5F 5F 2D 2D 5F 5F 2D 5F 5F 5F 5F 5F C3

Horizontal Display
End 3x5h 01h R/W 4F 4F 4F 4F 27 27 4F 4F 27 4F 4F 4F 4F 4F 9F

Start Horizontal
Blanking 3x5h 02h R/W 56 53 50 50 28 28 50 50 28 50 50 50 50 50 A1
End Horizontal
Blanking 3x5h 03h R/W 1A 17 82 82 90 90 82 82 90 82 82 82 82 82 85

Start Horizontal
Retrace 3x5h 04h R/W 50 50 54 54 2B 2B 55 55 2B 55 55 55 54 54 A6

End Horizontal
Retrace 3x5h 05h R/W E0 BA 80 80 A0 A0 81 81 A0 81 81 81 80 80 1F

Vertical
Total 3x5h 06h R/W 70 6C BF BF BF BF BF BF BF BF BF BF 0B BF 0B

Overflow 3x5h 07h R/W 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F 3E 1F 3E

Preset
Row Scan 3x5h 08h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
Maximum Scan
Line 3x5h 09h R/W 00 00 40 40 4D 4D 4D 4D 4F 4F 4F 4F 40 41 40

Cursor
Start 3x5h 0Ah R/W 00 00 00 00 0B 0B 0B 0B 0D 0D 0D 00 00 00 00

Cursor End 3x5h 0Bh R/W 07 00 00 00 0C 0C 0C 0C 0E 0E 0E 0E 00 00 00

Start Address
High 3x5h 0Ch R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Start Address
Low 3x5h 0Dh R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Cursor Location
High 3x5h 0Eh R/W 00 00 00 00 00 00 00 00 00 00 00 07 00 00 00

Cursor Location
Low 3x5h 0Fh R/W 00 00 00 00 00 00 00 00 00 00 00 9E 00 00 00

Start Vertical
Retrace 3x5h 10h R/W 5E 5E 83 83 83 83 83 83 9C 9C 9C 9C EA 9C EA
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
End Vertical
Retrace 3x5h 11h R/W 2E 2B 85 85 85 85 85 85 8E 8E 8E 8E 8C 8E 8C

Vertical Display
End 3x5h 12h R/W 5D 5D 5D 5D 5D 5D 5D 5D 8F 8F 8F 8F DF 8F DF

Offset 3x5h 13h R/W 14 14 28 28 14 14 28 28 14 28 28 28 28 28 80

Underline
Location 3x5h 14h R/W 00 0F 0F 0F 1F 1F 1F 1F 1F 1F 0F 1F 00 40 40

Start Vertical
Blanking 3x5h 15h R/W 5E 5F 63 63 63 63 63 63 96 96 96 96 E7 96 E7

End Vertical
Blanking 3x5h 16h R/W 6E 0A BA BA BA BA BA BA B9 B9 B9 B9 04 B9 04

Mode
Control 3x5h 17h R/W 8B 8B E3 E3 A3 A3 A3 A3 A3 A3 A3 A3 E3 A3 E3

Line
Compare 3x5h 18h R/W FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF
---------------------------------------------------------------------------
Legend:
3x4h - This is the CRT controller index register address which is dependent
on the mode of the adapter. The following shows the possible
address values and corresponding mode:
3B4 - If the adapter is in the monochrome mode.
3D4 - If the adapter is in the color/graphics mode.
3x5h - This is the CRT controller data register address which is dependent
on the mode of the adapter. The following shows the possible
address values and corresponding mode:
3B5 - If the adapter is in the monochrome mode.
3D5 - If the adapter is in the color/graphics mode.
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
=======================================================
====================

Table 8-16 (continued). Initial Register Values (In Hexadecimal Notation)

- Attribute Registers
=======================================================
====================
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
=======================================================
====================
Attribute Registers (Part 1 of 2):

Attribute
Index 3C0h -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

Palette
Register 0 3C0h 00h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Palette
Register 1 3C0h 01h R/W 01 01 01 01 13 13 17 08 01 01 01 01 01 01 01

Palette
Register 2 3C0h 02h R/W 02 02 02 02 15 15 17 08 02 02 02 02 02 02 02
Palette
Register 3 3C0h 03h R/W 03 03 03 03 17 17 17 08 03 03 03 03 03 03 03

Palette
Register 4 3C0h 04h R/W 04 04 04 04 02 02 17 08 04 04 04 04 04 04 04

Palette
Register 5 3C0h 05h R/W 05 05 05 05 04 04 17 08 05 05 05 05 05 05 05
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
---------------------------------------------------------------------------
Palette
Register 6 3C0h 06h R/W 06 06 06 06 06 06 17 08 06 06 06 06 06 06 06

Palette
Register 7 3C0h 07h R/W 07 07 07 07 07 07 17 08 07 07 07 07 07 07 07

Palette
Register 8 3C0h 08h R/W 10 10 10 10 10 10 17 10 10 10 10 10 10 10 10

Palette
Register 9 3C0h 09h R/W 11 11 11 11 11 11 17 18 11 11 11 11 11 11 11

Palette
Register A 3C0h 0Ah R/W 12 12 12 12 12 12 17 18 12 12 12 12 12 12 12

Palette
Register B 3C0h 0Bh R/W 13 13 13 13 13 13 17 18 13 13 13 13 13 13 13

Palette
Register C 3C0h 0Ch R/W 14 14 14 14 14 14 17 18 14 14 14 14 14 14 14

Palette
Register D 3C0h 0Dh R/W 15 15 15 15 15 15 17 18 15 15 15 15 15 15 15
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
---------------------------------------------------------------------------
Palette
Register E 3C0h 0Eh R/W 16 16 16 16 16 16 17 18 16 16 16 16 16 16 16

Palette
Register F 3C0h 0Fh R/W 17 17 17 17 17 17 17 18 17 17 17 17 17 17 17

Mode
Control 3C0h 10h R/W 08 08 08 08 01 01 01 0E 08 08 08 08 08 01 01

Overscan 3C0h 11h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Color Plane
Enable 3C0h 12h R/W 0F 0F 0F 0F 03 03 01 0F 0F 0F 0F 0F 0F 0F 0F

Horizontal
Panning 3C0h 13h R/W 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00
Color
Select 3C0h 14h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
---------------------------------------------------------------------------
Legend:
NP - This register is not programmed during the setting of a BIOS mode.
This register is set during the POST process and is never programmed
by the BIOS again.
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
Attribute Registers (Part 2 of 2):

Attribute
Index 3C0h -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

Palette
Register 0 3C0h 00h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Palette
Register 1 3C0h 01h R/W 08 01 08 01 01 01 01 01 01 01 08 01 01 01 01

Palette
Register 2 3C0h 02h R/W 00 00 00 02 02 02 02 02 02 02 08 02 02 02 02

Palette
Register 3 3C0h 03h R/W 00 00 00 03 03 03 03 03 03 03 08 03 03 03 03

Palette
Register 4 3C0h 04h R/W 18 04 18 04 04 04 04 04 04 04 08 04 04 04 04
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
Palette
Register 5 3C0h 05h R/W 18 07 18 05 05 05 05 05 05 05 08 05 05 05 05

Palette
Register 6 3C0h 06h R/W 00 00 00 14 14 14 14 14 14 14 08 14 14 06 06

Palette
Register 7 3C0h 07h R/W 00 00 00 07 07 07 07 07 07 07 08 07 07 07 07

Palette
Register 8 3C0h 08h R/W 00 00 00 38 38 38 38 38 38 38 10 38 38 08 08

Palette
Register 9 3C0h 09h R/W 08 01 08 39 39 39 39 39 39 39 18 39 39 09 09

Palette
Register A 3C0h 0Ah R/W 00 00 00 3A 3A 3A 3A 3A 3A 3A 18 3A 3A 0A 0A

Palette
Register B 3C0h 0Bh R/W 00 00 00 3B 3B 3B 3B 3B 3B 3B 18 3B 3B 0B 0B

Palette
Register C 3C0h 0Ch R/W 00 04 00 3C 3C 3C 3C 3C 3C 3C 18 3C 3C 0C 0C
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
Palette
Register D 3C0h 0Dh R/W 18 07 18 3D 3D 3D 3D 3D 3D 3D 18 3D 3D 0D 0D

Palette
Register E 3C0h 0Eh R/W 00 00 00 3E 3E 3E 3E 3E 3E 3E 18 3E 3E 0E 0E

Palette
Register F 3C0h 0Fh R/W 00 00 00 3F 3F 3F 3F 3F 3F 3F 18 3F 3F 0F 0F

Mode
Control 3C0h 10h R/W 0B 01 0B 01 08 08 08 08 0C 0C 0E 0C 01 41 41

Overscan 3C0h 11h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Color Plane
Enable 3C0h 12h R/W 05 05 05 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F

Horizontal
Panning 3C0h 13h R/W 00 00 00 00 00 00 00 00 00 08 08 08 00 00 00

Color
Select 3C0h 14h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
---------------------------------------------------------------------------
Legend:
NP - This register is not programmed during the setting of a BIOS mode.
This register is set during the POST process and is never programmed
by the BIOS again.
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
=======================================================
====================

Table 8-16 (continued). Initial Register Values (In Hexadecimal Notation)

- Graphics Controller Registers
=======================================================
====================
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
=======================================================
====================
Graphics Controller Registers (Part 1 of 2):
Index 3CEh -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

Set/
Reset 3CFh 00h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Enable Set/
Reset 3CFh 01h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Color
Compare 3CFh 02h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Data
Rotate 3CFh 03h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Read Map
Select 3CFh 04h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Mode 3CFh 05h R/W 10 10 10 10 30 30 00 10 10 10 10 10 10 10 10

Misc. 3CFh 06h R/W 0E 0E 0E 0E 0F 0F 0D 0A 0E 0E 0E 0E 0E 0E 05

Color Don't
Care 3CFh 07h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 0F 0F

Bit Mask 3CFh 08h R/W FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

3CFh 40h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 41h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 42h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 43h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 44h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 45h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 46h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 48h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 49h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
Graphics Controller Registers (Part 2 of 2):

Index 3CEh -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

Set/
Reset 3CFh 00h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Enable Set/
Reset 3CFh 01h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Color
Compare 3CFh 02h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Data
Rotate 3CFh 03h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
Read Map
Select 3CFh 04h R/W 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00

Mode 3CFh 05h R/W 10 10 00 00 10 10 10 10 10 10 10 10 00 40 00

Misc. 3CFh 06h R/W 07 07 05 05 0E 0E 0E 0E 0E 0E 0A 0E 05 05 05

Color Don't
Care 3CFh 07h R/W 0F 0F 05 0F 00 00 00 00 00 00 00 00 0F 0F 0F

Bit Mask 3CFh 08h R/W FF FF FF FF FF FF FF FF FF FF FF FF FF FF FF

3CFh 40h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP 41
3CFh 41h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 42h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 43h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 44h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 45h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP 00
3CFh 46h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP 08
3CFh 48h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
3CFh 49h R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP
---------------------------------------------------------------------------
Legend:
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
NP - Not programmed.
=======================================================
====================

Table 8-16 (continued). Initial Register Values (In Hexadecimal Notation)

- Video DAC Registers
=======================================================
====================
Register BIOS Modes
Group/Name Port Index Type 0 1 2 3 4 5 6 7 8 9 A B C D E
=======================================================
====================
Video DAC Registers (Part 1 of 2):

PEL Mask 3C6h -- R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP

DAC
State 3C7h -- R NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

PEL Address
Read 3C7h -- W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

PEL Address
Write 3C8h -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

PEL Data 3C9h -- R/W PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR

VDAC
Command 83C6 -- R/W * * * * * * * * * * * * * * *
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type F 10 F+ 10+ 0* 1* 2* 3* 0+ 2+ 7+ 11 12 13 2E
---------------------------------------------------------------------------
Video DAC Registers (Part 2 of 2):

PEL Mask 3C6h -- R/W NP NP NP NP NP NP NP NP NP NP NP NP NP NP NP

DAC
State 3C7h -- R NA NA NA NA NA NA NA NA NA NA NA NA NA NA NA

PEL Address
Read 3C7h -- W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

PEL Address
Write 3C8h -- R/W IX IX IX IX IX IX IX IX IX IX IX IX IX IX IX

PEL Data 3C9h -- R/W PR PR PR PR PR PR PR PR PR PR PR PR PR PR PR

VDAC
Command 83C6 -- R/W * * * * * * * * * * * * * * NP
---------------------------------------------------------------------------
Legend:
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
NP - This register is not programmed during the setting of a BIOS mode.
This register is set during the POST process and is never programmed
by the BIOS again.
NA - This is a read only type register that is not and cannot be programmed
at any time since it is read only.
PR - The video DAC color registers are programmed during a mode set to the
correct color values for that mode. See the color programming table
for the values programmed to these color registers.
* Only 1 bit changes (reset to zero). All other bits are unchanged.
=======================================================
====================

Table 8-17. 132 Column Initial Register Values (in Hexadecimal Notation)
=======================================================
====================
Register BIOS Modes
Group/Name Port Index Type 18 19 1A 1B 1C 22 23 24 27 28
=======================================================
====================
Control and Status Registers:

Miscellaneous
Output 3C2h -- W AA 6A 6A 6A EA AB 6B 6B 6B EB

Feature
Control 3xAh -- W NP NP NP NP NP NP NP NP NP NP
Input
Status 0 3C2h -- R NA NA NA NA NA NA NA NA NA NA

Input
Status 1 3xAh -- R NA NA NA NA NA NA NA NA NA NA

Video
Subsystem
Enable 46E8h -- R/W NP NP NP NP NP NP NP NP NP NP
---------------------------------------------------------------------------
Sequencer Registers:

Sequencer
Index 3C4h -- R/W IX IX IX IX IX IX IX IX IX IX

Reset 3C5h 00h R/W 03 03 03 03 03 03 03 03 03 03

Clocking
Mode 3C5h 01h R/W 01 01 01 01 01 01 01 01 01 01

Map Mask 3C5h 02h R/W 03 03 03 03 03 03 03 03 03 03

Character
Map
Select 3C5h 03h R/W 00 00 00 00 00 00 00 00 00 00

Memory
Mode 3C5h 04h R/W 02 02 02 02 02 02 02 02 02 02
---------------------------------------------------------------------------
LEGEND:
NP - This register is not programmed during the setting of a BIOS mode.
This register is set during the POST process and is never programmed
by the BIOS again.
NA - This is a read only type register that is not and cannot be programmed
at any time since it is read only.
3xAh - This is the feature control port/input status one register address,
which is dependent on the mode of the adapter. The following shows
the possible address values and the corresponding modes:
3BA - If the adapter is in the monochrome mode.
3DA - If the adapter is in the color/graphics mode.
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 18 19 1A 1B 1C 22 23 24 27 28
---------------------------------------------------------------------------
CRT Controller Registers:

Index 3x4h -- R/W IX IX IX IX IX IX IX IX IX IX

Horizontal
Total 3x5h 00h R/W A0 A0 A0 A0 A0 A0 A0 A0 A0 A0
Horizontal Display
End 3x5h 01h R/W 83 83 83 83 83 83 83 83 83 83

Start Horizontal
Blanking 3x5h 02h R/W 84 84 84 84 84 84 84 84 84 84

End Horizontal
Blanking 3x5h 03h R/W 83 83 83 83 83 83 83 83 83 83

Start Horizontal
Retrace 3x5h 04h R/W 8D 8D 8D 8D 8D 8D 8D 8D 8D 8D

End Horizontal
Retrace 3x5h 05h R/W 9B 9B 9B 9B 9B 9B 9B 9B 9B 9B

Vertical
Total 3x5h 06h R/W BF BF BF BF 8 BF BF BF BF 8

Overflow 3x5h 07h R/W 1F 1F 1F 1F 3E 1F 1F 1F 1F 3E

Preset
Row Scan 3x5h 08h R/W 00 00 00 00 00 00 00 00 00 00

Maximum
Scanline 3x5h 09h R/W 47 4F 4D 47 47 47 4F 4D 47 47
---------------------------------------------------------------------------
LEGEND:
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
3x4h - This is the CRT controller index register address, which is
dependent on the mode of the adapter. The following shows the
possible address values and corresponding mode:
3B4 - If the adapter is in the monochrome mode.
3D4 - If the adapter is in the color/graphics mode.
3x5h - This is the CRT controller data register address, which is dependent
on the mode of the adapter. The following shows the possible address
values and corresponding mode:
3B5 - If the adapter is in the monochrome mode.
3D5 - If the adapter is in the color/graphics mode.
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 18 19 1A 1B 1C 22 23 24 27 28
---------------------------------------------------------------------------
CRT Controller Registers (continued):

Cursor
Start 3x5h 0Ah R/W 06 0D 0B 06 06 06 0D 0B 06 06

Cursor End 3x5h 0Bh R/W 07 0E 0C 07 07 07 0E 0C 07 07

Start Address
High 3x5h 0Ch R/W 00 00 00 00 00 00 00 00 00 00
Start Address
Low 3x5h 0Dh R/W 00 00 00 00 00 00 00 00 00 00

Cursor Location
High 3x5h 0Eh R/W 00 00 00 00 00 00 00 00 00 00

Cursor Location
Low 3x5h 0Fh R/W 00 00 00 00 00 00 00 00 00 00

Start Vertical
Retrace 3x5h 10h R/W 83 9C 9C 9C EA 83 9C 9C 9C EA

End Vertical
Retrace 3x5h 11h R/W 85 8E 8E 8E 8C 85 8E 8E 8E 8C

Vertical Display
End 3x5h 12h R/W 57 8F 87 8F DF 57 8F 8F 87 DF

Offset 3x5h 13h R/W 42 42 42 42 42 42 42 42 42 42

Underline
Location 3x5h 14h R/W 1F 1F 1F 1F 1F 1F 1F 1F 1F 1F

Start Vertical
Blanking 3x5h 15h R/W 63 96 96 96 E7 63 96 96 96 E7

End Vertical
Blanking 3x5h 16h R/W BA B9 B9 B9 04 BA B9 B9 B9 04

Mode
Control 3x5h 17h R/W A3 A3 A3 A3 A3 A3 A3 A3 A3 A3

Line
Compare 3x5h 18h R/W FF FF FF FF FF FF FF FF FF FF
---------------------------------------------------------------------------
LEGEND:
3x5h - This is the CRT controller data register address, which is dependent
on the mode of the adapter. The following shows the possible
address values and corresponding mode:
3B5 - If the adapter is in the monochrome mode.
3D5 - If the adapter is in the color/graphics mode.
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 18 19 1A 1B 1C 22 23 24 27 28
---------------------------------------------------------------------------
Attribute Registers:

Attribute
Index 3C0h -- R/W IX IX IX IX IX IX IX IX IX IX

Palette
Register 0 3C0h 00h R/W 00 00 00 00 00 00 00 00 00 00

Palette
Register 1 3C0h 01h R/W 08 08 08 08 08 01 01 01 01 01

Palette
Register 2 3C0h 02h R/W 08 08 08 08 08 02 02 02 02 02

Palette
Register 3 3C0h 03h R/W 08 08 08 08 08 03 03 03 03 03

Palette
Register 4 3C0h 04h R/W 08 08 08 08 08 04 04 04 04 04

Palette
Register 5 3C0h 05h R/W 08 08 08 08 08 05 05 05 05 05

Palette
Register 6 3C0h 06h R/W 08 08 08 08 08 14 14 14 14 14

Palette
Register 7 3C0h 07h R/W 08 08 08 08 08 07 07 07 07 07
---------------------------------------------------------------------------
LEGEND:
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
3x5h - This is the CRT controller data register address, which is dependent
on the mode of the adapter. The following shows the possible
address values and corresponding mode:
3B5 - If the adapter is in the monochrome mode.
3D5 - If the adapter is in the color/graphics mode.
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 18 19 1A 1B 1C 22 23 24 27 28
---------------------------------------------------------------------------
Attribute Registers (continued):

Palette
Register 8 3C0h 08h R/W 10 10 10 10 10 38 38 38 38 38

Palette
Register 9 3C0h 09h R/W 18 18 18 18 18 39 39 39 39 39

Palette
Register A 3C0h 0Ah R/W 18 18 18 18 18 3A 3A 3A 3A 3A

Palette
Register B 3C0h 0Bh R/W 18 18 18 18 18 3B 3B 3B 3B 3B

Palette
Register C 3C0h 0Ch R/W 18 18 18 18 18 3C 3C 3C 3C 3C

Palette
Register D 3C0h 0Dh R/W 18 18 18 18 18 3D 3D 3D 3D 3D

Palette
Register E 3C0h 0Eh R/W 18 18 18 18 18 3E 3E 3E 3E 3E

Palette
Register F 3C0h 0Fh R/W 18 18 18 18 18 3F 3F 3F 3F 3F

Mode
Control 3C0h 10h R/W 0E 0E 0E 0E 0E 0C 0C 0C 0C 0C

Overscan 3C0h 11h R/W 00 00 00 00 00 00 00 00 00 00

Color Plane
Enable 3C0h 12h R/W 0F 0F 0F 0F 0F 0F 0F 0F 0F 0F

Horizontal
Panning 3C0h 13h R/W 00 00 00 00 00 00 00 00 00 00

Color
Select 3C0h 14h R/W NP NP NP NP NP NP NP NP NP NP
---------------------------------------------------------------------------
LEGEND:
NP - This register is not programmed during the setting of a BIOS mode.
This register is set during the POST process and is never programmed
by the BIOS again.
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 18 19 1A 1B 1C 22 23 24 27 28
---------------------------------------------------------------------------
Graphics Controller Registers:

Index 3CEh -- R/W IX IX IX IX IX IX IX IX IX IX

Set/
Reset 3CFh 00h R/W 00 00 00 00 00 00 00 00 00 00

Enable Set/
Reset 3CFh 01h R/W 00 00 00 00 00 00 00 00 00 00

Color
Compare 3CFh 02h R/W 00 00 00 00 00 00 00 00 00 00

Data
Rotate 3CFh 03h R/W 00 00 00 00 00 00 00 00 00 00

Read Map
Select 3CFh 04h R/W 00 00 00 00 00 00 00 00 00 00

Mode 3CFh 05h R/W 10 10 10 10 10 10 10 10 10 10

Misc. 3CFh 06h R/W 0A 0A 0A 0A 0A 0E 0E 0E 0E 0E

Color Don't
Care 3CFh 07h R/W 00 00 00 00 00 00 00 00 00 00

Bit Mask 3CFh 08h R/W FF FF FF FF FF FF FF FF FF FF

---------------------------------------------------------------------------
LEGEND:
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
---------------------------------------------------------------------------
Register BIOS Modes
Group/Name Port Index Type 18 19 1A 1B 1C 22 23 24 27 28
---------------------------------------------------------------------------
Video DAC Registers:

PEL Mask 3C6h -- R/W NP NP NP NP NP NP NP NP NP NP

DAC
State 3C7h -- R NA NA NA NA NA NA NA NA NA NA

PEL Address
Read 3CFh -- W IX IX IX IX IX IX IX IX IX IX

PEL Address
Write 3C8h -- R/W IX IX IX IX IX IX IX IX IX IX

PEL Data 3C9h -- R/W PR PR PR PR PR PR PR PR PR PR

---------------------------------------------------------------------------
LEGEND:
NP - This register is not programmed during the setting of a BIOS mode.
This register is set during the POST process and is never programmed
by the BIOS again.
NA - This is a read only type register that is not and cannot be programmed
at any time since it is read only.
IX - This is an index type register; that is, this register is used to
determine which of the other registers is accessed. This register
changes continually during the programming process to access the other
registers.
PR - The video DAC color registers are programmed during a mode set to the
correct color values for that mode. See the color programming table
for the values programmed to these color registers.
=======================================================
====================

9.1 INTRODUCTION

The CD-ROM Adapter is a portable lightweight device that provides an

interface between the computer and an external CD-ROM drive.

This chapter provides the following information:

o Functional description [9.2]

o Device Drivers and Utilities [9.3]
o I/O Port Description [9.4]
o Command Protocol [9.5]
o Connectors [9.6]

Figure 9-1 shows the CD-ROM Adapter.

ILLUSTRATION OF Figure 9-1. CD-ROM Adapter

9.2 FUNCTIONAL DESCRIPTION

The CD-ROM Adapter connects directly to the computer via the 198-pin
expansion connector.

Data transfers between the external CD-ROM drive and the CD-ROM Adapter are
provided by an 8-bit SCSI interface. A SCSI-2 type 50-pin connector is
provided on the CD-ROM Adapter. The adapter is I/O mapped at addresses
(3E0h - 3EFh). Internal hardware interrupt level (IRQ9) and DMA channel (3)
are used during data transfers.

The CD-ROM Adapter SCSI interface consists of a single SCSI Protocol

Processor chip and other support circuitry. Device drivers must conform
with the EMULEX SCSI (ESP-100A) processor chip design standards and
protocol. Refer to the EMULEX Corporation Technical Manual (#VLSI51002-00)
for details.

The adapter is powered from the computer power supply once the adapter is
connected. The external CD-ROM drive is provided with its own power supply.

NOTE: The computer and the CD-ROM drive must not have power applied to them
until after all connections have been made. To ensure that the
computer recognizes the external CD-ROM drive, power must be applied
to the CD-ROM drive before turning on the computer.

9.3 DEVICE DRIVERS AND UTILITIES

All CD-ROM Adapter to CD-ROM drive communications are under the control of
a specific device driver. Each device driver is written specifically for
the drive being used. The device driver works with the adapter to build
SCSI command descriptor blocks (CDBs) and then programs the SCSI protocol
chip to issue the CDB to the attached drive.

The CD-ROM device driver must be in the CONFIG.SYS file at "BOOT" time. A
copy of MSCDEX.EXE and CDSETUP.EXE are included on the CD-ROM Utilities
Diskette. The CDSETUP.EXE utility must be run prior to CD-ROM use and
MSCDEX.EXE must be loaded prior to using the CD-ROM drive.

CDPLAY Utility

The CDPLAY utility supports playing music from audio compact discs in a
CD-ROM drive. The CDPLAY utility allows you to play, stop, and restart
music from a digital audio disc under computer control. A copy of
CDPLAY.EXE is included on the CD-ROM utilities diskette.

9.4 I/O PORT DESCRIPTION

The CD-ROM Adapter interface is configured as a contiguous block of sixteen

I/O addresses. The entire 16-byte address range is decoded. All registers
are eight bits in width. Several registers are reserved for future use.
Access to these registers is by programmed I/O except as noted in the
register descriptions.
Registers

Table 9-1 describes the CD-ROM adapter I/O registers.

Table 9-1. CD-ROM Adapter I/O Register Description

=======================================================
====================
Address Read Write
---------------------------------------------------------------------------
3E1 Transfer count high Transfer Counter High

3E2 FIFO Port FIFO Port

3E3 Command Register Command Register

3E4 Status Register Destination Bus ID

3E5 Interrupt Register Select Timeout

3E6 Sequence Step Register Sync Transfer Period

3E7 FIFO Flags Register Sync Transfer Offset

3E8 Configuration Register 1 Configuration Register 2

3E9 reserved Clock Conversion Factor

3EA reserved Test Register

3EB Configuration Register 2 Configuration Register 1

3EC reserved reserved

3ED reserved reserved

3EE reserved reserved

3EF reserved reserved

=======================================================
====================

Transfer Counter Low Register (read/write)

This register is the low byte of the 16-bit transfer count that is used for
DMA transfers to or from the adapter. Writing zeros to both the high and
low bytes of this register specifies the maximum count of 65536. This
register counts down as each byte is transferred. When the count reaches
zero, the Transfer Count Zero bit in the Status Register is set.

Transfer Counter High Register (read/write)

This register is the high byte of the 16 bits of the 16-bit transfer count
that is used for DMA transfers to or from the adapter. Writing zeros to
both the high and low bytes of this register specifies the maximum count of
65536. This register counts down as each byte is transferred. When the
count reaches zero, the Transfer Count Zero bit in the Status Register is
set.

FIFO Port Register (read/write)

The FIFO Port Register is a 16-byte first-in first-out buffer placed

between the SCSI bus and the system. It is used for both data and Command
Descriptor Block transfers. When the adapter is performing DMA transfers,
this port is either the source or destination of the data.

Command Register (read/write)

The Command Register is used to initiate adapter functions. Various 4-bit

command codes define the action to be performed and are combined with the
mode bits to form an 8-bit operation code. The CD-ROM Adapter is a SCSI
Initiator and only operates in the Initiator or Disconnected modes.

BIT FUNCTION
----------------
7 1 = Enable DMA

6 1 = Disconnected Mode

5 1 = Target Mode (used in Target mode only)

4 1 = Initiator Mode

3..0 Command Code

Table 9-2 lists the Command codes used with the CD-ROM Adapter.

Table 9-2. Command Codes

=======================================================
====================
Command Opcode (hex)
Interrupt Non-DMA DMA
---------------------------------------------------------------------------
DISCONNECTED STATE
---------------------------------------------------------------------------
Reselect Sequence Yes 40 C0

Select without ATN Sequence Yes 41 C1

Select with ATN Sequence Yes 42 C2

Select with ATN3 Sequence Yes 46 C6

Select with ATN & Stop Sequence Yes 43 C3

Enable Reselection No 44 C4

Disable Reselection Yes 45 --

---------------------------------------------------------------------------
INITIATOR STATE
---------------------------------------------------------------------------
Transfer Information Yes 10 90

Command Complete Sequence Yes 11 91

Message Accepted Yes 12 --

Transfer Pad Yes -- 98

Set ATN No 1A --
---------------------------------------------------------------------------
MISCELLANEOUS
---------------------------------------------------------------------------
NOP No 00 --

Flush FIFO Port No 01 --

Reset Adapter No 02 --

Reset SCSI Bus No 03 --

=======================================================
====================

Status Register (read only)

The Status Register contains status information for the SCSI protocol
device and the phase of the SCSI bus. Bits 3 through 7 are reset whenever
the Interrupt Register is read.

BIT FUNCTION
----------------
7 1 = Interrupt

6 1 = Gross Error

5 1 = Parity Error

4 1 = Transfer Count Zero

3 1 = Command Transfer Complete (not used in Initiator mode)

2 MSG

1 C/D

0 I/O

Bits 0 through 2 are inverted, real time versions of the SCSI bus signals,
I-/O, C-/D, and MSG-, which determine the bus phase. The bus phases
indicated by these bits, all of which are collectively termed Information
Phases, are listed below:

==========================
Bits Phase
210
--------------------------
000 Data Out

001 Data In

010 Command

011 Status

110 Message Out

111 Message In
==========================

Bit 6, Gross Error, is set when the FIFO port overflows or underflows, or
when the DMA transfer direction does not match the SCSI bus phase.

Bit 7, Interrupt, allows polling for an interrupt.

Destination Bus ID Register (write only)

This register holds the SCSI bus ID of the CD-ROM drive. The ID is loaded
into bits 0 through 2. This ID is used when the adapter selects the CD-ROM
drive. Bits 3 through 7 must be set to zero.

Interrupt Register (read only)

The Interrupt Register contains information, used along with the Status
Register, to determine the cause of an interrupt. The Interrupt Register
should only be read in response to an interrupt because reading this
register clears bits in the Status and Sequence Step Registers, and
deasserts the system interrupt, IRQ9.

BIT FUNCTION
----------------
7 1 = SCSI Bus Reset Detected

6 1 = Invalid Opcode

5 1 = Disconnect

4 1 = Bus Service

3 1 = Function Complete

2 1 = Reselected

1 1 = Selected with ATN not used in Initiator mode)

0 1 = Selected not used in Initiator mode)

Bit 3 Function Complete, is asserted whenever a Disconnected mode opcode

has completed, following completion of a Command Complete Sequence opcode,
or when a Message byte has been received and ACK- is still asserted by the
CD-ROM drive.
Bit 4, Bus Service, is asserted whenever the CD-ROM drive is in one of the
Information Transfer Phases.

Bit 5, Disconnect, is asserted when the CD-ROM drive disconnects from the
bus and the SCSI bus is free, or when a selection timeout occurs.

Bit 7, SCSI Bus Reset Detected, is asserted when reset is detected only if
SCSI reset interrupts are enabled in Configuration Register 1.

Select Timeout Register (write only)

This register is written with 9Bh to establish a 250-ms timeout period for
Target selection. The timeout value is fixed for this adapter. If the
CD-ROM drive does not respond to selection within this timeout period, the
Disconnect bit will be set in the Interrupt Register.

Sequence Step Register (read only)

This register contains opcode sequence information that may be used for
driver debugging purposes. It is used for normal operations.

Sync Transfer Period Register (write only)

This register specifies the transfer period for Synchronous SCSI data
transfers. It is not used for CD-ROM transfers.

FIFO Flags Register (read only)

The FIFO Flags Register holds the count of bytes currently in the FIFO
Port. The count read from this register may not be accurate during a
transfer, because the register bits may be in transition.

The sequence Step Bits contain opcode sequence information that may be used
for driver debugging purposes. They are not used for normal operation.

BIT FUNCTION
----------------
7..5 Sequence Step Bits

4..0 FIFO Port Count

Sync Transfer Offset Register (write only)

This register specifies the transfer offset for synchronous SCSI data.

Configuration Register 1 (read/write)

Configuration Register 1 is used to specify adapter operating parameters.

BIT FUNCTION
----------------
7 1 = Slow Cable Mode

6 0 = SCSI Reset Interrupt Enable

5 1 = Parity Test Mode

4 1 = Parity Enable

3 1 = Test Mode

2..0 1 = Adapter SCSI Bus ID

The Adapter is typically designated as SCSI ID 7, since it is the highest

priority ID.

Clock Conversion Factor Register (write only)

This register is written with 03h to specify basic adapter timing. This
value is fixed for this adapter.

Test Register (write only)

This register is used to put the adapter into one of several test modes.
These test modes must be disabled for normal operation by writing all bits
in this register to zero.

Configuration Register 2 (read/write)

Configuration Register 2 contains additional adapter operating parameters.

BIT FUNCTION
----------------
7..5 Reserved

4 1 = Tristate DRQ3

3 1 = SCSI 2 Mode

2 1 = Target Bad Parity Abort (not used in Initiator mode)

1,0 Reserved

9.5 COMMAND PROTOCOL

The CD-ROM Adapter contains a single SCSI Protocol Processor chip to handle
communications with an attached CD-ROM drive. Issuing commands via the
CD-ROM Adapter requires detailed familiarity with the SCSI specification.
SCSI Command Descriptor Blocks (CDBs) must be built and various SCSI bus
phases must be managed. A single command to the CD-ROM drive requires a
number of separate adapter operations, depending on the specific command
issued. Each adapter operation involves loading the necessary adapter
registers with parameter or control bytes, writing the adapter command
register to issue the command, waiting for the interrupt. Most adapter
operations return an interrupt when they are complete.

Before issuing commands to the CD-ROM drive, the adapter must be

configured. This is accomplished by writing the Configuration, Select
Timeout, Clock Conversion, and Test Registers with the necessary values.
When complete, the adapter is ready to communicate with the CD-ROM drive.

Reset Procedure

To reset the CD-ROM Adapter, CD-ROM drive, and SCSI bus, the proper reset
opcode must be written to the Command Register.

Typical Read Operation

The following sequence is performed during a typical read from a CD-ROM

drive:

System Actions

Load the Destination Bus ID Register and prepare for the transfer of the
SCSI CDB. If Direct Memory Access (DMA) is not used for the CDB transfer,
load the CDB into the adapter FIFO Port Register. If DMA is used for the
CDB transfer, load the Transfer Count Register with the number of bytes in
the CDB and program the system DMA controller to send the CDB to the
adapter. Write the selected operation code to the Command Register.

Adapter Actions

Arbitrate for the SCSI bus, select the CD-ROM drive, send the CDB to the
drive, and generate an interrupt.

System Actions

Load the transfer length (number of bytes per CD-ROM block times the number
of blocks to be read) into the Transfer Count Registers, program the system
DMA controller, and write the Transfer Information opcode into the Command
Register.

Adapter Actions

Transfer the data bytes from the CD-ROM drive to the system via DMA. Send
an interrupt to the system.

System Actions

When the data transfer from the CD-ROM drive is complete, write the Command
Complete Sequence opcode into the Command Register.

Adapter Actions

Transfer the SCSI status and Message bytes and generate an interrupt.

System Actions

Read the Status and Message bytes from the FIFO port, validate the message,
write the Message Accepted opcode to the Command Register.

Adapter Actions

Release the ACK signal on the SCSI bus, wait for Bus Free Phase, and
interrupt the system.

This completes a typical read operation from the CD-ROM drive.

9.6 CONNECTOR

CD-ROM Adapter SCSI Connector

ILLUSTRATION OF Figure 9-2. CD-ROM Adapter SCSI Connector

The 198-pin External Options Connector is described in Appendix B,

"Connectors."

10.1 INTRODUCTION

The keyboard subsystem consists of the 79-key U.S. English, 80-key

national, or 84-key Japanese Enhanced Keyboard and keyboard controller. An
optional External Numeric Keypad, which has its own connector, may be
added. The computer and the optional Desktop Expansion Base have a
connector for an external full-sized Enhanced Keyboard.

This chapter discusses the following topics:

o Enhanced Keyboard [10.2]

o Optional External Numeric Keypad [10.3]
o Keyboard controller [10.4]
o Scan codes [10.5]
o External Keyboard/Pointing Device Interface [10.6]
o Trackball [10.7]

10.2 ENHANCED KEYBOARD

The 79-key U.S. English, 80-key national, or 84-key Japanese keyboard

provides all the functionality of the full-sized COMPAQ Enhanced Keyboard
through an embedded numeric keypad and separate cursor- and screen-control
cluster. Three of the keys, Caps Lock, Num Lock, and Scroll Lock, have LED
indicators to provide current status. A total of five LED indicators are
provided in a row above the function keys.

Figure 10-1 shows the U.S. English Enhanced Keyboard.

ILLUSTRATION OF Figure 10-1. U.S. English Enhanced Keyboard

Functional Description

After power-on occurs, the default (initial state) conditions of the

keyboard are:

o Keyboard is enabled if the optional external keyboard is not present

o All LEDS are off unless Num Lock is enabled through the Setup procedure
o Typematic rate = 10 characters/sec (+/- 20%)
o Typematic delay = 500 milliseconds (+/- 20%)

The keyboard itself contains no active electronic circuitry. Matrix lines

from the keyboard are connected to the keyboard controller on the system
board. All keyboard functions are performed by the controller and keyboard
ROM, and all communications occur at the system level.

The keyboard controller has both a first-in, first-out (FIFO) buffer and a
repeating key function. Both Make and Break codes are generated when keys
are used. Make codes are transmitted when a key is pressed, Break codes
when it is released. This combination of codes is referred to collectively
as the "scan codes" of a key.

If the system cannot immediately accept scan codes when they are generated,
scan codes for up to a maximum of 24 bytes (8 characters) are stored in the
FIFO buffer. If two or more keys are pressed simultaneously, the keyboard
processes the first scan code detected and stores the others in the buffer
in the order in which they are detected. If a key is pressed when the
buffer is full, no scan code is generated; an overrun code is stored in the
last buffer location, which is reserved for overrun conditions.

Modes of Operation

The keyboard controller has two modes of operation. The default mode at
power-up is the Normal mode. Enhanced operation is available in the Normal
mode. QWERTY, numeric pad, and separate cursor key functions are available.
The Select mode is the other available mode that allows any or all keys to
be reassigned to make only, make/break or Typematic operation.

Normal Mode

The Normal mode allows compatibility with a standard 11-bit serial keyboard
interface. Each key has a unique make and break code. The make code is
transmitted when the key is pressed and the break code is transmitted after
the key is released. The resulting codes are jointly referred to as scan
codes.

Select Mode

The Select mode also uses an 11-bit bidirectional interface and different
scan codes. The select mode is system selectable via software and allows
for any individual key or all keys to be reassigned to one of the following
states:

o Make only operation

o Make/break operation
o Typematic only operation
o Typematic and Make/Break operation

Typematic Function

When a key is held down it will have an autorepeating rate of 10 Hz (+/- 1)

after a delay of 500 (+/- 50) milliseconds. If multiple keys are depressed,
the last depressed key is valid for typematic action. Autorepeating will
stop when the last depressed key is released.

Break codes of keys released are sent during the typematic transmission.
The typematic action consists of multiple transmissions of the make code.
Enhanced Operation

The Enhanced Keyboard permits simulation of the full-sized COMPAQ Enhanced

Keyboard by means of the embedded numeric keypad and separate cursor keys.
When the embedded keypad is enabled, embedded numeric keys and
cursor-control keys will transmit the key codes of an enhanced numeric
keypad provided the optional keypad is not attached. Cursor keys in the
separate cursor-control cluster always transmit enhanced codes, regardless
of the state of the Num Lock or keypad presence.

NOTE: The keyboard sub-system is not capable of transmitting the scan codes
for a Ctrl+Alt+Delete sequence from the embedded keypad.

The (Fn) Key

Operation of the Fn (function) key is unique; its only purpose is to flag

the keyboard scan controller. No code is sent to the system controller. The
operation of the Fn key depends on the state of the Num Lock key:

o Num Lock Off (LED off): Operation of the Fn key and an embedded numeric
key transmits the enhanced numeric scan code of a key or the screen
control code of a cursor key.

o Num Lock On (LED on): Operation of the Fn key and an embedded numeric key
transmits the default (alpha) scan code of a key or the screen control
code of a cursor key.

All scan codes accessed via the Fn key will send complete make/break codes.
For example, if the Fn key is released while an embedded numeric key is
still pressed, the break code of the embedded character must be transmitted
before any subsequent make code is sent. This will occur regardless of the
state of the Num Lock key or keypad presence.

The following tables describe the combined effects of the optional keypad,
Fn key, and Num Lock key on the keyboard controls.

Optional Keypad not installed

=======================================================
====================
NUM LOCK = On NUM LOCK = Off
---------------------------------------------------------------------------
Embedded Numerics Active Embedded Numerics None

Keypad Numerics None Keypad Numerics None

Embedded Cursor Controls Inactive Embedded Cursor Controls Via Fn

Embedded Screen Controls Inactive Embedded Screen Controls Via Fn

=======================================================
====================

Optional Keypad installed

Keypad Numerics Active Keypad Numerics Inactive

Embedded Cursor Controls None Embedded Cursor Controls None

Embedded Screen Controls None Embedded Screen Controls None

=======================================================
====================

The Embedded Numeric Keypad

The embedded numeric keypad is a 16-key set of keys, shown on the U.S.
English keyboard in Figure 10-2.

ILLUSTRATION OF Figure 10-2. Embedded Numeric Keypad

Embedded Numeric Keypad Function

The embedded numeric keypad is enabled and disabled by the Num Lock key. If
Num Lock is ON, the embedded numeric keypad is enabled; if Num Lock is OFF,
the keypad is disabled. When enabled, the embedded keypad transmits the
scan codes of the enhanced numeric keypad. In this mode, the Shift key
enables the cursor-control functions instead of the numeric functions as it
would on an enhanced keyboard.

Figure 10-3 shows key results when the keypad is enabled.

ILLUSTRATION OF Figure 10-3. Embedded Numeric Keypad Enabled

If Num Lock is OFF, the embedded keypad may also be enabled if the Fn key
and the Shift key are pressed simultaneously. When these keys are released,
the keyboard returns to the QWERTY mode. If the Fn key alone is depressed,
the embedded keypad functions as cursor-control keys.

If Num Lock is ON, regular (QWERTY) keyboard activity can be enabled

temporarily by holding down the Fn key. When the Fn key is released, the
embedded keypad is enabled.

When the optional External Numeric Keypad is attached to the Enhanced

Keyboard, the embedded keypad is disabled no matter what the state of the
Num Lock key.

Cursor- and Screen-Control Function

The embedded numeric keypad also provides cursor- and screen-control

functions. During regular (QWERTY) keyboard activity, these functions can
be accessed by pressing the Fn key. Releasing the Fn key returns the keypad
to normal keyboard operations.

If Num Lock is ON (embedded numeric keypad enabled), pressing the SHIFT key
enables these functions. Releasing the Shift key returns the keypad to
numeric keypad operations.

When cursor- and screen-control functions are active, the *, +, -, and /

arithmetic functions are also active.

Figure 10-4 shows the key results when cursor- and screen-control functions
are enabled.

ILLUSTRATION OF Figure 10-4. Cursor- and Screen-Control Functions Enabled

NOTE: Some applications require the use of the cursor- and screen-control
functions in the embedded numeric keypad rather than in the
cursor-control cluster.

Resetting the system (warm boot) requires use of the Delete key in the
upper right corner of the keyboard rather than the delete function on the
embedded numeric keypad.

LED Indicators

The two green LED indicators, Caps Lock and Scroll Lock, will be OFF at
power-on and after each keyboard initialization. Each time the associated
key is pressed, the LED changes state. The Num Lock LED will be off after
each keyboard initialization and will be off at power-on unless Num Lock is
enabled by the Setup utility.

The Scroll Lock and Num Lock LEDs are accessed by pressing the Function
(Fn) key and the appropriate key.

The only exception is the (Ctrl + associated LED key) combination, which
will not cause a state change of the LED.

A change of state of the Num Lock key from off to on activates the Enhanced
operation mode if the optional numeric keypad is attached, otherwise it
will enable the embedded numeric pad.

The power-on LED will turn on when power is applied to the computer. The
standby LED will turn on when the computer is in the standby mode.

10.3 OPTIONAL EXTERNAL NUMERIC KEYPAD

The optional 24-key External Numeric Keypad duplicates the function of the
embedded keypad contained on the Laptop Enhanced Keyboard. The External
Numeric Keypad is shown below.

ILLUSTRATION OF Figure 10-5. External Numeric Keypad

The External Numeric Keypad is connected to the computer system by means of

a 2-conductor cord with a 2-pin connector which plugs into the Laptop
Enhanced Keyboard. The 2-pin connection provides power and a data
communication path to the External Numeric Keypad.

The keyboard controller must detect the presence of the external numeric
keypad. With the keypad connected, the numeric function of each embedded
numeric key shall be disabled. Keyboard cursor control keys remain
functional.

Table 10-1. Signals for the 2-Pin External

Numeric Keypad Connector
===========================================
Pin Signal Name
-------------------------------------------
1 Keypad Power and Data

2 Signal Ground
===========================================

10.4 KEYBOARD CONTROLLER

The keyboard controller is located on the system board inside the case of
the computer. It provides control for the following:

o Computer reset
o Computer system address line A20
o Keyboard communication
o System LED control
o Low battery detection
o Standby Mode

LED Control

The keyboard controller provides control of the standby LED (STBLED) and
power-on LED (PWRLED) indicators. A signal is provided to the keyboard
controller which indicates normal or standby mode of operation.

The following table shows the function of the LED indicators.

Table 10-2. LED Status

=======================================================
====================
Normal Mode Standby Mode
---------------------------------------------------------------------------
Battery Voltage Power Standby Power Standby
---------------------------------------------------------------------------
Operating
LBAT1 inactive and On Off Off Flash
LBAT2 inactive 1 Hz

Low Battery 1:
LBAT1 active and Flash Off Off Flash
LBAT2 inactive 1 Hz 2 Hz

Low Battery 2:
LBAT1 active and Flash Off Flash Flash
LBAT2 active 2 Hz 2 Hz 2 Hz
=======================================================
====================

Programming the Keyboard Controller

The keyboard controller is I/O mapped at port addresses 60h and 64h. The
controller's communication interface to the computer consists of an input
buffer, an output buffer, and a system interrupt signal. Data or commands
written from the computer to the controller are put into the controller's
input buffer. Data returned to the computer from the controller are put
into the output buffer.

Prior to writing a command or data to the controller's input buffer (output

ports 60h or 64h), the Controller Status register (input port 64h) must
indicate "Input Buffer Empty." Prior to reading data from port 60h, the
Controller Status register must be tested to ensure that the "Output Buffer
Full" condition exists.

Port 60h, Data I/O Register

The keyboard controller Data I/O register is used to send and receive data
from the keyboard, to send the second byte of multi-byte commands to the
keyboard controller, and to receive responses from the keyboard controller
for commands that return a response.

Use the IN Instruction to read data from the controller output. Data in the
Data I/O register are from the keyboard, unless the controller has been
given a command that returns a response, such as 20h, Read Command Byte.
When data are read from the output buffer, the controller resets the
"Output Buffer Full" flag in the Status register.

Use the OUT Instruction to send data to the keyboard. All data written to
the Data I/O register are transmitted to the keyboard, except for data
written after the controller has been given the first byte of a multi-byte
command, such as 60h, Write Command byte. To give a multi-byte command to
the system keyboard controller, write the first command byte to port 64h
and the second byte to port 60h. Be sure the "Input Buffer Empty" condition
exists before writing each byte.

Port 64h, Command/Status Register

The Command/Status register is used to send commands to the keyboard

controller and receive status of the controller and keyboard.

Use the IN Instruction to read the Controller's Status register. The

Controller Status register bit definitions are shown below.

Use the OUT Instruction to give a command to the controller. Writing to

this address automatically sets the Command/Data flag in the Status
register to 1.

The following bit map shows what each bit represents in the Command/Status
register.
BIT FUNCTION
----------------
7 1 = Parity error detected -- RESEND command is sent to the keyboard
once only, as an attempt to recover.

6 1 = Receive timeout error

Keyboard transmission started, but did not finish in 2 ms.

5 1 = Transmission timeout error

Bit <5> set -- keyboard did not supply clock
Bits <6,5> set -- keyboard did not respond with ACKnowledge

4 Reserved

3 0 = Output buffer contains data

1 = Output buffer contains command

2 0 = Power-on (cold boot)

1 = Software reset (warm boot)

1 0 = Input buffer is empty

1 = Input buffer is full

0 0 = No new data in buffer (output buffer empty)

1 = New data in buffer (output buffer full)

Keyboard Controller Command Codes

The keyboard controller command codes consist of commands to control

computer speed, reset, address line 20 (A20), and keyboard communications.
Each command is executed by the controller after the computer writes the
corresponding code to port 64h.

Special Read (A5h)

The data byte described in the following table is put into the controller's
output buffer. No "Output Buffer Full" is generated.

BIT FUNCTION
----------------
7 0 = Keyboard Data signal low (logic 0)
1 = Keyboard Data signal high (logic 1)

6 0 = Keyboard Clock signal high (logic 1)

1 = Keyboard Clock signal low (logic 0)

5 0 = 11-bit keyboard is in use

1 = Reserved

4 0 = Interrupt (IRQ1) generated when output buffer is full

1 = Interrupt (IRQ1) not generated when output buffer is full

3,2 Reserved

1 0 = Address Line 20 (A20) is held low (logic 0)

1 = Address Line 20 (A20) is enabled

0 1 = System RESET signal is inactive

Reset (F0h, F2h, F4h, F6h, F8h, FAh, FCh, FEh)

Directs the controller to pulse (strobe low) the RESET signal for
approximately 5 us. No other outputs are modified.

Read Output Port (D0h)

Directs the controller to transfer the status of controller output signals

to the output buffer. Use the Read Output Port command only when the output
buffer is empty. The following data are put into the output buffer:

BIT FUNCTION
----------------
7 0 = Keyboard Data signal low (logic 0)
1 = Keyboard Data signal high (logic 1)

6 0 = Keyboard Clock signal high (logic 1)

1 = Keyboard Clock signal low (logic 0)

5 1 = IRQ12 Active (pointing device)

0 = IRQ12 Inactive (pointing device)

4 0 = Output buffer full interrupt signal (IRQ1) is high (logic 1)

1 = Output buffer full interrupt signal (IRQ1) is low (logic 0)

3,2 Reserved

1,0 Reserved

Write Output Port (D1h)

Directs the controller to set the FORCE A20 signal either high or low
according to bit <1> of the next byte written to the controller's input
buffer. No other controller outputs are modified.

BIT FUNCTION
----------------
7..2 Reserved

1 0 = Hold address Line 20 (A20) low

1 = Hold address Line 20 (A20) enabled

0 Reserved

Read Command Byte (20h)

Put the current command byte in the controller's Data I/O register.

Write Command Byte (60h)

Load the next byte put into the controller's Data I/O register as the
command byte. The command byte controls the system keyboard controller
operation as shown in the table below.

BIT FUNCTION
----------------
7 Reserved

6 0 = Do not convert keyboard codes

1 = Convert keyboard codes to the 8088/8086 scan codes

5 0 = Enable pointing device interface

1 = Disable pointing device interface

4 0 = Enable keyboard interface

1 = Disable keyboard interface

3 Reserved

2 Type of reset
0 = Power on (cold boot)
1 = Software reset (warm boot)

1 0 = Pointing device interrupt disable

1 = Pointing device interrupt enable

0 0 = Do not generate interrupt when output buffer is full

1 = Generate interrupt when output buffer is full

Initialize Controller (AAh)

The controller initializes its output signals, disables the keyboard

interface, clears the buffer pointers, then places 55h in the output
buffer.

Interface Test (ABh)

Directs the controller to test the data and clock signals of the external
keyboard interface. The output buffer receives the test results as follows:

00h -- No error detected

01h -- Keyboard clock signal stuck low
02h -- Keyboard clock signal stuck high
03h -- Keyboard data signal stuck low
04h -- Keyboard data signal stuck high
05h -- Keyboard clock signal connected to the keyboard data signal

Disable External Keyboard Interface (ADh)

Sets bit <4> of the controller's command byte, which disables the external
keyboard interface. Data is not received until the external keyboard is
enabled again.

Enable External Keyboard Interface (AEh)

Resets bit <4> of the controller's command byte, which enables the keyboard
interface.

Read Input Port (C0h)

The external keyboard controller has no input port so D0h is returned in

the output buffer when this command is executed.

Read External Keyboard Signal Levels (E0h)

Directs the controller to put the current state of the external keyboard
clock and external keyboard data signals into the output buffer.

10.5 SCAN CODES

Scan codes for the keyboard subsystem, including the optional external
numeric keypad, are given in Tables 10-3, 10-4, and 10-5.

Normal Mode

Normal mode is the default mode of the enhanced keyboard. In this mode, the
keyboard controller translates the Make codes generated by the keyboard and
converts them to the system codes required by the system BIOS.

Table 10-3 lists the Make codes for the keyboard operating in Normal mode.

In the Normal mode, the keyboard generates the Break code, a 2-byte
sequence that consists of a Make code immediately preceded by F0h.

Table 10-3. Keyboard Scan Codes (Hex) for the Normal Mode
=======================================================
====================
Key Key Cap Make Code Break Code System
Location Legend (NOTE 1) (NOTE 1) Code NOTES
---------------------------------------------------------------------------
1 ' 0E 29

2 1 16 02

3 2 1E 03

4 3 26 04

5 4 25 05

6 5 2E 06

7 6 36 07

8 7 3D 08

9 8 3E 09

10 9 46 0A

11 0 45 0B
12 - 4E 0C

13 + 55 0D

15 Backspace 66 0E

16 Tab 0D 0F

17 Q 15 10

18 W 1D 11

19 E 24 12

20 R 2D 13

21 T 2C 14

---------------------------------------------------------------------------
NOTES: 1. All scan codes listed are for Shift, Alt, and Ctrl inactive and
unless noted, the Break code is the Make code preceded by F0h.
2. Scan codes listed are for Num Lock inactive.
3. A numeric cluster key.
4. NA means no legend.
5. No key number is assigned for the Break key. Break =
Ctrl + Pause or Fn + Key 86. Break key is make only with no
break code.
6. No key is assigned for the Sys Req key. Sys Req = Alt+ Print
Screen or Fn + key 76.
---------------------------------------------------------------------------
Key Key Cap Make Code Break Code System
Location Legend (NOTE 1) (NOTE 1) Code NOTES
---------------------------------------------------------------------------
22 Y 35 15

23 U 3C 16

24 I 43 17

25 O 44 18

26 P 4D 19

27 [ 54 1A

28 ] 5B 1B

29 \ 5D 2B 5

30 Caps Lock 58 3A

31 A 1C 1E

32 S 1B 1F
33 D 23 20

34 F 2B 21

35 G 34 22

36 H 33 23

37 J 3B 24

38 K 42 25

39 L 4B 26

40 ; 4C 27

41 ' 52 28

42 \ 5D 2B 4

44 (Left) Shift 12 2A

45 \ 61 56 4

46 Z 1A 2C

47 X 22 2D

48 C 21 2E

49 V 2A 2F

50 B 32 30

51 N 31 31

52 M 3A 32
53 , 41 33

54 . 49 34

55 / 4A 35

57 (Right) Shift 59 36

58 (Left) Ctrl 14 1D

59 Fn No make or break code is generated for this key

60 (Left) Alt 11 38

61 (Space) 29 39

62 (Right) Alt E0 11 E0 F0 11 E0 38

75 Ins E0 70 E0 F0 70 E0 52 2

76 Del E0 71 E0 F0 71 E0 53 2

80 Home E0 6C E0 F0 6C E0 47 2

81 End E0 69 E0 F0 69 E0 4F 2

83 (Up Arrow) E0 75 E0 F0 75 E0 48 2

84 (Down Arrow) E0 72 E0 F0 72 E0 50 2

85 Page Up E0 7D E0 F0 7D E0 49 2

86 Page Down E0 7A E0 F0 7A E0 51 2

89 (Right Arrow) E0 74 E0 F0 74 E0 4D 2

90 Num Lock 77 45 3
91 7 6C 47 3

92 4 6B 4B 3

93 1 69 4F 3

95 / E0 4A E0 F0 4A E0 35 3

96 8 75 48 3

97 5 73 4C 3

98 2 72 50 3

99 0 70 52

100 * 7C 37 3

101 9 7D 49 3

102 6 74 4D 3

103 3 7A 51 3

105 - 7B 4A 3

106 + 79 4E 3

108 Enter E0 5A E0 F0 5A E0 1C 3

110 Esc 76 01

112 F1 05 3B

113 F2 06 3C

114 F3 04 3D
115 F4 0C 3E

116 F5 03 3F

117 F6 0B 40

118 F7 83 41

119 F8 0A 42

120 F9 01 43

121 F10 09 44

122 F11 78 57

123 F12 07 58

124 Print Scrn E0 12 E0 F0 7C E0 2A

E0 7C E0 F0 12 E0 37

125 Scroll Lock 7E 46

126 Pause E1 14 77 E1 E0 1D 45
F0 14 F0 77 E1 9D C5

Break 14 E0 7E E0 1D E0 46 5
F0 7E FD 14 E0 C6 9D

SYS REQ 84 54 6
---------------------------------------------------------------------------
NOTES: 1. All scan codes listed are for Shift, Alt, and Ctrl inactive and
unless noted, the Break code is the Make code preceded by F0h.
2. Scan codes listed are for Num Lock inactive.
3. A numeric cluster key.
4. NA means no legend.
5. No key number is assigned for the Break key. Break =
Ctrl + Pause or Fn + Key 86. Break key is make only with no
break code.
6. No key is assigned for the Sys Req key. Sys Req = Alt+ Print
Screen or Fn + key 76.
=======================================================
===================

The following keys have special codes during Normal mode operation
depending on the state of the Shift, Num Lock, Alt, and Ctrl keys.
Table 10-4 gives the scan codes generated by these keys.

Table 10-4. Combination Scan Codes for the Normal Mode

=======================================================
====================
Key Location Key Cap Scan Code Break Code
Shift Active with Legend
Num Lock OFF:
---------------------------------------------------------------------------
75 Ins E0 F0 12 E0 70 E0 F0 70 E0 12

76 Del E0 F0 12 E0 71 E0 F0 71 E0 12

79 (Left Arrow) E0 F0 12 E0 6B E0 F0 6B E0 12

80 Home E0 F0 12 E0 6C E0 F0 6C E0 12

81 End E0 F0 12 E0 69 E0 F0 69 E0 12

83 (Up Arrow) E0 F0 12 E0 75 E0 F0 75 E0 12

84 (Down Arrow) E0 F0 12 E0 72 E0 F0 72 E0 12

85 Page Up E0 F0 12 E0 7D E0 F0 7D E0 12

86 Page Down E0 F0 12 E0 7A E0 F0 7A E0 12

89 (Right Arrow) E0 F0 12 E0 74 E0 F0 74 E0 12

---------------------------------------------------------------------------
Key Location Key Cap Scan Code Break Code
Shift Active with Legend
Num Lock ON:
---------------------------------------------------------------------------
75 Ins E0 12 E0 70 E0 F0 70 E0 F0 12

76 Del E0 12 E0 71 E0 F0 71 E0 F0 12

79 (Left Arrow) E0 12 E0 6B E0 F0 6B E0 F0 12

80 Home E0 12 E0 6C E0 F0 6C E0 F0 12

81 End E0 12 E0 69 E0 F0 69 E0 F0 12

83 (Up Arrow) E0 12 E0 75 E0 F0 75 E0 F0 12

84 (Down Arrow) E0 12 E0 72 E0 F0 72 E0 F0 12

85 Page Up E0 12 E0 7D E0 F0 7D E0 F0 12

86 Page Down E0 12 E0 7A E0 F0 7A E0 F0 12

89 (Right Arrow) E0 12 E0 74 E0 F0 74 E0 F0 12

---------------------------------------------------------------------------
Key Location Key Cap Scan Code Break Code
Shift Active with Legend
Num Lock OFF:
---------------------------------------------------------------------------
95 Keypad E0 F0 12 E0 4A E0 F0 4A E0 12

Shift Active or
Ctrl Active:
124 Print Scrn E0 7C E0 F0 7C

NOTE 2
124 SYS REQ 84 F0 84

NOTE 3
126 Break E0 7E E0 F0 7E
---------------------------------------------------------------------------
NOTES: 1. Key 126 is not repeating; it generates a scan code only on the
Make condition.
2. No key number is assigned for SYS REQ.
3. No key number is assigned for Break.
=======================================================
====================

Select Mode

The second keyboard mode, Select mode, generates a unique set of scan
codes. In this mode, the keyboard controller translations must be disabled,
because the controller is not capable of translating the scan code set
generated. Applications using the enhanced keyboard in the Select mode must
select this mode via the F0h keyboard command.

In the Select mode, the keyboard generates the Break code, a 2-byte
sequence that consists of a Make code immediately preceded by F0h.

Table 10-5 lists the scan codes for the keyboard operating in the Select
mode.

Table 10-5. Make Codes (Hex) for the Select Mode

=======================================================
====================
Key Key Cap Make Code NOTES
Location Legend (NOTE 1)
---------------------------------------------------------------------------
1 ` 0E 4

2 1 16 4

3 2 1E 4

4 3 26 4

5 4 25 4

6 5 2E 4

7 6 36 4

8 7 3D 4

9 8 3E 4

10 9 46 4
11 0 45 4

12 - 4E 4

13 + 55 4

15 Backspace 66 4

16 Tab 0D 4

17 Q 15 4

18 W 1D 4

---------------------------------------------------------------------------
NOTES: 1. All scan codes listed are for Shift, Alt, and Ctrl inactive.
2. NA means no legend.
3. A numeric cluster key.
4. Typematic function default.
5. Make/Break function default.
6. Make only default.
---------------------------------------------------------------------------
Key Key Cap Make Code NOTES
Location Legend (NOTE 1)
---------------------------------------------------------------------------
19 E 24 4

20 R 2D 4

21 T 2C 4

22 Y 35 4

23 U 3C 4

24 I 43 4

25 O 44 4

26 P 4D 4

27 [ 54 4

28 ] 5B 4

29 \ 5C 5

30 Caps Lock 14 4

31 A 1C 4

32 S 1B 4

33 D 23 4
34 F 2B 4

36 H 33 4

37 J 3B 4

38 K 42 4

39 L 4B 4

40 ; 4C 4

41 ' 52 4

42 \ 53 4,7

43 Enter 5A 4

44 (Left) Shift 12 5

45 \ 13 5,7

46 Z 1A 4

47 X 22 4

48 C 21 4

49 V 2A 4

50 B 32 4

51 N 31 4

52 M 3A 4

53 , 41 4

54 . 49 4

55 / 4A 4
---------------------------------------------------------------------------
NOTES: 1. All scan codes listed are for Shift, Alt, and Ctrl inactive.
2. NA means no legend.
3. A numeric cluster key.
4. Typematic function default.
5. Make/Break function default.
6. Make only default.
---------------------------------------------------------------------------
Key Key Cap Make Code NOTES
Location Legend (NOTE 1)
---------------------------------------------------------------------------
57 (Right) Shift 59 5

58 (Left) Ctrl 11 5

60 (Left) Alt 19 5

61 (Space Bar) 29 4

62 (Right) Alt 39 6

75 Ins 67 6

76 Del 64 4

79 (Left Arrow) 61 4

80 Home 6E 6

81 End 65 6

83 (Up Arrow) 63 4

84 (Down Arrow) 60 4

85 Page Up 6F 6

86 Page Down 6D 6

89 (Right Arrow) 6A 4

90 Num Lock 76 3&6

91 7 6C 3&6

92 4 6B 3&6

93 1 69 3&6

95 / 77 3&6

96 8 75 3&6

98 2 72 3&6

99 0 70 3&6

100 * 7E 3&6

101 9 7D 3&6

102 6 74 3&6

103 3 7A 3&6

104 . 71 3&6

105 - 84 3&6

106 + 7C 3&6

108 Enter 79 3&6

110 Esc 08 6

112 F1 07 6

113 F2 0F 6

114 F3 17 6

115 F4 1F 6

116 F5 27 6

117 F6 2F 6

118 F7 37 6

119 F8 3F 6

120 F9 47 6

121 F10 4F 6

122 F11 56 6
123 F12 5E 6

124 Print Scrn 57 6

125 Scroll Lock 5F 6

126 Pause 62 6

---------------------------------------------------------------------------
NOTES: 1. All scan codes listed are for Shift, Alt, and Ctrl inactive.
2. NA means no legend.
3. A numeric cluster key.
4. Typematic function default.
5. Make/Break function default.
6. Make only default.
=======================================================
====================

10.6 EXTERNAL KEYBOARD/POINTING DEVICE INTERFACE

The external keyboard/pointing device interface is accessed through a 6-pin

DIN connector. Hardware support for the signals to and from the auxiliary
input device is provided by the keyboard controller.

The Keyboard controller can send commands to the external device at any
time. When the external keyboard or pointing device is transmitting to the
system, the system first clamps the CLOCK signal line to request a device
transmission halt. To ensure that the external device recognizes the system
request, the clock line must remain low (0) for at least 60 us. When the
device transmission is past the rising edge of the parity bit Clock pulse,
the external device completes its transmission before clocking out the
controller command.

When the keyboard controller is ready to transmit a command to the external

device, it sets the Data line low (0). This action serves as both a
Request-to-Send and a start bit. Upon detecting the Data line low, the
pointing device sets the Clock line low, causing the start bit to be
clocked out of the controller. The controller then places the LSB, data
bit <0> on the Data line, and the external device clocks out the LSB on the
next negative going clock pulse. This process continues until all eight
data bits are clocked out of the controller.

After all data bits are clocked out of the controller, the controller
places an odd parity bit on the Data line. The external device repeats its
clocking of the parity bit as before. The external device then sets the
Data line low and clocks this line to the keyboard controller for a stop
bit. When the external device receives the stop bit, the controller sets
the Clock line low to inhibit the device while it is processing the
received data.

After the external device receives a controller command, the external

device returns an ACK code to the controller. If a parity error or time-out
occurs, a Resend command is sent to the keyboard controller.

Connector
The external keyboard cable or external pointing device has a 6-pin
circular-type DIN connector that plugs into a dedicated connector.
Table 10-6 lists the keyboard/pointing device connector signals.

Table 10-6. Keyboard Cable (DIN)

Connector Signals
==================================
Pin Signal
----------------------------------
1 Data

2 NC

3 GND

4 +5VDC

5 Clock

6 NC

Shield Chassis GND

==================================

10.7 TRACKBALL

The COMPAQ LTE Lite/25C and COMPAQ LTE Lite/25e both incorporate a built-in
EasyPoint trackball. The trackball is a serial device that is fully
compatible with the Microsoft serial mouse.

The trackball may be assigned to COM port 1 or 2. The default assignments

are COM port 2 and IRQ 3. IRQ 10 may be used instead of IRQ 3. The
trackball may be disabled when an external pointing device is used.

A block diagram of the trackball circuit is shown in Figure 10-6.

ILLUSTRATION OF Figure 10-6. Block Diagram of the Trackball Circuit

Acceleration Function

Determining the speed of rotation of the trackball is a function of the

trackball control circuit. As the trackball rotates, the trackball control
circuit receives input counts from the X/Y mounted optically coupled
phototransistor/diode encoders. The number of counts is checked at precise
intervals by the control circuit and the counts are scaled by an
acceleration function to determine the speed of rotation.

Figure 10-7 shows the Acceleration function of the trackball control

circuit.

ILLUSTRATION OF Figure 10-7. Acceleration Function

Data Format
The data transmitted by the trackball to the system consists of the X/Y
coordinates of the ball, and the status of the buttons. This data is
transmitted in a three-byte serial data packet that is compatible with the
Microsoft serial mouse.

The serial data is transmitted to the system using the following

parameters:

Baud Rate 1200 bps + 2%

Data Bits 7 bits
Start Bits 1 bit
Stop Bits 2 or more bits
Parity None

Figure 10-8 shows the serial data transmission sequence.

ILLUSTRATION OF Figure 10-8. Serial Data Transmission Sequence

Trackball Initialization

During power-up or system reset, and after a High/Low transition is

detected on the reset line, the trackball circuit will transmit a single
ASCII "M". This action confirms to the system that the trackball is ready
and functional. Figure 10-9 shows a timing diagram for trackball
initialization.

ILLUSTRATION OF Figure 10-9. Trackball Initialization Timing Diagram

Tables 10-7 through 10-9 show the COM port assignments for the trackball
and when an external mouse is present or the Options slot (Modem or serial
board) is installed.

Table 10-7. COM Port Assignments (No External Mouse)

=======================================================
====================
COM 1 COM 2 COM 3
---------------------------------------------------------------------------
Option slot not used 9-pin built-in trackball not used
IRQ=4 IRQ=3

modem or serial board modem/serial board built-in trackball 9-pin

installed IRQ=4 IRQ=3 (default) IRQ=15/10
=======================================================
====================

Table 10-8. COM Port Assignments (With External Serial Mouse)

modem or serial board modem/serial board 9-pin not used

installed IRQ=4 IRQ=3
=======================================================
====================

Table 10-9. COM Port Assignments (With External PS2 Mouse)

modem or serial board modem/serial board 9-pin not used

installed IRQ=4 IRQ=3
=======================================================
====================

11.1 INTRODUCTION

The power supply system consists of the External AC Adapter, Internal Power
Supply, Battery Pack, and Auxiliary Battery. Optional equipment includes
the External Battery Charger and the Automobile Adapter.

This chapter contains the following information:

o Functional Description [11.2]

o Internal Power Supply [11.3]
o Battery Packs [11.4]
o Auxiliary Battery [11.5]
o AC Adapter [11.6]
o Automobile Adapter [11.7]
o External Battery Charger [11.8]

11.2 FUNCTIONAL DESCRIPTION

The computer is powered from an internal rechargeable battery pack. The

standard battery pack for the COMPAQ LTE Lite/25C, COMPAQ LTE Lite/25E, and
COMPAQ LTE Lite/25 is the Nickel Metal Hydride (NiMH) type. The standard
battery pack for the COMPAQ LTE Lite/20 is a Nickel Cadmium (NiCd)type.

The internal power supply is a DC/DC converter that converts the input DC
voltage to the voltages required by the computer and display circuitry. An
external AC Adapter provides power for the computer and power to recharge
both the battery pack and auxiliary battery. Refer to Figure 11-1.

The auxiliary battery powers the computer for a short period of time in a
reduced power state or standby mode. This reduced power state occurs when
the main battery pack is removed in order to replace it with another
battery pack.
Figure 11-1 shows a block diagram of the power supply system.

ILLUSTRATION OF Figure 11-1. Block Diagram of the Power Supply System

11.3 INTERNAL POWER SUPPLY

The computer has an internal power supply that converts the AC Adapter DC
output voltage or battery pack voltage to levels required by the circuitry
of the computer and display. The internal power supply provides +5 volts
output.

Powergood

The powergood signal indicates that the +5 volt output is within the
required operating limits. This signal is initially low and remains low for
approximately 200 milliseconds after the +5 volt output reaches its
specified limits. The signal then goes high which indicates the computer is
ready to operate. When the Powergood signal is low, the computer is in a
reset condition.

The Powergood signal appears inverted on pin 76 of the expansion connector

as the Resetdrv signal. In addition to being generated at power-up, the
Resetdrv signal is also generated whenever the computer leaves the low
power or standby mode and returns to normal operation.

Power-on

The Power-on signal activates the internal power supply when it is driven
low (0). Poweron is normally high and is held high by a 40Kohm pullup
resistor to the battery voltage. This signal is normally driven low by the
computer or can be driven low with external circuitry to control the
computer remotely. The internal circuitry (Power-On Switch) is prevented
from driving this signal low if the Expandb signal on the expansion
connector is connected to ground.

External Power Drain

The AC Adapter and internal power supply can provide a maximum of 350
milliamps of current at +5 volts to any external equipment connected to the
computer. The battery pack can supply a maximum of 250 milliamps of current
to external equipment.

NOTE: The length of time that the battery pack can maintain power during
the low power or standby mode is dependent on many factors. The
condition of the battery, the amount of battery charge, the amount of
load that internal and external devices place on the battery will
affect the amount of time that power is sustained in the standby or
low power mode.

External equipment connected to the computer should be designed to enter a

low power mode or turn off when the computer is in the standby mode.

Specifications
Specifications for the internal power supply are shown in Table 11-1.

Table 11-1. Internal Power Supply Specifications

=======================================================
====================
Input DC Voltage Range: 10.0 to 18 VDC

Power Output:
Steady State 18.5W
Peak 21.0W

Output Current: Maximum Peak

3.64A 4.13A

Voltage Regulation:
Output Nominal Regulation
+5VDC +5.075 VDC 3% of Nominal Voltage
=======================================================
====================

11.4 BATTERY PACKS

The standard battery pack for the COMPAQ LTE Lite/25C, COMPAQ LTE Lite/25E,
and COMPAQ LTE Lite/25 is the Nickel Metal Hydride (NiMH) type. The
standard battery pack for the COMPAQ LTE Lite/20 is the Nickel Cadmium
(NiCd) type. Both battery packs provide the same operating voltage and have
the same physical dimensions. The Nickel Metal Hydride battery pack has a
higher energy density and will provide more power.

The battery pack is charged at two different rates, fast charge and trickle
charge. The charge rate is dependent on the charge level of the battery
pack and the internal temperature of the battery pack.

Both types of battery packs contain a microprocessor for monitoring the

condition of the internal battery cells and for controlling the charge to
the cells. The battery pack microprocessor senses when and at what rate the
battery cells are being charged or discharged. Since the microprocessor is
located within the battery pack and powered by the battery pack, the charge
level of the battery is accurate even when the battery is removed from the
computer and later reinstalled. Battery power usage (fuel gauge data) is
derived from the information sent by the battery microprocessor to the
computer.

The battery packs have an amber LED on the front. The LED indicates when
the battery pack is in a fast charge condition and is not fully charged.

Specifications

The electrical specifications of the Nickel Cadmium battery pack are shown
in Table 11-2.

Table 11-2. Nickel Cadmium Battery Pack Electrical Specifications

=======================================================
====================
Parameter Value Notes
---------------------------------------------------------------------------
Open circuit voltage: 12.0V Nominal

Capacity: 1.75 Amp-hours 0.34A discharge rate

after full charge at
77oF (25oC)

Discharge rate: 0.9A Typical

Charge rate:
Fast 2.2A Typical
Trickle 0.1A Typical

Temperature:
Charge 10oC to 40oC
Storage 0oC to 50oC

Cycle life: 500 cycles

Minimum (cycle =
full charge/full
discharge)
=======================================================
====================

The electrical specifications of the Nickel Metal Hydride battery pack are
shown in Table 11-3.

Table 11-3. Nickel Metal Hydride Battery Pack Electrical Specifications

Capacity 2.2 AMP-hours 0.34A discharge rate after full

charge at 77oF (25oC)

Discharge rate: 0.9A Typical

Charge rate:
Fast 2.2A Typical
Trickle 0.1A Typical

Temperature:
Charge 10oC to 40oC
Storage 0oC to 50oC

Cycle life:500 cycles Minimum (cycle = full charge / full

discharge) at 25 degrees C
=======================================================
====================

The physical specifications for both types of battery packs are shown in
Table 11-4.

Table 11-4. Battery Pack

Physical Specifications
========================================
English Metric
----------------------------------------
Height 0.77 in 1.95 cm

Depth 5.63 in 14.29 cm

Width 3.77 in 9.59 cm

Weight 1.30 lb 600 gr

========================================

11.5 AUXILIARY BATTERY

The auxiliary battery is a small internal Nickel Cadmium (NiCd) battery

used to power the computer in the low power or standby mode while the
battery pack is removed. The auxiliary battery can power the computer at
reduced voltage (6 to 8 volts) for up to one minute maximum. The current
drain from any external equipment should not exceed 250 milliamps maximum
during this low power mode.

The auxiliary battery is charged whenever the computer is operating and not
in Standby and when the AC Adapter is powering the system. The charging
system is designed to recharge the auxiliary battery in three hours if the
battery was discharged for one minute at 250 milliamps.

11.6 AC ADAPTER

The external AC Adapter converts AC current into DC, to operate the

computer and for charging the battery pack and auxiliary battery. The AC
Adapter is designed to accept a wide range of AC input voltages. A green
LED indicates the AC Adapter is powered and operational. The AC Adapter
connects to the computer by means of a 3-conductor cable.

Figure 11-2 shows the AC Adapter and power cord.

ILLUSTRATION OF Figure 11-2. AC Adapter

Connector

Table 11-5 shows the signals for the 3-pin AC Adapter connector.

Table 11-5. AC Adapter Connector

=======================================================
====================
Pin Signal Name Description
---------------------------------------------------------------------------
1 DC Output 18 VDC maximum

2 Ground Ground

3 NC No Connection
=======================================================
====================
Specifications

Table 11-6 provides physical and operating specifications for the AC

Adapter.

Table 11-6. AC Adapter Specifications

=======================================================
====================
Unit size:
Width 5.3 in (13.5 cm)
Height 1.4 in (3.6 cm)
Depth 3.3 in (8.4 cm)

Weight: 0.8 lb (0.36 kg)

AC Input:
Voltage 100 - 120/220 - 240 Volts AC
Frequency 50 - 60 Hz
Current 0.8 /0.4 amps

DC Output:
Voltage 18 VDC maximum
Current 2.5 amps maximum
Power 35 watts maximum
=======================================================
====================

11.7 AUTOMOBILE ADAPTER

The optional Automobile Adapter provides a source of DC power from the

electrical system of an automobile. This adapter, like the AC Adapter, is
used to power the computer and to charge the battery pack. It is intended
to be used with the 12 VDC negative ground electrical systems found in
commercially available motor vehicles today.

The Adapter connects to the automobile electrical system by means of the

vehicle's cigarette lighter.

Figure 11-3 shows the Automobile Adapter.

ILLUSTRATION OF Figure 11-3. Automobile Adapter

Specifications

Table 11-7 shows the specifications for the Automobile Adapter.

Table 11-7. Automobile Adapter Specifications

=======================================================
====================
Input Voltage Range 10 - 18 VDC

Maximum Current 2.5A

Maximum Output Power 35w

Dimensions
Height 1.5 in (3.8 cm)
Depth 3.9 in (9.9 cm)
Width 1.5 in (3.8 cm)

Weight 0.55 lb (0.25 kg)

=======================================================
====================

11.8 EXTERNAL BATTERY CHARGER

The optional External Battery Charger provides the capability of recharging

two battery packs outside of the system unit. Power for the external
battery charger is provided by the AC Adapter.

Figure 11-4 shows the External Battery Charger.

ILLUSTRATION OF Figure 11-4. External Battery Charger

When two batteries are installed, the charger completes the charge of one
battery then begins the charge of the second battery. The charger controls
the sequence of charging for the two batteries and provides signals to the
AC Adapter to control the output of the adapter.

When two battery packs are being charged at the same time, they need not be
the same type of battery pack. Both types of battery packs can be charged
in the charger.

Specifications

Table 11-8 shows the External Battery Charger specifications.

Table 11-8. External Battery Charger Specifications

=======================================================
====================
Dimensions
Width 4.63 in (11.8 cm)
Height 1.56 in (3.98 cm)
Depth 4.06 in (10.35 cm)

Weight 0.48 lb (0.22 kg)

Power
Operating Voltage 10.0 to 18.3 VDC
Operating Current 2.0A
Peak Power 60.0w
=======================================================
====================

12.1 INTRODUCTION
The computer comes equipped with one 3 1/2-inch diskette drive with 1.44
megabytes of data storage possible per diskette. Optional 5 1/4-inch
diskette drives with 1.2 megabytes or 360 Kbytes of data storage per
diskette may be added with the optional External Storage Module or the
Desktop Expansion Base.

This chapter contains the following diskette drive information:

o Diskette Drives [12.2]

o Diskette Drive Controller [12.3]
o Diskette Drive Control Signals [12.4]
o Specifications [12.5]

12.2 DISKETTE DRIVES

The internal 3 1/2-inch 1.44-megabyte diskette drive is by default drive A.

The diskette drive is hardwired, with no jumpers or switches added.

If an optional External Storage Module containing a 5 1/4-inch diskette

drive is installed, the Drive Selection switch on the Storage Module
permits the user to designate the external drive as either drive A or as
drive B. The internal drive then becomes either drive B or A. The computer
must be reset either by pressing the Ctrl + Alt + Del keys or by turning
the computer off then on again for the switch setting to be recognized.
This feature permits booting from the external drive if it is installed.

Figure 12-1 is a functional block diagram for a diskette drive.

ILLUSTRATION OF Figure 12-1. Diskette Drive Functional Block Diagram

1.44-Megabyte Diskette Drive

The 1.44-megabyte diskette drive is a high-capacity diskette drive with the

following features:

o 0.6-inch high, 3 1/2-inch diskette drive

o Two transfer rates: 250 Kb/s (low density) or 500 Kb/s (high density)
o Data storage on 80 tracks (135 tpi)
o Write- and read-compatible with low density (720-Kbyte) 3 1/2-inch media

1.2-Megabyte Diskette Drive

The optional 1.2-megabyte diskette drive is a high-capacity diskette drive

with the following features:

o 1/3-height, 5 1/4-inch diskette drive

o Two transfer rates: 300 Kb/s (low density) or 500 Kb/s (high density)
o Data storage on 80 tracks (96 TPI)

To read or write to 48-tpi media, the software must step the 96-tpi drive
head twice between each 48-tpi track. Because the track width of the 96-tpi
diskette drive is half the track width of the 48-tpi diskette drive,
standard 48-tpi diskette drives may not be able to reliably read diskettes
written by the 96-tpi drive in the 48-tpi format.
360-Kbyte Diskette Drive

The optional 360-Kbyte diskette drive has the following features:

o 1/3-height, 5 1/4-inch diskette drive

o Single transfer rate of 250 Kb/s
o Double-sided, double-density (DSDD) on 40 tracks (48 tpi)

12.3 DISKETTE DRIVE CONTROLLER

The diskette drive controller circuitry, through dedicated I/O port

addresses, transmits data to and from a diskette drive. The controller also
regulates drive functions, and reads the current drive status.

Table 12-1 lists the port addresses of the diskette drive controller.

Table 12-1. Port Addresses for the Diskette Drive Controller Circuits
=======================================================
====================
Port Read/Write Register Function
----
1 2
---------------------------------------------------------------------------
3F1h R Media ID

3F2h 372h W Drive Control

3F4h 374h R Main Status

3F5h 375h R/W Data

3F7h 377h R/W Data Transfer Rate Control

Diskette Drive Status/Fixed Disk
Drive Status
=======================================================
====================

Diskette Drive Controller Registers

The Diskette Drive Controller registers are described in the following

paragraphs.

Media ID (3F1h, Read Only)

The Media ID register can be used to identify a 3 1/2-inch diskette drive

and the media installed in the drive. The format for this register is:

BIT FUNCTION
----------------
7 LOW DENSITY- media ID bit

6..0 Reserved

To identify 3 1/2-inch diskette drives:

1. Select drive, turn motor on using 3F2h.

2. Set the data rate to 250 kilobits per second (Kb/s) by writing 02h to
3F7h.

3. Wait two milliseconds.

4. Read bit <7> at 3F1h LOW DENSITY-. If LOW DENSITY- is low, the drive
(type) is a 3 1/2-inch diskette drive. If LOW DENSITY- is high, the
drive is indeterminate and the media ID bit cannot be used to determine
the type of media installed.

To identify media type:

(If the drive is determined not to be a 3 1/2-inch diskette drive using the
above procedure, the media type is indeterminate. If the drive is a 3
1/2-inch diskette drive, the following procedure can be used.)

1. Select drive, turn motor on using 3F2h.

2. Clear the DISKETTE CHANGE- signal if it is active.

3. Set the data rate to 500 Kb/s by writing 00h to 3F7h.

4. Read bit <7> at location 3F1. If the bit is low, 720-megabyte media
is installed. If the bit is high then 1.44-megabyte media is installed.

Drive Control (3F2h, Write Only)

The Drive Control register controls the functions of interrupt and DMA
enable, Drive Motor ON, Drive Select, and controller reset. The format for
this register is:

BIT FUNCTION
----------------
7,6 Reserved

5 0 = Diskette drive 2 motor OFF

1 = Diskette drive 2 motor ON

4 0 = Diskette drive 1 motor OFF

1 = Diskette drive 1 motor ON

3 0 = Interrupts and DMA disabled

1 = Interrupts and DMA enabled

2 0 = Reset drive controller

1 = Reenable drive controller

1,0 00 = Diskette drive 1 selected

01 = Diskette drive 2 selected
10 = Reserved
11 = Tape drive selected
Main Status (3F4h, Read Only)

The Main Status register of the diskette drive controller IC is used as the
Diskette Drive Status register.

Data (3F5h)

Commands and data are written to this port. Data and status bytes are read
from this port.

Data Transfer Rate Control (3F7h, Write Only)

This register contains the current data transfer rate in kilobits per
second (Kb/s). The format for this register is:

BIT FUNCTION
----------------
7..2 Reserved

1,0 Data Transfer Rate (Kb/s)

00 = 500
01 = 300
10 = 250
11 = 1000

Diskette Drive and Fixed Disk Drive Status (3F7h, Read Only)

This register provides both diskette drive status information (bit <7>) and
fixed disk drive status information (bits <6..0>). The format for this
register is as follows:

BIT FUNCTION
----------------
7 Diskette change

6..0 Reserved for fixed disk drive

Drive Controller

The drive controller accepts commands from the computer that control most
drive functions and transfers of data to the drives.

The drive controller operates in the ISA-compatible DMA mode for data
transfers to and from the system. It issues a DMA request (DRQ2) signal and
receives a DMA acknowledge (DACK2-) signal for each byte transferred.

All drive controller commands have three operating phases:

o The command phase, in which the drive controller receives the command
from the system

o The execution phase, in which the drive controller carries out the
command

o The results phase, in which the status and results are read back from the
drive controller to the system

Programmable Data Transfer Rate

The system can transfer data at various rates depending on the drive and
the type of media being used.

The Data Transfer Rate Control register (3F7h) contains the bits that
specify the transfer rate. Table 12-2 lists the data transfer rates of
various peripheral devices and medias.

Table 12-2. Programmable Data Transfer Rate

=======================================================
====================
Data Transfer When Using:
Rate (in Kb/s)
---------------------------------------------------------------------------
1000 80-/120-MB tape drive with 80-/120-MB media

500 1.2-MB diskette drive with 1.2-MB media

500 60-MB tape drive with 40-MB media

500 1.44-MB diskette drive with 1.44-MB media

300 1.2-MB diskette drive with 360-KB media

250 360-KB double-density diskette drive with 360-KB media

250 60-MB tape drive with 10-MB media

250 1.44-MB diskette drive with 720-KB media

=======================================================
====================

Write Precompensation

Write precompensation is a process of time shifting write data bits to help

cancel out an opposite shift induced during magnetic recording. This
process increases data integrity at high data densities. The data density
increases as the diskette drive head approaches the center tracks. Write
precompensation is always ON and is always 125 ns for all data-transfer
rates (500, 300, and 250 Kb/s).

12.4 DISKETTE DRIVE CONTROL SIGNALS

The internal diskette drive has one connector. This connector supplies both
power and control signals. Table 12-3 describes the diskette drive control
signals.

Table 12-3. Diskette Drive Control Signals

=======================================================
====================
Pin Signal I/O Description
---------------------------------------------------------------------------
1 GND
2 STEP- 1 Instructs diskette drive to step the heads one
track
3 GND
4 WRITE DATA- 1 Data stream sent to diskette when WRITE GATE-
is enabled
5 GND

6 WRITE GATE- 1 Enables Write circuits

7 GND
8 TRACK 00- 0 Indicates heads are at Track 0
9 KEY
10 WRITE PROTECT- 0 Indicates media is write protected
11 GND
12 READ DATA- 0 Data-stream read from the enabled diskette
13 GND
14 SIDE 1 SELECT- 1 Selects side (Head 1)
15 GND
16 DISKETTE CHANGE- 0 Instructs the controller that the drive door
has been opened
17 LOW DENSITY- 1 Selects low density mode for dual mode drives
18 +5 VDC POWER
19 MEDIA ID- 0 Identifies media type
20 INDEX- 0 Instructs controller that media index hole is
under index sensor
21 +5 VDC POWER
22 DIRECTION IN- 1 Selects the direction the head is moving when
a step pulse is issued
23 MOTOR 1 ON- 1 Activates the drive motor for physical drive 1
24 DRIVE 0 SELECT- 1 Selects physical drive 0
25 DRIVE 1 SELECT- 1 Selects physical drive 1
26 MOTOR 0 ON- 1 Activates the drive motor for physical drive 0
=======================================================
====================

12.5 SPECIFICATIONS

Table 12-4 lists the physical and electrical specifications for the
1.44-megabyte, 1.2-megabyte and the 360-Kbyte diskette drives that are
installable in the External Storage Module.

Table 12-4. Diskette Drive Physical and Electrical Specifications

=======================================================
====================
1.44-MB 1.2-MB 360-KB
Diskette Drive Diskette Drive Diskette Drive
(excluding 5 1/4
inch adapters)
---------------------------------------------------------------------------
Drive Type 4 2 1

Size
Width 4.8 in 5.8 in 5.8 in
(10.2 cm) (14.6 cm) (14.6 cm)
Height 1.0 in 1.0 in 1.0 in
(2.5 cm) (2.5 cm) (2.5 cm)
Depth 6.056 in 8.0 in 8.0 in
(15.4 cm) (20.3 cm) (20.3 cm)

Capacity
Unformatted 2,000,000 bytes 1,600,000 bytes 500,000 bytes
Formatted 1,474,560 bytes 1,228,800 bytes 368,640 bytes

Flux reversal
density 17,434 FRPI 9875 FRPI 5876 FRPI
(Track 79) (Track 79) (Track 39)

Data transfer rate

high/low density 500/250 Kb/s 500/300 Kb/s 250 Kb/s

Sectors/track
high/low density 18/9 15/9 9

Bytes/sector 512 512 512

Seek time
Track-to-track 3 ms 3 ms 6 ms
Average 80 ms 80 ms 80 ms
Settling time 15 ms 15 ms 15 ms

Rotational speed 300 RPM +/- 1.0% 360 RPM +/- 1.0% 300 RPM +/- 1.5%

Motor start time 700 ms 500 ms 500 ms

=======================================================
====================

13.1 INTRODUCTION

The computer accommodates one hard drive. The four hard drive sizes
available are 120-MB, 84-MB, 60-MB, or 40-MB. One additional hard drive a
210-MB, 120-MB, or 84-MB may be added externally by using the optional
Desktop Expansion Base.

This chapter provides the following information about the hard drive
subsystem:

o Functional description [13.2]

o Hard drive programming [13.3]
o Connector [13.4]
o Specifications [13.5]

13.2 FUNCTIONAL DESCRIPTION

Integrated hard drives are used with this computer. The hard drive and
controller are contained in one assembly. The assembly includes the
following components:

o A sealed head-disk assembly

o A printed circuit board containing the drive electronics and the hard
drive controller

o A spindle motor

o A head-positioning mechanism

Each hard drive functions as follows:

o Connects directly to the system board for data buffering and I/O address
decoding

o Has its drive control circuitry I/O mapped into specific I/O addresses

o Transfers data to and from the host in 16-bit I/O operations

o Automatically retracts the heads and locks them in a "nondata zone" at

power down

Figure 13-1 shows a functional block diagram of the Hard Drive subsystem.

ILLUSTRATION OF Figure 13-1. Hard Drive Subsystem Functional Block Diagram

13.3 HARD DRIVE PROGRAMMING

All COMPAQ hard drive controllers are fully compatible. The addresses,
registers, and command structures are identical.

Registers

Table 13-1 lists the standard and alternate I/O addresses for the hard
drive controller.

Table 13-1. Hard Drive Controller I/O Addresses

=======================================================
====================
I/O Address Read/Write Register
-----------
1 2
---------------------------------------------------------------------------
1F0h 170h R/W Data

1F1h 171h R Error

1F1h 171h W Write Precompensation Cylinder

1F2h 172h R/W Sector Count

1F3h 173h R/W Sector Number

1F4h 174h R/W Cylinder Low

1F5h 175h R/W Cylinder High

1F6h 176h R/W Drive Select/Head

1F7h 177h R Status

1F7h 177h W Command

3F6h 376h R Alternate Status

3F6h 376h W Control

3F7h 377h R Drive Address (see NOTE)

3F7h 377h W Not used for hard drive

---------------------------------------------------------------------------
NOTE: Only bits <6..0> are resident on the hard drive controller.
Bit <7> of this I/O address is resident on the system board.
=======================================================
====================

Data (1F0h)

All data sent to the hard drive controller must pass through the Data
register. The Data register is also the port to which the sector table is
transferred during format commands. All transfers are high-speed 16-bit I/O
operations except for Error Correction Code (ECC) bytes transferred during
Read/Write Long commands.

Error (1F1h, Read Only)

The Error register contains an error status from the last command executed
by the hard drive controller. The contents of this register are valid when
both the following conditions exist:

o The error bit is set in the Status register

o The hard drive controller has completed execution of its internal

diagnostics

The contents of the Error register are interpreted as a diagnostic status

byte after the execution of a diagnostic command or when the system is
initialized.

The format of the Error register byte is shown below.

BIT FUNCTION
----------------
7 1 = A bad-block mark was detected in the requested sector
ID field

6 1 = A non-correctable data error has occurred

5 Reserved

4 1 = The requested sector ID field could not be found

3 Reserved
2 1 = The requested command has been aborted because the hard drive
status is invalid or because the command code is invalid

1 1 = Track 0 has not been found during a Recalibrate command

0 1 = The data address mark has not been found after finding the
correct ID field

Write Precompensation Cylinder (1F1h, Write Only)

The Write Precompensation Cylinder register defines the cylinder on which

write precompensation begins. Precompensation time-shifts write data bits
to help negate an opposite shift induced by the magnetic recording process.
The controller multiplies the value in the register by 4, giving the bits
of this register greater than usual value, or "weight."

BIT FUNCTION
----------------
7 1 = 29

6 1 = 28

5 1 = 27

4 1 = 26

3 1 = 25

2 1 = 24

1 1 = 23

0 1 = 22

The following tabulation gives some bit values and the resulting starting
cylinders for write precompensation:

==========================
Bit Values Starting
Cylinder
--------------------------
00000001 4

00000010 8

00000100 16

00001000 32

00010000 64

00100000 128

01000000 256
10000000 512
==========================

Sector Count (1F2h)

First, the Sector Count register defines either the number of sectors of
data to be read or written or the number of sectors per track for format
commands. If the value in this register is zero, a count of 256 sectors is
specified. The sector count is decremented as each sector is accessed. The
Sector Count register contains the number of sectors left to access when an
error occurs in a multisector operation. During the Initialize Drive
Parameters command, the Sector Count register contains the number of
sectors per track.

Sector Number (1F3h)

The Sector Number register contains the starting sector number for any hard
drive access.

BIT FUNCTION
----------------
7..0 Starting sector number

At the completion of each sector and at the end of the command, this
register is updated to reflect the last sector correctly read or the sector
on which an error occurred.

Cylinder Low and Cylinder High (1F4h and 1F5h)

The Cylinder Low and Cylinder High registers contain the starting cylinder
number for any hard drive access.

The Cylinder Low register is for the least-significant 8 bits of the 11-bit
cylinder number. The three most-significant bits of the cylinder number,
bits <10..8>, should be loaded into the Cylinder High register. Bit <2> of
the Cylinder High register is the most-significant bit of the 11-bit
cylinder address. At the completion of a command, these registers are
updated to reflect the current cylinder number.

Cylinder Low register:

BIT FUNCTION
----------------
7..0 Least-significant 8 bits of 11-bit cylinder numbers

Cylinder High register:

BIT FUNCTION
----------------
7..3 Reserved
2..0 Most-significant 3 bits of 11-bit cylinder number

Drive Select/Head (1F6h)

This register contains the parameters defined below:

BIT FUNCTION
----------------
7 Reserved

6,5 Sector size

00 = Reserved
01 = 512 Bytes/sector
10 = Reserved
11 = Reserved

4 Drive select
0 = Drive 1
1 = Drive 2

3..0 Head select number

0000 = 0 1000 = 8
0001 = 1 1001 = 9
0010 = 2 1010 = 10
0011 = 3 1011 = 11
0100 = 4 1100 = 12
0111 = 5 1101 = 13
0110 = 6 1110 = 14
0111 = 7 1111 = 15

NOTE: Setting bit <4> (Drive Select 2) to 1 when no Drive 2 is present may
cause the remaining Controller registers not to respond until Drive 1
is selected again.

Status (1F7h, Read Only)

This register contains the hard drive controller and hard drive status. The
contents of this register are updated at the completion of each command. If
the Busy bit is set, no other bits are valid. Reading this register clears
the hardware interrupt line, IRQ14.

BIT FUNCTION
----------------
7 1 = Controller is busy executing a command. Other hard drive
controller register contents are not valid until this bit is
reset (= 0).

6 1 = Drive READY- signal is active (see NOTE)

5 1 = Drive WRITE FAULT- signal is active (see NOTE)

4 1 = Drive SEEK COMPLETE- signal is active (see NOTE)

3 1 = Data request. The controller is ready for a byte or

word-length data transfer. Verify the state of this bit before
a data transfer.

2 1 = A correctable data error has occurred and has been corrected.

This condition does not terminate a multisector read operation.
1 1 = Drive INDEX- signal is active.

0 1 = Error has been detected. Examine Error register and the other
bits in this register to determine the source.

NOTE: When an error exists, the state of the signals does not change until
the error is read by the system.

Command (1F7h, Write Only)

Hard drive controller commands are written to the Command register.

Following is a list of executable commands, command codes, and necessary
command parameters.

=======================================================
====================
Command Command Code Parameters Used
---------------------- ------------------
BIT 7 6 5 4 3 2 1 0 PC SC SN CY DH
---------------------------------------------------------------------------
Initialize Drive
Parameters 1 0 0 1 0 0 0 1 N Y N N Y

Seek 0 1 1 1 X X X X N N N Y Y

Recalibrate 0 0 0 1 X X X X N N N N D

Read Sector(s) 0 0 1 0 0 0 L R N Y Y Y Y

Write Sector(s) 0 0 1 1 0 0 L R Y Y Y Y Y

Read Verify Sector(s) 0 1 0 0 0 0 0 R N Y Y Y Y

Write Verify Sector(s) 0 0 1 1 1 1 0 0 Y Y Y Y Y
Format Track 0 1 0 1 0 0 0 0 Y Y N Y Y
Execute Drive Diagnostics 1 0 0 1 0 0 0 0 N N N N D
Identify Drive 1 1 1 0 1 1 0 0 N N N N D
Read Sector Buffer 1 1 1 0 0 1 0 0 N N N N D
Write Sector Buffer 1 1 1 0 1 0 0 0 N N N N D
---------------------------------------------------------------------------
LEGEND: PC -- the Write Precompensation register
SC -- the Sector Count register
SN -- the Sector Number register
CY -- the Cylinder register
DH -- the Drive/Head register
L -- the long bit; if 1, read/write long commands are executed,
if 0, normal read/write commands are executed
R -- the retry bit; if 0, retries are enabled, if 1, retries are
disabled
Y -- indicates the register contains a valid parameter; for the
Drive/Head register, Y means both the drive and the head
parameters are used
N -- indicates the register does not contain a valid parameter for
command
D -- indicates drive parameter is valid
X -- don't care
=======================================================
====================

Alternate Status (3F6h, Read Only)

The contents of this register are similar to those of the Status register,
except in the timing and latch control of the specified signals. Reading
this register does not clear any hardware conditions.

BIT FUNCTION
----------------
7 1 = Controller is busy (executing a command). The contents of the
other registers are not valid until this bit is reset (= 0)

6 1 = READY- signal is active

5 1 = WRITE FAULT- signal is active

4 1 = SEEK COMPLETE- signal is active

3 1 = Data request. The controller is ready for a byte- or

word-length data transfer. Verify the state of this bit before
a data transfer.

2 1 = A correctable data error has occurred and has been corrected.

This condition does not terminate a multisector read operation.

1 1 = INDEX- signal is active

0 1 = Error has been detected. Examine the Error register and the
other register bits to determine source.

Drive Control (3F6h, Write Only)

The Drive Control register defines several functions of the hard drive
controller.

BIT FUNCTION
----------------
7..3 Reserved

2 1 = Resets controller
0 = Reenables the controller

1 0 = Enables interrupts
1 = Disables interrupts

0 Reserved

Drive Address (3F7h, Read Only)

This register loops back the drive select and head select addresses of the
most recently selected hard drive.
BIT FUNCTION
----------------
7 Reserved for the diskette drive controller.

6 0 = Drive WRITE GATE- signal is active.

5..2 Head select

0000 = 15 1000 = 7
0001 = 14 1001 = 6
0010 = 13 1010 = 5
0011 = 12 1011 = 4
0100 = 11 1100 = 3
0101 = 10 1101 = 2
0110 = 9 1110 = 1
0111 = 8 1111 = 0

1 0 = Drive 1 selected

0 0 = Drive 0 selected

Commands

Commands are issued to the controller by loading the pertinent registers

with the needed parameters, enabling the hard drive controller interrupt,
and then writing the command code to the Command register. Command
execution begins when a command is written to the Command register (1F7h).

Table 13-2 lists the hard drive controller commands.

Table 13-2. Hard Drive Controller Commands

=======================================================
====================
Command Value
---------------------------------------------------------------------------
Initialize Drive Parameters 91h

Seek 7xh

Recalibrate 1xh

Read Sectors with retries 20h (without retries 21h)

Read Long with retries 22h (without retries 23h)

Write Sectors with retries 30h (without retries 31h)

Write Long with retries 32h (without retries 33h)

Verify Sectors with retries 40h (without retries 41h)

Format Track 50h

Execute Controller Diagnostic 90h

Enter Low Power 94h

Enter Idle 95h

Enter Low Power and Enable/Disable time-out 96h

Enter Idle and Enable/Disable time-out 97h

Check Status 98h

Identify ECh

Read Buffer E4h

Write Buffer E8h

=======================================================
====================

Initialize Drive Parameters (91h)

The Initialize Drive Parameters command enables the host to configure the
controller to work with hard drives that have different capacities and
characteristics.

Before this command is executed the Drive Select/Head register must contain
the maximum head number and the Sector Count register must contain the
number of sectors per track.

The parameters loaded into the register prior to issuance of the command
define the drive configuration for the specified hard drive.

Seek (7xh)

The Seek command initiates a seek to the track and selects the head
specified. The hard drive need not be formatted for a seek to execute
properly. The controller supports buffered step seeks, allowing overlapped
seeks on the drives.

After initiating a seek on one hard drive, another command can be issued to
the other drive. If a new command is received for a hard drive with an
outstanding seek, then the controller waits, with the Busy bit in the
Status register active, for the seek to complete before executing the new
command. There is no time-out condition in the controller while waiting for
buffered-step seeks to complete.

Recalibrate (1xh)

The Recalibrate command moves the Read/Write heads to cylinder 0. If the

hard drive is unable to reach cylinder 0, the command is aborted with the
error bit set in the Status register and the Track 0 bit set in the Error
register.

Read Sectors (20h or 21h)

The Read Sectors command reads from 1 to 256 sectors as specified in the
Sector Count register, beginning at the specified sector. If the hard drive
is not already on the requested track, an implied seek is performed at the
stepping rate defined in the last Recalibrate command.

After reaching the specified track, the controller begins searching for the
appropriate ID field. If retries are enabled (20h), 16 revolutions are
taken before reporting an ID Not Found error. If retries are disabled
(21h), a maximum of 2 revolutions are taken. If the ID is read correctly,
the data address mark must be recognized within a fixed number of bytes, or
the Data Address Mark Not Found error will be reported.

After the data address mark is found, the data field is read and the sector
read is finished with either no error, a correctable data error, or a
non-correctable data error, depending on whether or not the ECC bytes are
correct for the preceding data field.

If an error occurs during a multiple-sector read, the read terminates at

the sector where the error occurs. The system may then read the registers
and determine what error has occurred and on which sector.

Read Long (22h or 23h)

A Read Long command returns the data field and the ECC bytes contained in
the data field of the desired sector.

If retries are enabled (22h), a maximum of 16 revolutions are taken before

the ID Not Found error is reported. If retries are not enabled (23h), only
two revolutions are taken before the ID Not Found error is reported.

During a Read Long operation, the controller does not check the ECC bytes
to determine if there has been any type of data error. The data bytes are
read out of the sector buffer at the completion of the command, which is
signaled by an interrupt. All data transfers are high-speed 16-bit
operations, all ECC byte transfers on Read Long commands are slower 8-bit
operations.

Write Sectors (30h or 31h)

The Write Sectors command writes from 1 to 256 sectors of data, as

specified in the Sector Count register, beginning at the specified sector.
If the hard drive is not already on the requested track, an implied seek is
performed at the stepping rate defined in the last Recalibrate command.

The controller begins searching for the appropriate ID field. If retries

are enabled (30h), 16 revolutions are taken before reporting an ID Not
Found error. If retries are disabled (31h), a maximum of two revolutions
are taken. If the ID is read correctly, the data loaded in the sector
buffer are written to the data field of the sector, along with the
appropriate number of ECC bytes. If an error occurs during a
multiple-sector write, the write terminates at the sector where the error
occurs. The system may then read the registers and determine what error has
occurred and on which sector.

Write Long (32h or 33h)

The Write Long command writes the data field and the ECC bytes directly
from the sector buffer; the controller does not generate the ECC bytes. All
data transfers are high-speed 16-bit operations; all ECC byte transfers on
Write Long commands are slower 8-bit operations.

If retries are enabled (32h), a maximum of 16 revolutions are taken before

the ID Not Found error is reported. If retries are not enabled (33h), only
two revolutions are taken before the ID Not Found error is reported.

Verify Sectors (40h or 41h)

This command is identical to the Read Sectors command, except that no data
are transferred back to the system and no Read Long operations are
permitted. The read procedure described in the Read command is followed and
any errors encountered are reported to the system.

This command executes retries the same as the Read command does, whether
enabled (40h) or disabled (41h).

Format Track (50h)

This command formats the track specified by the head and cylinder
parameters in the Cylinder High (1F5h) and Cylinder Low (1F4h) registers
and the Drive Select/Head register (1F6h). Once the command is issued, a
sector table is output to the Data register; additional bytes should be
loaded into the buffer until it is full (512 bytes). If the hard drive is
not already on the specified track, an implied seek is performed at the
last Recalibrate command. After the specified track is reached, the ID and
data fields are written using the sector table in the sector buffer.

The sector table contains 2 bytes per sector on the track. The first byte
is 00h if the sector is to be formatted normally, or 80h if the sector is
formatted "bad." The second byte is the logical sector number of the
sector.

As soon as the hard drive controller senses the index pulse from the hard
drive, formatting begins by writing the first physical sector with the
logical sector number in the first entry of the sector table.

Subsequent physical sectors are formatted in turn from the sector table.
The order of the sector table entries will correspond to the interleave
factor of the track. Media defects may be marked bad on a sector level,
allowing the remainder of the track to be used.

Execute Diagnostic (90h)

This command performs the internal diagnostic tests implemented by the

controller. The results of the test are reported to the Error register
immediately after execution of the command. The value in the Error register
should be viewed as a unique 8-bit code and not as the single-bit flags
previously defined.

Table 13-3 lists the error codes and the corresponding description.

Table 13-3. Hard Drive Controller Error Codes

=================================================
Error Code Description
-------------------------------------------------
01h No error detected

02h Formatter device error

03h Sector buffer error

04h ECC circuitry error

05h Controller microprocessor error

=================================================

Enter Low Power (94h)

The Enter Low Power command immediately puts the hard drive into Low Power
without waiting for the hard drive Inactivity time-out.

Enter Idle (95h)

The Enter Idle command immediately puts the hard drive into Idle from Low
Power. At this point the hard drive spins up to speed and is ready to be
accessed.

Enter Low Power and Enable/Disable Time-out (96h)

The Enter Low Power and Enable/Disable time-out command immediately puts
the hard drive into Low Power without waiting for the hard drive Inactivity
time-out. It disables the time-out if the Sector Count register value = 0
or enables the time-out if the Sector Count register value = other than 0.
The length of the hard drive Inactivity time-out is the Sector Count
register value times 5 seconds. The programmable range is from 12 (60
seconds) to 220 (1100 seconds).

Enter Idle and Enable/Disable Time-out (97h)

This command immediately puts the hard drive into Idle from Low Power. It
disables the time-out if the Sector Count register value = 0 or enables the
time-out if the Sector Count register value = other than 0. The length of
the hard drive inactivity time-out is the Sector Count register value times
5 seconds. The programmable range is from 12 (60 seconds) to 220 (1100
seconds).

Check Status (98h)

The Check Status command allows determination of status of the hard drive.
If the drive is in Low Power, the value 00h is loaded into the Sector Count
register. Otherwise the value FFh is loaded.

Identify (ECh)

The Identify command allows the host to receive parameter information from
the hard drive. When the command is issued, the controller gets the
parameters from the hard drive, stores them in the sector buffer, sets the
DRQ bit in the Status register, and allows the host to read the information
out of the sector buffer. The parameter words in the buffer are described
in Table 13-4.

Table 13-4. Identify Command Parameter Words

=======================================================
====================
Word Contents
---------------------------------------------------------------------------
0 General configuration

1 Number of fixed cylinders

2 Reserved

3 Number of heads

4 Number of unformatted bytes per physical track

5 Number of unformatted bytes per sector

6 Number of physical sectors per track

7 Number of bytes in the intersector gaps

8 Number of bytes in the sync fields

9 Number of words vendor unique status

10..19 Serial number (20 ASCII characters, 0 = not specified)

20 Controller type:
0000 Not specified
0001 Single ported single sector buffer
0003 Dual ported multiple sector buffer with a look-ahead read
all other values are RESERVED

21 Controller buffer size in 512-byte increments (0 = not specified)

22 Number of ECC bytes passed on read/write long commands

(0 = not specified)

23..26 Controller firmware revision (8 ASCII characters,

0 = not specified)

27..46 Model number (40 ASCII characters, 0 = not specified)

47..255 Reserved
=======================================================
====================

Table 13-5 gives bit definitions of the general configuration word.

Table 13-5. Configuration Word Bit Definitions

=======================================================
====================
Bit Definition
---------------------------------------------------------------------------
0 Reserved

1 1 = Hard-sectored

2 1 = Soft-sectored

3 1 = Not MFM encoded

4 1 = Head switch time greater than 15 us

5 1 = Spindle motor control option implemented

6 1 = hard drive

7 1 = Removable cartridge drive

8 1 =Transfer rate less than or equal to 5 Mb/s

9 1 =Transfer rate greater than 5 Mb/s, but less than or equal to

10 Mb/s

10 1 =Transfer rate greater than 10 Mb/s

11 1 = Rotational speed tolerance is greater than 0.5%

12 1 = Data strobe offset option implemented

13 1 = Track offset option implemented

14 1 = Format speed tolerance gap required

15 0 = Magnetic disk drive

1 = Nonmagnetic disk drive
=======================================================
====================

Read Buffer (E4h)

The Read Buffer command allows the system to read the current contents of
the controller's sector buffer. When this command is issued, the controller
goes busy, sets up the sector buffer for a read operation, sets the Data
Request bit (DRQ), and goes not busy. The system can then read as many as
512 bytes of data.

Write Buffer (E8h)

The Write Buffer command allows the system to overwrite the contents of the
controller sector buffer with any data pattern desired. When this command
is issued, the controller goes busy, sets up the sector buffer for a write
operation, sets the DRQ bit, and goes busy. The system can then write as
many as 512 bytes of data.

Hard Drive Controller Error Reporting

Figure 13-2 Shows the errors that are valid for each command.

ILLUSTRATION OF Figure 13-2. Errors that are valid

13.4 CONNECTOR

Table 13-6 shows the hard drive connector signals.

Table 13-6. Hard Drive Connector Signal Definitions

=======================================================
====================
Pin Signal Description Pin Signal Description
---------------------------------------------------------------------------
1 RESET- Reset 23 IOW- I/O Write

2 GND Ground 24 GND Ground

3 DD7 Data bit <7> 25 IOR- I/O Read

4 DD8 Data bit <8> 26 GND Ground

5 DD6 Data bit <6> 27 RSVD Reserved

6 DD9 Data bit <9> 28 RSVD Reserved

7 DD5 Data bit <5> 29 IOCHRDY I/O Channel Ready

8 DD10 Data bit <10> 30 GND Ground

9 DD4 Data bit <4> 31 IRQ Interrupt Request

10 DD11 Data bit <11> 32 IO16- 16-bit I/O

11 DD3 Data bit <3> 33 DA1 Address 1

12 DD12 Data bit <12> 34 PDIAG- Pass Diagnostics

13 DD2 Data bit <2> 35 DA0 Address 0

14 DD13 Data bit <13> 36 DA2 Address 2

15 DD1 Data bit <1> 37 CSO- Chip Select

16 DD14 Data bit <14> 38 CS1- Chip select

17 DD0 Data bit <0> 39 ACTIVE- Drive Activity

18 DD15 Data bit <15> 40 GND Ground

19 GND Ground 41 +5V +5V Logic

20 Clipped Key 42 +5V +5V Motor

21 RSVD Reserved 43 GND Ground

Track-to-Track (ms) <5
Average (ms) < 19
Maximum (ms) < 40

Physical Configuration
Cylinders 823
Heads 4
Sectors/Track 38 + 1
Bytes/Sector 512

Logical Configuration
Cylinders 820
Heads 4
Sectors/Track 38
Bytes/Sector 512
=======================================================
====================

Table 13-10. 40-Megabyte Hard Drive Physical and Electrical Specifications

=======================================================
====================
Formatted Capacity Per Drive 42.65 MB

Drives Supported 1
Drive Type(s) Supported 53

Transfer Rate (Mb/s) 12 Mb/s

Sector Interleave 1:1

Access Time (including settling)

Track-to-Track (ms) <5
Average (ms) < 19
Maximum (ms) < 40

Physical Configuration
Cylinders 1097
Heads 4
Sectors/Track 38 + 1
Bytes/Sector 512

Logical Configuration
Cylinders 548
Heads 4
Sectors/Track 38
Bytes/Sector 512
=======================================================
====================

14.1 INTRODUCTION

The computer system supports one tape drive. The 60-megabyte and the
80-/120-megabyte drives, both with compression, are available for use in
the External Storage Module or the Desktop Expansion Base. Refer to Chapter
15, "Desktop Expansion Base," or Chapter 16, "External Storage Module," for
more information.

This chapter contains the following information on the tape drive

subsystem:

o Functional Description [14.2]

o Tape Drive Commands [14.3]
o Tape Drive Connector Signals [14.4]
o Tape Drive Specifications [14.5]

14.2 FUNCTIONAL DESCRIPTION

Each tape drive consists of a microprocessor, firmware, stepper motor,

drive motor, read/write data head and control circuitry. The logic board
uses a Z8 microprocessor with 8 Kbytes of ROM to control the drive.

The tape drive logic board interfaces with the:

o Movable head, which reads and writes data

o Cartridge-installed sensor
o Write-protect sensor
o Beginning-of-Tape/End-of-Tape (BOT/EOT) sensor
o Stepper motor, which positions the head
o Drive motor, which advances and rewinds the tape

Figure 14-1 is a functional block diagram of the optional tape drive.

ILLUSTRATION OF Figure 14-1. Functional Block Diagram of the Optional Tape

Drive

14.3 TAPE DRIVE COMMANDS

The following five fundamental processes are performed by the commands sent
to the tape drive:

1. Servo Write, which initializes the tape media by writing index

information.

2. Tape Format, which writes block, sector, and track information onto the
tape. This information joins the indexing information previously
written by Servo Write. This process prepares the data areas consistent
with the Diskette Controller Chip (DCC) data format.

3. Write Data, which writes information in the same layout as standard

diskette tracks.

4. Read Data, which reads information in the same layout as the diskette
tracks.

5. Erase, which erases all information on tape (including servo and data
information).

NOTE: Tape cartridges that are preformatted for 60- and 80-/120-megabyte
capacities are recommended for use with COMPAQ drives.

The Servo Write operation is initiated by executing an Enter Format Mode

command followed by the Servo Write command. This action moves the tape to
the beginning at Block 0 and Head 0 and then writes encoding index pulses
on the tape in a streaming-write mode. These pulses are used solely by the
tape drive and are not available to the programmer.

NOTE: If the Servo Write operation is interrupted, the tape cartridge must
be fully erased before it can be used again.

The format operation for tape is similar to the format process for diskette
drives. To format the tape, the integrated fixed disk drive controller on
the system board takes control of the interface and supplies the track and
sector data for every block on the track. The data format on the tape has
the characteristics of a diskette.

The tape drive accepts commands as pulses on the step line. The number of
pulses determines the desired command. Any number of pulses not recognized
as commands are ignored. The tape drive does not recognize the step pulses
unless the DCC is programmed for a 3- or 6-ms gap between pulses.

Table 14-1. Tape Drive Command Summary

=======================================================
====================
Step Command Action
Pulses
---------------------------------------------------------------------------
2 Stop Motion This command stops tape motion. The BUSY-
line is active for 500 ms after power is
removed from the motor. If the tape is not
moving when the command is issued, the
drive returns a 2-ms pulse on BUSY-; any
tape motion command except LOAD POINT may
be terminated early by execution of this
command. Execution of the Stop Motion
command clears an active status indication
(BUSY- being active); this acts as an
acknowledgment that the host has read the
status reported.

3 Pause This command stops tape motion, moves the

tape in the logical reverse direction at
least two blocks, then stops the tape. This
command leaves the tape positioned for
reading or writing a block that has been
missed. INDEX pulses are output by the
drive while the tape is moving, but reading
and writing are disabled. BUSY- goes
inactive when tape movement stops.

4 Seek to Load Point This command causes drive to SEEK TO

TRACK 0 Load Point and rewind the tape at
50 ips to the load point position just
inside the beginning of tape (BOT)
position. The drive automatically executes
a SEEK TO LOAD POINT command whenever power
is applied to the drive and a cartridge is
installed, or whenever a new cartridge is
inserted into the drive. BUSY- is active
while executing this command.

5 Move Tape Physically This command moves the tape at 60 ips

Forward toward physical end of tape (EOT) position.
BUSY- is active during execution of this
command. While tape is in motion, the drive
will output index pulses at a rate
equivalent to that of data blocks passing
beneath the head. The tape is at EOT when
this command is issued, and the drive
responds with a 2-ms pulse on the BUSY-
line.

---------------------------------------------------------------------------
Step Command Action
Pulses
---------------------------------------------------------------------------
6 Move Tape Physically This command moves the tape at 60 ips
Reverse toward the Physical BOT position. BUSY- is
active during the Reverse execution of this
command. If the tape is at BOT when this
command is issued, the drive responds with
a 2-ms pulse on the BUSY- line.

7 Report Normal This command causes drive to activate the

Completion BUSY- line if the previous TAPE MOTION
command (MOVE TAPE PHYSICALLY FORWARD or
REVERSE) was completed normally. If the
command did not complete normally, BUSY-
remains inactive.

8 Report Drive Causes drive to activate the BUSY- line if

the drive is present and capable of
interpreting and responding to the command.
If the drive is not present or unable to
recognize the command, BUSY- remains
inactive.

9 Report End of Tape Causes the drive to activate BUSY- if the

head is over the EOT position. If the head
is anywhere else, BUSY- remains inactive.

10 Report Beginning Causes the drive to activate BUSY- if the

of Tape head of Tape is over the BOT position. If
the head is anywhere else, BUSY- remains
inactive.

11 Report Cartridge Causes the drive to activate BUSY- if the

cartridge is installed in the drive. If the
cartridge is not present, BUSY- remains
inactive.

12 Report Track Found Causes drive to activate the BUSY- line if

the head is positioned over the track
specified in the last SEEK TRACK command.
If the head is not over the track, BUSY-
remains inactive. This status remains valid
until the next TAPE MOTION command is
issued.

---------------------------------------------------------------------------
Step Command Action
Pulses
---------------------------------------------------------------------------
13 Report New Cartridge Causes drive to activate the BUSY- line if
Present the Cartridge Present indication on the
drive has been active, gone inactive, and
come back active again. If this sequence
has not occurred, BUSY- remains inactive.
If this status is TRUE, it will be cleared
by executing this command.

14 Move Tape Logically Initiates tape movement in the direction

Reverse that logically does not allow reading or
writing of data to reverse the tape. The
physical direction of tape motion depends
on what track the heads are over because of
the serpentine track pattern used on the
tape. BUSY- is active during execution of
this command. There will be no response
from the drive if the heads are logically
at the end of the track.

15 Move Tape Logically Initiates tape movement in the direction

Forward that allows reading or writing of data to
the tape. The physical direction of tape
motion depends on what track the heads are
over because of the serpentine track
pattern used on the tape. BUSY- is active
during execution of this command and index
pulses continue to be produced as long as
the head is track following. There will be
no response from the drive if the heads are
logically at the beginning of the track.

16 Enter Format Mode Puts the drive in the mode where INDEX
pulses are generated at both the beginning
and end of each tape block. The drive
issues a 2-ms pulsed response to this
command.

17 Enter Normal Mode Puts the drive in the mode where INDEX
pulses are generated only at the beginning
of each tape block. The drive issues a 2-ms
pulsed response to this command.

18 Report Expanded The drive gives a positive (TRUE) 2-ms

Instruction Set pulsed response.

---------------------------------------------------------------------------
Step Command Action
Pulses
---------------------------------------------------------------------------
19 Status The drive gives a positive (TRUE) 2-ms
pulsed response. The user responds with "N"
step pulses to query the inserted tape
cartridge.

N = 4 through 11 For one group of commands (N = 4, 5, 6, 7,

8, 10, 11), the drive gives a positive
(TRUE) latched response if the
cartridge/drive type is TRUE. The drive
gives no response if the answer is FALSE.

These commands are described as follows:

5 True High-density (>6400 bpi) tape installed

False Low-density (6400 bpi) tape installed

6 True 145/245/285 drive

False 110/125/225 drive

7 True DC2000 Long Length capability

False No DC2000 Long Length capability

8 True Write Enable gated with Drive Select

False Write Enable not gated with Drive Select

10 True Dual-speed drive installed

False Dual-speed drive not installed

11 True Dual-speed drive set to standard data

transfer rate
False Dual-speed drive set to optional data
transfer rate

=======================================================
============

---------------------------------------------------------------------------
Step Command Action
Pulses
---------------------------------------------------------------------------
19 Status (Continued)
N = 12 through 16 For a second set of commands (N = 12, 13,
14, 15, 16), the drive will give a
multiple-bit response. After receipt of the
initial commands (19 step pulses), the
drive will give a positive (TRUE) 2-ms
pulse response. The user responds with "N"
step pulses to query the desired status.
The drive will then give a positive (TRUE)
latched response, indicating the start of
the reporting sequence. The user will then
send a Pause/Continue (three step pulses)
command to increment the drive to the next
bit in the sequence, which is bit <0> (LSB)
of the status response. A positive (TRUE)
latched response on the BUSY- line
indicates a "1" bit, while a negative
(FALSE) response indicates a "0" bit. The
user continues to read the status bits and
to increment to the next bit with the
Pause/Continue Command until all of the
status bits have been reported. The number
of bits in the response is dependent upon
the command being used.

After the last bit of the status has been

received, a Pause/Continue command is sent
to advance to the terminating state of the
command. The drive will give a positive
(TRUE) response to indicate the end of the
reporting sequence. This confirms that the
communication is still active after a
string of zeros has been sent. The final
latched response can then be cleared with a
Stop (two step pulse) command.

Commands N = 12 through 16 are described on

the below.
---------------------------------------------------------------------------
Step Command Action
Pulses
---------------------------------------------------------------------------
19 Status (Continued)
N = 12 Provides the drive type and the tape format
in two 5-bit responses as follows:

Drive Type

===========================================
B4 B3 B2 B1 B0 Drive Type
-------------------------------------------
0 0 0 0 0 110/210

0 0 0 0 1 120/220

0 0 0 1 0 125/225

0 0 0 1 1 145/245

0 0 1 0 0 146/246

0 0 1 0 1 165/265

0 0 1 1 0 Reserved

: : : : :

24-track)

0 1 0 1 0 Reserved
: : : : :
1 1 1 1 1 Reserved
===========================================

BIT FUNCTION
----------------
7 1 = Cartridge installed, long length

6 1 = DC2000 cartridge

5 1 = New cartridge inserted

4 1 = Track found

3 1 = Cartridge present

2 1 = Tape at BOT
1 1 = Tape at EOT

0 1 = Normal completion

===========================================
N = 14 This command has an 8-bit response:
Dec. B7 B6 B5 B4 B3 B2 B1 B0
-------------------------------------------
00 0 0 0 0 0 0 0 0
Error: Normal status -- no error already
reported

01 0 0 0 0 0 0 0 1
Error: Tape format not allowed for this
drive

02 0 0 0 0 0 0 1 0
Error: Undefined tape format encountered.

03 0 0 0 0 0 0 1 1
Error: Drive failed to reach operating
speed.

04 0 0 0 0 0 1 0 0
Error: After reaching speed, tape speed
below error limit.

07 0 0 0 0 0 1 1 1
Error: No tape in cartridge when attempted
load point.

08 0 0 0 0 1 0 0 0
Error: Failed to find the load point hole
in load point.

09 0 0 0 0 1 0 0 1
Error: Illegal cartridge found on load
point.

10 0 0 0 0 1 0 1 0
Error: Load point stall occurred.

11 0 0 0 0 1 0 1 1
Error: Tape run-off in load point.

12 0 0 0 0 1 1 0 0
Error: BOT double hole encountered while
searching for ID bursts.

13 0 0 0 0 1 1 0 1
Error: Illegal attempt to servo-write a
300 foot tape.

14 0 0 0 0 1 1 1 0
Error: Failed conventional edge of tape
test.

15 0 0 0 0 1 1 1 1
Error: Failed head travel test.

16 0 0 0 1 0 0 0 0
Error: Invalid servo-write attempt

255 1 1 1 1 1 1 1 1
Error: No errors since processor power-up
or reset.
===========================================

BIT FUNCTION
----------------
7 Reserved

6 Track-Following Limit
0 = Limiter ON
1 = Limiter OFF

5 Format Mode
0 = Normal mode
1 = Format mode

4 Head Positioner Lock

0 = Lock OFF
1 = Lock ON

3 Mapper State
0 = Mapper OFF
1 = Mapper ON

2..0 Transfer Rate

000 = 250 Kb/s
001 = 500 Kb/s
010 = Reserved
011 = 1.0 Mb/s

19 Status (Continued)
N = 16 Provides firmware revision level:
This command gives a 10-bit response for
the firmware revision level. The revision
level is defined by a two-digit code, which
can contain letters, numbers or both. The
most-significant digits are represented by
bits <9..5>. The least-significant digits
are represented by bits <4..0>.

===========================================
Bits Bits
9..5/ 9..5/
4..0 Digit 4..0 Digit
-------------------------------------------
00000 0 10000 G
00001 1 10001 H
00010 2 10010 J
00011 3 10011 K
00100 4 10100 L
00101 5 10101 M
00110 6 10110 N
00111 7 10111 P
01000 8 11000 Q
01001 9 11001 R
01010 A 11010 S
01011 B 11011 T
01100 C 11100 U
01101 D 11101 V
01110 E 11110 W
01111 F 11111 X
===========================================

---------------------------------------------------------------------------
Step Command Action
Pulses
---------------------------------------------------------------------------
20 Seek Track 0 Initiates tape motion at 50 ips and
positions the head over Track 0. While the
positioning operation is taking place,
INDEX pulses are inhibited. Once the
destination track is reached, INDEX pulses
are reenabled and tape motion continues at
50 ips to allow reading or writing.

21 Seek Track 1 Initiates tape motion at 50 ips and

positions the head over Track 1. While the
positioning operation is taking place,
INDEX pulses are inhibited. Once the
destination track is reached, INDEX pulses
are reenabled and tape motion continues at
50 ips to allow reading or writing.

22 Seek Track 2 Initiates tape motion at 50 ips and

positions the head over Track 2. While the
positioning operation is taking place,
INDEX pulses are inhibited. Once the
destination track is reached, INDEX pulses
are reenabled and tape motion continues at
50 ips to allow reading or writing.

23 Seek Track 3 Initiates tape motion at 50 ips and

positions the head over Track 3. While the
positioning operation is taking place,
INDEX pulses are inhibited. Once the
destination track is reached, INDEX pulses
are reenabled and tape motion continues at
50 ips to allow reading or writing.

24 Seek Track 4 Initiates tape motion at 50 ips and

positions the head over Track 4. While the
positioning operation is taking place,
INDEX pulses are inhibited. Once the
destination track is reached, INDEX pulses
are reenabled and tape motion continues at
50 ips to allow reading or writing.

---------------------------------------------------------------------------
Step Command Action
Pulses
---------------------------------------------------------------------------
25 Seek Track 5 Initiates tape motion at 50 ips and
positions the head over Track 5. While the
positioning operation is taking place,
INDEX pulses are inhibited. Once the
destination track is reached, INDEX pulses
are reenabled and tape motion continues at
50 ips to allow reading or writing.

26 Seek Track 6 Initiates tape motion at 50 ips and

positions the head over Track 6. While the
positioning operation is taking place,
INDEX pulses are inhibited. Once the
destination track is reached, INDEX pulses
are reenabled and tape motion continues at
50 ips to allow reading or writing.

27 Seek Track 7 Initiates tape motion at 50 ips and

positions the head over Track 7. While the
positioning operation is taking place,
INDEX pulses are inhibited. Once the
destination track is reached, INDEX pulses
are reenabled and tape motion continues at
50 ips to allow reading or writing.

28 Seek Track "N" Where N = Track Number + 4 and where Track

Number = 0 to 19. The drive shall give a
positive (TRUE) 2-ms pulsed response. The
user shall respond with "N" step pulses
indicating the desired tape track the
device will seek. Tape motion will begin,
BUSY will go true, and INDEX pulses will be
sent when the tape head is track-following
on the desired track.

---------------------------------------------------------------------------
Step Command Action
Pulses
---------------------------------------------------------------------------
29 Erase Tape Moves the tape to the LOAD POINT with the
head at the edge of the tape and then
erases the entire tape. If a cartridge is
not present or is write-protected, this
command will be ignored. BUSY- is active
during execution of this command and a
continuous 250-KHz clock is transmitted
over the Read Data Line. Immediately prior
to issuing this command, an ENTER FORMAT
MODE command must be issued. If not
preceded by the ENTER FORMAT MODE command,
the erase tape command will be ignored.

30 Diagnostic Type "N" The drive will give a positive (TRUE) 2-ms
pulsed response. The user will respond to
Type "N" with "N" step pulses indicating
the type of action to be taken by the
drive. The drive will then give a positive
(TRUE) response indicating receipt of the
command.

Command N = 4 turns the margin verify

circuit OFF. The circuit is also turned off
when the cartridge is removed from the
drive.

Command N = 11 requires a third user

response "R" (transfer rate) for
completion. This command causes the drive
to report the search range of the edge of
tape algorithm that is in use. This allows
test equipment to compute the distance the
cam is set below the edge of tape.

The drive will go active and send a number

of INDEX pulses equal to the number of
temporary bursts taken to locate the edge
of tape. Once the INDEX pulses have been
sent, the drive returns to an inactive
state. This is the default mode which does
not allow reading and writing.

=======================================================
============
"N" Command Description
-------------------------------------------------------------------
1 Invalid command
2 Terminate command sequence
3 Invalid command
4 Margin verify off
5 Margin verify on
6 Lock head positioner
7 Step head up
8 Step head down
9 Unlock head positioner
10 Indicate edge of tape algorithm
11 Set drive transfer rate:
1 = Invalid
2 = Terminate command
3 = Invalid
4 = 250 Kb/s
5 = 500 Kb/s
6 = Reserved Kb/s
7 = 1.0 Mb/s
12 Reserved
13 Enable track following limit
14 Disable track following limit

=======================================================
============

31 Servo Write Moves the tape to the LOAD POINT with the
cartridge head over Track 0, then writes
the servo information used for head
positioning on all 20 tracks. If a
cartridge is not present or is
write-protected, this command will be
ignored. BUSY- is active during execution
of this command. Immediately prior to
issuing this command, an ENTER FORMAT MODE
command must be issued. If not preceded by
the ENTER FORMAT MODE command, the SERVO
WRITE command will be ignored. The drive
will only execute this command when a
DC2000 cartridge is installed (cartridge
presence status is true).

32 Recalibrate This command does nothing but issue a 14-ms

pulse on the BUSY- line to mimic the
operation of a diskette drive. No tape
drive action is taken.
=======================================================
====================

Tape Drive Directory Information

All blocks after "0" and "1" on Track 0 contain directory and file
information. If the backup spanned multiple directories, the first sector
of the Save Set would contain directory information. This information tells
the tape utility which directories to create on the destination disk during
the tape restore process. These sectors are marked as allocated in the File
Allocation Table.

Table 14-2 lists the format of the directory information.

Table 14-2. Directory Information Format

============================================
Function Bytes
--------------------------------------------
Directory name 1 78

Last entry flag 2

Reserved 2

Directory name N 78

Last entry flag 2

Reserved 2
============================================

Table 14-3 lists the directory information parameters.

Table 14-3. Directory Information Parameters

=======================================================
====================
Parameter Description
---------------------------------------------------------------------------
Directory name Directory path name, padded with zeros to 78 bytes,
resulting in a standard null-terminated string

Last entry flag Indicates status of directory name list

1 = last entry in directory list
0 = more entries in directory list

Reserved --
=======================================================
====================

Only the pathnames of the lowest-level subdirectories are saved. All

intermediate subdirectories can be recreated from these.

Example: The following directory names are generated for the directory
shown in Figure 14-2:

\DOS
\TOOLS\EDITOR
\MISC\REPORTS\TEMP
\MISC\MEMOS
\MISC\EXPENSE

ILLUSTRATION OF Figure 14-2. Sample Directory

Tape Drive File Information

Following the directory information are the sectors containing the file
information. The first sector of each file contains a header, which
contains various information about the file.

Table 14-4 describes the file information.

Table 14-4. File Information

=======================================================
====================
Function Bytes
---------------------------------------------------------------------------
Header signature (55h, AAh) 2

Filename 108

File attribute 2

Original file time 2

Original file date 2

File size (in bytes) 4

Backup time 2

Backup date 2

Aux file attribute 1 2

Aux file attribute 2 2

=======================================================
====================

The tape file information parameters are given in Table 14-5.

Table 14-5. Tape File Information Parameters

=======================================================
====================
Parameter Description
---------------------------------------------------------------------------
Header signature The 2-byte header signature is 55h, AAh. This
signature is used to identify the header or
separate it from the rest of the tape information.

Filename The filename may be up to 107 characters in length,

padded with zeros to 108 bytes, resulting in a
standard null-terminated string. No structure is
imposed on the filename other than maximum length,
but both the TAPE Utility Version 2.1 and 2.2
expect a DOS-style path name (without a drive
letter).

File attribute This word value is used by the TAPE Utility to

retain the original attributes of the file as
specified by the operating system. For MS-DOS and
MS OS/2, only the low-order byte is used.

Original date/time Original date/time of the file.

File size 32-bit file size (in bytes).

Backup time and date The date and time the file was backed up. This value
is the same as the corresponding value in the
headers of all the other files that were part of
the same backup.

Aux file attribute 1 Used with MS-DOS only. Not used in COMPAQ TAPE
Utility prior to Version 1.10. In Version 1.10 and
later: Bit <0>, if set (= 1), means that this file
is continued on the next tape. In this case, the
file size indicates only the portion of the file
that is on this tape.

Bit <1>, if set (= 1), means that this file is

continued from the previous tape. In this case, the
file size indicates only the portion of the file
that is on this tape. Bit <1>, set (= 1) with
bit <0> reset (= 0), indicates the last portion of
the file.

Aux file attribute 2 Reserved, must be "0".

=======================================================
====================

14.4 TAPE DRIVE CONNECTOR SIGNALS

Tape drives use the same cable, connectors, and pin arrangements as the
diskette drives use, for the connections to the main circuit board and the
DC power supply.

The signal functions are different, and special software drivers are used
to control the tape drive. Table 14-6 describes the signal functions.

Table 14-6. Tape Drive Signal Functions

INDEX- Indicates to the system board that one block has

passed

READ DATA- The data stream of data and clock pulses from the
Tape Drive

STEP- Pulses give commands to the tape drive

BUSY- Indicates to the system board that the tape drive

is still executing a command

WRITE DATA- This stream of data is written to the tape when

WRITE GATE- is enabled

WRITE GATE- Enables the drive-logic disk-write circuits so data

from the WRITE DATA- signal are written
WRITE PROTECT- Indicates to the system board that the cartridge in
the drive is write-protected
=======================================================
====================

14.5 SPECIFICATIONS

The following tables show the physical and electrical specifications for
the tape drives.

Table 14-7. 60-Megabyte Tape Drive Specifications

=======================================================
====================
Physical Size:
Width 5.7 in (14.5 cm)
Height 1.0 in (2.54 cm)
Depth 8.0 in (20.3 cm)
Weight 1.7 lb (0.77 kg)

Formatted capacity (with ECC) 60.9 MB

Flux reversal density 10,000 FRI

Bit density Data 10,000 bpi

Transfer rate 500 Kb/s

Head positioning time:

Adjacent tracks 250 ms
Move (worst case) 1 sec

Tape speed:
Read/Write 50 ips
Rewind/Fast Forward 60 ips

Tape end-to-end
positioning time: DC1000 DC2000
Read/Write 44 sec 49 sec
Forward/Reverse 35 sec 35 sec

Track density 128 TPI

Number of tracks 20

Blocks/track 124/186

Sectors/block 16 Data + 2 ECC

Bytes/sector 1024
=======================================================
====================

Table 14-8. 80-/120-Megabyte Tape Drive Specifications

=======================================================
====================
Physical Size:
Width 5.7 in (14.5 cm)
Height 1.0 in (2.54 cm)
Depth 8.0 in (20.3 cm)
Weight 1.7 lb (0.77 kg)

Formatted capacity (with ECC) 81.7/123.7 MB (with ECC)

Flux reversal density 11,600 FRI

Bit density 11,600 bpi

Data Transfer rate 500 Kb/s (80-MB) 1Mb/s (120-MB)

Head positioning time:

Adjacent tracks 250 ms
Move (worst case) 5.5 sec

Tape speed: 500 Kb/s 1 Mb/s

Read/Write 43 ips 86 ips
Rewind/Fast Forward 86 ips 86 ips

Tape end-to-end
positioning time: DC 2080 DC 2120
Read/Write 29 sec 43 sec
Forward/Reverse 29 sec 43 sec

Track density 128 TPI

Number of tracks 32

Blocks/track 86/130

Sectors/block 29 Data + 3 ECC

Bytes/sector 1024
=======================================================
====================

15.1 INTRODUCTION

The Desktop Expansion Base (Figure 15-1) provides the COMPAQ LTE Lite with
full desktop computer capabilities. The COMPAQ LTE Lite system unit easily
plugs (docks) into the Desktop Expansion Base using a 198-pin connection.
When the system unit is connected and the Desktop Expansion Base is turned
on, any optional boards or peripherals installed in or connected to the
Desktop Expansion Base are fully integrated into the system unit.

ILLUSTRATION OF Figure 15-1. Desktop Expansion Base with COMPAQ LTE Lite
Installed and External Keyboard and Video Monitor Attached

The Desktop Expansion Base provides the following functions:

o Provides full peripheral access to the functions and features of the

COMPAQ LTE Lite.
o Provides mounting bays for a diskette drive (1/3 height) and a tape drive
(1/2 height).

o Provides two full size 8-/16-bit ISA expansion slots.

o Duplicates the parallel, serial, pointing device (mouse), and external

VGA-compatible monitor connectors on the COMPAQ LTE Lite system unit and
adds an external keyboard interface, allowing such devices to be left
attached to the Desktop Expansion Base when the system unit is detached.

o Duplicates the AC Adapter by providing DC power to the system unit and by

fast charging the system unit battery.

o Automatically adjusts to any input line voltage from 90 to 264 VAC, 50 or

60 Hz.

o Provides a convenient, sturdy mounting base for an external

VGA-compatible monitor.

15.2 FUNCTIONAL DESCRIPTION

Figure 15-2 shows a functional block diagram of the Desktop Expansion Base.
The following paragraphs provide a discussion of the functions of the
Desktop Expansion Base.

Mass Storage Device Support

The Desktop Expansion Base provides mounting bays for two mass storage
devices; one 1/3 height device (such as a diskette drive) and one 1/2
height (such as a tape drive). When a diskette drive is installed in the
Desktop Expansion Base, an A/B switch on the rear panel allows the
selection of that drive as being either drive A (boot disk) or drive B.

ISA Expansion Bus Support

The Desktop Expansion Base can accommodate two full-size 8-/16-bit ISA
expansion boards. A detailed description of ISA expansion bus operation is
provided in Chapter 5, "Expansion Support."

ILLUSTRATION OF Figure 15-2. Desktop Expansion Base Block Diagram

Power Supplies

The Desktop Expansion Base contains two separate power supplies. One power
supply provides DC power and battery charging for a docked system unit.
This power supply is active as long as the Desktop Expansion Base is
plugged into an AC outlet and in effect replaces the AC Adapter of the
system unit.

The second power supply provides DC power to the fan, external keyboard,
pointing device, and any ISA expansion boards and mass storage devices that
may be installed in the Desktop Expansion Base. This power supply is
controlled by the power switch at the front of the Desktop Expansion Base.
When this power switch is turned on, a Power On signal is applied to the
system unit (if docked), logically overriding the power switch on the
system unit and forcing the system unit to a powered up condition.

Connectors

When a COMPAQ LTE Lite system unit is docked with the Desktop Expansion
Base, a 198-pin connection is made that allows the transfer of DC-power and
ISA expansion bus signals, and allows duplication of the following I/O
interfaces of the system unit:

o Serial interface
o Parallel interface
o Keyboard interface
o VGA monitor interface

For pinouts of the 198-pin External Options Interface Connector and the
duplicated connectors refer to Appendix B, "Connectors."

ISA Expansion Bus Connectors

The Desktop Expansion Base provides two full size ISA expansion bus slots
to accommodate 8-/16-bit ISA expansion boards. Figure 15-3 shows the ISA
connectors and pinouts for these slots. Refer to Chapter 5, "Expansion
Support," for a description of the expansion bus signals.

ILLUSTRATION OF Figure 15-3a. ISA Expansion Bus Connector (Part 1 of 2)

ILLUSTRATION OF Figure 15-3b. ISA Expansion Bus Connector (Part 2 of 2)

Switches

A DIP switch located on the system board of the Desktop Expansion Base
provides control of optional mass storage devices. Table 15-1 lists the
functions of the DIP switch positions.

Table 15-1. DIP Switch Settings

=======================================================
====================
Switch Function Setting
---------------------------------------------------------------------------
1 Hard Drive Enable OFF = Disabled
ON = Enabled

2 Hard Drive IRQ Select OFF = IRQ10

ON = IRQ11

3 Reserved n/a

4 Diskette Interface Used OFF = Not used

ON = Diskette/tape installed

5 A/B Switch Enable

OFF = Enabled
ON = Disabled
=======================================================
====================
16.1 INTRODUCTION

The External Storage Module and External Options Adapter combination

permits the addition of an external diskette or tape drive. The External
Storage Module and External Options Adapter combination connect to the
198-pin External Options Connector on the rear panel of the computer. The
External Storage Module has its own AC power supply.

The External Storage Module (Figure 16-1) supports one of the following
options:

o A one-third height 5 1/4-Inch 1.2-megabyte diskette drive

o A one-third height 5 1/4-Inch 360-Kbyte diskette drive
o A one-third height 80-/120-megabyte Tape Drive
o A one-third height 60-megabyte Tape Drive

ILLUSTRATION OF Figure 16-1. External Storage Module

If a diskette drive is installed in the unit, a switch on the External

Storage Module (Figure 16-2) allows the user to configure the external
diskette drive as drive A (bootable) or as drive B.

ILLUSTRATION OF Figure 16-2. A/B Diskette Drive Selection Switch

16.2 FUNCTIONAL DESCRIPTION

A block diagram for the External Storage Module is shown in Figure 16-3.
The External Storage Module includes a self-contained AC power supply and
supports one diskette or tape drive.

ILLUSTRATION OF Figure 16-3. Block Diagram of the External Storage Module

16.3 EXTERNAL STORAGE MODULE CONNECTORS

The External Storage Module comes with a 24-inch long cable and a 28-pin
SCSI-type connector that attaches to the External Options Adapter. Signal
descriptions are given in Table 16-1.

Table 16-1. 28-Pin SCSI-Type Connector Signals

=======================================================
====================
Pin I/O Signal Name Function
---------------------------------------------------------------------------
1..5 GND Ground

6 I STEP- Tells the diskette drive to step the heads

one track
7 I DIR IN- Selects the direction in which to move the
head when a step pulse is issued

8 I MOTOR- Activates the drive motor

9 I DSEL-EV- External installed diskette drive select

10 I INDEX- Indicates to the diskette drive controller

that the diskette index hole is under the
sensor

11 O DSK CHNG- Indicates to the diskette drive controller

that the drive door has been opened and
that different diskette may have been
installed

12 I DR-SEL4- Allows selection of an installed tape drive

13 O LOWDENMEDIA- Indicates low-density diskette

14 I LOWDEN- When high-capacity drives are in use,

selects HIGH (500 Kb/s) or LOW (300 Kb/s)
mode

15 I HIGHDEN Select for high density diskette drives

16 -- GND Ground

17 O BOOT Causes the diskette drive installed in the

External Storage Module to be recognized as
Drive A or Drive B

18 O EXT-FLPY- Indicates that diskette drive is installed

in the External Storage Module

19 I HEAD1 SEL- Selects side one head on the diskette drive

20 O RDATA- The data stream read from the diskette drive

containing CLOCK and DATA signals

21 O WRTPROT- Indicates to the diskette drive controller

that the media is write-protected

22 O TRACK 0- Indicates to the diskette drive controller

that the heads are at track 0

23 I WRTGATE- Enables the diskette drive write circuits

so that the WRTDATA signal is written

24 I WRTDATA- The data stream to be written to the

diskette drive when WRTGATE- is enabled

25..28 -- GND Ground

=======================================================
====================
The connector used to connect the tape or diskette drive to the External
Storage Module has 34-pins. The signals found in the 34-pin connector are
described in Table 16-2.

Table 16-2. 34-Pin Connector Signals

=======================================================
====================
Pin Signal Name Pin Signal Name
---------------------------------------------------------------------------
1 GND 18 DIRIN-

2 LOWDEN- 19 GND

3 GND 20 STEP-

4 LOWDENMEDIA- 21 GND

5 GND 22 WRTDATA-

6 DRVSEL4- 23 GND

7 GND 24 WRTGATE-

8 INDEX- 25 GND

9 GND 26 TRACK 00-

10 Reserved 27 GND

11 GND 28 WRTPROT-

12 DSEL-EV- 29 GND

13 GND 30 RDATA-

14 Reserved 31 GND

15 GND 32 HEAD1SEL-

16 MOTOR- 33 GND

17 GND 34 DSK CHNG-

=======================================================
====================

16.4 SPECIFICATIONS

Table 16-3 gives the specifications for the External Storage Module.

Table 16-3. External Storage Module Specifications

=======================================================
====================
Unit size
Width 6.5 in (16.5 cm)
Height 2.3 in (5.8 cm)
Depth 12.0 in (30.5 cm)

Weight
Without storage device 2.6 lb (1.2 kg)
With drive installed 4.5 lb (2.0 kg)

Power requirements
Input voltage 110 to 240 VAC
Output power 5 VDC at 0.6A continuous
0.8A peak (100 ms)
12 VDC at 1.0A continuous
2.5A peak (1.8 sec)

Temperature
Operating 50oF to 95oF (10oC to 39oC)
Non-operating -22oF to 140oF (-30oC to 60oC)

Relative humidity (non-conducting)

Operating 20% to 80%
Non-operating 5% to 95%

Shock
Operating 5 G 0.5 sine, 11 ms, any axis
Non-operating 30 G 0.5 sine, 11 ms, any axis

Vibration (2-hour duration)

Operating 0.25 G 5 to 500 Hz 0.5 oct/min sweep
Non-operating 0.50 G 5 to 500 Hz 0.5 oct/min sweep

Heat output Varies according to option(s) installed

Noise level Varies according to option(s) installed

Maximum altitude above

mean sea level
Operating 10,000 ft (3048 m)
Non-operating 30,000 ft (9144 m)

Agency compliances UL, CSA, TUV, FCC

=======================================================
====================

16.5 EXTERNAL OPTIONS ADAPTER

The External Options Adapter is required when connecting the External

Storage Module to the computer. The External Options Adapter has three
separate connectors. The 198-pin connector plugs into the External Options
Connector on the rear of the computer. The 28-pin SCSI type connector
accepts the connector on the cable from the External Storage Module. The
third connector is the External keyboard connector. Figure 16-4 shows the
External Options Adapter.

ILLUSTRATION OF Figure 16-4. External Options Adapter

Specifications

Table 16-4 provides physical specifications for the External Options

Adapter.

Table 16-4. External Options Adapter Specifications

======================================================
Dimensions
Width 2.65 in (7.7 cm)
Height 2.40 in (6.1 cm)
Depth 0.86 in (2.8 cm)

Weight 0.15 lbs (2.4 oz)

======================================================

APPENDIX A. ERROR MESSAGES

The following tables list the error codes and a brief description of the
probable source of the error. Your computer will generate only those codes
applicable to your configuration and options.

Power-On Self-Test Messages

Table A-1 lists error messages that may occur as part of the Power-On
Self-Test (POST).

Table A-1. Power-On Self-Test Messages

=======================================================
====================
Message Beeps Probable Cause
------------------------------------------------------------------------
(Two very short beeps) 2 Short Invalid time or date

RESUME = "F1" key 2 Very Short Power-on successful

No visible message None Any failure

101-I/O ROM error 1 Option ROM checksum

101-ROM error 1 Long, 1 Short System ROM checksum

102-System Board Failure None DMA or timers

102-System or Memory
Board failure None High-order addresses

162-System Options Error 2 Short No diskette drives or

mismatch in drive types

162-System Options Not Set 2 Short System SETUP

163-Time & Date Not Set 2 Short Invalid time or date

164-Memory Size Error 2 Short Memory size discrepancy

167 RTC Lost Power 2 Short Clock/Calendar battery

XX000Y ZZ 201-Memory Error None RAM failure

XX000Y ZZ 203-Memory Error None RAM failure

---------------------------------------------------------------------------
NOTE: XX000Y ZZ = Address (XX), byte (Y), data bit (ZZ) of failed memory
test
---------------------------------------------------------------------------
Message Beeps Probable Cause
---------------------------------------------------------------------------
205-Cache Memory Failure None Cache Memory Failure

301-Keyboard Error None Keyboard failure

301-Keyboard Error or Test

Fixture Installed None Keyboard test fixture

303-Keyboard Controller
Error None Keyboard controller

304-Keyboard or System
Unit Error None Keyboard interface

601-Diskette Drive
Controller Error None Diskette drive controller

602-Diskette Drive Boot

Record Error None Diskette drive does not
have a valid boot record

605-Diskette Drive Type

Error None Wrong drive type used in
SETUP utility

610-External Storage Device

Failure None External Storage Module
connected but turned off

702-Coprocessor Detection
Error None Configuration error

1125-Internal Serial Port

Failure None Configuration error

1150 Comm Port Error 2 Short Configuration error

1771-Primary Hard Drive

Port Address Assignment
Conflict 2 Short Internal and external
Hard Drive controllers
assigned to primary
address
---------------------------------------------------------------------------
Message Beeps Probable Cause
---------------------------------------------------------------------------
1780-Hard Drive 0 Failure None Hard drive format error

1781-Hard Drive 1 Failure None Hard drive format error

1782-Hard Drive Controller

Failure None Hard drive controller
error

1790-Hard Drive 0 Error None Defective Hard drive

1791-Hard Drive 1 Error None Defective Hard drive

XX000Y ZZ Parity Check 2 None Parity RAM failure

Audible 1 Short Power-on successful

Audible 2 Short Power-on successful

(RESUME = "F1" KEY) None As indicated to continue

---------------------------------------------------------------------------
XX000Y ZZ = Address (XX), byte (Y), data bit (ZZ) of failed memory test
=======================================================
====================

Diagnostics Error Messages

The following tables list error messages that may occur during Diagnostics
testing.

Processor

Table A-2 lists error messages that relate to the system processor or to
other system board devices.

Table A-2. Processor Error Messages

=======================================================
====================
Message Probable Cause
---------------------------------------------------------------------------
101-01 CPU test failed

101-02 32-Bit CPU test failed

101-91 Multiplication test failed

:
101-94
---------------------------------------------------------------------------
102-01 Numeric coprocessor initial status word incorrect

102-02 Numeric coprocessor initial control word incorrect

102-03 Numeric coprocessor tag word not all ones

102-04 Numeric coprocessor tag word not all zeros

102-05 Numeric coprocessor exchange command failed

102-06 Numeric coprocessor masked exception incorrectly handled

102-07 Numeric coprocessor unmasked exception incorrectly handled

102-08 Numeric coprocessor wrong mask bit set in Status register

102-09 Numeric coprocessor unable to store real number

102-10 Numeric coprocessor real number calculation test failed

102-11 Numeric coprocessor speed test failed

102-12 Numeric coprocessor pattern test failed

102-15 Numeric coprocessor is inoperative or socket is unoccupied

---------------------------------------------------------------------------
103-01 DMA page registers test failed

103-02 DMA byte controller test failed

103-03 DMA word controller test failed

---------------------------------------------------------------------------
104-01 Interrupt controller master test failed

104-02 Interrupt controller slave test failed

104-03 Interrupt controller software RTC is inoperative

---------------------------------------------------------------------------
105-01 Port 61 bit <6> not at zero

105-02 Port 61 bit <5> not at zero

105-03 Port 61 bit <3> not at zero

105-04 Port 61 bit <1> not at zero

105-05 Port 61 bit <0> not at zero

105-06 Port 61 bit <5> not at one

105-07 Port 61 bit <3> not at one

105-08 Port 61 bit <1> not at one

105-09 Port 61 bit <0> not at one

105-10 Port 61 I/O test failed

105-11 Port 61 bit <7> not at zero

105-12 Port 61 bit <2> not at zero

105-13 No interrupt generated by failsafe timer

105-14 NMI not triggered by failsafe timer

106-01 Keyboard controller self-test failed

---------------------------------------------------------------------------
107-01 CMOS RAM test failed
---------------------------------------------------------------------------
108-02 CMOS interrupt test failed

108-03 CMOS interrupt test, CMOS not properly initialized

---------------------------------------------------------------------------
109-01 CMOS clock load data test failed

109-02 CMOS clock rollover test failed

109-03 CMOS clock test, CMOS not properly initialized

---------------------------------------------------------------------------
110-01 Programmable timer load data test failed

110-02 Programmable timer dynamic test failed

110-03 Program timer 2 load data test failed

---------------------------------------------------------------------------
111-01 Refresh detect test failed
---------------------------------------------------------------------------
112-01 Speed test Slow mode out of range

112-02 Speed test Mixed mode out of range

112-03 Speed test Fast mode out of range

112-04 Speed test unable to enter Slow mode

112-05 Speed test unable to enter Mixed mode

112-06 Speed test unable to enter Fast mode

112-07 Speed test system error

112-08 Unable to enter Auto mode in speed test

112-09 Unable to enter High mode in speed test

112-10 Speed test High mode out of range

112-11 Speed test Auto mode out of range

112-12 Speed test Variable speed mode inoperative

---------------------------------------------------------------------------
113-01 Protected mode test failed
---------------------------------------------------------------------------
114-01 Speaker test failed
---------------------------------------------------------------------------
116-xx Way 0 read/write test failed
---------------------------------------------------------------------------
199-00 Installed devices test failed
=======================================================
====================

Memory

Table A-3 lists error messages for memory-related errors.

Table A-3. Memory Error Messages

200-05 Extended memory size changed

200-06 Invalid memory configuration

200-07 Extended memory size changed

200-08 CLIM memory size changed

---------------------------------------------------------------------------
201-01 Memory machine ID test failed
---------------------------------------------------------------------------
202-01 Memory system ROM checksum failed

202-02 Failed RAM/ROM map test

202-03 Failed RAM/ROM protect test

---------------------------------------------------------------------------
203-01 Memory read/write test failed

203-02 Error while saving block under test in read/write test

203-03 Error while restoring block under test in read/write test

---------------------------------------------------------------------------
204-01 Memory address test failed

204-02 Error while saving block under test in address test

204-03 Error while restoring block under test in address test

204-04 A20 address test failed

204-05 Page hit address test failed

---------------------------------------------------------------------------
205-01 Walking I/O test failed

205-02 Error while saving block under test in walking I/O test
205-03 Error while restoring block under test in walking I/O test
---------------------------------------------------------------------------
206-xx Increment pattern test failed
---------------------------------------------------------------------------
210-01 Memory increment pattern test

210-02 Error while saving memory in increment pattern test

210-03 Error while restoring memory in increment pattern test

---------------------------------------------------------------------------
211-01 Memory random pattern test

211-02 Error while saving memory in random memory pattern test

211-03 Error while restoring memory in random memory pattern test

=======================================================
====================

Keyboard

Table A-4 lists error messages for keyboard-related errors.

Table A-4. Keyboard Error Messages

301-02 Keyboard short test, interface test failed

301-03 Keyboard short test, echo test failed

301-04 Keyboard short test, keyboard reset failed

301-05 Keyboard short test, keyboard reset failed

---------------------------------------------------------------------------
302-01 Keyboard long test, failed
---------------------------------------------------------------------------
303-01 Keyboard LED test, controller self-test failed

303-02 Keyboard LED test, reset test failed

303-03 Keyboard LED test, reset failed

303-04 Keyboard LED test, LED command test failed

303-05 Keyboard LED test, LED command test failed

303-06 Keyboard LED test, LED command test failed

303-07 Keyboard LED test, LED command test failed

303-08 Keyboard LED test, command byte restore test failed

303-09 Keyboard LED test, LEDs failed to light
---------------------------------------------------------------------------
304-01 Keyboard repeat key test failed

304-02 Unable to enter mode 3

304-03 Incorrect scan code from keyboard

304-04 No Make code observed

304-05 Cannot disable repeat key feature

304-06 Unable to return to Normal mode

=======================================================
====================

Printer

Table A-5 lists error messages for printer-related errors.

Table A-5. Printer Error Messages

402-02 Printer Control register failed

402-03 Printer Data register and Control register failed

402-04 Printer loopback test failed

402-05 Printer loopback test and Data register failed

402-06 Printer loopback test and Control register failed

402-07 Loopback test, Data register, and Control register failed

402-08 Printer interrupt test failed

402-09 Printer interrupt test and Data register failed

402-10 Printer interrupt test and Control register failed

402-11 Printer Data register, and Control register failed

402-12 Printer interrupt test and loopback test failed

402-13 Printer interrupt test, loopback test, and the

Data register failed

402-14 Printer interrupt test, loopback test, and Control

402-15 Printer interrupt test, loopback test, Data register, and

Control register failed

402-16 Printer unexpected interrupt received

---------------------------------------------------------------------------
403-01 Printer pattern test failed
---------------------------------------------------------------------------
498-00 Printer failed or not connected
=======================================================
====================

Diskette Drive

Table A-6 lists error messages for diskette drive-related errors.

Table A-6. Diskette Drive Error Messages

600-05 Failed to reset controller

600-20 Failed to get drive type

---------------------------------------------------------------------------
601-xx Diskette drive format

601-05 Failed to reset controller

601-09 Failed to format a track

601-23 Failed to set drive type in ID media

---------------------------------------------------------------------------
602-xx Diskette read test

602-01 Exceeded maximum soft error limit

602-02 Exceeded maximum hard error limit

602-03 Previously exceeded maximum soft error limit

602-04 Previously exceeded maximum hard error limit

602-05 Failed to reset controller

602-06 Fatal error while reading

---------------------------------------------------------------------------
603-xx Diskette drive read/write compare test

603-01 Exceeded maximum soft error limit

603-02 Exceeded maximum hard error limit

603-03 Previously exceeded maximum soft error limit

603-04 Previously exceeded maximum hard error limit

603-05 Failed to reset controller

603-06 Fatal error while reading

603-07 Fatal error while writing

603-08 Failed compare of read/write buffers

---------------------------------------------------------------------------
604-xx Diskette drive random seek test

604-01 Exceeded maximum soft error limit

604-02 Exceeded maximum hard error limit

604-03 Previously exceeded maximum soft error limit

604-04 Previously exceeded maximum hard error limit

604-05 Failed to reset controller

604-06 Fatal error while reading

---------------------------------------------------------------------------
605-xx Diskette drive ID media test

605-20 Failed to get drive type

605-24 Failed to read diskette media

605-25 Failed to verify diskette media

---------------------------------------------------------------------------
606-xx Diskette drive speed test

606-26 Failed to read media in speed test

606-27 Failed speed limits

---------------------------------------------------------------------------
607-xx Diskette wrap test

607-10 Failed sector wrap test

---------------------------------------------------------------------------
608-xx Diskette drive write-protect test

608-28 Failed write-protect test

---------------------------------------------------------------------------
609-xx Diskette drive reset controller test

609-05 Failed to reset controller

---------------------------------------------------------------------------
610-xx Diskette drive change line test
610-21 Failed to get change line status

610-22 Failed to clear change line status

---------------------------------------------------------------------------
694-00 Pin 34 not cut on 360-Kbyte diskette drive
---------------------------------------------------------------------------
697-00 Diskette type error
---------------------------------------------------------------------------
6xx-01 Exceeded maximum soft error limit

6xx-02 Exceeded maximum hard error limit

6xx-03 Previously exceeded maximum soft error limit

6xx-04 Previously exceeded maximum hard error limit

6xx-05 Failed to reset controller

6xx-06 Fatal error while reading

6xx-07 Fatal error while writing

6xx-08 Failed compare of read/write buffers

6xx-09 Failed to format a track

6xx-10 Failed sector wrap test

6xx-20 Failed to get drive type

6xx-22 Failed to clear change line status

6xx-23 Failed to set drive type in ID media

6xx-24 Failed to read diskette media

6xx-25 Failed to verify diskette media

6xx-26 Failed to read media in speed test

6xx-27 Failed speed limits

6xx-28 Failed write-protect test

---------------------------------------------------------------------------
698-00 Diskette drive speed not within limits
---------------------------------------------------------------------------
699-00 Drive/media ID error -- rerun SETUP
=======================================================
====================

Serial Communications

Table A-7 lists error messages for serial communications-related errors.

Table A-7. Serial Communications Error Messages

1101-02 Serial port test, line input or UART fault

1101-03 Serial port test, address line fault

1101-04 Serial port test, data line fault

1101-05 Serial port test, UART control signal failure

1101-06 Serial port test, UART THRE bit failure

1101-07 Serial port test, UART DATA READY bit failure

1101-08 Serial port test, UART TX/RX buffer failure

1101-09 Serial port test, INTERRUPT circuit failure

1101-10 Serial port test, COM1 set to invalid interrupt

1101-11 Serial port test, COM2 set to invalid interrupt

1101-12 Serial port test, DRIVER/RECEIVER control signal failure

1101-13 Serial port test, UART control signal interrupt failure

1101-14 Serial port test, DRIVER/RECEIVER data failure

---------------------------------------------------------------------------
1109-01 Clock register initialization failure

1109-02 Clock register rollover failure

1109-03 Clock reset failure

1109-04 Input line or clock failure

1109-05 Address line fault

1109-06 Data line fault

---------------------------------------------------------------------------
1150-xx Comm port SETUP error (run SETUP)
=======================================================
====================

Modem Communications

Table A-8 lists modem communications error messages.

Table A-8. Modem Error Messages

1201-01 UART DLAB bit failure

1201-02 Line input or UART failure

1201-03 Address line fault

1201-04 Data line fault

1201-05 UART control signal failure

1201-06 UART THRE bit failure

1201-07 UART DATA READY bit failure

1201-08 UART TX/RX buffer failure

1201-09 Interrupt circuit failure

1201-10 COM1 set to invalid interrupt

1201-11 COM2 set to invalid interrupt

1201-12 DRIVER/RECEIVER control signal failure

1201-13 UART control signal interrupt failure

1201-14 DRIVER/RECEIVER data failure

1201-15 Modem detection failure

1201-16 Modem ROM, checksum failure

1201-17 Tone detection failure

---------------------------------------------------------------------------
1202-xx Modem internal test

1202-01 Time-out waiting for SYNC (local loopback mode)

1202-02 Time-out waiting for response (local loopback mode)

1202-03 Exceeded data block retry limit (loopback mode)

1202-11 Time-out waiting for SYNC (loopback originate mode)

1202-12 Time-out of modem response (loopback originate mode)

1202-13 Exceeded data block retry limit (loopback originate mode)

1202-21 Time-out waiting for SYNC ( loopback answer mode)

1202-22 Time-out (analog loopback answer mode)

1202-23 Exceeded data block retry limit (loopback answer mode)
---------------------------------------------------------------------------
1203-xx Modem external termination test

1203-01 Modem external TIP/RING failure

1203-02 Modem external DATA TIP/RING failure

1203-03 Modem line termination failure

---------------------------------------------------------------------------
1204-xx Modem auto originate test

1204-01 Modem time-out waiting for SYNC

1204-02 Modem time-out waiting for response

1204-03 Modem exceeded data block retry limit

1204-04 RCV exceeded carrier lost limit

1204-05 XMIT exceeded carrier lost limit

1204-06 Time-out waiting for dial tone

1204-07 Dial number string too long

1204-08 Modem time-out waiting for remote response

1204-09 Modem exceeded maximum redial limit

1204-10 Line quality prevented remote connection

1204-11 Modem time-out waiting for remote connection

---------------------------------------------------------------------------
1205-xx Modem auto answer test

1205-01 Modem time-out waiting for SYNC

1205-02 Modem time-out waiting for response

1205-03 Modem exceeded data block retry limit

1205-04 RCV exceeded carrier lost limit

1205-05 XMIT exceeded carrier lost limit

1205-06 Time-out waiting for dial tone

1205-07 Dial number string too long

1205-08 Modem time-out waiting for remote response

1205-09 Modem exceeded maximum redial limit

1205-10 Line quality prevented remote connection

1205-11 Modem time-out waiting for remote connection

---------------------------------------------------------------------------
1206-xx Dial multi-frequency tone test

1206-17 Tone detection failure

---------------------------------------------------------------------------
1210-xx Modem direct connect test

1210-01 Modem time-out waiting for SYNC

1210-02 Modem time-out waiting for response

1210-03 Modem exceeded data block retry limit

1210-04 RCV exceeded carrier lost limit

1210-05 XMIT exceeded carrier lost limit

1210-06 Time-out waiting for dial tone

1210-07 Dial number string too long

1210-08 Modem time-out waiting for remote response

1210-09 Modem exceeded maximum redial limit

1210-10 Line quality prevented remote connection

1210-11 Modem time-out waiting for remote connection

=======================================================
====================

Hard Drive

Table A-9 lists error messages for hard drive-related errors.

Table A-9. Hard Drive Error Messages

1700-05 Failed to reset controller

1700-09 Failed to format a track

1700-41 Failed to ID hard drive (drive not ready)

1700-42 Failed to recalibrate drive

1700-45 Failed to get drive parameters from ROM

1700-46 Invalid drive parameters found in ROM

1700-66 Failed to initialize drive parameter

1700-69 Failed to read drive size from controller

1700-70 Failed translate mode

1700-71 Failed non-translate mode

---------------------------------------------------------------------------
1701-xx Hard drive format

1701-05 Failed to reset controller

1701-09 Failed to format a cylinder

1701-42 Failed to recalibrate drive

1701-58 Failed to write sector buffer

1701-59 Failed to read sector buffer

1701-66 Failed to initialize drive parameter

---------------------------------------------------------------------------
1702-xx Hard drive read test

1702-01 Exceeded maximum soft error limit

1702-02 Exceeded maximum hard error limit

1702-03 Previously exceeded maximum soft error limit

1702-04 Previously exceeded maximum hard error limit

1702-05 Failed to reset controller

1702-06 Fatal error while reading

1702-40 Failed cylinder 0

1702-65 Exceeded maximum bad sectors per track

1702-68 Failed to read long

1702-70 Failed translate mode

1702-71 Failed non-translate mode

1702-72 Bad track limit exceeded

1702-73 Previously exceeded bad track limit

---------------------------------------------------------------------------
1703-xx Hard drive read/write compare test

1703-01 Exceeded maximum soft error limit

1703-02 Exceeded maximum hard error limit

1703-03 Previously exceeded maximum soft error limit

1703-04 Previously exceeded maximum hard error limit

1703-05 Failed to reset controller

1703-06 Fatal error while reading

1703-07 Fatal error while writing

1703-08 Failed compare of read/write buffers

1703-40 Cylinder 0 error

1703-55 Cylinder 1 error

1703-63 Failed soft error rate

1703-65 Exceeded maximum bad sectors per track

1703-67 Failed to write long

1703-68 Failed to read long

1703-70 Failed translate mode

1703-71 Failed non-translate mode

1703-72 Bad track limit exceeded

1703-73 Previously exceeded bad track limit

---------------------------------------------------------------------------
1704-xx Hard drive random seek test

1704-01 Exceeded maximum soft error limit

1704-02 Exceeded maximum hard error limit

1704-03 Previously exceeded maximum soft error limit

1704-04 Previously exceeded maximum hard error limit

1704-05 Failed to reset controller

1704-06 Fatal error while reading

1705-40 Cylinder 0 error

1704-55 Cylinder 1 error

1704-65 Exceeded maximum bad sectors per track

1704-70 Failed translate mode

1704-71 Failed non-translate mode

1704-72 Bad track limit exceeded

1704-73 Previously exceeded bad track limit

---------------------------------------------------------------------------
1705-xx Hard drive controller test

1705-05 Failed to reset controller

1705-44 Failed controller diagnostics

1705-56 Failed controller RAM diagnostics

1705-57 Failed controller to drive diagnostics

---------------------------------------------------------------------------
1706-xx Hard drive ready test

1706-41 Drive not ready

---------------------------------------------------------------------------
1707-xx Hard drive recalibrate test

1707-42 Failed to recalibrate drive

---------------------------------------------------------------------------
1708-xx Hard drive format bad track test

1708-02 Exceeded maximum hard error limit

1708-05 Failed to reset controller

1708-09 Format bad track failed

1708-42 Recalibrate drive failed

1708-58 Failed to write sector buffer

1708-59 Failed to read sector buffer

---------------------------------------------------------------------------
1709-xx Hard drive reset controller test

1709-05 Failed to reset controller

---------------------------------------------------------------------------
1710-xx Hard drive park head test

1710-45 Failed to get drive parameters from ROM

1710-47 Failed to park heads

---------------------------------------------------------------------------
1714-xx Hard drive file write test

1714-01 Exceeded maximum soft error limit

1714-02 Exceeded maximum hard error limit

1714-03 Previously exceeded maximum soft error limit

1714-04 Previously exceeded maximum hard error limit

1714-05 Failed to reset controller

1714-06 Fatal error while reading

1714-07 Fatal error while writing

1714-08 Failed compare of read/write buffers

1714-10 Failed diskette sector wrap during read

1714-48 Failed to move disk table to RAM

1714-49 Failed to read diskette media in file write test

1714-50 Failed file I/O write test

1714-51 Failed file I/O read test

1714-52 Failed file I/O compare test

1714-55 Failed cylinder 1

1714-65 Exceeded maximum bad sectors per track

1714-70 Failed translate mode

1714-71 Failed non-translate mode

1714-72 Bad track limit exceeded

1714-73 Previously exceeded bad track limit

---------------------------------------------------------------------------
1715-xx Hard drive drive/head select test

1715-45 Failed to get drive parameters from ROM

1715-53 Failed drive/head register test

1715-54 Failed digital input register test

---------------------------------------------------------------------------
1716-xx Hard drive conditional format test

1716-01 Exceeded maximum soft error limit

1716-02 Exceeded maximum hard error limit

1716-05 Failed to reset controller

1716-06 Fatal error while reading

1716-07 Fatal error while writing

1716-08 Failed compare of read/write buffers

1716-40 Cylinder 0 error

1716-42 Failed to recalibrate

1716-55 Cylinder 1 error

1716-58 Failed to write sector buffer

1716-59 Failed to read sector buffer

1716-60 Failed to compare sector buffer

1716-65 Exceeded maximum bad sectors per track

1716-66 Failed to initialize drive

1716-70 Failed translate mode

1716-71 Failed non-translate mode

1716-72 Bad track limit exceeded

1716-73 Previously exceeded bad track limit

---------------------------------------------------------------------------
1717-xx Hard drive ECC test

1717-01 Exceeded maximum soft error limit

1717-02 Exceeded maximum hard error limit

1717-03 Previously exceeded maximum soft error limit

1717-04 Previously exceeded maximum hard error limit

1717-05 Reset controller failed

1717-06 Fatal error while reading (BIOS status > 0 x 20)

1717-07 Fatal error while writing

1717-08 Compare data failed

1717-40 Cylinder 0 failed

1717-55 Cylinder 1 failed

1717-61 Failed uncorrectable error

1717-62 Failed correctable error

1717-65 Exceeded maximum bad sectors per track

1717-67 Failed to write long

1717-68 Failed to read long

1717-70 Failed translate mode

1717-71 Failed non-translate mode

1717-73 Previously exceeded bad track limit

---------------------------------------------------------------------------
1719-xx Hard drive power mode test failed
---------------------------------------------------------------------------
17xx-01 Exceeded maximum soft error limit

17xx-02 Exceeded maximum hard error limit

---------------------------------------------------------------------------
1719-03 Previously exceeded maximum soft error limit

1719-04 Previously exceeded maximum hard error limit

1719-05 Failed to reset controller

1719-06 Fatal error while reading

1719-07 Fatal error while writing

1719-08 Failed compare of read/write/compare

1719-09 Failed to format a track

1719-10 Failed sector wrap test

1719-19 Controller failed to deallocate bad sectors

1719-40 Failed cylinder 0

1719-41 Drive not ready

1719-42 Recalibrate failed

1719-43 Failed to format bad track

1719-44 Failed Hard drive controller diagnostics

1719-45 Failed to get drive parameters from ROM

1719-46 Invalid drive parameters found in ROM

1719-47 Failed to park heads

1719-48 Failed to move Hard drive table to RAM

1719-49 Failed to read media in file write test

1719-50 Failed file I/O write test

1719-51 Failed file I/O read test

1719-52 Failed file I/O compare test

1719-53 Failed drive/head register test

1719-54 Failed digital input register test

1719-55 Failed cylinder 1

1719-56 Hard drive controller RAM diagnostics failed

1719-57 Hard drive controller to drive test failed

1719-58 Failed to write sector buffer

1719-59 Failed to read sector buffer

1719-60 Failed to compare sector buffer

1719-61 Failed uncorrectable ECC error

1719-62 Failed correctable ECC error

1719-63 Failed soft error rate

1719-65 Exceeded maximum bad sectors per track

1719-66 Failed initial drive parameter

1719-67 Failed to write long

1719-68 Failed to read long

1719-69 Failed to read drive size from controller

1719-70 Failed translate mode

1719-71 Failed non-translate mode

1719-72 Bad track limit exceeded

1719-73 Previously exceeded bad track limit

1719-74 Failed sleep mode

1719-75 Failed idle mode

1719-76 Failed standby mode

1719-77 Failed to change mode

1719-78 Exceeded spinup time limit

=======================================================
====================

Tape Drive

Table A-10 lists error messages for tape drive-related errors.

Table A-10. Tape Drive Error Messages

=======================================================
====================
Message Probable Cause
---------------------------------------------------------------------------
1900-xx Tape ID failed

1900-01 Hard drive not installed

1900-02 Cartridge not installed

1900-26 Cannot identify Hard drive

1900-27 Hard drive incompatible with controller

---------------------------------------------------------------------------
1901-xx Tape Servo Write

1901-01 Drive not installed

1901-02 Cartridge not installed

1901-03 Tape motion error

1901-04 Drive busy error

1901-05 Track seek error

1901-06 Tape write-protected error

1901-07 Tape already Servo written

1901-08 Unable to Servo Write

1901-11 Drive recalibration error

1901-21 Got Servo pulses second time, but not first

1901-22 Never got to EOT after Servo check

1901-25 Unable to erase cartridge

1901-27 Drive not compatible with controller

1901-91 Power lost during test, replace cartridge, or bulk erase it

---------------------------------------------------------------------------
1902-xx Tape format

1902-01 Drive not installed

1902-02 Cartridge not installed

1902-03 Tape motion error

1902-04 Drive busy error

1902-05 Track seek error

1902-06 Tape write-protected error

1902-09 Unable to format

1902-10 Format mode error

1902-11 Drive recalibration error

1902-12 Tape not Servo Written

1902-13 Tape not formatted

1902-21 Got servo pulses second time, but not first

1902-22 Never got to EOT after servo check

1902-27 Drive not compatible with controller

1902-28 Format gap error

---------------------------------------------------------------------------
1903-xx Tape drive sensor test

1903-01 Drive not installed

1903-23 Change line unset

1903-27 Drive not compatible with controller

---------------------------------------------------------------------------
1904-xx Tape BOT/EOT test

1904-01 Drive not installed

1904-02 Cartridge not installed

1904-03 Tape motion error

1904-04 Drive busy error

1904-05 Track seek error

1904-15 Sensor error flag

1904-27 Drive not compatible with controller

1904-30 Exception bit not set

1904-31 Unexpected drive status

1904-32 Device fault

1904-33 Illegal command

1904-34 No data detected

1904-35 Power-on reset occurred

---------------------------------------------------------------------------
1905-xx Tape read test

1905-01 Drive not installed

1905-02 Cartridge not installed

1905-03 Tape motion error

1905-04 Drive busy error

1905-05 Track seek error

1905-14 Drive time-out error

1905-16 Block locate (block ID) error

1905-17 Soft error limit exceeded

1905-18 Hard error limit exceeded

1905-19 Write error (probable ID error)

1905-27 Drive not compatible with controller

1905-30 Exception bit not set

1905-31 Unexpected drive status

1905-32 Device fault

1905-33 Illegal command

1905-34 No data detected

1905-35 Power-on reset occurred

---------------------------------------------------------------------------
1906-xx Tape read/write compare test failed

1906-01 Drive not installed

1906-02 Cartridge not installed

1906-03 Tape motion error

1906-04 Drive busy error

1906-05 Track seek error

1906-06 Tape write-protected error

1906-14 Drive time-out error

1906-16 Block locate (block ID) error

1906-17 Soft error limit exceeded

1906-18 Hard error limit exceeded

1906-19 Write error (probable ID error)

1906-20 NEC fatal error

1906-27 Drive not compatible with controller

1906-30 Exception bit not set

1906-31 Unexpected drive status

1906-32 Device fault

1906-33 Illegal command

1906-34 No data detected

1906-35 Power-on reset occurred

---------------------------------------------------------------------------
1907-xx Tape write-protected test

1907-24 Failed write-protected test

1907-30 Exception bit not set

1907-31 Unexpected drive status

1907-32 Device fault

1907-33 Illegal command

1907-34 No data detected

1907-35 Power-on reset occurred

---------------------------------------------------------------------------
19xx-01 Drive not installed

19xx-02 Cartridge not installed

19xx-03 Tape motion error

19xx-04 Drive busy error

19xx-05 Track seek error

19xx-06 Tape write-protected error

19xx-07 Tape already Servo Written

19xx-08 Unable to Servo Write

19xx-09 Unable to format

19xx-10 Format mode error

19xx-11 Drive recalibration error

19xx-12 Tape not Servo Written

19xx-13 Tape not formatted

19xx-14 Drive time-out error

19xx-15 Sensor error flag

19xx-16 Block locate (block ID) error

19xx-17 Soft error limit exceeded

19xx-18 Hard error limit exceeded

19xx-19 Write (probably ID) error

19xx-20 NEC fatal error

19xx-21 Got servo pulses second time but not first

19xx-22 Never got to EOT after servo check

19xx-23 Change line unset

19xx-24 Write-protect error

19xx-25 Unable to erase cartridge

19xx-26 Cannot identify drive

19xx-27 Drive not compatible with controller

19xx-28 Format gap error

19xx-36 Failed to set FLEX format mode

19xx-37 Failed to reset FLEX format mode

19xx-38 Data mismatched on directory track

19xx-39 Data mismatched on track 0

19xx-40 Failed self-test
=======================================================
====================

Video

Table A-11 lists the error codes for the Video subsystem.

Table A-11. Video Error Messages

=======================================================
====================
Message Probable Cause
---------------------------------------------------------------------------
2402-01 Video memory test failed
---------------------------------------------------------------------------
2403-01 Video attribute test failed
---------------------------------------------------------------------------
2404-01 Video character set test failed
---------------------------------------------------------------------------
2405-01 Video 80 x 25 mode 9 x 14 character cell test failed
---------------------------------------------------------------------------
2406-01 Video 80 x 25 mode 8 x 8 character cell test failed
---------------------------------------------------------------------------
2407-01 Video 40 x 25 mode test failed
---------------------------------------------------------------------------
2408-01 Video 320 x 200 mode color set 0 test failed
---------------------------------------------------------------------------
2409-01 Video 320 x 200 mode color set 1 test failed
---------------------------------------------------------------------------
2410-01 Video 640 x 200 mode test failed
---------------------------------------------------------------------------
2411-01 Video screen memory page test failed
---------------------------------------------------------------------------
2412-01 Video gray scale test failed
---------------------------------------------------------------------------
2414-01 Video white screen test failed
---------------------------------------------------------------------------
2416-01 Video noise pattern test failed
---------------------------------------------------------------------------
2418-01 Video memory test failed

2418-02 Video Shadow RAM test failed

---------------------------------------------------------------------------
2419-01 Video ROM checksum test failed
---------------------------------------------------------------------------
2420-01 Video attribute test failed
---------------------------------------------------------------------------
2421-01 Video 640 x 200 Graphics mode test failed
---------------------------------------------------------------------------
2422-01 Video 640 x 350 16-color set test failed
---------------------------------------------------------------------------
2423-01 Video 640 x 350 64-color set test failed
---------------------------------------------------------------------------
2424-01 Video monochrome Text mode test failed
---------------------------------------------------------------------------
2425-01 Video monochrome graphics mode test failed
---------------------------------------------------------------------------
2431-01 Video 640 x 480 graphics test failure
---------------------------------------------------------------------------
2432-01 Video 320 x 200 Graphics (256-color mode) test failure
=======================================================
====================

Pointing Device Interface

Table A-12 lists the error messages pointing device interface-related

errors.

Table A-12. Pointing Device Interface Error Messages

8601-01 Mouse ID fails

8601-02 Left button is inoperative

8601-03 Left button is stuck closed

8601-04 Right button is inoperative

8601-05 Right button is stuck closed

8601-06 Left block not selected

8601-07 Right block not selected

8601-08 Time-out occurred

8601-09 Mouse loopback test failed

8601-10 Pointing device is inoperative

=======================================================
====================

B.1 INTRODUCTION

This appendix describes the connectors used in the COMPAQ LTE Lite Family
of Personal Computers.

B.2 CONNECTORS

The connectors described in this appendix include the following:

o Parallel connector
o Serial connector
o Pointing Device/External Keyboard connector
o External Numeric Keypad connector
o VGA monitor connector
o AC Adapter connector
o External Options connector

Figure B-1 shows the location of all of the connectors found on the rear
panel of the computer.

Connector Locations

ILLUSTRATION OF Figure B-1. Connector Locations

Figures B-2 through B-8 detail each connector found on the rear panel of
the computer.

Parallel Connector

ILLUSTRATION OF Figure B-2. Parallel Connector

Serial Connector

ILLUSTRATION OF Figure B-3. Serial Connector

Pointing Device/External Keyboard Connector

ILLUSTRATION OF Figure B-4. Pointing Device/External Keyboard Connector

External Numeric Keypad Connector

ILLUSTRATION OF Figure B-5. External Numeric Keypad Connector

VGA Monitor Connector

ILLUSTRATION OF Figure B-6. VGA Monitor Connector

AC Adapter Connector

ILLUSTRATION OF Figure B-7. AC Adapter Connector

External Options Connector

ILLUSTRATION OF Figure B-8a. External Options Connector (Part 1 of 4)

ILLUSTRATION OF Figure B-8b. External Options Connector (Part 2 of 4)

ILLUSTRATION OF Figure B-8c. External Options Connector (Part 3 of 4)

ILLUSTRATION OF Figure B-8d. External Options Connector (Part 4 of 4)

C.1 INTRODUCTION

The COMPAQ LTE Lite contains power conservation features that are designed
to extend operating time while running under battery power. These features
are user-controllable with hotkey combinations and though the SETUP and
PWRCON utilities. Note that when the system unit is powered from an AC
source, the power conservation features are not available.

Power conservation involves the control and interaction of three elements:

o Battery condition
o Power conservation level setting
o Mode of reduced power operation.

A new feature, Hibernation, has been added that provides data loss
security, protection from battery rundown, and a "bookmark" function.

C.2 BATTERY CONDITIONS

The computer recognizes two battery conditions: low battery 1 and low
battery 2.

Low Battery 1 -- In this condition, the battery pack has approximately six
percent of its charge remaining. The computer indicates this condition by
flashing the power/low battery light once every second and, initially,
beeping the speaker six times (if the speaker is enabled).

Low Battery 2 -- When this condition is reached, the battery pack has only
two percent of its charge remaining. This condition is indicated by the
power/low battery light flashing twice every second, and the speaker (if
enabled), initially beeping twice per second.

C.3 POWER CONSERVATION LEVELS

The COMPAQ LTE Lite features user-selectable power conservation levels. The
power conservation level determines parameters such as subsystem timeouts,
display brightness, and processor speed, all which affect the amount of
drain the system places on the battery pack. The power conservation levels
are selected with hotkey combinations (from the integrated keyboard only).
Table C-1 shows the power conservation level settings.

Table C-1. Power Conservation Level Settings

=======================================================
====================
Parameter High Medium * Drain Custom #
---------------------------------------------------------------------------
System idle timeout 1 min 3 min 0 min 0 (disabled) -17 min

Standby timeout 5 min 10 min 0 min 0 (disabled) -17 min

Hard drive timeout 1 min 2 min 0 min 0 (disabled) -31 min

Screen save timeout 2 min 5 min 0 min 0 (disabled) -31 min

Display brightness 50% 100% 100% 0 - 100%

Processor speed:
LTE Lite/25 and
LTE Lite/25C 12.5 MHz 25 MHz 25 MHz 3, 6, 12, 25 MHz

LTE Lite/20 10.0 MHz 20 MHz 20 MHz 2, 5, 10, 20 MHz

---------------------------------------------------------------------------
* Default at power-up
# Configured with PWRCON utility or SETUP
=======================================================
====================

C.4 REDUCED POWER CONDITIONS

The computer can be in one of two conditions of reduced power operation:

system idle or system standby. The computer can enter these modes only
while operating on battery power.

System Idle

The computer achieves the system idle condition when various subsystems,
after a period of inactivity, are placed in a reduced power mode. A power
management firmware routine is then run that clears timer registers, slows
the CPU clock speed, and dims the LCD panel. The subsystems that determine
the status of system idle condition are then monitored for I/O port or IRQ
activity, which, if detected, results in a System Management Interrupt
(SMI) being generated and immediately brings the computer out of the system
idle condition. Table C-2 lists the subsystems and respective ports/IRQs
that are monitored.

Table C-2. Subsystems Monitored for Activity During System Idle

=======================================================
====================
Subsystem Monitored Ports or IRQs
---------------------------------------------------------------------------
Keyboard/Mouse IRQ1/IRQ12

Hard Drive 1F0h - 1F7h and 3F6h, 3F7h

Diskette Drive IRQ6

Serial Ports 3F8h - 3FFh and 2F8 - 2FFh

Parallel Port 378h - 37Fh, 278h - 27Fh, or 3BCh - 3BFh

Enhanced Option Slot 3F8h - 3FFh, 2F8h - 2Fh, or variable address

location and range
=======================================================
====================
The monitoring function is provided by the 386SL chipset, which uses local
trap/timeout registers (to monitor specific I/O ports) and global
trap/timeout registers (to monitor specific IRQs). Refer to the
documentation listed in Chapter 1, "Introduction," for more detailed
information on these registers.

The following paragraphs discuss subsystem details concerning the system

idle condition.

Processor During System Idle

During system idle, the CPU speed is slowed to 1/8 of normal speed. This is
accomplished by firmware placing 11b into the Fast CPU field of the
CPUWRMODE register. Processing continues during system idle, but at
reduced performance.

NOTE: The turbo pin of the 386SL is permanently pulled up in the COMPAQ LTE
Lite so that the processor, in normal operation, always runs in turbo
mode.

Keyboard/Mouse Interface During System Idle

The keyboard/mouse interface is monitored during system idle by global

trap/timer registers of the 386SL chipset. The trap/timer registers monitor
IRQ 1 (for the keyboard) and IRQ12 (for the mouse if so configured). Note
that if the mouse is not configured, or is configured for another IRQ (as
indicated in the miscellaneous options register) then the system idle and
system standby conditions will not be contingent on mouse activity.

The inactivity timers of the traps are set with the value of the system
idle timeout value selected by the user. Note that in the case for the
global traps, activity detected from the keyboard (IRQ1), mouse (IRQ12), or
the diskette drive controller (IRQ6) will cause an SMI that results in the
inactivity register being reset for all three subsystems.

Video Subsystem During System Idle

In the system idle condition, the brightness of the LCD is dimmed. This is
achieved by the firmware setting the pulse width modulation (PWM1) signal
(that controls the LCD back or edge lighting) to a duty cycle that
corresponds to the user-selected dim level. The PWM1 Compare (System
Processor Index 87h, R/W) and the PW Prescaler (System Processor Index 97h,
R/W) registers are used to determine the amount of dimming (percentage of
PWM1's duty cycle) desired.

If an external monitor is attached to the computer and the video DAC is

enabled, the external monitor will continue to provide a normal display
during system idle.

Hard Drive During System Idle

The operating mode of the hard drive is basically independent of the system
idle condition of the computer, except when a drive access occurs, which
will bring the computer out of the system idle condition. The hard drive
has four operating modes:
o Normal
o Idle
o Spin Down
o Off

Hard Drive Normal Mode

In Normal mode, the hard drive circuitry is completely powered up and the
platters are spinning.

Hard Drive Idle Mode

The hard drive has its own Idle mode, during which time no read, write, or
seek operations are occurring and part of the drive circuitry is turned off.
This Idle mode is controlled by the drive itself, completely independent of
other system hardware and firmware.

Hard Drive Spin Down Mode

The hard drive Spin Down mode is determined by the hard drive timeout
parameter set by the user. After a predefined period of drive inactivity,
the drive motors and a large portion of the drive circuitry are turned off.
A drive access request will bring the hard drive out of the Spin Down mode,
but requires approximately 10 seconds for the drive platters to spin up to
speed before the request is serviced. The hard drive can exit the Spin Down
mode by entering the Off mode, being activated by a read/write request, or
as the result of the system unit being plugged into AC power with the AC
Adapter (this last situation will be discussed later).

Hard Drive Off Mode

The hard drive enters an Off mode after two minutes of inactivity in the
Spin Down mode. In the Off mode, the hard drive interface signals are
tristated and the circuitry turned off. For the hard drive to achieve
the Off mode, two trap timers (one to monitor ports 1F0h - 1F7h and the
other to monitor ports 3F6h and 3F7h) must both time out. The firmware then
sets bit 6 of the SMOUT_CNTRL register (of the 386SL), resulting in the
following:

o Signals HD7, HDCS0-, and HDCS1- (data bit 7 and chip selects) from the
82360SL are tristated

o Signals HDENL- and HDENH- are driven high to disable the data buffers

o DEV1 signal driven low to remove power from the hard drive circuitry

The hard drive can still, in the "off" mode, detect a request for drive
access, in which case the drive becomes fully operational (after a spin up
time of about 10 seconds). After the access is complete, the inactivity
(trap) timers are reset and the drive returns to its own "idle" mode.

Another situation that will bring the hard drive out of the "off" mode is
when AC power is connected to the system unit through the AC Adapter. Refer
to the section "Exiting Standby by Connecting AC Power" later in the
appendix.

Diskette Drive Controller During System Idle

During the system idle condition, the diskette controller disables the
internal clock signal and powers down a portion of the drive circuitry. An
access (writing to the diskette controller data register or to the main
status register) will bring the diskette controller out of its low power
mode, requiring several milliseconds delay while the clock is enabled. An
access brings the computer out of system idle by generating an IRQ6 that is
detected by global trap/timer registers of the 386SL chipset.

Serial Interface During System Idle

The serial interface is monitored during system idle by two sets of local
trap/timer registers of the 386SL chipset. The trap/timer registers monitor
the I/O port ranges of 3F8h - 3FFh and 2F8h - 2FFh. The inactivity timers
of the traps are set with the value of the system idle timeout value
selected by the user.

Parallel Interface During System Idle

The Parallel interface is monitored during system idle by local trap/timer

registers of the 386SL chipset. The trap/timer registers monitor the I/O
port ranges of either LPT1, LPT2, or LPT3, (see Table C-2) depending on the
configuration (LPT1 is the default). The inactivity timers of the traps are
set with the value of the system idle timeout value selected by the user.

Enhanced Option Slot Interface During System Idle

The enhanced option slot interface is monitored during system idle by local
trap/timer registers of the 386SL chipset. The trap/timer registers monitor
the I/O port ranges of either COM1, COM2, or the programmed ranged address
range (see Table C-2). The inactivity timers of the traps are set with the
value of the system idle timeout value selected by the user.

The modems currently available to use in the option slot include power
management logic that acts independently of the system firmware (i.e., they
can power themselves down).

The option slot includes an output signal, SLOTON-, which can be used to
turn off a modem or other peripheral device that is installed in the
enhanced option slot IF the peripheral device is designed to support this
feature. The SLOTON- signal can be driven low by firmware to turn off the
peripheral device to conserve power, and then driven high again to turn on
the peripheral if needed.

System Standby
In system Standby, processing is stopped and a large portion of the system
is either powered off or placed in a low power mode (Table C-3). In this
condition, the LCD is completely turned off and the system memory is held
active so that data in memory is not lost. The system Standby condition is
entered usually from the system idle condition and uses the least amount of
battery power. The computer may sustain the system Standby condition for
up to 48 hours for the COMPAQ LTE Lite/20 and COMPAQ LTE Lite/25, and up to
80 hours for the COMPAQ LTE Lite/25E and COMPAQ LTE Lite/25C, depending on
battery condition at the time Standby is entered.

Table C-3. Subsystem Status During System Standby

=======================================================
====================
Subsystem Status
---------------------------------------------------------------------------
Processor Low Power

Coprocessor (if installed) Powered Off

Cache Memory Powered Off

BIOS Flash ROM Low Power

Keyboard/Mouse Interface Low Power

Hard Drive Powered Off

Diskette Drive Powered Off

Diskette Drive Controller Low Power

Video Graphics Controller Low Power

LCD Powered Off

Serial Port Low Power

Parallel Port Low Power

Enhanced Option Slot --

=======================================================
====================

Entering Standby

The computer can be placed in the system Standby condition by one of four
methods:

o By pressing the standby button

o Automatically due to peripheral inactivity
o Automatically due to critical low-battery condition
o With special application software

In any case, the computer must be operating from battery power in order to
enter the Standby condition. Regardless of how the "entry into standby"
procedure is initiated, the basic procedure is the same.

The system monitors the same subsystems for Standby that it does for system
idle (see Table C-2). If all peripheral timers expire (indicating no
peripheral activity), then the system firmware implements the standby
procedure. If the system detects activity in a monitored peripheral, an SMI
for that activity will not be generated and the system will remain in the
normal operating mode until that SMI is generated.

During the course of entering Standby, the operating state of some

subsystems must be saved prior to being powered down. The internal register
data of the hard drive and the state of the numeric (math) coprocessor must
be preserved. The pre-Standby status of these subsystems are saved in a
portion of memory called system management (SM)RAM. The SMRAM is enabled
only during the processing of an SMI, and is disabled when the SMI service
is complete.

The video controller status is not saved to SMRAM because data is held by
the video controller during Standby. The video ASIC, upon receiving a low
DEV 4 signal from the 82360SL, enters its low power mode and turns off the
LCD. The video RAM data is preserved. If an external monitor is being
used, the display will be blanked in the Standby condition due to the video
(RAM) DAC being placed in a low power mode by the video ASIC.

Cache memory data is not saved to the SMRAM because when the computer exits
Standby, a CPU reset occurs that invalidates the cache anyway.

The 82360SL peripheral controller provides a group of signals that are used
to power down various subsystems while entering the system Standby
condition. These signals are controlled by local Standby registers also
contained within the 82360SL. The register that directly controls the
subsystem (device) power, the SMOUT_CNTL (CMOS 0FEh) register, is shown
below with which subsystems the outputs affect.

BIT FUNCTION
----------------
7,6 Reserved

5 DEV 5 -- Hard drive controller

4 DEV 4 -- Video graphics controller

3 DEV 3 -- Speaker, diskette drive

2 DEV 2 -- RS-232 driver, communications port

1 DEV 1 -- Hard drive power

0 DEV 0 -- Unused

The final step in achieving system Standby is for the firmware to set the
SUS_STAT bit of the SPND_STS register (of the 82360SL). This action results
in the 386SL chipset being placed in its suspend mode and the SUS_STAT- pin
being driven low to power-off clock logic, the diskette drive controller,
the math coprocessor, the cache memory, and the amplifier for the speaker.
Entering Standby With The Standby Button

When the Standby button is pressed, the keyboard processor detects the
generated pulse and a suspend warning timer is set to run. After this timer
has timed out (allowing the processor to finish any CPU cycles that need to
be finished), the SMI handler routine is invoked. The system firmware then
configures the peripheral activity local/global trap timers to four
seconds. Once all monitored subsystems have been detected as inactive for
four seconds, the firmware continues with the procedure (as described
earlier) of placing the computer into the Standby condition.

Entering Standby By Peripheral Inactivity

The system Standby condition may be entered due to peripheral inactivity.

The inactivity requirements for Standby are basically the same as those for
system idle (see Table C-2). In most cases, this method of entering system
Standby will be the result of the computer having been in the system idle
condition. However, if the user configures the Standby timeout parameter to
be shorter than the system idle timeout value, then the computer will,
after a period of inactivity, simply enter the system Standby condition
directly.

When the inactivity timers monitoring peripherals all timeout, the system
firmware immediately turns off the LCD and resets the inactivity timers to
four seconds. If the timers are allowed to count down four seconds and
timeout, the firmware proceeds to place the computer into the system
Standby condition.

Entering Standby Due To A Low Battery Condition

The condition of the battery pack is monitored at regular intervals. This

monitoring function is handled by a controller within the battery pack
itself and the keyboard controller. A serial data link is used between the
battery controller and the keyboard controller to transfer the battery
status byte, which is placed in a register of the keyboard controller. The
battery status byte value is compared to a low battery 1 set point
(LBAT1SP) value.

When the battery status byte equals or is less than the LBAT1SP value, the
battery check process continues for ten more seconds. This ten second
"grace" period prevents a sudden current surge from prematurely placing the
computer in a low battery condition. If, after the grace period the system
condition has not changed, the EXTSMI- input pin of the 82360SL is driven
low and the suspend warning timer is loaded with the value of the
SUS_WRN_TMR register of the 82360SL. When the suspend warning timer times
out, an SMI is generated. The 82360SL then determines the cause of the SMI
as being the low battery 1 condition, and the SMI handler configures all of
the local and global trap/timer registers for a timeout value of two
minutes. If an activity occurs, the timers are reset again and the process
continues.

The battery status process, in the meantime, continues as before. If

peripheral activity occurs often enough (within every two minutes, keeping
the system in a normal condition) the system will eventually reach low
battery 2 condition, which is detected the same way as is the low battery 1
condition. If low battery 2 condition is reached, the SMI handler
configures the trap/timer registers for 20 seconds. If 20 seconds pass
without peripheral activity, then the firmware will place the computer into
the system Standby condition.

If peripheral activity continues to refuse to allow the computer to enter

Standby, the system will reach a point where the battery voltage will be
insufficient to operate the power supply logic, which will then shut down.
In this situation the system Standby condition is never achieved and data
loss can occur because the computer simply dies.

Entering Standby With Software

The computer includes the ability of allowing software to initiate the

system Standby condition. Software-initiated Standby may be useful in an
application where unattended processing such as a data transfer over modem
is to take place. At the end of the data transfer (or if the transfer
cannot be accomplished) the application software can force the computer
into the system Standby condition instead of waiting for the computer to go
through the timeout procedures that use more battery power.

Software-initiated system Standby is affected by using the INT15 call,

which is what previous COMPAQ products used for power management functions.
When the system receives a Standby condition request with the INT15 call,
the firmware loads a suspend warning timer with a timeout value and sets
the SW_REQ bit of the SM_REQ_STS register (of the 82360SL). The SUS_WRN_TMR
(of the 82360SL) is loaded and the timeout is started automatically. When
the suspend timer times out, an SMI is generated. The firmware determines
the cause of the SMI from the SM_REQ_STS register and, if the cause is the
software application, places the computer into the system Standby
condition.

Exiting Standby

Recovery from Standby can be initiated in the following ways:

o Pressing the standby button or a keyboard key

o Automatically due to serial port activity
o Automatically due to Hibernation
o Connecting AC power to the computer

While in the system Standby condition, the keyboard controller and a

portion of the 82360SL are kept active to maintain vigilance over the
system.

Exiting Standby With the Standby Button or Keyboard Key

When the standby button or any key on the keyboard is pressed, the SRBTN-
input signal of the 82360SL is driven low. The 82360SL then generates a
CPU reset and also drives the SUS_STAT- signal high. This action re-enables
the system clock sources. The CPU reset brings the 386SL chipset out of the
suspend mode. Following the CPU reset, the SUS_STAT bit of the SPND_STS
register is read, which in this case should be set indicating the CPU reset
is due to the Standby exit routine and not from another situation.
The firmware then clears the SUS_STAT bit and restores the system to the
condition it was in prior to entering the Standby condition. This involves
powering up devices and subsystems that were shut off, and re-enabling
components that were in a low power mode. Device configurations are then
restored to the pre-Standby state.

It should be noted that the hard drive is not powered up and re-enabled
during the Standby exit routine. The hard drive remains powered down until
an access is requested with the computer in the normal condition

NOTE: If the computer is in the low battery 2 condition while in the

Standby condition, the standby button cannot be used to bring the
computer out of Standby. This is due to the masking of a "standby
button push" bit when the low battery 2 condition is detected.

Exiting Standby Due To Serial Port Activity

The computer can be brought out of the Standby condition by the modem
(connected to the serial port or installed in the option slot) receiving a
ring on the line. For this to occur, the RING_MSK bit of the RESUME_MASK
register (of the 82360SL) must be set by firmware. In the case of a modem
connected to the serial port, a ring received by the modem will result in
the COMARI- input to the 82360SL to go low and initiating the CPU reset
routine described in the previous paragraph. In the case of a modem
installed in the option slot, a ring received by the modem generates an
IRQA that initiates the CPU reset routine by driving the COMBRI- input to
the 82360SL low.

Exiting Standby With Hibernation

The user can configure the computer to enter the Hibernation condition
after being in Standby for a certain period of time. The Hibernation
routine is discussed in the following section.

Exiting Standby By Connecting AC Power

The Standby condition will be exited upon the connection of AC power

(through the AC Adapter) to the computer. The AC detection function is
performed by the keyboard controller using the battery pack controller
serial data link described earlier in the "entering Standby due to a low
battery condition" section. Upon detection of AC power, the keyboard
controller unmasks the STBTPSH bit in the PMpST/CNT register and then will
set that bit to start the exit Standby routine (CPU reset, enable clocks,
etc.) as described earlier. Note again that the hard drive, even in this
routine, is NOT powered up until an access is requested.

C.5 HIBERNATION

The Hibernation feature provides three functions: it helps in preventing

data loss due to automatic shut down when the computer is left unattended,
and it provides a convenient "bookmark" function. Hibernation, when
initiated, saves all information in memory to disk, including information
that marks exactly where the user is in an application, and then powers
down the computer. Upon exiting Hibernation, the computer boots up, runs
the application last used and returns to the point the user was at when the
computer powered down.

Hibernation must be enabled (through the PWRCON utility) before it can be

initiated. Once enabled, Hibernation can be initiated one of three ways:

o After a specified period of time in Standby

o Upon reaching condition Low Battery 2

o With the Fn key and standby button (valid under battery or external
power, but NOT while using the system unit docked in the Desktop
Expansion Base)

When Hibernation is enabled, the PWRCON utility generates a hidden system

file called HIBRN8.DAT that is placed in the root directory (C:). A pointer
is written to configuration (CMOS) memory that points to a directory sector
in that file. The BIOS ROM can use this file independent of the operating
system. When Hibernation is initiated, the entire state of the system is
written to HIBRN8.DAT and a CMOS flag is set. Upon the next power up cycle,
the CMOS flag tells the system to read HIBRN8.DAT and restore the system
accordingly.

C.6 PROGRAMMING INFORMATION

The 386SL microprocessor features a new interrupt that is used specifically

for power management functions. This interrupt, called the system
management interrupt (SMI), has the highest priority of all interrupts
(even over the NMI).

In the COMPAQ LTE Lite, the SMI is generated by writing parameters to

INPUT: 00h = successful,
01h = error during operation

CMOS Location 72h - 74h: Not used

Get Battery Condition

I/O Port 10h

OUTPUT: 0Dh

I/O Port 11h

INPUT: 00h = successful,
01h = error during operation

CMOS Location 72h: See bit map below.

BIT FUNCTION
----------------
7..3 Reserved

2..0 Battery condition

(Only valid values are shown):
000 = External power
001 = Battery good
011 = Low battery 1
101 = Low battery 2

Get Battery Charge Left Condition

I/O Port 10h
OUTPUT: 0Eh

I/O Port 11h

INPUT: 00h = successful,
01h = error during operation

Get Memory Size

This function returns the total amount of system memory, measured in

256 Kbyte increments.

I/O Port 10h

OUTPUT: 12h

I/O Port 11h

INPUT: 00h = successful,
01h = error during operation

CMOS Location 72h, Bits 7..0: Total memory size in 256 Kbyte increments.

D.1 INTRODUCTION

This appendix provides information to aid a system administrator and

program developer in the use of the security and network features of the
COMPAQ LTE Lite Personal Computer. Topics discussed in this appendix
include:

o Feature Descriptions [D.2]

o System Configuration Procedure [D.3]
o Programming Information [D.4]

D.2 FEATURE DESCRIPTIONS

The following paragraphs describe the security and network features and how
they are used.

Power-On Password

This feature prevents unauthorized user access at power-on by requiring the

user to enter a password specified through the SETUP utility. This feature
must be enabled in order to use the Network Server Mode and
QuickLock/QuickBlank features.

The Power-On Password feature is established through the SETUP utility.

When the switch is set to OFF (default), the POST routine checks the
non-volatile configuration memory to determine if password protection is
being used, and, if so, displays an icon prompting the user to enter the
password to gain access.

Keyboard Password

This feature can be invoked to disable the keyboard and pointing device
during system operation and, to regain system control, require the user to
enter a password specified through the KP Utility on the User Programs
diskette. (The KP Utility operates in the MS-DOS and OS/2 operating system
environments. This feature is sustained only as long as the unit is powered
up. When the unit is turned off, the KP Utility must be executed when the
unit is powered back up.)

QuickLock/QuickBlank

The QuickLock feature allows a user to lock the keyboard while within an
application by invoking a hotkey combination. This action guards against
tampering with a system while the user is away from the workstation. When
enabling the QuickLock feature, the user has the additional option of
enabling/disabling the QuickBlank feature.
The QuickBlank feature, when enabled, blanks the screen when the QuickLock
feature is invoked. The user reaccesses the system by entering the power-on
password, which must also be enabled for this feature to function. The
QuickLock/QuickBlank feature is enabled/disabled through the SETUP utility.

Network Server Mode

The Network Server Mode, when enabled, allows the system to completely boot
up, but the keyboard is locked until the power-on password is entered. This
feature is useful for units being used as network servers. The Network
Server Mode is enabled/disabled through the SETUP utility. The network
server mode can only be invoked if the power-on password is set.

DriveLock

The fixed disk drive may be locked to prevent read/write access to data on
that drive. The DriveLock feature is configured with the COMPAQ SETUP
utility.

The user has three options of configuring the fixed disk drive password
feature:

o NONE (No security, password disabled) -- The fixed disk drive is unlocked
following POST. All operating system commands dealing with the fixed disk
drive are usable.

o Level 1 (maximum security, password enabled) -- The fixed disk drive is

unlocked only upon entering the correct user-defined password during
POST. If the correct password is not entered, the fixed disk drive
remains locked and all operating system commands dealing with the fixed
disk drive are unusable. If the password is forgotten, the only way to
regain access to the fixed disk drive is to use the WIPEDATA command (on
the Diagnostics diskette) to reformat the disk and disable the password.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>> CAUTION
<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<

Selecting level 1 (maximum) DriveLock security increases the possibility of

losing data should the password be forgotten.

>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>><<<<<<<<<<<<<<<<<<
<<<<<<<<<<<<<<<<<<<<

o Level 2 (high security, password enabled) -- The fixed disk drive is

unlocked upon entering the correct user-defined password during POST. If
the correct password is not entered, the fixed disk drive remains locked
and all operating system commands dealing with the fixed disk drive are
unusable. If the password is forgotten, the user must return the system
to the dealer who, upon verification of ownership, will enter a
COMPAQ-defined password (supplied by COMPAQ Service) to unlock the drive.

As suggested by the previous paragraph, there are actually two passwords

stored on the fixed disk drive: a user-defined password and a
COMPAQ-defined password. Only one is required to unlock the drive. Both
passwords are stored in non-data areas on the disk, and are not transferred
during disk backup procedures.

NOTE: The DriveLock feature cannot be used with the Network Server Mode.

Cable Lock Provision

The system unit includes a slot on the side of the chassis that facilitates
the use of a cable lock. A cable lock allows the system administrator to
secure the system unit to a desk or table, discouraging the unauthorized
removal or theft of the system unit.

D.3 PROGRAMMING INFORMATION

This section describes I/O ports and memory locations that are used by
security and network features. During the boot sequence, the BIOS ROM
reads the parameters stored in the RTC configuration (non-volatile) memory
by the COMPAQ SETUP utility. Additionally, software programs may access the
configuration memory and certain I/O ports to read the status of the
security features.

Status Read Of Security Features

The byte at RTC configuration memory location 13h includes the status of
the security features as shown below:

RTC Configuration Memory Location 13h

BIT FUNCTION
----------------
7..3 Reserved -- DO NOT CHANGE (Bits used for other functions.)

2 Power-on QuickLock status

0 = Disabled (default)
1 = Enabled

1 Network server mode

0 = Disabled (default)
1 = Enabled

0 Power-on password
0 = Disabled (default)
1 = Enabled

NOTICE

The information in this guide is subject to change without notice.

Compaq Computer Corporation shall not be liable for technical or editorial

errors or omissions contained herein; nor for incidental or consequential
damages resulting from the furnishing, performance, or use of this
material.

This guide contains information protected by copyright. No part of this

guide may be photocopied or reproduced in any form without prior written
consent from Compaq Computer Corporation.
Copyright 1993 Compaq Computer Corporation.
All rights reserved. Printed in the U.S.A.

Compaq, Deskpro, LTE

Registered U. S. Patent and Trademark Office.

The software described in this guide is furnished under a license

agreement or nondisclosure agreement. The software may be used or copied
only in accordance with the terms of the agreement.

Product names mentioned herein may be trademarks and/or registered

trademarks of their respective companies.

TECHNICAL REFERENCE GUIDE SUPPLEMENT

Compaq LTE Lite Family of Personal Computers

First Edition (June 1993)

Part Number: 018A/0693

1.1 ABOUT THIS SUPPLEMENT

Date: June 1993

Part Number: 018A/0693

This supplement provides information on specific 486SL-based models of the

Compaq LTE Lite Family of Personal Computers. The models covered feature
the Intel 486SL microprocessor.

The supplement covers the following 486SL-based models of the Compaq LTE
Lite Family of Personal Computers:

o Compaq LTE Lite 4/33C

o Compaq LTE Lite 4/25C
o Compaq LTE Lite 4/25E
o Compaq LTE Lite 4/25

For information on the 386SL-based members of the Compaq LTE Lite Family
and for subjects common to all models refer to the Compaq LTE Lite Family
of Personal Computers Technical Reference Guide, part number
(PN 140097-001).

For additional information on the 486SL microprocessor, refer to the

following Intel publications:

o Intel 486SL Microprocessor SuperSet Data Book -- PN 241325-001

o Intel 486SL Microprocessor Programmer's Reference Manual -- PN 241327-001
o Intel 486SL Microprocessor SuperSet System Design Guide -- PN 241326-001

This chapter covers the following subjects related to the 486SL-based

models listed above.

o Standard Features [1.2]

o Differences Data [1.3]
1.2 STANDARD FEATURES

Date: June 1993

Part Number: 018A/0693

The following features are standard on all 486SL-based Compaq LTE Lite
products:

o 486SL microprocessor
o Integrated coprocessor
o 4 megabytes of 32-bit system memory expandable to 20 megabytes
o 8-Kbyte integrated cache
o EasyPoint trackball
o Support for the Optional Desktop Expansion Base and QuickConnect Options
o Advanced Power Management features
o Nickel Metal Hydride (NiMH) battery pack
o Auxiliary battery

1.3 DIFFERENCE DATA

Date: June 1993

Part Number: 018A/0693

This section outlines the differences in standard features between the

members of the 486SL-based Compaq LTE Lite Family. These differences focus
on the speed of the microprocessor, type, and size of LCD display.

DIFFERENCE DATA

Table 1-1 lists the differences among the 486SL-based Compaq LTE Lite
products.

Table 1-1. 486SL-Based Compaq LTE Lite Difference Data

=======================================================
====================
Feature: Processor Speed

LTE Lite 4/25 25-MHz

LTE Lite 4/25E 25-MHz
LTE Lite 4/25C 25-MHz
LTE Lite 4/33C 33-MHz

---------------------------------------------------------------------------
Feature: Cache Memory

LTE Lite 4/25 8-Kbyte internal

LTE Lite 4/25E 8-Kbyte internal
LTE Lite 4/25C 8-Kbyte internal
LTE Lite 4/33C 8-Kbyte internal

---------------------------------------------------------------------------
Feature: Math coprocessor

LTE Lite 4/25 Integrated

LTE Lite 4/25E Integrated
LTE Lite 4/25C Integrated
LTE Lite 4/33C Integrated

---------------------------------------------------------------------------
Feature: Standard 32-bit Memory

LTE Lite 4/25 4 Mbytes

LTE Lite 4/25E 4 Mbytes
LTE Lite 4/25C 4 Mbytes
LTE Lite 4/33C 4 Mbytes

---------------------------------------------------------------------------
Feature: Maximum Memory

LTE Lite 4/25 20 Mbytes

LTE Lite 4/25E 20 Mbytes
LTE Lite 4/25C 20 Mbytes
LTE Lite 4/33C 20 Mbytes

---------------------------------------------------------------------------
Feature: LCD

LTE Lite 4/25 9.5" Monochrome STN (measured diagonally)

LTE Lite 4/25E 9.5" B/W TFT (measured diagonally)
LTE Lite 4/25C 8.4" Color TFT (measured diagonally)
LTE Lite 4/33C 8.4" Color TFT (measured diagonally)

---------------------------------------------------------------------------
Feature: Integrated Track Ball

LTE Lite 4/25 Yes

LTE Lite 4/25E Yes
LTE Lite 4/25C Yes
LTE Lite 4/33C Yes
=======================================================
====================

2.1 INTRODUCTION

Date: June 1993

Part Number: 018A/0693

This chapter describes the key design and technical features of the
486SL-based Compaq LTE Lite Family of Personal Computers.

The 486SL-based Compaq LTE Lite products are notebook computers weighing
between 6.3 and 6.5 pounds. The computers will operate for 2 to 5 hours of
continuous use on a single battery charge, depending upon which computer
and peripheral combination is chosen. The computer incorporates several
features that allow the user to conserve battery power while maintaining
operating efficiency. The computer may be connected to an optional Desktop
Expansion Base or QuickConnect option to expand it's functionality.

2.2 SYSTEM ARCHITECTURE

Date: June 1993
Part Number: 018A/0693

The 486SL-based computers like the 386SL-based computers, utilize a

concurrent bus architecture that allows the microprocessor to operate more
efficiently with the memory and peripheral subsystems.

The 486SL-based Compaq LTE Lite products feature the Intel 486SL
microprocessor and the 82360SL ISA peripheral controller. The core logic
of the 486SL microprocessor requires only 3.3 volts to operate thus
lowering the demand on the battery supply. The 486SL microprocessor
provides full 486DX processing capability with system power management,
32-bit memory management, ISA bus control, status, address, and data
interface logic added. The 82360SL peripheral controller provides
peripheral power management, real-time clock, and memory map functions.
The 82360SL also controls the DMA and interrupt controllers, and the
serial and parallel ports.

The diskette interface, hard drive interface, enhanced option slot

interface, and keyboard/ pointing device interfaces are contained in a
custom application-specific integrated circuit (ASIC). This ASIC also
provides distribution control of DMA and interrupt functions.

The video subsystem includes a video controller ASIC, 512 Kbytes of video
RAM, and either a monochrome or color liquid crystal display (LCD).

Figure 2-1 shows a block diagram of the 486SL-based Compaq LTE Lite
computers.

ILLUSTRATION OF Figure 2-1. 486SL-based Compaq LTE Lite Computer, Block

Diagram

Microprocessor

The 486SL microprocessor is similar in function to the 486DX

microprocessor. The architecture provides 32-bit processing internally and
interfacing with external subsystems over a 32-bit data bus. The 486SL
also includes an integrated bus controller, 32-bit memory controller,
integrated coprocessor, and integrated cache controller with an 8-Kbyte
4-way set associative cache. The 486SL microprocessor employs a static
design that allows the system clock to be shut off to preserve battery
power. The microprocessor includes a System Management Interrupt (SMI)
controller and power management hardware that provide overall system power
conservation. The core logic of the 486SL microprocessor requires only 3.3
volts to operate.

The 486SL microprocessor is supported by the 82360SL Input/Output

controller chip. The 82360SL provides most standard system peripheral
controllers and provides system management support.

BIOS Flash ROM

The Basic Input/Output System (BIOS) is contained in flash ROM. Flash ROM
retains data without power applied just like standard ROM. Unlike standard
ROM, data can be rewritten into flash ROM. This allows the BIOS to be
easily updated as necessary by using dedicated BIOS update utility
software.

System Memory

The system memory provides temporary storage of programs and data. The
486SL-based models have 4 megabytes of 80-ns enhanced page Dynamic Random
Access Memory (DRAM) that operates at processor speed. A maximum of 20
megabytes of memory may be installed using optional 4-,8-, or 16-megabyte
extended refresh memory cards that are easily installed without
disassembling the unit.

Mass Storage

The computer comes standard with a 3 1/2-Inch 1.44 megabyte diskette

drive. The 3 1/2 Inch 1.44 megabyte diskette drive reads and writes to
both 1.44 megabyte and 720-Kbyte diskettes.

The 486-based Compaq LTE Lite computers accommodate one internal hard
drive. Two hard drive capacities, 209-megabytes and 120-megabytes, are
available. Both hard drive types have 2 1/2-inch platters to save space
and limit weight. Refer to Chapter 6, "Hard Drive Subsystem", for
additional information.

Video Subsystem

The Compaq LTE Lite video subsystem consists of a VGA controller,

512 Kbytes of video RAM, and a liquid crystal display (LCD). The Compaq
LTE Lite 4/25 is equipped with a monochrome passive matrix VGA display and
video subsystem that supports VGA, EGA, and CGA video modes and provides
up to 64 shades of gray.

The Compaq LTE Lite 4/25E features an active matrix black and white VGA
display and video subsystem that provides high contrast scaling with up to
64 shades of gray.

The Compaq LTE Lite 4/25C and Compaq LTE Lite 4/33C feature a color TFT
active matrix VGA display with a color video subsystem that supports 256
simultaneous colors in 640 x 480 VGA resolution.

In addition to the integrated LCD, the video controller on all models can
simultaneously support either the Reduced Emissions Video Graphics Color
Monitor, the Video Graphics Color Monitor, or the Video Graphics
Monochrome Monitor. The video controller supports:

o 640-pixel x 480-line VGA-compatible graphics resolution

o 640-pixel x 350-line EGA-compatible graphics resolution
o 320-pixel x 200-line CGA-compatible graphics resolution
o 1056-pixel x 400-line text mode (external monitor only)
o 720-pixel x 400-line text resolution (external monitor only)
o Up to 256 colors out of a 262,144 color palette

To maintain the high performance requirements of the Compaq LTE Lite

computers, the BIOS code for the video graphics controller is copied into
the system RAM during the boot procedure to provide faster video
performance.

Enhanced Option Slot

The enhanced option slot allows the installation of an optional

communications device such as an enhanced modem or a second serial port.
The communications parameters of this interface are software-programmable.

2.3 SPECIFICATIONS

Date: June 1993

Part Number: 018A/0693

The environmental, electrical, and physical specifications of the

486SL-based Compaq LTE Lite products are provided in the following tables.

Table 2-1 lists the environmental specifications for a completely

assembled 486SL-based Compaq LTE Lite computer.

Table 2-1. Environmental Specifications

=======================================================
====================
Parameter Operating Nonoperating
=======================================================
====================
Air Temperature 50oF to 104oF -22oF to 140oF
(10oC to 40oC) (-30oC to 60oC)

Shock 5 G for 11 ms half-sine pulse 40 G for 11 ms

half-sine pulse

Vibration 0.15 G for 5-500 Hz sinusoidal 1 G for 5 - 500 Hz

sinusoidal

Humidity 10% to 90% (noncondensing) 5% to 95%

(noncondensing)

Maximum Altitude 10,000 ft (3048 m) 30,000 ft (9144 m)

=======================================================
====================

Table 2-2 lists the electrical specifications of the 486SL-based Compaq

LTE Lite computers.

Table 2-2. Electrical Specifications

=====================================
Parameter
=====================================
Input Voltage 12 VDC

Power Consumption
Average 10.0W
Peak 21.0W
=====================================
Table 2-3 lists the physical specifications (closed) of the 486SL-based
Compaq LTE Lite computers.

Table 2-3. Physical Specifications (Closed)

=======================================================
====================
English Metric
=======================================================
====================
Dimensions
Height 2.0 in 5.08 cm
Weight 11.0 in 27.9 cm
Depth 8.5 in 21.6 cm

Weight
Lite 4/25C and Lite 4/33C 6.5 lb 2.93 kg
Lite 4/25E 6.4 lb 2.88 kg
Lite 4/25 6.3 lb 2.84 kg
=======================================================
====================

3.1 INTRODUCTION

Date: June 1993

Part Number: 018A/0693

This chapter briefly describes the Intel 486SL microprocessor. The CPU
core is similar to the 486DX microprocessor with system power management
features added. Full programming compatibility across the entire 80X86
microprocessor family is standard.

Figure 3-1 is a simplified block diagram of the 486SL microprocessor.

ILLUSTRATION OF Figure 3-1. 486SL System Processor, Block Diagram

3.2 486SL MICROPROCESSOR

Date: June 1993

Part Number: 018A/0693

All 486SL-based Compaq LTE Lite computers were designed using the Intel
486SL microprocessor. The 486SL microprocessor has a 32-bit internal
architecture and interfaces with external functions and subsystems having
a 32-bit data bus. The 486SL includes a static CPU core, ISA bus control
logic, a 32-bit system memory controller, power management logic, and an
integrated cache controller with an 8-Kbyte 4-way set-associative cache.

The 486SL microprocessor is reset when internal (battery) or external

power is applied to the system board or if the system is already powered
and the user presses Ctrl + Alt + Delete. After reset, the microprocessor
addresses ROM for instructions. The initial boot in ROM checks the system
RAM and ROM for errors (checksums), then initializes the system.
Initializing or restarting the system loads the initialization and
configuration values into programmable devices. After initializing the
system, the microprocessor loads the operating system into memory either
from the diskette drive or from the hard drive.

Integrated Cache

The 486SL microprocessor has an integrated cache controller with an

8-Kbyte serial cache with a 16-byte line width. The cache is a 4-way
set-associative type and is grouped into four banks. The 4-way
set-associative cache permits each location in memory to map into any four
locations within the cache. When a cache miss occurs, the control logic
uses a least recently used algorithm to determine which of the four cache
locations to update first.

The internal cache operates normally in write-through mode so that when

the CPU writes to the cache, system memory is updated.

The cache controller also has bus-snooping logic to help maintain cache
coherency. The cache controller monitors the system address bus and
invalidates any cache data present that corresponds to newly overwritten
data in system memory.

External Interfacing

The 486SL microprocessor uses three data buses for external data
transfers. A memory bus, a peripheral interface bus, and an ISA bus are
required for external data transfers.

The memory bus provides data transfers at processor speed between the
microprocessor and system memory. The 486SL microprocessor includes an
integrated memory controller that supports up to 20 megabytes of physical
memory with optional 4-, 8- or 16-MB memory cards.

The system bus handles data transfers between the 486SL microprocessor and
the peripheral subsystems. The system bus has the functionality of two
buses: the peripheral bus, where transactions occur at processor speed,
and the ISA expansion bus, which provides full support of ISA transactions
at 8-MHz speed. The system bus operates as a peripheral bus during video
operations and as an ISA expansion bus for all other functions.

Table 3-1 lists the signals shared by peripheral and ISA operations on the
system bus.

Table 3-1. Peripheral/ISA Ops System Bus Signals

=======================================================
====================
Signal Function
=======================================================
====================
SA<19..0> System address signals

LA<23..17> Latchable address signals

SD<15..0> System data signals

SBHE- Bus high byte enable signal
=======================================================
====================

Table 3-2 shows control signals used by the system bus operating in the
peripheral mode.

Table 3-2. Peripheral Ops (Only) System Bus Signals

=======================================================
====================
Signal Function
=======================================================
====================
PSTART- P-bus start

PCMD- P-bus command

PRDY- P-bus ready

PMI/O- P-bus memory/I/O cycle

PW/R- P-bus write/read cycle

VGACS- VGA (video) chip select

FLSHDCS- Flash disk chip select

=======================================================
====================

All devices outside the 486SL microprocessor are addressed as either

memory-mapped or I/O-mapped devices. The PM/IO signal specifies whether a
memory-mapped or an I/O-mapped device or location is being addressed for
both peripheral and ISA modes.

Software Concepts

The 486SL microprocessor allows software compatibility by providing the

same operating modes as the 80286. The Real and Protected modes of the
486SL are fully compatible with 80286 instructions that use 8- and 16-bit
operands. In addition, the 486SL microprocessor extends register width as
well as address and data paths to 32 bits. This improves performance on
large integer calculations, data transfers, and large memory models. These
additional functions are transparent to applications not taking advantage
of them.

When power is applied or a reset operation occurs, the 486SL enters the
Real mode. The 486SL then provides all the capabilities and limitations
of Real mode, including compatibility with the 8086 and the 80286. The
Real mode allows only one megabyte of physical memory to be addressed and
does not provide any memory protection features. Memory is addressed via
the segment registers with the traditional 64-Kbyte limitation on segment
size. The major distinction between the Real mode of the 486SL and that of
the 80286 microprocessor is that 32-bit operands can be used with the
extended instruction set of the 486SL. This superset of the 80286
instruction set allows operations, such as multiplication, to use 32-bit
register or memory operands.

The improved functions allow implementation of much more powerful software

products. Many applications, such as artificial intelligence expert
systems, require a large linear address space and exceptional processor
performance to accommodate their size and complexity.

The 486SL microprocessor also offers the Virtual mode to provide

significantly improved compatibility with, and protection for, concurrent
execution of Real mode applications with Protected mode operating systems.
The Virtual mode allows applications written for 8088, 8086, or 80286 Real
mode to be executed within the privilege levels defined by Protected mode.
In contrast, the 80286 does not allow for security in real mode
applications because the microprocessor must be in the Real mode to
execute these applications.

The Virtual mode, in combination with memory paging, allows the Real mode
address space to be simulated anywhere in the physical address space of
the 486SL. In addition, the I/O protection features permit the operating
system to trap all or a selected set of I/O ports for device protection.

The Compaq Expanded Memory Manager (CEMM) enables the use of these
features.

Speed Control

Both 486SL-based and 386SL-based Compaq LTE Lite computers implement an

innovative feature that simulates system speeds less than the
(micro)processor speed. This feature has been implemented to provide
compatibility with a small number of software products that contain
programs dependent on certain system speeds. Typically, these programs
contain timing idiosyncrasies associated with the diskette copy protection
mechanisms. The processor speed can be slowed when the program accesses
the diskette drive to allow for compatibility with these copy protection
schemes.

The processor and system memory operate at processor (CPU) speed. Access
to the expansion bus and I/O devices always occurs at 8 MHz. The expansion
bus and I/O accesses are not affected by simulated changes in CPU
operating speed.

This simulated speed control is also useful for adjusting the computer to
handle action software games written for 8088-based personal computers.
Reduction of the system speed to simulate the system speed of an
8088-based personal computer allows these games to be played at a
realistic speed. Many games require the user to boot from the game
diskette. The computer accommodates this requirement by allowing the user
to restart the system, using Ctrl + Alt + Delete, without affecting the
selected system speed. The system remains at the selected speed until a
new speed has been selected or a power-on reset occurs.

The speed of the computer can be set to values that correspond to the
equivalent speeds of an 8088-based personal computer and 6- and 8-MHz
80286-based products. These values can be entered with the Mode command
(MODE SPEED = xx) from Microsoft MS-DOS or can be set with the "Set System
Speed" BIOS function (CX=xx) to simulate the computing speed of other
personal computer products.

MODE SPEED = AUTO is typically used for accessing a diskette drive at a

MODE SPEED = HIGH is typically used to provide maximum performance where

an application is not speed sensitive. In this mode, the CPU operates at
processor speed at all times.

Simulated CPU speed control is achieved by including special hardware on

the system board that uses extended refresh cycles to reduce the system
bus bandwidth. Since the CPU is in a HOLD state during refresh cycles, the
execution speed of programs is reduced as the length of the refresh cycles
is increased.

The lengthening of the refresh cycles, however, has been carefully

implemented so as not to increase the DMA latency period that is otherwise
present during refresh cycles of a normal length. A DMA request (for
access to the bus) that takes place during the extension of a refresh
cycle is immediately granted access to the bus, since the microprocessor
is already in a HOLD state.

Power Management Feature

The 486SL microprocessor includes an interrupt called the System

Management Interrupt (SMI). This feature is similar to the 386SL-based
models System Management Interrupt. The SMI, which is non-maskable and
has the highest priority (even over the NMI), is the mechanism by which
Advanced Power Management (APM) functions such as hibernation are
controlled. The SMI is initiated by writing Advanced Power Management
parameters to configuration memory locations 72h, 73h, and 74h, then
writing an SMI function code to port 10h.

For additional information about advanced power management, refer to the

APM specification, revision 1.0, available from Intel Corporation sales
offices and from Microsoft.

4.1 INTRODUCTION

Date: June 1993

Part Number: 018A/0693
The 486SL-based Compaq LTE Lite products memory subsystem includes the
following:

o BIOS Flash ROM [4.2]

o Configuration memory [4.3]
o System memory [4.4]

Figure 4-1 shows the 486SL-based Compaq LTE Lite memory subsystem block
diagram.

ILLUSTRATION OF Figure 4-1. 486SL-based Compaq LTE Lite Memory Subsystem

Block Diagram

4.2 BIOS FLASH ROM

Date: June 1993

Part Number: 018A/0693

The Basic Input/Output System (BIOS) and video firmware are contained in a
single 128K x 8 Flash Read Only Memory (ROM). Flash ROM operates like
standard ROM, providing nonvolatile storage of data, but has the added
convenience of being easily reprogrammed. Without removing the ROM chip,
the BIOS can be updated with appropriate utility software that will write
the new BIOS firmware into the ROM.

The BIOS Flash ROM is accessed through the X-bus (which is off the system
bus) during the power-on self-test (POST) routine (read cycle) and when
the BIOS is being updated (write cycle). Since system memory provides
higher performance than the Flash ROM, the contents of the Flash ROM are
copied into system memory (between F0000h and FFFFFh) during POST. All
subsequent BIOS calls are serviced as system memory accesses.

4.3 CONFIGURATION MEMORY

Date: June 1993

Part Number: 018A/0693

The configuration memory is contained within the 82360SL peripheral

controller.

Table 4-1 lists the configuration memory locations. Configuration memory

locations are not accessed directly. Instead, all configuration memory
accesses are accomplished by writing the desired configuration memory
address with an ISA bus write cycle to I/O port 70h and then writing or
reading configuration memory data to or from I/O port 71h.

Table 4-1. Configuration Memory Locations

=======================================================
====================
Register Function
=======================================================
====================
00h Seconds

01h Seconds Alarm

02h Minutes

03h Minutes Alarm

04h Hour

05h Hour Alarm

06h Day of Week

07h Day of Month

08h Month

09h Year

0Ah Status register A-Byte

0Bh Status register B-Byte

0Ch Status register C-Byte

0Dh Status register D-Byte

0Eh Diagnostic Status Byte

0Fh Reset Code Byte

10h Diskette Drive Type

11h Reserved

12h Fixed Disk Drive Type

13h Keyboard Options

14h Equipment Installed

15h,16h Base Memory Size

17h,18h Memory Amount

19h Drive C Extended Fixed Disk Drive Value

1Ah Drive D Extended Fixed Disk Drive Value (not used)

=======================================================
====================
Register Function
=======================================================
====================
1Bh Reserved

20h Reserved

21h Reserved

22h Reserved

23h Reserved

24h Fixed Disk Drive Timeout

25h Reserved

26h Reserved

27h External Drive Information (External Storage

Module)

28h Internal Base Memory/Extended Memory Allocation

29h Peripheral Configuration

2Ah Reserved

2Bh System Inactivity Timeout/Power Conservation

Power-Up Condition

2Ch Screen Time-Out

2Dh Additional Flags

2Eh,2Fh Memory Checksum

30h,31h Extended Memory

32h Date, Century

33h System Information

34h through 3 Fh Reserved

72h through 73h System Management

=======================================================
====================

Time, Calendar, and Alarm Rules

The first ten bytes, 00h through 09h, hold time, calendar, and alarm
information. The contents of these bytes may be in either binary or BCD
format, but not a mixture. For the format to be switched, all ten bytes
must be re-initialized in the new format.

Status and Configuration Bytes

The status and configuration bytes contain parameters that are stored in
configuration memory and used by the ROM BIOS to determine system
configuration during the boot sequence.

Status Register A -- Byte 0Ah

BIT FUNCTION
----------------
7 0 = All right to read device
1 = Time update in progress; device read not all right.

6..4 These bits specify the time base frequency. The default value is
010 (32.768 KHz).

3..0 These bits specify the divider frequency for the clock. The
default value is 0110 (1.024 KHz).

Status Register B -- Byte 0Bh

BIT FUNCTION
----------------
7 0 = Normal operation (default)
1 = Disable time updating so that time can be set

6 0 = Interrupt disabled (default)

1 = Enable interrupt at frequency specified by Status register A

5 0 = Disable alarm interrupt (default)

1 = Enable alarm interrupt

4 0 = Enable End-of-Update interrupt (default)

1 = Disable End-of-Update interrupt

3 0 = Output disabled (default)

1 = Enables frequency output selected by Status register A

2 0 = Time and Date in BCD format (default)

1 = Time and Date in Binary format

1 0 = 12-hour mode
1 = 24-hour mode (default)
0 0 = No Daylight Savings Time (default)
1 = Daylight Savings Time selected

Status Register C -- Byte 0Ch (Read Only)

BIT FUNCTION
----------------
7 1 = Interrupt Output signal active

6 1 = Periodic Interrupt Flag

5 1 = Alarm Interrupt Flag

4 1 = End-of-Update Interrupt Flag

3..0 Reserved

Status Register D -- Byte 0Dh

BIT FUNCTION
----------------
7 0 = Real-Time Clock has lost power
1 = Real-Time Clock has not lost power

6..0 Reserved

Configuration Byte Register 0Eh -- Diagnostic Status Byte

The diagnostic status byte tells the system when there is a problem (time
invalid, faulty fixed disk drive controller, etc.) with the configuration
of the subsystems.

BIT FUNCTION
----------------
7 1 = Real-Time Clock has lost power

6 1 = CMOS Checksum invalid

5 1 = System initialization equipment check does not match the

equipment specified in the configuration memory.

4 1 = The amount of memory detected during the system initialization

is not the same as the amount specified in the configuration
memory.

3 1 = Fixed disk drive or controller failed power-on test

2 1 = Time not valid

1,0 Reserved

Configuration Byte Register 0Fh -- Reset Code Byte

Configuration Byte Register 10h -- Diskette Drive Type

This byte keeps track of drive types for two diskette drives including an
optional diskette drive installed in the External Storage Module or the
Desktop Expansion Base.

BIT FUNCTION
----------------
7..4 Primary diskette drive type:
0100 = 1.44-megabyte diskette drive only

3..0 Secondary diskette drive type:

0000 = No diskette drive
0001 = 360-Kbyte diskette drive
0010 = 1.2-megabyte diskette drive
0011 = Reserved
0100 = 1.44-megabyte diskette drive
0101 = Reserved
:
1111 = Reserved

Configuration Byte Register 12h -- Fixed Disk Drive Type

The computer supports only one fixed disk drive, which is designated the
primary drive.

3..0 Reserved

Configuration Byte Register 13h -- Password/Network Server Mode

This byte contains the password and network server mode status.
BIT FUNCTION
----------------
7..2 Reserved

1 Password
1 = Exists
0 = not available

0 Network Server Mode

1 = Enabled
0 = Disabled

Configuration Byte Register 14h -- Equipment Installed

This byte tells the system the type of equipment installed in the unit.

BIT FUNCTION
----------------
7,6 Number of diskette drives installed:
00 = 1 drive
01 = 2 drives
10 = Reserved
11 = Reserved

5,4 Type of video display controller and operating mode:

00 = Reserved
01 = Color/Graphics, 40-column
10 = Color/Graphics, 80-column
11 = Monochrome/text

3,2 Reserved

1 0 = No coprocessor installed
1 = Coprocessor installed

0 0 = No diskette drives installed

1 = Diskette drive(s) installed

Configuration Byte Registers 15h and 16h -- Base Memory Size

Bytes 15h and 16h comprise a 16-bit value that specifies the base memory
size in increments of one Kbyte. The word is stored with the
least-significant byte at the lower address (in this case, 15h).

Table 4-2 defines valid sizes for the base memory.

Table 4-2. Valid Base Memory Size

=======================================================
====================
Byte 16h Byte 15h Memory Size (in Kbytes)
=======================================================
====================
01h 00h 256
02h 00h 512

02h 80h 639

04h 00h 1024

08h 00h 2048

=======================================================
====================

Configuration Byte Registers 17h and 18h -- Memory Amount

Table 4-3 defines the extended memory sizes for memory on all memory
option boards.

Table 4-3. Extended Memory Size

=======================================================
====================
Byte 18h Byte 17h Memory Size (in Kbytes)
=======================================================
====================
02h 00h 512

04h 00h 1024

06h 00h 1536

: : :
20h 00h 8192

20h 80h 8320

=======================================================
====================

Configuration Byte Register 19h -- Drive C Type

This byte contains the type number. If the fixed disk drive is an extended
drive type (type 15 or greater), bits <7..4> of byte 12h contain 1111
(binary).

Configuration Byte Register 1Ah -- Reserved

Configuration Byte Register 27h -- Memory Allocation/Base Memory Size

Since an additional external diskette drive may be installed in the

optional Desktop Expansion Base or External Storage Module which may be
configured as drive A or B, bits <1,0> are used to keep track of this
information. Bits <5..2> store diskette drive type(s) from Configuration
Byte register 10h. Bit <6> keeps track of CPU speed.

BIT FUNCTION
----------------
7 Reserved

6 CPU speed
0 = Auto
1 = High

5..2 Configuration Byte register 10h save value

1 External drive select:

0 = Drive B
1 = Drive A

0 External drive state:

0 = External drive not installed
1 = External drive installed

Configuration Byte Register 28h -- Peripheral Configuration

Bit 7 defines the source of hardware interrupt IRQ12. Bits <6,5> hold the
Base Memory Size and indicate how much base memory (640 Kbytes, 512
Kbytes, or 256 Kbytes) to enable. The system ROM writes out this amount to
the Memory Installed register (I/O port 1065h).

BIT FUNCTION
----------------
7 IRQ12 select:
0 = Pointing device (mouse)
1 = Expansion bus

6,5 Base Memory Size

00 = 640 Kbytes
01 = 512 Kbytes
10 = 256 Kbytes
11 = Illegal

4..0 Reserved

Configuration Byte Register 29h -- Peripheral Configuration

BIT FUNCTION
----------------
7 Printer Interrupt Select
0 -- Printer = IRQ5
1 -- Printer = IRQ7 (default)

6,5 Printer I/O Port Select

00 -- Primary I/O port (default)
01 -- Secondary I/O port
10 -- Tertiary I/O port
11 -- Disable I/O port
4 Internal Fixed Disk Drive Enable
0 -- Disable internal fixed disk drive
1 -- Enable internal fixed disk drive (default)

3 Serial/Modem Interrupt Select

0 = Serial = IRQ3; Modem = IRQ4
1 = Serial = IRQ4; Modem = IRQ3 (default)

2 Modem State
0 = OFF (default)
1 = ON

1 Serial State
0 = OFF
1 = ON (default)

0 Serial/Modem I/O Port Select

0 = Serial = COM1; Modem = COM2 (default)
1 = Serial = COM2; Modem = COM1

Configuration Byte Register 2Ah -- Fixed Disk Drive Timeout/Modem Status

This Power Conservation variable determines how much time, in one minute
multiples, before the fixed disk drive enters low power mode where power
to the motor is turned off.

This register is also used to determine the power-on state of the Power
Control register (I/O port 0865h), specifically for the fixed disk drive
and modem devices.

BIT FUNCTION
----------------
7 Reverse video
0 = White on black
1 = Black on white

6 Modem installed in system unit power-on state

0 -- OFF (default)
1 -- ON

5 Modem installed in system unit

0 -- Not installed (default)
1 -- Installed

4..0 Fixed disk drive timeout (minutes)

00000 -- No timeout
00001 -- 1 minute
00010 -- 2 minutes
:
10101 -- 21 minutes

Configuration Byte Register 2Bh -- Power Conservation Parameter

The first 5 bits, <4..0>, hold a Power Conservation parameter which

BIT FUNCTION
----------------
7,6 Power Conservation power-on condition
00 = PC AUTO (enable after 70 seconds)
01 = PC ON
10 = PC OFF

5 Run-Time Beep
0 = Enable
1 = Disable

4..0 System inactivity timeout (minutes)

00000 -- No timeout
00001 -- 1 minute
00010 -- 2 minutes
:
10101 -- 21 minutes

Configuration Byte Register 2Ch -- Screen Time-Out

The first 6 bits of this byte, <5..0>, hold a Power Conservation

parameter, which determines in one minute increments how long a period of
keyboard inactivity will elapse before the Backlit Display goes blank.
Bit <6> determines the Num Lock key status.

BIT FUNCTION
----------------
7 Reserved

6 Num Lock status

0 = Off 1 = On

5..0 Screen timeout value at power-on: (minutes)

000000 -- No timeout
000001 -- 1 minute
000010 -- 2 minutes
:
111111 -- 63 minutes

Configuration Byte Register 2Dh -- Additional Flags

This byte allows the configuration of special video features and disables
or enables keyclicking.

BIT FUNCTION
----------------
7..3 Reserved

2 0 = Video display controller not manufactured by Compaq installed

in Desktop Expansion Base
1 = Compaq Video Display Controller installed

1 0 = Disable keyclick
1 = Enable keyclick

0 0 = Monitor installed not dual-scan

1 = Dual-scan LCD installed

Configuration Byte Register 2Eh and 2Fh -- Memory Checksum

Value stored is the checksum for memory addresses 20h..2Dh.

Byte 2Eh = high byte of checksum

Byte 2Fh = low byte of checksum

Configuration Byte Registers 30h and 31h -- Extended Memory

Values indicate the amount of system memory in excess of 1 megabyte

detected at power-on. Bytes 17h and 18h are user defined. Bytes 30h and
31h are tested by ROM and compared with 17h and 18h. The table below
defines the extended memory sizes.

Configuration Byte Register 32h -- Date, Century

This is the century part of the current time and date encoded in BCD
(binary-coded decimal). The BIOS sets and reads this value.

Configuration Byte Register 33h -- System Information

BIT FUNCTION
----------------
7 1 = More than 1 megabyte of memory installed
0 = Less than 1 megabyte of memory installed

6 Used by SETUP procedures

5 Reserved

4 Coprocessor
1 = Installed
0 = Not installed

3 Run-Time Beep
1 = Disabled
0 = Enabled

2..0 Reserved

4.4 SYSTEM MEMORY

Date: June 1993

Part Number: 018A/0693

Compaq LTE Lite computers come with four megabytes of 80-ns enhanced-page
Dynamic Random Access Memory (DRAM) as standard system memory. The memory
controller is integrated into the 486SL microprocessor. This controller
supports LIM 4.0 EMS mapping and permits traditional Direct Memory Access
(DMA). The 82360SL provides local memory refresh support and allows bus
master control of memory.

Figure 4-2 shows the arrangement of the standard four megabytes of system
memory.

ILLUSTRATION OF Figure 4-2. Standard Four Megabytes of System Memory,

Block Diagram

Memory Map

System memory is typically configured with 640 Kbytes of base memory with
the extended memory mapped as shown in Figure 4-3.

ILLUSTRATION OF Figure 4-3. System Memory Map

Memory Expansion

The 486SL-based Compaq LTE Lite computers have a dedicated internal

expansion slot which permits increasing system memory by adding an
optional 4-, or 8-, or 16-Megabyte Memory Card for a total of up to 20
megabytes.

Memory Control

The 486SL microprocessor accesses data from system memory as a byte (8

bits) or as a word (16 bits), or a double word (32 bits). Words are stored
as two consecutive bytes with the low order bytes (D [7: 0] ), located at
the lowest address. Double words are stored as four consecutive bytes with
the lowest order byte (D [7: 0] ), at the lowest address and the highest
order byte (D [31: 24] ), at the highest address. The address of a word or
double word is always referenced at the address of the lowest order byte.

Memory Refresh

Refresh is provided to prevent loss of data in DRAM devices. The memory

controller of the 486SL microprocessor performs a DRAM refresh when the
REFREQ signal is asserted by the 82360SL peripheral controller. Refresh is
usually initiated by the 82360SL but can also be initiated with the
REFRESH- signal sent from a bus master installed in the Desktop Expansion
Base to the 82360SL.

If a refresh is in progress when a DMA cycle is requested, the DMA cycle

The standard DRAM used in Compaq LTE Lite computers feature low power
consumption and slow refresh times to provide longer battery usage. The
optional memory cards specifically designed for Compaq LTE Lite computers
also share the low power and slow refresh characteristics. The refresh
rates are dependent on the configuration of the system and whether or not
the system is in Standby.

Table 4-4 shows the system memory refresh rates for the various system
configurations.

Table 4-4. DRAM Refresh Specifications

=======================================================
====================
Configuration System Memory Refresh Rate
=======================================================
====================
Stand-alone Unit -- Normal operation:
No expansion memory 124.8 usec
80 nsec 4 MB/8 MB expansion memory 124.8 usec
80 nsec expansion memory/16-MB memory card 62.4 usec

Stand-alone unit -- Standby operation:

No expansion memory 124.8 usec
80 nsec 4 MB/8 MB expansion memory 124.8 usec
80 nsec expansion memory/16-MB memory card 62.4 usec

Unit with Desktop Expansion Base:

No expansion memory 15.6 usec
80 nsec 4 MB/8 MB expansion memory 15.6 usec
80 nsec expansion memory/16-MB memory card 15.6 usec
=======================================================
====================

5.1 INTRODUCTION

Date: June 1993

Part Number: 018A/0693

The power supply system for the 486SL-based Compaq LTE Lite products is
similar to the 386SL-based models with the addition of a 3.3 volt output,
required to power the 486SL microprocessor.

The power supply system consists of the external AC Adapter, internal DC

to DC converter, main Battery Pack, and Auxiliary Battery. Optional
equipment includes the external Battery Charger, Automobile Adapter, and
the Desktop Expansion Base.

Refer to the Compaq LTE Lite Family Technical Reference Guide

(PN 140097-001) for details on the individual sections of the power supply
system.
This chapter contains the following information:

o Functional Description [5.2]

o Specifications [5.3]

5.2 FUNCTIONAL DESCRIPTION

Date: June 1993

Part Number: 018A/0693

The computer is powered from an internal rechargeable battery pack. The

standard battery pack for the 486SL-based Compaq LTE Lite computers is the
Nickel Metal Hydride (NiMH) type.

The external AC Adapter provides power for the internal power supply
(DC/DC converter) and power to recharge both the battery pack and
auxiliary battery.

The internal power supply is a DC/DC converter that converts the input DC
voltage, from the AC Adapter or battery pack, to the voltages required by
the computer, memory, and display circuitry. The power supply provides an
additional 3.3-volt output. This voltage is required to power the low
power 486SL microprocessor.

The auxiliary battery operates the computer for a short period of time in
a reduced power state or standby mode. This reduced power state occurs
when the main battery pack is removed in order to replace it with another
battery pack.

Figure 5-1 shows a block diagram of the power supply system.

ILLUSTRATION OF Figure 5-1. Block Diagram of the Power Supply System

5.3 SPECIFICATIONS

Date: June 1993

Part Number: 018A/0693

Power supply specifications for the 486SL-based Compaq LTE Lite computers
are shown in Table 5-1.

Table 5-1. Internal Power Supply Specifications

=======================================================
====================
Input DC Voltage Range: 10.0 to 20.0 VDC

Power Output:
Steady State 16.5W
Peak 20.OW

Output Current: Maximum Peak

5.0 VDC Output 2.75A 3.50A
3.3 VDC Output 0.60A 0.60A
Voltage Regulation:
Output Nominal Regulation
+5.0 VDC +5.075 VDC +/- 3% of Nominal Voltage
+3.3 VDC +3.30 VDC +/- 10% of Nominal Voltage
=======================================================
====================

6.1 INTRODUCTION

Date: June 1993

Part Number: 018A/0693

This chapter describes the hard drives available for the 486SL-based
Compaq LTE Lite products. The 486SL-based Compaq LTE Lite products
accommodate one internal hard drive. Two hard drive capacities, 209-MB and
120-MB, are available. Both hard drive types have 2 1/2-inch platters.

One additional hard drive, a 1/2 height 210-MB, 120-MB, or 84-MB may be
added externally when using the optional Desktop Expansion Base.

For additional information about the Compaq LTE Lite Hard Drive Subsystem,
refer to the Compaq LTE Lite Technical Reference Guide (PN 140097-001).

6.2 SPECIFICATIONS

Date: June 1993

Part Number: 018A/0693

The following specifications are for the 209-MB and 120-MB hard drives
available in the 486SL-based Compaq LTE Lite computers.

Table 6-1. 209-Megabyte Hard Drive Physical and Electrical Specifications

=======================================================
====================
Formatted Capacity Per Drive: 209.7 MB

Drives Supported: 1

Drive Type(s) Supported: 16

Transfer Rate (AT Interface): 4.0 MB/s

Sector Interleave: 1:1

Access Time (including settling):

Track-to-Track (ms) <5
Average (ms) <16
Maximum (ms) <35

Physical Configuration:
Cylinders 1024
Heads 6
Sectors/Track 37 - 51
Bytes/Sector 512
Logical Configuration:
Cylinders 983
Heads 13
Sectors/Track 32
Bytes/Sector 512
=======================================================
====================

Table 6-2. 120-Megabyte Hard Drive Physical and Electrical Specifications

=======================================================
====================
Formatted Capacity Per Drive: 121.41 MB

Drives Supported: 1

Drive Type(s) Supported: 50

Transfer Rate (AT Interface): 4.0 MB/s

Sector Interleave: 1:1

Access Time (including settling):

Track-to-Track (ms) <5
Average (ms) <16
Maximum (ms) <35

Physical Configuration
(Drives installed from
either supplier):
Cylinders 1065 1122
Heads 6 4
Sectors/Track 34 - 47 (3 zones) 53
Bytes/Sector 512 512

Logical Configuration:
Cylinders 760
Heads 8
Sectors/Track 39
Bytes/Sector 512
=======================================================
====================

6.3 CONNECTOR

Date: June 1993

Part Number: 018A/0693

Table 6-3 lists the 44-pin hard drive Power/Interface connector signals.

Table 6-3. Hard Drive Connector Signal Definitions

=======================================================
====================
Pin Signal Description Pin Signal Description
=======================================================
====================
1 RESET- Reset 23 IOW- I/O Write

2 GND Ground 24 GND Ground

3 DD7 Data bit <7> 25 IOR- I/O Read

4 DD8 Data bit <8> 26 GND Ground

5 DD6 Data bit <6> 27 IORDY I/O Ready

6 DD9 Data bit <9> 28 RSVD Reserved

7 DD5 Data bit <5> 29 DMA ACK DMA Acknowledge

8 DD10 Data bit <10> 30 GND Ground

9 DD4 Data bit <4> 31 IRQ Interrupt Request

10 DD11 Data bit <11> 32 IO16- 16-bit I/O

11 DD3 Data bit <3> 33 DA1 Address 1

12 DD12 Data bit <12> 34 PDIAG- Pass Diagnostics

13 DD2 Data bit <2> 35 DA0 Address 0

14 DD13 Data bit <13> 36 DA2 Address 2

15 DD1 Data bit <1> 37 CSO- Chip Select

16 DD14 Data bit <14> 38 CS1- Chip Select

17 DD0 Data bit <0> 39 ACTIVE- Drive Activity

18 DD15 Data bit <15> 40 GND Ground

19 GND Ground 41 +5V +5V Logic

20 Clipped Key 42 +5V +5V Motor

21 RSVD Reserved 43 GND Ground

22 GND Ground 44 RSVD Reserved

=======================================================
====================

7.1 INTRODUCTION

Date: June 1993

Part Number: 018A/0693

The 486SL-based Compaq LTE Lite computers, like the 386SL-based Compaq LTE
Lite computers, have power conservation features that are designed to
extend operating time while running under battery power. These features
are user-controllable with hotkey combinations and through the SETUP and
PWRCON utilities. Note that when the computer is powered from an AC
source, the power conservation features are not available.

For additional information on power conservation for the Compaq LTE Lite
computers, refer to the Compaq LTE Lite Family of Personal Computers
Technical Reference Guide (PN 140097-001).

Compaq LTE Lite computers also implement Advanced Power Management

functions as specified in the Intel/Microsoft APM specification, revision
1.0. APM consists of a layered environment that allows the operating
system, system BIOS, and application programs to work together to reduce
power consumption. For additional information about advanced power
management, refer to the APM specification available from Intel
Corporation sales offices and from Microsoft.

7.2 POWER CONSERVATION LEVELS

Date: June 1993

Part Number: 018A/0693

The 486SL-based Compaq LTE Lite computers feature user-selectable power

conservation levels. The power conservation level determines parameters
such as subsystem timeouts, display brightness, and processor speed, all
of which affect the amount of drain the system places on the battery pack.
The power conservation levels are selected with hotkey combinations (from
the integrated keyboard only).

Table 7-1 shows the power conservation level settings.

Table 7-1. Power Conservation Level Settings

=======================================================
====================
Parameter High Medium * Drain Custom #
=======================================================
====================
System idle timeout 1 min 3 min 0 min 0 (disabled) - 17 min

Standby timeout 5 min 10 min 0 min 0 (disabled) - 17 min

Hard drive timeout 1 min 2 min 0 min 0 (disabled) - 31 min

Screen save timeout 2 min 5 min 0 min 0 (disabled) - 31 min

Display brightness 50% 100% 100% 0 - 100%

Processor speed:
LTE Lite 4/25 12.5 MHz 25 MHz 25 MHz 3, 6, 12.0, 25 MHz
LTE Lite 4/25E 12.5 MHz 25 MHz 25 MHz 3, 6, 12.0, 25 MHz
LTE Lite 4/25C 12.5 MHz 25 MHz 25 MHz 3, 6, 12.0, 25 MHz
LTE Lite 4/33C 16.5 MHz 33 MHz 33 MHz 4, 8, 16.5, 33 MHz
---------------------------------------------------------------------------
* Default at power-up
# Configured with PWRCON utility or SETUP
=======================================================
====================

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