EEE/ECE 365

Microprocessor

Lecture #8-9
External Interrupts, Multiple Ext. Interrupts
Md Rakibul Hasan
Lecturer, Dept. of EEE, BRAC University
Slide Courtesy of Imtiaz Ahmed, Lecturer, Dept. of EEE
BRAC University
 What is an Interrupt?
• Interrupt is a method of giving attention to a task which is not
scheduled as an usual task.
• In microcontroller usual task is to follow line by line execution of a
program.
• If a programmer wants to break the flow and attend a different task ,
then that has to be done by Interrupt.
• Whenever such a situation occurs, microcontroller raises a flag
corresponding to that task.
• The programmer set microcontroller in such a way that
microcontroller on its own monitor the flag and does the task
automatically – using ISR.
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 How Interrupt is handled with the help of
an ISR?
• Interrupts are basically events that require immediate attention by
the microcontroller.
• When an interrupt event occurs the microcontroller pause its current
task and attend to the interrupt by executing an Interrupt Service
Routine (ISR).
• At the end of the ISR the microcontroller returns to the task it had
paused and continue its normal operations.
• Usually each enabled interrupt has its own ISR.
• ISR is also called Interrupt Handler.

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 Interrupt Flags and Enabled bits
• Each interrupt is associated with two (2) bits in two different registers.
• An Interrupt Flag Bit and an Interrupt Enable Bit. These bits are
located in the I/O registers associated with the specific interrupt.
• The Interrupt Flag Bit is set whenever the interrupt event occurs,
whether or not the interrupt is enabled.
• The Interrupt Enable Bit is used to enable or disable a specific
interrupt. Basically it tells the microcontroller whether or not it should
respond to the interrupt if it is triggered.

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 Global Interrupt Enable Bit
• Apart from the enabled bits for the specific interrupts the global
interrupt enabled bit MUST be enabled for interrupts to be activated
in the microcontroller.
• For the 8-bits AVR microcontroller this bit is located in the Status I/O
Register (SREG).
Status Register, SREG
I T H S V N Z C
D7 D6 D5 D4 D3 D2 D1 D0
 Upon RESET all interrupts are disabled (masked).
 It means that none will be responded by the microcontroller if they
occur.
 So, the interrupts must be enabled by software in order for the
microcontroller to respond to them. 5
 Both bits should be high
• In summary basically both the Interrupt Flag and the Interrupt
Enabled are required for an interrupt service routine to be executed as
shown in the figure below.

Global Interrupt Enable

Interrupt Bit Interrupt
Enable Bit Interrupt Flag Service
Bit Routine

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 Internal and External Interrupt Sources
• The AVR 8-bits microcontroller provide both internal and external
interrupt sources. The internal interrupts are associated with the
microcontroller's peripherals.
• They are the Timer/Counter, Analog Comparator, etc.
• The external interrupts are triggered via external pins.
• On AVR ATmega32 microcontroller there are four (4) external interrupts:
• RESET Interrupt - Triggered from pin 9.
• External Interrupt 0 (INT0) - Triggered from pin 16.
• External Interrupt 1 (INT1) - Triggered from pin 17.
• External Interrupt 2 (INT2) - Triggered from pin 3.
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External Interrupt Pins

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 External Interrupts INT0, INT1 and INT2

• The hardware interrupts must be enabled before they can take effect.
• This is done using INTx bit located in GICR (General Interrupt Control
Register).
GICR Register
INT1 INT0 INT2 - - - IVSEL IVCE

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 Interrupt Sense Control bits for INT0
MCUCR (MCU Control Register)
SE SM1 SM2 SM0 ISC11 ISC10 ISC01 ISC00

ISC01 and ISC00 - These bits define the level or edge on the external INT0
pin that activates the interrupts, as shown in the following table

ISC01 ISC00 Description

0 0 The low level of INT0 generates an interrupt request
0 1 Change on INT0 generates an interrupt request
1 0 Falling edge of INT0 generates an interrupt request
1 1 Rising edge of INT0 generates an interrupt request
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 Interrupt Sense Control bits for INT1

MCUCR (MCU Control Register)

SE SM1 SM2 SM0 ISC11 ISC10 ISC01 ISC00

ISC11 and ISC10 - These bits define the level or edge on the external
INT1 pin that activates the interrupts, as shown in the following table

ISC11 ISC10 Description

0 0 The low level of INT1 generates an interrupt request
0 1 Change on INT1 generates an interrupt request
1 0 Falling edge of INT1 generates an interrupt request
1 1 Rising edge of INT generates an interrupt request

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 Interrupt Sense Control bit for INT2
• Interrupt 2 (INT2) can only be configures as edge triggered mode.
• In other words it can NOT be configured as level triggered.
• ISC2 bit of MCUCSR (MCU Control and Status Register) defines whether
INT2 interrupt will activate on falling or rising edge.

MCUCSR Register
JTD ISC2 - JTRF WDRF BORF EXTRF PORF

ISC2 Description
0 Falling edge of INT2 generates an interrupt request
1 Rising edge of INT2 generates an interrupt request
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 Sampling the edge-triggered and level-
triggered interrupts
• The edge-interrupt (the falling edge, the rising edge or the change
level) is latched by the AVR.
• It is latched by the INTFx bits of GIFR (General Interrupt Flag
Register).
• This means that when an external interrupt is in an edge-triggered
mode (falling edge, rising edge or level change), upon triggering an
interrupt request, the related INTFx flag becomes set.

GIFR Register
INTF1 INTF0 INTF2 - - - - -
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 Experiment with Int0
• A push button switch is connected in INT0 (PD.2) pin of the ATmega32
microcontroller.
• Eight numbers of LEDs are connected in Port C.
• One 7-segement display is connected in Port B.
• Normally LEDs will toggle at an interval of 1 second and 7-segment display
remains blank.
• If push button is pressed the LED task is hold up and the digits 0-9 will be
displayed on the display and finally again becomes blank.
• The LED task is resumed.

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 Experiment with Int0 (continued)
• The INT0 bit in the GICR register has to be set (i.e. INT0 will be
enabled.
• At first, we set falling edge as Interrupt sense control.
• We have to write an ISR to show 0-9 in the 7-segment display which
will be executed only when a falling edge (from 1 to 0) is generated at
INT0 pin.

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Schematic Design for a Single Interrupt

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#include <mega32.h> The Code [Use of Interrupt]
#include <delay.h>
#define segment_ddr DDRB void main(void)
#define segment_port PORTB {
#define led_ddr DDRC segment_ddr=0xFF;
#define led_port PORTC led_ddr=0xFF;
unsigned int GICR=(0<<INT1) | (1<<INT0) | (0<<INT2);
cathode[10]={0x3F,0x06,0x5B,0x4F, MCUCR=(0<<ISC11) | (0<<ISC10) |
0x66,0x6D,0x7D,0x07,0x7F,0x6F}; (1<<ISC01) | (0<<ISC00);
unsigned int i=0; // Global enable interrupts
interrupt [EXT_INT0] void ext_int0_isr(void) #asm("sei")
{ led_port=0x00;
for (i=0;i<10;i++) { while (1)
segment_port=cathode[i]; {
delay_ms(1000); led_port=~led_port;
} delay_ms(1000);
segment_port=0x00; }
} }
 Interrupt within an Interrupt
• When AVR is executing an ISR corresponding to an interrupt, what
happens if another interrupt is activated?
• In fact, when the AVR begins to execute an ISR, microcontroller, on its
own, disables the ‘I’ bit [Global Interrupt Bit] of the SREG register.
• So, no other interrupts occur while serving that ISR.
• When ISR is finished, the microcontroller again, on its own, enables the “I”
bit, causing other interrupts to be served.
• If you want another interrupt to be served while the current interrupt is
being served you can set the ‘I’ bit using SEI instruction.

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 Experiment Demonstrating Multiple
Interrupts
• Let us say we have two tasks to do.
• Task #1 - to show 0-9 digits one by one in a 7-segment display with a
delay of 1 sec.
• Task #2 - to glow one LED within a group of eight LEDs. Only the
leftmost LED will glow first. After one second, only its adjacent one
and so on until it reaches to the right most one.
• Task #1 will be executed with the interrupt Int0 and Task #2 with Int1.
• In the main program both the 7-segment display and the LED group
will be made OFF.

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Schematic Diagram for Multiple Interrupt

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 Observation in the Experiment
1. What happens if we interrupt Int0 when Int1 is being executed and vice
versa.
2. If you enable Global Interrupt Bit only in the ISR for Int0 what happens if
you interrupt Int1 while ISR for Int0 is being served and vice versa.
3. Observe the outcome by enabling Global Interrupt Bit in ISR for Int1 only.
4. Observe the outcome by enabling Global Interrupt Bit in both the ISRs.

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 Header file and Variable declaration

#include <mega32.h>
#include <delay.h>

unsigned int cathode[10] =

{0x3F,0x06,0x5B,0x4F,0x66,0x6D,0x7D,0x07,0x7F,0x6F};
unsigned int i=0, k=0;

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void main(void)
{
GICR=(1<<INT1) | (1<<INT0) | (0<<INT2);
MCUCR=(1<<ISC11) | (0<<ISC10) | (1<<ISC01) | (0<<ISC00);
MCUCSR=(0<<ISC2);

DDRB=0xFF;
DDRC=0xFF;
#asm("sei")
while (1)
{ Main Program
PORTB=0x00;
PORTC=0x00;
multi_int
}
} 23
 ISR for INT0
// External Interrupt 0 service routine
interrupt [EXT_INT0] void ext_int0_isr(void)
{
for (i=0; i<10; i++)
{
PORTB=cathode[i];
delay_ms(1000);
}
}

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 ISR for INT1
// External Interrupt 1 service routine
interrupt [EXT_INT1] void ext_int1_isr(void)
{
PORTC=0x80;
delay_ms(1000);
for (k=1; k<8; k++)
{
PORTC=PORTC>>1;
delay_ms(1000);
}
} 25
Thanks
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