BCSE 2"d year Semester (2dClass Test) [Set-31

Sub: Computer Organisation

Answer am three
IMarks: 30
(a) What are the advantages and disadvantages of hardwited control unit in cofnpurison with mieroprogramned cons
unit? (b) Which type of micreinstruetions provide beter parallelism? (c) How does the Nanoprogram control unit 6
reduce the memory space requlred in comparison with the micro-prograned control unit?
(a) Consider a system with a maii memory access time of 250ns supported hy a cache having a 25ns access time and a hit 4-6
rate of 75% Suppose scoess t0 cache and main mernoy occus cocurenitly. Whut would be etfective access time (EAT)
for this tuo-level memory (consider everlapping accesj What fappen if thiey do not overtap? (b) With the help of a
circuit diagram, discuss with working principle of a static RAM cell
38(a) How do you use a two state machine for branch prediction in pipelining 2+

(bi Let's cosider that 42650t is the lust six digits of your class roll number. Now, design a reervation tabe fot a 4-stage
pipeline arctitecture (Feteh-Decode-Eecute Write), and execute instructions (i te ts). Scan your roll nuimber from
right to left, and add delays using the following rule: if the digit is an odd number, add 2 detays for that instruction,
otherwise add one delay (you can àdd delays at any of the four stuges of the pipeline). For example, for the given roll
umber, two and one delays will be added for li and 1h, respectively, If the roll number (coesidering all 6 digits) ls an odd
humber, I: would be a branch instruction, otherwise 1s would be the brunch instruction. Consider that this architecture i
iaving an instruction pre-fetch queue. so that any cache miss for the instruction hazard can be casily solved. For cach
delay you will add, mention the hazard type due to which it got delayed.
() Describe the working principle of SSD (transistor level) (b) Describe the shortcomings of SSD. (c) Give some 52
solutions to those problems. 3

BCSE 2 year 1"Semester (2 Class Test) (Set4|

Sub: Computer Organisation
Answer any liree
Full Marks 30
Time: What are key functions of a control unit? (b) Give examples when data processing unit can send sgnals to the control 11
unit (c) Design the miero-programmed based control unit. Ciivea beief description of this design +8

2. (a) How does the read head woek in the maanetic disc? (b) Discuss the pros and cons of two dsk layouts: Constant244
delay.
Angular Velocity and Multiple Zone Reconding. (c) Define the disk performance parameters: seck time, rotational
access time and transfer time.
1aWhat are the limitations of handling data aa 2+8
be Now. desien a reservation table for a 4stage
(b) Let's cosider that 42650I is the last six digits of your
fion
pipeline architecture (Fetch-Decode-Execute-Write), and execute 8 instructions (I to h). Scan your roll number
rirht to left, and add delays using the following rule: if the digit is an odd number, add 2 delays for that instruction
oll
otherwisc add one delay (you can add delays at any of the four stages of the pipeline). For example, for the given
all 6 digits) is an odd
number, two ind one delays will be added Sor I and ls. respectively. If the roll number (considering
number, n would be a branch instraction, otherwise ls would be the branch instruction.
Consider that this architecture is
solved. For esch delay
hasing an instraction pre-fetch queue, so thut any cache miss for the instruction hazard can be casily
sou will dd, nention the hazard type due to which it got delay ed.
(Y534422001I), Now 4+5
41a)orisider the last 10 digits of your class roll number (X-l100224455), and reverse the namber
Now form XZ by appending Z after X
from Y. form Z. where you will subtract I from cach digit (24433119900),
that in yoar
XZ-11002244554433119900, This is your reference string Le.. dita reside in main memory, Now consider
to caleulate the number of
cache there are 3 lines Apply two page replacement algorithms, LRU and LFU, separately
cache misses. (b) Mention one advantage and one disadvantage of Write Back poliey.
 BCSE 2d year Semester (2d Class Test) [Set1|
Sub: Computer Organisation
Aniswer any three Full Marks: 30
Time: Ihr. unit. tb) What is the role of CMAR and alk 9+1
1.(a Discuss three implementation strategies of hurdwired control
regisders? (Y 5544220011)45
the
2. ) Consider the last 10 dgits of your class roll number (X-11002244SS, and revetse number
Now form XZ by appending Z atter1
Now from Y, forn Z. where sou will suberact from each digit (Z4413|199001
main menory, Now conider that in
X. NZ-110022445S4433119900, This is jour reference string ie, duta reside in
algorithms LRU and LFU, separatcly to calculate the nurher
your cache there are 4 lines. Appty two puge replacement
puge replacemcnt and shy?
of cache misses (b) Which memory mapping technique does not require
3. (a) Mention some solutions to the problem of control hazards
for a 4
class oll number. Nos, design a feservation table
(b) Let's consider that 426501 DecodeEsecute.Weite) und esecute 8 instructions ( to l). Scan your roll

ieht to let and add delavs sing the following rule: if the digit is an odd number.
instruction, otherwise add one delay (you can add delays at any of the four stages of the peme
add zd h e
given roll number, tso and one delays will be adted tor and l. a bnch instruction Consider that
digits) is an odd number, would be a hranch truet, u n e s i for the instruction hazard can he casily
is aret
solved. For each delay you detion the harad tpe due to which it ut delaycu
principle of a dynamie RAM cell, (b) Give the diagram of
4
4.(u) Wih the help of a circuit diagram, discuSs with working been lsed
all three levels of cache nemory. LL L2 and L3, have
the Pentium-IV cache memery organization, where
und muin memory occurs concurrently Let's consider
(C) There ba two-stage memory system, wherc access to eache
main memory access timeo f 150ns supported by a cache having a 1Sos acoess
time anda hit rate of 85%. What would
be effective access time (EAT) for thissystem if the aceesses overlap?

BCSE 2"d year 1" Semester (2 Class Test) (Set-2|

Sub: Computer Organisation
Answer any three Full Marks: 30
cons of 63
Time: 1hr. code based error detection method. (b) Discuss the pros and
1aWth asuitable example, discuss the Hamming
the utiique characteristic of DDR-SDRAM
logical cache and gp1ysical cache. (c) Mention memory and vice 74
suitable example, discuss how direct memory mapping (from cache memory to main
(a) Witha set-associative pproaches2
this approach? (c How does associative and
versa) works (b) What is the limitation of
overcome this limitation?
248
1How side effects create the data hazard?
for a 4
of your class rol number Now, design a reservatien table
bi Lests oonsider that 426501 is the last six digits roll numbe
(Fetch-Decode-Execute Writei, and execute &instructinns (i to l). Scan your
stage pipeline architecture foe that
and add delays using the following rule: if the digit is an odd number, add 2 delays
fom riglht to left, example, for the
at any of the four stages of the pipeline). For
instruction, otherwse add one delay (you can add delays number (cosidering all 6
he added foe i and Is. respectively. If the roll
eiven roll number, two and one delays will Consider that
instruction, otherwise would be the branch instructiun.
diaitsi is an odd number. Ia would bea branch
the istruction hazard can be casily
pre-fetch queue, so that any cache miss for
this architccture is having an instruction
die to which it got delayed.
dved. For cach delay you will add, mention the hazard type of343
main characteristics of RAID irespective of its level? (b) How many disks are required for cach
4(a) What are three
of Winchester Disk torat.
the 7 lcvels of RAIDP e) Define different fields