Full-Scan Design

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 The Scan Concept

VLSI System Testing 66 Jiun-Lang Huang, GIEE/ICDA, NTU

 The Scan-Design Rules
• The designers must adhere to the rules so that the design is scan-testable.
• Rule I: Use only D-type master-slave FFs.
• Rule II: At least one PI pin must be available for TC.
• Scan-in and out can be shared (using MUX) with functional
PI and PO.

• Rule III: All FF clocks must be controllable from PI.

• This is necessary for FFs to function as a scan register.
• Rule IV: Clock must NOT feed the data inputs of FFs.
• To avoid potential race conditions in the normal mode.
VLSI System Testing 67 Jiun-Lang Huang, GIEE/ICDA, NTU
VLSI System Testing 68 Jiun-Lang Huang, GIEE/ICDA, NTU
 Tests for Scan Circuits
• Phase I:
• Shift test
• Targets the scan flip-flops.
• Phase II:
• Combinational test
• Target the faults in the combinational circuit.

VLSI System Testing 69 Jiun-Lang Huang, GIEE/ICDA, NTU

 Phase I: Shift Test
• A toggle sequence
• 00110011… of length n+4 is scanned in.
• n is the maximum number of FFs in a scan chain.
• Each SFF experiences all four transitions: 0→1, 0→0, 1→1, 1→0.
• The shift test covers most single stuck-at faults in the FFs.
• The shift test also verifies the correctness of the shift operation.

VLSI System Testing 70 Jiun-Lang Huang, GIEE/ICDA, NTU

 Phase II: Combinational Test
• Each test vector consists of I and S i i

• Scan-test length
•n comb(n + 1) + n

•n comb: number of combinational tests

VLSI System Testing 71 Jiun-Lang Huang, GIEE/ICDA, NTU

 Multiple Scan Chains
• To reduce test time.
• However, each scan register has its own scan-in and scan-out.
• The scan registers may differ in length.
• Test time determined by the longest one.

VLSI System Testing 72 Jiun-Lang Huang, GIEE/ICDA, NTU

 Problem w/ Scan Design
• Area/performance overhead
• Increased gate count and routing area
• MUXed input (in single-clock SFF design)
• Extra load capacitance at FF output.
• Long test application time.
• Not applicable to all designs.
• Must follow the scan design rules.
• High power dissipation during testing.
VLSI System Testing 73 Jiun-Lang Huang, GIEE/ICDA, NTU
 Design Automation

VLSI System Testing 74 Jiun-Lang Huang, GIEE/ICDA, NTU

 Physical Design of Scan w/ Standard Cells
• Placing the cells without scan wiring.
• Replace FFs with SFFs.
• Wider than original.
• Add TC control line.
• At most one track in every alternate
routing channel.

• Scan path routing.

• One track in every alternate routing
channel is possible.

VLSI System Testing 75 Jiun-Lang Huang, GIEE/ICDA, NTU

 At-Speed Test Application
• For timing-related faults, need two-vector patterns.
• However, a scan cell only stores one vector.
• LoC (Launch-on-Capture) or LoS (Launch-on-Shift).

VLSI System Testing 76 Jiun-Lang Huang, GIEE/ICDA, NTU

 Delay Faults
• Cause excessive delay along a path such that the total propagation delay
falls outside the specified limit.

• Chips with delay faults may pass DC testing, e.g., stuck-at-fault testing, but
fail when tested at speed.
circuit test response

• Delay fault testing has become

< V1 , V2 >
under test sampled

mandatory.
t1 t2 t3

• Delay fault testing generally V1 V2

requires two-vector tests.

slow clock period
rated clock
period

VLSI System Testing 77 Jiun-Lang Huang, GIEE/ICDA, NTU

 Scan-Based LoC Test Pattern Application
at-speed
cycle
clk PI
combinational
PO

logic
se
PI I1 I2 PPI PPO

PPI S1 S2 FFs SE
SO SI
V1 ready launch V2 capture response

• An LoC pattern consists of two vectors.

•V 1 = < I1, S1 >, V2 = < I2, S2 > where I/S corresponds to PI/PPI.

•S 2 is generated by CUT.

• At-speed cycle is identical or similar to functional

operation.
78
ITC-Asia 2021 20210819
 University of Maryland Baltimore County
LAUNCH-ON-SHIFT (LOS)
Baltimore, MD 21250
tehrani,plusquel @umbc.edu
• Skewed-load

IC LC CC

CLK
ng fre-
aunch- SEN

ch-off-
lt test- Scan−in pattern i Scan−in pattern i+1
Scan−out response i−1 Scan−out response i
sed at- (a)
t scan
encap-
IC LC CC
opera- GIEE/ICDA, NTU VLSI System Testing 79
 LOW COST TESTER LIMITATIONS
• PI hold constant from launch to capture
• PO masked

GIEE/ICDA, NTU VLSI System Testing 80

 LOC VS. LOS
• Fault coverage
• Hardware requirement
• Test power

GIEE/ICDA, NTU VLSI System Testing 81

 Logic Built-In Self-Test (LBIST)

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 BIST Overview
• BIST — A design for testability (DFT) technique in which a portion of the
circuit on a chip, board, or system is used to test the digital logic circuit
itself.

• Reduce tester performance requirements or eliminate the need for external testers.
• BIST circuits may reside inside or outside the chip under test (internal BIST or external
BIST).

• With a properly designed BIST, the added cost will be more than balanced
by the benefits in terms of reliability and reduced maintenance cost.

VLSI System Testing 83 Jiun-Lang Huang, GIEE/ICDA, NTU

 Figure 5.2 shows a typical logic BIST system using the structural
technique. The test pattern generator (TPG) automatically generates
Typical Structural Offline BIST for application to the inputs of the circuit under test (CUT). The outp
analyzer (ORA) automatically compacts the output responses of the
signature. Specific BIST timing control signals, including scan enable

• The logic BIST controller coordinates the BIST operation among the TPG,
clocks, are generated by the logic BIST controller for coordinati
operation among the TPG, CUT, and ORA. The logic BIST controlle
CUT, and ORA. pass/fail indication once the BIST operation is complete. It includes
logic to compare the final signature with an embedded golden signatur

•
comprises diagnostic logic for fault diagnosis. As compaction is com
For example, the generation of timing for
control
outputsignals,
responseincluding
analysis, it scan-enable
is required thatand
all clocks.
storage elements

• Must meet BIST-specific design rules to Test Pattern Generator

facilitate fault detection or diagnosis. (TPG)

• Initialize TPG, ORA, and CUT to known states Logic

before self-testing. BIST -^"-M Circuit Under Test
(CUT)
Controller

• No unknown values from CUT to ORA.

•^^-H Output Response Analyzer
(ORA)

FIGURE 5.2

VLSI System Testing 84 logic BIST system.

A typical Jiun-Lang Huang, GIEE/ICDA, NTU
 BIST Advantages
• Manufacturing test costs are reduced due to reduced test time, tester
memory requirements, or tester investment costs.

• At-speed testing is inherent in BIST and can be used to detect many delay
faults.

• Facilitate in-system testing without an external tester.

• Faulty chip identification at the board or system level in a post-deployment environment.

VLSI System Testing 85 Jiun-Lang Huang, GIEE/ICDA, NTU

 BIST Disadvantages
• More stringent BIST-specific design rules are required to deal with unknown
(X) values.

• Extra hardware or memory storage may be required to achieve the desired

fault coverage.

• Must add test points or include ATPG patterns to make up for the deficiency of pseudo-
random patterns in detecting random-pattern-resistant faults.

VLSI System Testing 86 Jiun-Lang Huang, GIEE/ICDA, NTU

 Reality of Logic BIST
• BIST is NOT a replacement for scan design.
• In fact, most BIST approaches are built on top of full-scan.
• BIST does NOT result in fewer patterns.
• It usually uses many more patterns than ATPG patterns.
• BIST does NOT remove the need for testers.
• The tester is still required to initiate tests, read responses, and apply ATPG patterns.

VLSI System Testing 87 Jiun-Lang Huang, GIEE/ICDA, NTU

 BIST Design Rules Overview
• BIST design rules are more stringent than scan design rules.
• All scan design rules, even optional ones, are mandatory.
• Most logic-BIST rules are related to the propagation of unknown (X) values.
• Unknown inputs at ORA inputs will jeopardize response analysis and cannot be
tolerated.

VLSI System Testing 88 Jiun-Lang Huang, GIEE/ICDA, NTU

 the more typically used X-bounding methods for blocking an unknown (X) source:
The 0-control point forces an X source to 0; the 1-control point controls the X
source to 1; the bypass logic allows the output of the X source to receive both 0

Unknown Source Blocking

and 1 from a primary input (PI) or an internal node; the control-only scan point
drives both 0 and 1 through a storage element, such as D flip-flop; and, finally, the
scan point can capture the X-source value and drive both 0 and 1 through a scan
cell, such as scan D flip-flop or level-sensitive scan design (LSSD) shift register

• X-bounding (or X-blocking)

latch (SRL) [Eichelberger 1977].
Depending on the nature of each unknown (X) source, several X-bounding meth-
ods can be appropriate for use. The most common problems inherent in these

• Block or fix (using DfT repair) unknown values so that they cannot propagate to the ORA
approaches include: (1) that they might increase the area of the design, and (2) that
they might impact timing.
inputs directly or
5.2-/./ Analog Blocks indirectly.

• X-bounding examples:
Examples of analog blocks are analog-to-digital converters (ADCs). Any analog
block output that can exhibit unknown (X) behavior during test has to be forced to a

BIST_mode BIST_mode from PI or

Internal node
BIST_mode
Typical X-bounding methods for blocking an unknown (X)
source: (a) 0-control point; (b) 1-control point; (c) bypass logic;
(a) (b) (c) (d) control-only scan point; and (e) scan point.

X
' ^
r- i)
D- D
SE
D Q
J 11
CK—>CK BIST_mode BIST_mode
( >CK

(d) (e)

FIGURE 5.3
VLSI System Testing 89 Jiun-Lang Huang, GIEE/ICDA, NTU
 X-Blocking Practices
• Analog blocks, e.g., ADC:
• Bypass logic and control-only scan point are recommended to achieve higher fault
coverage.

• Memories and non-scan storage elements

• Use bypass logic to block unknown values originating from them.
• Properly initialize them to a known state.
• No performance overhead.
• Make sure that BIST operations do not corrupt the state.

VLSI System Testing 90 Jiun-Lang Huang, GIEE/ICDA, NTU

 • Combinational feedback loops
• Break them if they are unavoidable.
• A scan point yields higher fault coverage and is preferable to a 0/1-control point.
• Asynchronous set/reset signals
• Must be disabled during the shift operation — by using SE.
• The data logic and set/reset logic should be tested separately during the capture
operation.

VLSI System Testing 91 Jiun-Lang Huang, GIEE/ICDA, NTU

 tion. This may become cumbersome for BIST applications where there is a need
to use the pin for other purposes. Thus, we recommend using the existing scan

• Asynchronous set/reset signals (cont'd)

enable (SE) signal to protect each shift operation and adding a set/reset clock point
(SRCK) on each set/reset signal to test the set/reset circuitry, as shown in Figure 5.4
[Abdel-Hafez 2004].
• Recommend adding an SRCK test point on each set/reset signal.

Scan-In Logic Built-in Self-Test 269

FIGURE 5.4
Shift Window Capture Window Shift Window Capture Window Shift Window \
Set/reset clock point for testing a set/reset-type scan cell.
C1
CK JL ... J I n _n n_ JX ... SL
02
SRCK n
SE

FIGURE 5.5
VLSI System Testing 92 Jiun-Lang Huang, GIEE/ICDA, NTU
 Bus contention occurs when two drivers force different values on the same bus
• Tristate
which canbuses
damage the chip; hence, it is important to prevent bus conflicts during
normal operation as well as shift operation [Cheung 1996]. For BIST applications,
• Must
since be disabled during
pseudo-random the BIST
patterns areoperation.
commonly used, it is also crucial to protect the
capture operation [Al-Yamani 2002]. To avoid potential bus contention, it is best
• The use of pseudo-random patterns mandates deactivation during the capture
to resynthesize each bus with multiplexers. If this is impractical, make sure only
operation.
one tristate driver is enabled at any given time. The one-hot decoder shown in
Figure 5.6 is an example of a circuit that can ensure that only one driver is selected
• It is recommended that buses with
during each shift or capture operation. multiplexers be re-synthesized.

• Or, ensure only one tristate driver is enabled at any given time.
EN1 EN1
H 5 ^
D1
EN2
D2 EN2 —4

VLSI System Testing

(a) 93
(b)
Jiun-Lang Huang, GIEE/ICDA, NTU
 Multiple-cycle paths are normal functional paths but data are expected to arrive
after two or more cycles. Similar to false paths, they can cause mismatches if
• False paths
exercised during delay fault testing, as they are intended to be tested in one cycle. To
avoid this potential problem, we recommend adding a 0-control point or 1-control
• They are not normal functional paths but may be activated by pseudo-random patterns.
point to each multiple-cycle path or holding certain scan cell output states to avoid
•
those multiple-cycle paths.
They typically do not meet timing specifications, which can result in a mismatch during
logic BIST delay fault testing.
5.2.1.9 Floating Ports
• Recommend adding a 0-control point or 1-control point to each false path.
Neither primary inputs (Pis) nor primary outputs (POs) can be floating. These

• ports must have a proper connection to power (VDD) or ground (Vss). Also, floating
Critical paths
inputs to any internal modules must be avoided. This has a potential chance to
•
propagate unknown (X) values to the ORA.
Remove an unknown (X) value from a critical path by adding an extra input pin to a
selected combinational gate on the critical path to minimize the added delay.

-{>- H BIST_mode
BIST_mocle

(a) (b) (c)

VLSI System Testing 94 Jiun-Lang Huang, GIEE/ICDA, NTU
 • Floating ports
• Neither primary inputs nor primary outputs can be floating.
• Must provide proper connection to V or ground.
DD

• Bidirectional I/O Ports

• Make sure to fix the direction of each bidirectional I/O port to either input or output
mode.
Logic Built-in Self-Test 271
• Example: forcing a bidirectional I/O to output mode.
EN
^
SE D <I>IO
BIST_mode ' Z

FIGURE
VLSI 5.8
System Testing 95 Jiun-Lang Huang, GIEE/ICDA, NTU
 Re-Timing
• The distance from TPG and ORA to the CUT may result in large clock skew
Logic Built-in Self-Test
which leads to races and hazards.

• Between the TPG and the (scan chain) inputs of the CUT. EN ^
SE <I>IO
• Between the (scan chain) outputs of the CUTBIST_mode
and the ORA.
'
D
Z

• This can be fixed by inserting re-timing logic.

FIGURE 5.8

• At least one negative-edgeForcing

and one positive-edge
a bidirectional D flip-flop.
port to output mode.

• Example: D Q D Q D Q D Q
CK1, CK2, and CK3 could belong to CUT
J>CK J>CK i>CK r-t>CK
one clock tree. z\

CK1 CK2 CK3

VLSI System Testing 96 Jiun-Lang Huang, GIEE/ICDA, NTU
 Logic Built-In Self-Test (LBIST)

LFSR — Theory and Operation

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 Linear Feedback Shift Register (LFSR)
• Consists of n D-type flip-flops and a selected number of exclusive-OR
(XOR) gates.

• flip-flop: one cycle delay.

• XOR: modulo-2 addition.
• connection: modulo-2 multiplication
• Example:
initial value (seed)

VLSI System Testing 98 Jiun-Lang Huang, GIEE/ICDA, NTU

 selected number1982].
LFSR[Golomb oi exclusive-OR (XOR) gates. Because XOR gates are placed on the
external feedback path, the standard LFSR is also referred to as an extemal-XOR
LFSR[Golomb
Modular LFSR 1982].
Standard
Similarly, an n-stageand
Modular LFSR Modular
modular LFSR with each XOR gate LFSRs
placed between two adja-
cent D flip-flops, as shown in Figure 5.11, is referred to as an intemal-XOR LFSR
Similarly, an n-stage
[Golomb 1982]. The modular
modular LFSR
LFSR with
runs each
fasterXOR
thangate
itsplaced between two
corresponding adja-
standard

• Standard LFSR is also called external LFSR.

cent
LFSR,D because
flip-flops,each
as shown in Figure 5.11,
stage introduces is referred
at most to as andelay.
one XOR-gate intemal-XOR LFSR
[Golomb 1982]. The modular LFSR runs faster than its corresponding standard
LFSR, because each stage introduces at most one XOR-gate delay.

• Modular LFSR is also called internal LFSR.

FIGURE 5.10

An A?-stage (external-XOR) standard LFSR.

FIGURE 5.10

• Faster than standard LFSR.

An A?-stage (external-XOR) standard LFSR.

FIGURE 5.11

An A7-stage (internal-XOR) standard LFSR.

FIGURE 5.11

An A7-stage (internal-XOR) standard LFSR.

VLSI System Testing 99 Jiun-Lang Huang, GIEE/ICDA, NTU

 erage, we can use pseudo-exhaustive testing [McCluskey 1986] to generate 2^ or
Modular LFSR 2^-1 test patterns, where w <k<n, when each output of the n-input combinational
CUT at most depends on w inputs. For testing delay faults, hazards must also be
Characteristic Polynomial
Similarly, an n-stage modular LFSR with each XOR gate placed between twointo
taken
cent D flip-flops, as shown in Figure 5.11, is referred to as an intemal-XOR LFSR
adja-consideration.

[Golomb 1982]. The modular LFSR runs faster than its corresponding standard
LFSR, because each stage introduces at most one XOR-gate delay. Standard LFSR

• The internal structure of the n-stage LFSR can be described by specifying a

Figure 5.10 shows an n-stage standard LFSR. It consists of n D flip-flops and a
selected number oi exclusive-OR (XOR) gates. Because XOR gates are placed on the
characteristic polynomial of degree n, f(x). external feedback path, the standard LFSR is also referred to as an extemal-XOR
LFSR[Golomb 1982].

• f (x) = 1 + h1x + h2x + − + hn⋯1x + x

2 n⋯1Modularn LFSR
Similarly, an n-stage modular LFSR with each XOR gate placed between two adja-
cent D flip-flops, as shown in Figure 5.11, is referred to as an intemal-XOR LFSR

• hi is either 1 or 0, depending on the existence or absence of the feedback path.

FIGURE 5.10

An A?-stage (external-XOR) standard LFSR.

[Golomb 1982]. The modular LFSR runs faster than its corresponding standard
LFSR, because each stage introduces at most one XOR-gate delay.

FIGURE 5.11 FIGURE 5.10

An A7-stage (internal-XOR) standard LFSR. An A?-stage (external-XOR) standard LFSR.

VLSI System Testing 100 Jiun-Lang Huang, GIEE/ICDA, NTU

 Figure 5.12b, below. The characteristic polynomials, f{x), used to construct both
LFSRs are l-^x'^+x'^ and \-\-x-\-x^, respectively.
4-Stage Standard and Modular LFSRs
The test sequences generated by each LFSR, when its initial contents, SQ, are set
to [0001] or SQ(X) =X^, are listed in Figures 5.12c and 5.12d, respectively. Because
2 4 4
1+x +x 1+x+x

(a) (b)

0001 0001
1000 1100
0100 0 110
1010 0011
0101 1101
00 10 10 10
0001 0101
1000 1110
0100 0111
1010 1111
0101 1011
0010 1001
0001 1000
1000 0100
0100 0010
1010 0001

(c) (d)

VLSI System Testing • FIGURE 5.12 101 Jiun-Lang Huang, GIEE/ICDA, NTU
 Galois Field GF(2)
• Operation
• Modulo-2 addition, subtraction, multiplication, and division of binary values.
• Properties
• Modulo-2 addition and subtraction are identical.
• 0 ± 0 = 0, 0 ± 1 = 1, 1 ± 0 = 1, 1 ± 1 = 0
• Examples

VLSI System Testing 102 Jiun-Lang Huang, GIEE/ICDA, NTU

 LFSR Properties
• Maximum-length sequence:
• A sequence generated by an n-stage LFSR is called a maximum-length sequence if it has
a period of 2n-1.

• A maximum-length sequence is called an m-sequence.

• Primitive polynomial
• The characteristic polynomial associated with an m-sequence is called a primitive
polynomial.

VLSI System Testing 103 Jiun-Lang Huang, GIEE/ICDA, NTU

 • Numbers of 1s and 0s
• The number of 1s in an m-sequence differs from the number of 0s by one.
• Pseudo-random sequence
• The sequence generated by an LFSR is a pseudo-random sequence.
• The correlation
• Very close to zero between any two output bits.
• Consecutive run of 1s and 0s
• An m-sequence produces an equal number of runs of 1s and 0s.
• In every m-sequence, one-half of the runs have length 1, one-fourth of the runs have
length 2, one-eighth of the runs have length 3, and so forth.

VLSI System Testing 104 Jiun-Lang Huang, GIEE/ICDA, NTU

 LFSR — Polynomial Multiplication

g x =x +x + x +x +

+ D4 + D3 D2 D1

Output stream D4 D 3 D 2 D 1 Input stream

0 0 0 0 1 1 0 1
Add-and-shift
1 1 0 0 1 1 0 1
1 0 1 0 1 1 0 1
1 0 1 0 1 1 0 1
1 0 1 1 0 1 0 1
x 7 x 5 x 4 x 2 1

(x +x + ) × (x +x + )= x +x +x +x +

VLSI System Testing 105 Jiun-Lang Huang, GIEE/ICDA, NTU

 LFSR — Polynomial Division

Input 4
g( x ) = x + x + 1 3
Output Q(x)
011011011 11001
M(x) + D1 D2 D3 + D4
x+x2+x4+x5+x7+x8 1+x+x4

M(x) D1 D 2 D 3 D 4 Q(x) Quotient

0 1 1 0 1 1 0 1 1 0 0 0 0
after 4 0 1 1 0 1 1 0 1 1
shifts 0 1 1 0 0 1 0 0 1
0 1 1 0 0 1 0 0 1
0 1 1 0 0 1 0 0 1
0 0 1 0 1 1 0 0 1
1 0 1 1 1 1 0 0 1
Remainder 1 +x2+x3 1 +x +x4

(x8+x7+x5+x4+x2+x) ÷ (x4+x3+1) = x4+x+1

R(x) = x3+x2+1

VLSI System Testing 106 Jiun-Lang Huang, GIEE/ICDA, NTU

 Logic Built-In Self-Test (LBIST)

Test Pattern Generation

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 Overview
• Three forms of testing
stuck-at fault
fault simulation pattern count comments
coverage

exhaustive 100% no 2n long test time

suffer long fault

pseudo-random < 100% yes
simulation time

pseudo-exhaustive 100% maybe can still be large may need DfT

• LFSR-based TPGs are most common for logic BIST applications.

VLSI System Testing 108 Jiun-Lang Huang, GIEE/ICDA, NTU

 Pseudo-Random Testing
• Testing of a circuit with pseudo-random patterns.
• Reproducible and with many characteristics of random patterns.
• Not all 2n patterns are generated.

• Suffer random-pattern-resistant faults.

• Non-trivial test quality (fault coverage) evaluation:
• Lengthy fault simulation
• Fault detection probability analysis
• Estimation of test length as a function of fault coverage
VLSI System Testing 109 Jiun-Lang Huang, GIEE/ICDA, NTU
 Weighted Test Generation
• Adjust the distribution of 0s and 1s to increase coverage of pseudo-random-
pattern-resistant faults.

• Such a generator can be realized using an LFSR and combinational logic.

• Determine the set of weights in advance.
Logic Built-in Self-Test 279
• Weights for different parts of the
circuit may differ.

• Example:
A 4-stage weighted LFSR with
0.25 0-probability.

VLSI System Testing 110 Jiun-Lang Huang, GIEE/ICDA, NTU

 Signals of Arbitrary Weights

• Decompose the desired probability into a sum of basic weights (2 ⋯n

).

• Use AND and OR gates to realize the weight.

• Example: to realize 1-probability of 5/32.
• 5/32 = 1/8 + 1/32

VLSI System Testing 111 Jiun-Lang Huang, GIEE/ICDA, NTU

 Adaptive Test Generation
• Multiple sets of weights are employed.
• Derived with the help of fault simulation.
• More efficient tests, but more complicated TPG hardware.
• Example:
Programmable weighted
LFSR.

VLSI System Testing 112 Jiun-Lang Huang, GIEE/ICDA, NTU

 Logic Built-In Self-Test (LBIST)

Output Response Analysis

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 Need of ORA
• For BIST operations, it is impossible to store all output responses on-chip,
on-board or in-system to perform a bit-by-bit comparison.

• Output responses are compacted into a signature and compared with a

golden signature either embedded on-chip or stored off-chip.

• Compaction vs. compression: the former is lossy, and the latter lossless.
• Aliasing probability should be kept low.

VLSI System Testing 114 Jiun-Lang Huang, GIEE/ICDA, NTU

 cept that the signature is defined as the number of 0-to-l and 1-to-O transitions.
theory behind transition count testing is similar to that for ones count testing,
he transition count test technique [Hayes 1976] simply requires using
ept that the signature is defined as the number of 0-to-l and 1-to-O transitions. a D flip-
Ones and Transition Count Testing
optransition
and an XOR gate connected to a ones counter (see Figure 5.28), to
count test technique [Hayes 1976] simply requires using a D flip- count the
and an XOR gate connected to a ones counter (see Figure 5.28), to count the

/ w
CUT Counter
•
i V
/ w
CUT Counter
•
i V

CLK >
C (L, m) ⋯ 1
— i

CLK > P (m) =

2L ⋯ 1 L: bitstream length
— i
FIGURE 5.27 m: the number of 1s

GURE 5.27
es counter as ORA.
counter as ORA.

T - — J CUT D Q ^ Counter 7^-^ Signature

T - — J CUT D Q ^ Counter 7^-^ Signature
2C (L ⋯ 1,m) ⋯ 1
CLK- P (m) =
CLK-
2L ⋯ 1
FIGURE 5.28
GURE 5.28
ansition counter as ORA.
VLSI System Testing 115 Jiun-Lang Huang, GIEE/ICDA, NTU
 responses from a CUT having a single output, and (2) parallel signature analysis
for compacting responses from a CUT having multiple outputs.

Signature Analysis using SISR 5A.3.1 Serial Signature Analysis

Consider the n-stage single-input signature register (SISR) shown in Figure 5.29.
This SISR uses an additional XOR gate at the input for compacting an L-bit

• Single-input signature register (SISR)

• Add an XOR gate at the input of a modular
LFSR to compact an L-bit bitstream. M •©—H

•
FIGURE 5.29

After shifting the L-bit bitstream, M, into the modular LFSR, the contents
An n-stage single-input signature register (SISR).

(remainder) of the SISR, r, satisfy M (x) = q (x) f (x) + r (x).

• M = {m0m1m2−mL⋯1}:M (x) = m0 + m1x + m2x + − + mL⋯1x . 2 L⋯1

• { }
2 n⋯1
r = r0r1r2−rn⋯1 : r (x) = r0 + r1x + r2 x + − + rn⋯1x is the signature.

• Aliasing probability: P (n) × 2 ⋯n

if L ≠ n.

VLSI System Testing 116 Jiun-Lang Huang, GIEE/ICDA, NTU

 The remainder [1011] is equal to the signature derived from Figure 5.30a when
SISR is first initialized to a starting pattern (seed) of [0000].
SISR Example Now, assume fault f^ produces an erroneous output stream M' = {11001011

• f (x) = 1 + x + x
we 4obtain q\x) =x^ +x^ and r\x) = 1 —
M-M H •
-i-x-\-x^ ^J
M'{x) = l+x-\-x^ ~\-x^-\-x^, as given in Figure 5.30b. Using polynomial divi
—or• R = {1110}. Because the f

signature jR', {1110}, is different from the fault-free signature R, [1011], fault

•
detected.
M ro For fault/2 with
3 M4' ' = {11001101}
6 7 or M''(^) = 1+^+-^^-f-^^ H-^^ as giv
M = {10011011}, M (x) = 1 + x + x + x + x
^1 rz A3 M' To r^ 1-2 Tg M " ^0 r^ ^2 ^
1 0 0 0 0 1 0 0 0 0 1 0 0 0 0

•
1 1 0 0 0 1 1 2 0 30 0 0 1 0 0 0
Using polynomial0 division,
1 1 0 we 0have q (x) 0 = x
1 + x
1 0 0 and 1 0 1 0 0
2 1 30
r (x) = 1 + x + x . 1 1 0 M-M
1
H
0 1—•
1 —•
0 ^J 1 1 0 1 0
1 1 0 1 1 0 1 0 1 1 0 1 1 0 1
M ro ^1 rz A3 M' To Tg M " ^0

•
0 0 0 0 1 0 0 0 0 r^ 1-2 1 0 r^
1 ^20 ^3 1 0
M' detected; 0 1 11 00 0 0 0 0 1 1
1 0 0 0 0
1 0 0 1
1 0 0 0 0
0 1 0 1
1 1 0 0 0 1 1 0 0 0 0 1 0 0 0
M'' not detected.1 0 01 11 1 0 0 0 1 0 1 1 1 1 00 00 1 10 1 01 0 1
0 0
R 1 10 01 1 1 1 0 R' 1 1 0 1 1 11 00 1 H- 1 01 10 0 1 1
1 1 0 1 1 0 1 0 1 1 0 1 1 0 1
0
(a) 0 0 0 1 0 0 (b)0 0 1 0 1 0 1(c) 0
0 1 1 0 0 1 1 1 0 0 1 0 1 0 1
1 0 1 1 0 1 1 1 0 0 1 0 1 1 0
• FIGURE 5.30 R 1 0 1 1 R' 1 1 1 0 H- 1 0 1 1

(a) (b) (c)

VLSI System Testing A four-stage SISR: (a) fault-free signature;
117 (b) signature for fault f^; and (c)
Jiun-Lang signature
Huang, GIEE/ICDA, for
NTUf
 CUT. It is possible to reduce the hardware cost by using an m-to-1 mu
this increases the test time m times. Consider the n-stage multiple-i
ture register (MISR) shown in Figure 5.31. The MISR uses n extra X
Multiple-Input Signature Register (MISR) compacting n L-bit output sequences, MQ to M„_i, into the modular L
neously.

• MISR uses n extra XOR gates for compacting

n L-bit output sequences, M0 to Mn-1 into the 0/7i 0/?2 0/7n-2 Q/^n-l
modular LFSR simultaneously. $-H # > r^ m^ -^M''n #H
Mn M, Mn M.'n-2 Mn

FIGURE 5.31

• The n-input MISR can be remodeled as a single-input SISR with effective

An n-stage multiple-input signature register (MISR).

input sequence M(x) as

n⋯2 n⋯1
M (x) = M0 (x) + xM1 (x) + − + x Mn⋯2 (x) + x Mn⋯1 (x).

• Aliasing probability: P (n) × 2 ⋯n

if L ≠ n.

VLSI System Testing 118 Jiun-Lang Huang, GIEE/ICDA, NTU

 If L » n, then PpsA(n) ^ 2-". When n = 20, PpsA{n) < 2-^0 = 0.0001%. The resuh
suggests that PPSA{^) mainly depends on n, when L ^ n. Hence, increasing the
MISR
numberExample
of MISR stages or using the same MISR but with a different f{x) can
substantially reduce the aliasing probability [Hassan 1984] [Williams 1987].
^-N ^-H e-H
Mn Mi Mp Mo

• FIGURE 5.32 ^-N ^-H e-H

A four-stage MISR. Mi Mp Mo
Mn

• FIGURE 5.32
Mo 1 0 0 1 0
A four-stage MISR.
01010
M2 1 1 000
M3 10011
M
Mo 1100001110 0 1 1
01010
FIGURE 5.33 M2 1 1 000
M3 10011
An equivalent M sequence.
M 10011011
VLSI System Testing 119 Jiun-Lang Huang, GIEE/ICDA, NTU
 Logic Built-In Self-Test (LBIST)

LBIST Architecture

VLSI System Testing Jiun-Lang Huang, GIEE/ICDA, NTU

 patterns are shifted G in at the same Rtime while test responses are being shifted out.
This BIST architecture is referred to as self-testing using MISR and parallel SRSG
FIGURE 5.35 (STUMPS) [Bardell 1982]. Due to the ease of integration with traditional scan
BIST Architectures for Scan Design architecture, the STUMPS architecture is the only BIST architecture widely used
The built-in evaluation and self-test (BEST) architecture.
in industry to date. In order to further reduce the lengths of the PRPG and MISR
and improve the randomness of the PRPG, a STUMPS-based architecture that

• In general, test per scan. includes an optional linear phase shifter and an optional linear phase compactor
isSin—HPRPG
>\ SISR • S,
often used in industrial applications [Nadeau-Dostie 2000] [Cheon 2005]. The
linear phase shifter and linear phase compactor typically comprise a network of

• LSSD on-chip self-test:

XOR gates. Figure 5.38 shows CUT the STUMPS-based architecture.
PIs- (C) v - ^ POs
Si S,
5.5.3 BIST Architectures Using Register
SRL SRL
Reconfiguration
A concern with BIST designs is the amount of test time required. One technique

• STUMPS (Self-Testing Using MISR and Parallel SRSG):

FIGURE 5.36 for reducing the test time is to make use of the storage elements already in the
design for both test generation and response analysis. The storage elementsLogicare
Built-
The LSSD on-chip self-test (LOCST) architecture.
redesigned so they can function as pattern generators or signature analyzers for
test purposes. This BIST architecture is generally referred to as a test-per-clock
• The only widely adopted BIST architecture
integration with scan architecture.
due to 2000].
BIST system [Bushnell its ease of PRPG

n Linear Phase Shifter

PRPG

• Add a linear phase shifter and a linear phase ^

• ••
CUT r
CUT
• ••
compactor to reduce the PRPG and MISR lengths • • •
(C)

(C)
^
and improve the PRPG randomness.
f

Linear Phase Compactor

i ^ T • • •
T T
MISR
MISR
FIGURE 5.37

VLSI System Testing FIGURE 5.38

121 using IVIISR and parallel Jiun-Lang Huang, GIEE/ICDA, NTU
The self-testing (STUMPS) architecture.