Unit-3: Arithmetic and Combinational Circuits

• In a processor/controller/ASIC, the arithmetic operations on integer binary

numbers are performed by Arithmetic Logic Unit (ALU) while arithmetic
operations on floating point numbers are performed by Floating Point Unit
(FPU).
• A Floating Point Unit itself is built from multiple ALUs.
• Within a Central Processing Unit (CPU) or Graphics Processing Unit (GPU) of a
computer/computing device, there are many ALU and/or FPU (where FPU
themselves are built from multiple ALU).
• The digital circuits can be either of the two types –
1) Combinational Logic Circuits or 2) Sequential Logic Circuits.
• In a combinational circuit, the output of the circuit depends only on the input
values at that time.
• In sequential circuits, the output depends not only on the present input but
also past output values.
• The ALU are built by combinational circuits.
• The ALU is typically designed to perform the following operations :-
 Unit-3: Arithmetic and Combinational Circuits
• 1) Arithmetic Operations – Generally, the arithmetic operations supported by
the ALU are addition, addition with carry, subtraction, subtraction with borrow,
two’s complement, increment, decrement and pass through.
• 2) Bitwise Logical Operations – The logical operations supported by the ALU
are AND, OR, Exclusive-OR and One’s Complement.
• 3) Bit Shift Operations – The bit shift operations implemented in an ALU
include arithmetic shift, logical shift, rotate and rotate through carry.
• So, ALU can perform arithmetic operations like addition and subtraction, and
so multiplication and division on integer binary numbers.
• A binary number may be available to the ALU of a digital processor either as
parallel 8-bit, 16-bit, 32-bit or 64-bit input depending upon if it is 8-bit, 16-bit,
32-bit or 64-bit processor.
• The basic building blocks of the ALU are adders.
• The adder circuits are built by logic gates and flip-flops.
• The semiconductor adder circuits can perform addition in a time less than 1
microseconds.
 Unit-3: Arithmetic and Combinational Circuits
Combinational Logic circuits:
• The combinational logic circuits are the circuits that contain different types of
logic gates.
• Simply, a circuit in which different types of logic gates are combined is known
as a combinational logic circuit.
• The output of the combinational circuit is determined from the present
combination of inputs, regardless of the previous input.
• The input variables, logic gates, and output variables are the basic components
of the combinational logic circuit.
• There are different types of combinational logic circuits, such as Adder,
Subtractor, Decoder, Encoder, Multiplexer, and De-multiplexer.
• combinational circuits – half-adder, full-adder, half-subtractor, full-subtractor,
N-bit parallel adder, N-bit parallel subtractor etc that are generally part of an
ALU.
• There are the following characteristics of the combinational logic circuit:
 Unit-3: Arithmetic and Combinational Circuits
1) At any instant of time, the output of the combinational circuits depends only on
the present input terminals.
2) The combinational circuit doesn't have any backup or previous memory. The
present state of the circuit is not affected by the previous state of the input.
3) The n number of inputs and m number of outputs are possible in combinational
logic circuits.
• Combinational circuits consist of Logic gates. These circuits operate with
binary values. The outputs of combinational circuit depends on the
combination of present inputs.
• The following figure shows the block diagram of combinational circuit.
 Unit-3: Arithmetic and Combinational Circuits
• The 'n' input variable comes from the external source while the 'm' output
variable goes to the external destination.
• In many applications, the source or destinations are storage registers.
• This combinational circuit has ‘n’ input variables and ‘m’ outputs. Each
combination of input variables will affect the output.
Design procedure of Combinational circuits:
1) Find the required number of input variables and outputs from given
specifications.
2) Formulate the Truth table. If there are ‘n’ input variables, then there will be 2n
possible combinations. For each combination of input, find the output values.
3) Find the Boolean expressions for each output. If necessary, simplify those
expressions.
4) Implement the above Boolean expressions corresponding to each output by
using Logic gates.
 Arithmetic Circuits- Half Adder
Binary Adder:
• The most basic arithmetic operation is addition. The circuit, which performs
the addition of two binary numbers is known as Binary adder. First, let us
implement an adder, which performs the addition of two bits.
Half Adder:
• The Half-Adder is a basic building block of adding two numbers as two inputs
and produce out two outputs.
• The adder is used to perform OR operation of two single bit binary numbers.
• The augent and addent bits are two input states, and 'carry' and 'sum 'are two
output states of the half adder.
 Arithmetic Circuits- Half Adder
• The two inputs are the two 1-bit numbers A and B while the two outputs are the
sum (S) of A and B and the carry (C). The truth table for a half adder is as follows –

In the above table,

• 'A' and' B' are the input states, and 'sum' and 'carry' are the output states.
• The carry output is 0 in case where both the inputs are not 1.
• The least significant bit of the sum is defined by the 'sum' bit.
• The SOP form of the sum and carry are as follows:
• Sum = x‘.y+x.y‘ (Exclusive-OR)
Carry = x.y (AND)
 Arithmetic Circuits- Half Adder
Construction of Half Adder Circuit:
• In the block diagram, we have seen that it contains two inputs and two
outputs.
• The augent and addent bits are the input states, and carry and sum are the
output states of the half adder. The half adder is designed with the help of the
following two logic gates:
1) 2-input AND Gate.
2) 2-input Exclusive-OR Gate or Ex-OR Gate
1) 2-input Exclusive-OR Gate or Ex-OR Gate:
• The Sum bit is generated with the help of the Exclusive-OR or Ex-OR Gate.
 Arithmetic Circuits- Half Adder
• The above is the symbol of the EX-OR gate. In the above diagram, 'A' and 'B'
are the inputs, and the 'SUMOUT' is the final outcome after performing the
XOR operation of both numbers.
• The truth table of the EX-OR gate is as follows:

• From the above table, it is clear that the XOR gate gives the result 1 when both
of the inputs are different. When both of the inputs are the same, the XOR
gives the result 0.
 Arithmetic Circuits- Half Adder
2) 2-input AND Gate:
The XOR gate is unable to generate the carry bit. For this purpose, we use another
gate called AND Gate. The AND gate gives the correct result of the carry.

• The above is the symbol of the AND gate. In the above diagram, 'A' and 'B' are
the inputs, and 'OUT' is the final outcome after performing AND operation of
both numbers.
• There is the following truth table of AND Gate:
 Arithmetic Circuits- Half Adder
• From the above table, it is clear that the AND gate gives the result 1 when both of
the inputs are 1. When both of the inputs are different and 0, the AND gates gives
the result 0.
Half-Adder logical circuit:
• So, the Half Adder is designed by combining the 'XOR' and 'AND' gates and provide
the sum and carry.

• There is the following Boolean expression of Half Adder circuit:

Sum= A XOR B
Carry= A AND B C= A.B
 Arithmetic Circuits- Half Adder
Fig:Symbol and Logic Gate Diagram of Half Adder
 Arithmetic Circuits- Full Adder
Full Adder:
• The half adder is used to add only two numbers.
• To overcome this problem, the full adder was developed.
• The full adder is used to add three 1-bit binary numbers A, B, and carry C.
• The full adder has three input states and two output states i.e., sum and carry.
• Full adder is a combinational circuit, which performs the addition of three
bits A, B and Cin. Where, A & B are the two parallel significant bits and Cin is the
carry bit, which is generated from previous stage.
• This Full adder also produces two outputs sum, S & carry, Cout, which are
similar to Half adder.
• A half adder has only two inputs and there is no provision to add a carry
coming from the lower order bits when multiple bit addition is performed.
• For this purpose full adder is designed.
• A full adder is designed to perform the arithmetic sum of three input bits and
produces a sum output and a carry.
 Arithmetic Circuits- Full Adder
Fig : Shows Block Diagram of Full Adder

Truth Table:
 Arithmetic Circuits- Full Adder
In the above table,
• 'A' and' B' are the input variables. These variables represent the two significant
bits which are going to be added
• 'Cin' is the third input which represents the carry. From the previous lower
significant position, the carry bit is fetched.
• The 'Sum' and 'Carry' are the output variables that define the output values.
• The eight rows under the input variable designate all possible combinations of
0 and 1 that can occur in these variables.
Note: We can simplify each of the output 'Boolean function' with the help of the
unique map method.
The SOP form can be obtained with the help of K-map as:
 Arithmetic Circuits- Full Adder
3-Input Ex-OR Gate:
• In some cases, we need to have XOR Gates with more than 2 inputs. More than
2 input XOR function is called as “Odd function”.
• The Boolean function for the 3- input XOR gate is:
A ⊕ B ⊕ C = A’ B ’C + A’ B C’ + A B’ C’ + A B C
3 Input EX-OR Logic Symbol:

Truth Table:
 Arithmetic Circuits- Full Adder
• Sum = x' y' z+ x'yz’+ xy'z'+ xyz (Exxclusive OR of x,y,z) = Q = x ⊕ y ⊕ z
Carry = xy+xz+yz
ie xy’z + xyz = xz(y + y’) = xz
x’yz + xyz = yz(x + x’) = yz
xyz + xyz’ = xy(z + z’) =xy
Therefore Carry= xy + xz + yz
Construction of Full Adder Circuit:
 Arithmetic Circuits- Full Adder
The above block diagram describes the construction of the Full adder circuit.
In the above circuit, there are two half adder circuits that are combined using the
OR gate.
• The first half adder has two single-bit binary inputs A and B.
• As we know that, the half adder produces two outputs, i.e., Sum and Carry.
• The 'Sum' output of the first adder will be the first input of the second half
adder, and the 'Carry' output of the first adder will be the second input of the
second half adder.
• The second half adder will again provide 'Sum' and 'Carry'.
• The final outcome of the Full adder circuit is the 'Sum' bit.
• In order to find the final output of the 'Carry', we provide the 'Carry' output of
the first and the second adder into the OR gate.
• The outcome of the OR gate will be the final carry out of the full adder circuit.
• The MSB is represented by the final 'Carry' bit.
 Arithmetic Circuits- Full Adder
• The full adder logic circuit can be constructed using the 'AND' and the ‘XOR’
gate with an ’OR’ Gate.

• Let, sum, S is the Least significant bit and carry, Cout is the Most significant bit of
resultant sum.
• It is easy to fill the values of outputs for all combinations of inputs in the truth
table. Just count the number of ones present at the inputs and write the
equivalent binary number at outputs.
• If Cin is equal to zero, then Full adder truth table is same as that of Half adder truth
table.
 Arithmetic Circuits- Full Adder
• We will get the following Boolean functions for each output after
simplification.
S=A⊕B⊕Cin
cout=AB+(A⊕B).Cin
• The sum, S is equal to one, when odd number of ones present at the inputs.
We know that Ex-OR gate produces an output, which is an odd function. So, we
can use either two 2input Ex-OR gates or one 3-input Ex-OR gate in order to
produce sum, S. We can implement carry, Cout using two 2-input AND gates &
one OR gate. The circuit diagram of Full adder is shown in the following figure
 Arithmetic Circuits- Full Adder
This adder is called as Full adder because for implementing one Full adder, we
require two Half adders and one OR gate.
If Cin is zero, then Full adder becomes Half adder. We can verify it easily from the
above circuit diagram or from the Boolean functions of outputs of Full adder.
• The full adder circuit construction can also be represented in a Boolean
expression.
Sum:
• Perform the XOR operation of input A and B.
• Perform the XOR operation of the outcome with carry. So, the sum is (A XOR B)
XOR Cin which is also represented as:
(A ⊕ B) ⊕ Cin
Carry:
• Perform the 'AND' operation of input A and B.
• Perform the 'XOR' operation of input A and B.
• Perform the 'OR' operations of both the outputs that come from the previous
two steps. So the 'Carry' can be represented as:
A.B + (A ⊕ B) Cin
 Arithmetic Circuits- Full Adder
Fig: Symbol and Logic Circuit Diagram of Full Adder

It can be noted that full adder is formed by two half adder circuits and an OR gate.
 Differences between Half Adder Vs Full Adder
Sl.No Half Adder Full Adder
1 Half Adder is combinational logic Full adder is combinational logical circuit
circuit which adds two 1-bit digits. that performs an addition operation on
The half adder produces a sum of the three one-bit binary numbers. The full
two inputs. adder produces a sum of the three inputs
and carry value.

2 Previous carry is not used. Previous carry is used.

3 In Half adder there are two input bits In full adder there are three input bits (A,
( A, B). B, C-in).
4 Logical Expression for half adder is : Logical Expression for Full adder is :
S=a⊕b ; C=a*b. S=a⊕b⊕Cin; Cout=(a*b)+(Cin*(a⊕b)).
5 It consists of one EX-OR gate and one It consists of two EX-OR, two AND gate
AND gate. and one OR gate.
6 It is used in Calculators, computers, It is used in Multiple bit addition, digital
digital measuring devices etc. processors etc.
 Arithmetic Circuits- Half Subtractor
Half Subtractor:
• The half subtractor is also a building block for subtracting two binary numbers.
• It has two inputs and two outputs.
• This circuit is used to subtract two single bit binary numbers A and B.
• The 'diff' and 'borrow' are two output states of the half subtractor.
Block diagram:
 Arithmetic Circuits- Half Subtractor
Truth Table:

• The SOP form of the Diff and Borrow is as follows:

Diff= A'B+AB'
Borrow = A'B
In the above table,
• 'A' and 'B' are the input variables whose values are going to be subtracted.
• The 'Diff' and 'Borrow' are the variables whose values define the subtraction
result, i.e., difference and borrow.
• The first row and the last row, the difference is 0, the 'Borrow' variable is 0.
• The second row is different from the remaining one. When we subtract the bit
0 from the bit 1, the borrow bit 1 is produced.
• The Third row is When we subtract the bit 1 from the bit 0, the borrow bit 0 is
produced
 Arithmetic Circuits- Half Subtractor
This can be implemented by connecting the inputs to an exclusive OR gate.
The Borrow Output (Bout) is 1 only if B is 1 but not A.
The borrow output Bout is 1 whenever A is lesser than B, then the subtraction is
done by borrowing 1 from the next higher order bit. This can be implemented
by AND operation between Not A and B.
Construction of Half Subtractor Circuit:
• In the block diagram, we have seen that it contains two inputs and two
outputs.
• The Diff and Borrow are the output states of the half subtractor.
• The half subtractor is designed with the help of the following logic gates:
1) 2-input AND gate.
2) 2-input Exclusive-OR Gate or Ex-OR Gate
3) NOT or inverter Gate
1) 2-input Exclusive-OR Gate or Ex-OR Gate:
• The Diff bit is generated with the help of the Exclusive-OR or Ex-OR gate.
 Arithmetic Circuits- Half Subtractor

• The above is the symbol of the EX-OR gate. In the above diagram, 'A' and 'B'
are the inputs, and 'Diff' is the final outcome after performing the XOR
operation of both numbers.
• The truth table of the EX-OR gate is as follows:

• From the above table, it is clear that the XOR Gate gives the result 1 when both
of the inputs are different.
• When both of the inputs are the same, the XOR gives the result 0.
 Arithmetic Circuits- Half Subtractor
2) 2-input AND gate:
• The XOR gate is unable to generate the carry bit. For this purpose, we use
another gate called AND gate. The AND gate is not enough to give the correct
result of 'Borrow'. We will use the NOT gate with the 'AND' gate to get the
correct result.

• The above is the symbol of the AND gate.

• In the above diagram, 'A' and 'B' are the inputs, and 'OUT' is the final outcome
after performing AND operation of both numbers.
• There is the following truth table of AND gate:
 Arithmetic Circuits- Half Subtractor

From the above table, it is clear that the AND gate gives the result 1 when both of
the inputs are 1. When both of the inputs are different and 0, the AND gates
gives the result 0.
3) NOT or Inverter Gate:
The NOT gate is used to get the inverse output. We can combine the 'AND' and
'NOT' gates in order to get the combinational gate 'NAND'. By inverting the
input 'A' using 'NOT' gate and then use the output of the 'NOT' gate as the
input of the 'AND' gate, we can get the 'Borrow' bit.
 Arithmetic Circuits- Half Subtractor
Truth Table of NOT Gate:

Half-Subtractor logical circuit:

• So, the Half Subtractor is designed by combining the 'XOR', 'AND', and 'NOT'
gates and provide the Diff and Borrow.
 Arithmetic Circuits- Half Subtractor
The Boolean expression of the Half Subtractor circuit is given below:
Diff= A XOR B (A⊕B)
Borrow= not-A AND B (A'.B)

Fig: Symbol and Logic Gate Diagram of Half Subtractor

 Arithmetic Circuits- Full Subtractor
Full Subtractor:
• The Half Subtractor is used to subtract only two numbers.
• To overcome this problem, a full subtractor was designed.
• The full subtractor is used to subtract three 1-bit numbers A, B, and C, which
are minuend, subtrahend, and borrow, respectively.
• The full subtractor has three input states and two output states i.e., diff and
borrow.
Block Diagram:
 Arithmetic Circuits- Full Subtractor
Truth Table:

In the above table,

• 'A' and' B' are the input variables. These variables represent the two significant
bits that are going to be subtracted.
• 'Borrowin' is the third input which represents borrow.
• The 'Diff' and 'Borrow' are the output variables that define the output values.
• The eight rows under the input variable designate all possible combinations of
0 and 1 that can occur in these variables.
 Arithmetic Circuits- Full Subtractor
Note: We can simplify each of the Boolean output functions with the help of the
unique map method.
The SOP form can be obtained with the help of K-map as:

Diff=x' y' z + x’yz‘ + xy’z’ + xyz( Exclusive OR)

 Arithmetic Circuits- Full Subtractor
Group1: x’y’z + x’yz = x’z(y + y’) = x’z
Group 2: x’yz + x’yz’ = x’y(z + z’) = x’y
Group 3: x’yz + xyz = yz( x + x’) = yz
Therefore Borrow=x' z + x' y + yz
Construction of Full Subtractor Circuit:
 Arithmetic Circuits- Full Subtractor
The above block diagram describes the construction of the Full subtractor circuit.
In the above circuit, there are two half Subtractor circuits that are combined using
the OR gate.
The first half subtractor has two single-bit binary inputs A and B.
As we know that, the half subtractor produces two outputs, i.e., 'Diff' and
'Borrow'.
The 'Diff' output of the first subtractor will be the first input of the second half
subtractor, and the 'Borrow' output of the first subtractor will be the second
input of the second half subtractor.
The second half subtractor will again provide 'Diff' and 'Borrow'.
The final outcome of the Full subtractor circuit is the 'Diff' bit.
In order to find the final output of the 'Borrow', we provide the 'Borrow' of the
first and the second subtractor into the OR gate.
The outcome of the OR gate will be the final carry 'Borrow' of full subtractor
circuit.
The MSB is represented by the final 'Borrow' bit.
 Arithmetic Circuits- Full Subtractor
The full subtractor logic circuit can be constructed using the 'AND', 'XOR', and
NOT gate with an OR gate.
 Arithmetic Circuits- Full Subtractor
• The actual logic circuit of the full subtractor is shown in the above diagram.
The full subtractor circuit construction can also be represented in a Boolean
expression.
Diff:
• Perform the XOR operation of input A and B.
• Perform the XOR operation of the outcome with 'Borrow'. So, the difference is
(A XOR B) XOR 'Borrowin' which is also represented as:
(A ⊕ B) ⊕ 'Borrowin'
Borrow:
• Perform the 'AND' operation of the inverted input A and B.
• Perform the 'XOR' operation of input A and B.
• Perform the 'OR' operations of both the outputs that come from the previous
two steps. So the 'Borrow' can be represented as:
A'.B + (A ⊕ B)‘ Borrowin
 Arithmetic Circuits- Full Subtractor
Fig: Symbol and Logic Gate Diagram of Full Subtractor
 N Bit Parallel Adder
• The registers play an important role in performing the micro-operations.
• The registers hold the digital component and the data which performs the
arithmetic operation
• The Binary Adder is a logical circuit which is used to perform the addition
operation of two binary number of any length.
• The Binary Adder is formed with the help of the Full-Adder circuit.
• The Full-Adders are connected in series, and the output carry of the first Adder
will be treated as the input carry of the next Full-Adder.
N-Bit Parallel Adder:
• The Full Adder is used to sum two single-bit binary numbers with carry input.
• In digital calculation, we need to add two n-bit binary numbers rather than
only single-bit binary numbers.
• For this purpose, we need to use n-bit parallel Adder.
• In order to get N-bit parallel adder, we cascade the n number of Full Adders.
• The carry output of the first Adder is treated as the carry input of the second
Adder.
 N Bit Parallel Adder
4-bit Binary Adder:

• The 'A' and 'B' are the augend, and addend bits are defined by the subscript
numbers. The subscripts start from right to left, and the lower-order bit is
defined by subscript '0'.
• The C0, C1, C2, and C3 are the carry inputs which are connected together as a
chain using Full Adder. The C4 is the carry output produced by the last Full-
Adder.
• The Cout of the first Adder is connected as the Cin of the next Full-Adder.
 N Bit Parallel Adder
4-bit Binary Adder:
• The S0, S1, S2, and S3 are the sum outputs that produce the sum of augend
and addend bits.
• The inputs for the input variable 'A' and 'B' are fetched from different source
registers. For example, the bit for the input variable 'A' comes from register
'R1', and a bit for the input variable 'B' comes from register 'R2'.
• The outcome produced by adding both input variables is stored into either
third register or to one of the source registers.
• Like a 4-bit parallel adder, can be constructed by cascading four full-adder
circuits.
• In the circuit A0 and B0 represent the LSB of the four bit words A and B where
Full Adder-0 is the lowest stage.
• Hence its Cin has been permanently made 0.
• The rest of the connections are exactly same as those of n-bit parallel adder.
• The four bit parallel adder is a very common logic circuit.
 N Bit Parallel Subtractor
N-Bit Parallel Subtractor:
• The subtraction can be carried out by taking the 1’s or 2’s complement of the
number to be subtracted.
• For example, the subtraction (A-B) can be performed by adding either 1’s or 2’s
complement of B to A.
• So, a binary adder can be used to perform the binary subtraction.
• Just as a parallel binary adder can be implemented by cascading several full
adders, a parallel binary subtractor can also be implemented by cascading
several full subtractors.
Like a 4 – bit binary parallel subtractor that subtracts a 4 – bit number Y3 Y2 Y1 Y0
from another 4 – bit number X3 X2 X1 X0 will have 4 difference outputs and
borrow output (Bout).
The Bin of the LSB full subtractor is connected to 0 and Bout of previous full
subtractor is connected to Bin of next full subtractor.
 N Bit Parallel Subtractor
A 4-bit parallel subtractor can be shown by the following block diagram:
Fig:
 N Bit Parallel Subtractor
Advantages of parallel Adder/Subtractor :
• The parallel adder/subtractor performs the addition operation faster as
compared to serial adder/subtractor.
• Time required for addition does not depend on the number of bits.
• The output is in parallel form i.e all the bits are added/subtracted at the same
time.
• It is less costly.
Disadvantages of parallel Adder/Subtractor :
• Each adder has to wait for the carry which is to be generated from the previous
adder in chain.
• The propagation delay( delay associated with the travelling of carry bit) is
found to increase with the increase in the number of bits to be added.
 Combinational Circuit- Multiplexer
Multiplexer:
• A multiplexer is a combinational circuit that has 2n input lines and a single
output line.
• Simply, the multiplexer is a multi-input and single-output combinational
circuit.
• The binary information is received from the input lines and directed to the
output line.
• On the basis of the values of the selection lines, one of these data inputs will
be connected to the output.
• Unlike encoder and decoder, there are n selection lines and 2n input lines.
• So, there is a total of 2N possible combinations of inputs.
• A multiplexer is also treated as Mux.
There are various types of the multiplexer which are as follows:
1) 2 x 1 Multiplexer
2) 4×1 Multiplexer
3) 8 ×1 multiplexer
4) 16 x 1 Multiplexer
 Combinational Circuit- Multiplexer
2×1 Multiplexer:
• In 2×1 multiplexer, there are only two inputs, i.e., A0 and A1, 1 selection line,
i.e., S0 and single outputs, i.e., Y.
• On the basis of the combination of inputs which are present at the selection
line S0, one of these 2 inputs will be connected to the output.
• The block diagram and the truth table of the 2×1 multiplexer are given below.
Block Diagram:
 Combinational Circuit- Multiplexer
Truth Table:

• The logical expression of the term Y is as follows:

Y=S0'.A0+S0.A1
• Logical circuit of the above expression is given below:
 Combinational Circuit- Multiplexer
4×1 Multiplexer:
• In the 4×1 multiplexer, there is a total of four inputs, i.e., A0, A1, A2, and A3, 2
selection lines, i.e., S0 and S1 and single output, i.e., Y.
• On the basis of the combination of inputs that are present at the selection
lines S0 and S1, one of these 4 inputs are connected to the output.
• The block diagram and the truth table of the 4×1 multiplexer are given below.
Block Diagram:
 Combinational Circuit- Multiplexer
Truth Table:

The logical expression of the term Y is as follows:

Y=S1' S0' A0+S1' S0 A1+S1 S0' A2+S1 S0 A3
Logical circuit of the above expression is given below:
 Combinational Circuit- Multiplexer
8 to 1 Multiplexer:
• In the 8 to 1 multiplexer, there are total eight inputs, i.e., A0, A1, A2, A3, A4, A5,
A6, and A7, 3 selection lines, i.e., S0, S1and S2 and single output, i.e., Y.
• On the basis of the combination of inputs that are present at the selection
lines S0, S1, and S2, one of these 8 inputs are connected to the output.
• The block diagram and the truth table of the 8×1 multiplexer are given below.
 Combinational Circuit- Multiplexer
Truth Table:

The logical expression of the term Y is as follows:

Y=S0'.S1'.S2'.A0+S0.S1'.S2'.A1+S0'.S1.S2'.A2+S0.S1.S2'.A3+S0'.S1'.S2 A4+S0.S1'.S2 A5+S0'.S1.
S2 .A6+S0.S1.S2.A7
 Combinational Circuit- Multiplexer
Logical circuit of the above expression is given below:
 Combinational Circuit- Multiplexer
8 ×1 multiplexer using 4×1 and 2×1 multiplexer:
• We can implement the 8×1 multiplexer using a lower order
multiplexer.
• To implement the 8×1 multiplexer, we need two 4×1 multiplexers
and one 2×1 multiplexer.
• The 4×1 multiplexer has 2 selection lines, 4 inputs, and 1 output.
• The 2×1 multiplexer has only 1 selection line.
• For getting 8 data inputs, we need two 4×1 multiplexers.
• The 4×1 multiplexer produces one output.
• So, in order to get the final output, we need a 2×1 multiplexer.
• The block diagram of 8×1 multiplexer using 4×1 and 2×1
multiplexer is given below.
 Combinational Circuit- Multiplexer
8 ×1 multiplexer using 4×1 and 2×1 multiplexer:
 Combinational Circuit- Multiplexer
16 to 1 Multiplexer:
• In the 16 to 1 multiplexer, there are total of 16 inputs, i.e., A0, A1, …, A15, 4
selection lines, i.e., S0, S1, S2, and S3 and single output, i.e., Y.
• On the basis of the combination of inputs that are present at the selection
lines S0, S1, and S2,S3 one of these 16 inputs will be connected to the output.
• The block diagram and the truth table of the 16×1 Multiplexer.
 Combinational Circuit- Multiplexer
Truth Table:
 Combinational Circuit- Multiplexer
The logical expression of the term Y is as follows:

Y=A0.S0'.S1'.S2'.S3'+A1.S0'.S1'.S2 '.S3+A2.S0'.S1'.S2.S3'+A3.S0'.S1 '.S2.S3+A4.S0'.S1.S2'.S3'+

A5.S0 '.S1.S2'.S3+A6.S1.S2.S3'+A7.S0 '.S1.S2.S3+A8.S0.S1'.S2'.S3'+A9 .S0.S1'.S2'.S3+
A10.S0.S1'.S2.S3 '+A11.S0.S1'.S2.S3+A12S0.S1.S2 '.S3'+A13.S0.S1.S2'.S3+A14.S0.S1 .S2.S3‘
+A15.S0.S1.S2'.S3

Logical circuit of the above expression is given below:

Combinational Circuit- Multiplexer
 Combinational Circuit- Multiplexer
16×1 multiplexer using 8×1 and 2×1 multiplexer:
• We can implement the 16×1 multiplexer using a lower order
multiplexer.
• To implement the 16×1 multiplexer, we need two 8×1
multiplexers and one 2×1 multiplexer.
• The 8×1 multiplexer has 3 selection lines, 8 inputs, and 1 output.
• The 2×1 multiplexer has only 1 selection line.
• For getting 16 data inputs, we need two 8 ×1 multiplexers.
• The 8×1 multiplexer produces one output.
• So, in order to get the final output, we need a 2×1 multiplexer.
• The block diagram of 16×1 multiplexer using 8×1 and 2×1
multiplexer is given below.
 Combinational Circuit- Multiplexer
16×1 multiplexer using 8×1 and 2×1 multiplexer:
 Combinational Circuit- De-Multiplexer
De-multiplexer:
• A De-multiplexer is a combinational circuit that has only 1 input line and
2N output lines.
• Simply, the demultiplexer is a single-input and multi-output combinational
circuit.
• The information is received from the single input lines and directed to the
output line.
• On the basis of the values of the selection lines, the input will be connected to
one of these outputs.
• De-multiplexer is opposite to the multiplexer.
• Unlike encoder and decoder, there are n selection lines and 2n outputs.
• So, there is a total of 2n possible combinations of inputs.
• De-multiplexer is also treated as De-mux.
• There are various types of De-multiplexer which are as follows:
1) 1 x 2 De-multiplexer
2) 1 x 4 De-multiplexer
3) 1 x 8 De-multiplexer
4) 1 x 16 De-multiplexer
 Combinational Circuit- De-Multiplexer
1×2 De-multiplexer:
• In the 1 to 2 De-multiplexer, there are only two outputs, i.e., Y0, and Y1, 1
selection lines, i.e., S0, and single input, i.e., A.
• On the basis of the selection value, the input will be connected to one of the
outputs.
• The block diagram and the truth table of the 1×2 multiplexer are given below.
Block Diagram:
 Combinational Circuit- De-Multiplexer
Truth Table:

• The logical expression of the term Y is as follows:

Y0=S0'.A
Y1=S0.A
Logical circuit of the above expressions is given below:
 Combinational Circuit- De-Multiplexer
1×4 De-multiplexer:
• In 1 to 4 De-multiplexer, there are total of four outputs, i.e., Y0, Y1, Y2, and Y3, 2
selection lines, i.e., S0 and S1 and single input, i.e., A.
• On the basis of the combination of inputs which are present at the selection
lines S0 and S1, the input be connected to one of the outputs.
• The block diagram and the truth table of the 1×4 multiplexer are given below.
Block Diagram:
 Combinational Circuit- De-Multiplexer
Truth Table:

The logical expression of the term Y is as follows:

Y0=S1' S0' A
Y1=S1' S0 A
Y2=S1 S0' A
Y3=S1 S0 A
 Combinational Circuit- De-Multiplexer
Logical circuit of the above expressions is given below:
 Combinational Circuit- De-Multiplexer
1×8 De-multiplexer:
• In 1 to 8 De-multiplexer, there are total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4,
Y5, Y6, and Y7, 3 selection lines, i.e., S0, S1and S2 and single input, i.e., A.
• On the basis of the combination of inputs which are present at the selection
lines S0, S1 and S2, the input will be connected to one of these outputs.
• The block diagram and the truth table of the 1×8 de-multiplexer are given
below.
Block Diagram:
 Combinational Circuit- De-Multiplexer
Truth Table:

The logical expression of the term Y is as follows:

Y0=S0'.S1'.S2'.A Y1=S0 .S1'.S2.A Y2=S0'.S1.S2'.A Y3=S0.S1.S2'.A

Y4=S0'.S1'.S2 A Y5=S0.S1'.S2 A Y6=S0'.S1.S2 A Y7=S0.S1.S3.A

 Combinational Circuit- De-Multiplexer
Logical circuit of the above expressions is given below:
 Combinational Circuit- De-Multiplexer
1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer:
• We can implement the 1×8 de-multiplexer using a lower order de-
multiplexer.
• To implement the 1×8 de-multiplexer, we need two 1×4 de-multiplexer
and one 1×2 de-multiplexer.
• The 1×4 demultiplexer has 2 selection lines, 4 outputs, and 1 input.
• The 1×2 de-multiplexer has only 1 selection line.
• For getting 8 data outputs, we need two 1×4 de-multiplexer.
• The 1×2 de-multiplexer produces two outputs.
• So, in order to get the final output, we have to pass the outputs of 1×2
de-multiplexer as an input of both the 1×4 de-multiplexer.
• The block diagram of 1×8 de-multiplexer using 1×4 and 1×2 de-
multiplexer is given below.
 Combinational Circuit- De-Multiplexer
1×8 De-multiplexer using 1×4 and 1×2 de-multiplexer:
 Combinational Circuit- De-Multiplexer
1 x 16 De-multiplexer:
• In 1×16 de-multiplexer, there are total of 16 outputs, i.e., Y0, Y1, …, Y15, 4
selection lines, i.e., S0, S1, S2, and S3 and single input, i.e., A. On the basis of the
combination of inputs which are present at the selection lines S0, S1, and S2, S3
the input will be connected to one of these outputs. The block diagram and
the truth table of the 1×16 de-multiplexer are given below.
Block Diagram:
 Combinational Circuit- De-Multiplexer
Truth Table:
 Combinational Circuit- De-Multiplexer
The logical expression of the term Y is as follows:
Y0=A.S0'.S1'.S2'.S3'
Y1=A.S0'.S1'.S2'.S3
Y2=A.S0'.S1'.S2.S3'
Y3=A.S0'.S1'.S2.S3
Y4=A.S0'.S1.S2'.S3'
Y5=A.S0'.S1.S2'.S3
Y6=A.S0'.S1.S2.S3'
Y7=A.S0'.S1.S2.S3
Y8=A.S0.S1'.S2'.S3'
Y9=A.S0.S1'.S2'.S3
Y10=A.S0.S1'.S2.S3'
Y11=A.S0.S1'.S2.S3
Y12=A.S0.S1.S2'.S3'
Y13=A.S0.S1.S2'.S3
Y14=A.S0.S1.S2.S3'
Y15=A.S0.S1.S2'.S3
Logical circuit of the above expressions is given below:
Combinational Circuit- De-Multiplexer
 Combinational Circuit- De-Multiplexer
1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer:
• We can implement the 1×16 de-multiplexer using a lower order de-multiplexer.
• To implement the 1×16 de-multiplexer, we need two 1×8 de-multiplexer and
one 1×2 de-multiplexer.
• The 1×8 demultiplexer has 3 selection lines, 1 input, and 8 outputs.
• The 1×2 de-multiplexer has only 1 selection line.
• For getting 16 data outputs, we need two 1×8 de-multiplexer.
• The 1×8 de-multiplexer produces eight outputs.
• So, in order to get the final output, we need a 1×2 de-multiplexer to produce
two outputs from a single input.
• Then we pass these outputs into both the de-multiplexer as an input.
• The block diagram of 1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer is
given below.
 Combinational Circuit- De-Multiplexer
1×16 de-multiplexer using 1×8 and 1×2 de-multiplexer:
Realization of logic functions using universal gates(NAND and NOR
Gate)
• NAND gate and NOR gate are considered to be ‘Universal Logic Gates’.
• The reason behind this is, NAND gate and NOR gate can perform (or can
function like) all the 3 basic gates, such as AND gate, OR gate and NOT gate.
• We can design any basic logic gate by using NAND gate or NOR gate. This is
why they are called as “Universal Gates”.
1) Implementation of Boolean functions using NAND gates:
NAND gate is actually a combination of two logic gates i.e. AND gate followed by
NOT gate.
So its output is complement of the output of an AND gate.
This gate can have minimum two inputs, output is always one.
By using only NAND gates, we can realize all logic functions: AND, OR, NOT, X-OR,
X-NOR, NOR. So this gate is also called as universal gate.

1.1)NAND gates as NOT gate:

• A NOT produces complement of the input. It can have only one input, tie the
inputs of a NAND gate together. Now it will work as a NOT gate. Its output is
Y = (A.A)’
Y = (A)’
Realization of logic functions using universal gates(NAND and NOR
Gate)
Figure:NAND gates as NOT gate

Figure:Truth table of NOT

Realization of logic functions using universal gates(NAND and NOR
Gate)
1.2)NAND gates as AND gate:
• A NAND produces complement of AND gate. So, if the output of a NAND gate is
inverted, overall output will be that of an AND gate.
Y = ((A.B)’)’
Y = (A.B)
Figure: NAND gates as AND gate

Figure: Truth table of AND

Realization of logic functions using universal gates(NAND and NOR
Gate)
1.3)NAND gates as OR gate:
From DeMorgan’s theorems:
(A.B)’ = A’ + B’
(A’.B’)’ = A’’ + B’’ = A + B
So, give the inverted inputs to a NAND gate, obtain OR operation at output.
Figure:NAND gates as OR gate

Figure:Truth table of OR
Realization of logic functions using universal gates(NAND and NOR
Gate)
1.4)NAND gates as Ex-OR gate:
• The output of a two input Ex-OR gate is shown by: Y = A’B + AB’. This can be
achieved with the logic diagram shown in the left side.
Realization of logic functions using universal gates(NAND and NOR
Gate)
Figure:NAND gates as Ex-OR gate

Figure:Truth table of Ex-OR

 Realization of logic functions using universal gates(NAND and NOR
Gate)
1.5)NAND gates as Ex-NOR gate:
• Ex-NOR gate is actually Ex-OR gate followed by NOT gate. So give the output of Ex-
OR gate to a NOT gate, overall output is that of an Ex-NOR gate.
Y = AB+ A’B’
Figure: NAND gates as Ex-NOR gate

Figure:Truth table of Ex-NOR

 Realization of logic functions using universal gates(NAND and NOR
Gate)
1.6) Implementing the simplified function with NAND gates only:
• We can now start constructing the circuit. First note that the entire expression
is inverted and we have three terms ANDed. This means that we must use a 3-
input NAND gate. Each of the three terms is, itself, a NAND expression. Finally,
negated single terms can be generates with a 2-input NAND gate acting as an
inverted. Figure illustrates a circuit using NAND gates only.
F=((C'.B.A)'(D'.C.A)'(C.B'.A)')‘
Realization of logic functions using universal gates(NAND and NOR
Gate)
2) Implementation of Boolean functions using NOR gates:
NOR gate is actually a combination of two logic gates: OR gate followed by NOT
gate.
So its output is complement of the output of an OR gate.
This gate can have minimum two inputs, output is always one.
By using only NOR gates, we can realize all logic functions: AND, OR, NOT, Ex-OR,
Ex-NOR, NAND. So this gate is also called universal gate.
2.1)NOR gates as NOT gate:
A NOT produces complement of the input. It can have only one input, tie the
inputs of a NOR gate together. Now it will work as a NOT gate. Its output is
Y = (A+A)’
Y = (A)’
Figure:NOR gates as NOT gate Figure:Truth table of NOT
Realization of logic functions using universal gates(NAND and NOR
Gate)
2.2)NOR gates as OR gate:
• A NOR produces complement of OR gate. So, if the output of a NOR gate is
inverted, overall output will be that of an OR gate.
Y = ((A+B)’)’
Y = (A+B)
Figure:NOR gates as OR gate

Figure:Truth table of OR
Realization of logic functions using universal gates(NAND and NOR
Gate)
2.3)NOR gates as AND gate:
From DeMorgan’s theorems:
(A+B)’ = A’B’
(A’+B’)’ = A’’B’’ = AB
So, give the inverted inputs to a NOR gate, obtain AND operation at output.
Figure: NOR gates as AND gate Figure-1:Truth table of AND
Realization of logic functions using universal gates(NAND and NOR
Gate)
2.4)NOR gates as Ex-NOR gate:
• The output of a two input Ex-NOR gate is shown by: Y = AB + A’B’. This can be
achieved with the logic diagram shown in the left side.
Realization of logic functions using universal gates(NAND and NOR
Gate)
Figure: NOR gates as Ex-NOR gate

Figure:Truth table of Ex-NOR

Realization of logic functions using universal gates(NAND and NOR
Gate)
2.5)NOR gates as Ex-OR gate:
• Ex-OR gate is actually Ex-NOR gate followed by NOT gate. So give the output of
Ex-NOR gate to a NOT gate, overall output is that of an Ex-OR gate.
Y = A’B+ AB’
Figure:NOR gates as Ex-OR gate Figure:Truth table of Ex-OR
Realization of logic functions using universal gates(NAND and NOR
Gate)
2.6)Constructing a circuit with NOR gates only:
Designing a circuit with NOR gates only uses the same basic techniques as
designing a circuit with NAND gates; that is, the application of deMorgan’s
theorem. The only difference between NOR gate design and NAND gate design
is that the former must eliminate product terms and the later must eliminate
sum terms.
F=(((C.B'.A)+(D.C'.A)+(C.B'.A))')‘
Figure:Implementing the simplified function with NOR gates only
 Encoder & Decoder
Encoders:
• The combinational circuits that change the binary information into N output
lines are known as Encoders.
• The binary information is passed in the form of 2N input lines. The output lines
define the N-bit code for the binary information.
• In simple words, the Encoder performs the reverse operation of the Decoder.
• At a time, only one input line is activated for simplicity.
• The produced N-bit output code is equivalent to the binary information.
 Encoder & Decoder
There are various types of encoders which are as follows:
4 to 2 line Encoder:
• In 4 to 2 line encoder, there are total of four inputs, i.e., Y0, Y1, Y2, and Y3, and
two outputs, i.e., A0 and A1.
• In 4-input lines, one input-line is set to true at a time to get the respective
binary code in the output side.
• Below are the block diagram and the truth table of the 4 to 2 line encoder.
Block Diagram:
 Encoder & Decoder
Truth Table:
Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1
The logical expression of the term A0 and A1 is as follows:
A1=Y3+Y2 A0=Y3+Y1
Logical circuit of the above expressions is given below:
 Encoder & Decoder
8 to 3 line Encoder:
• The 8 to 3 line Encoder is also known as Octal to Binary Encoder.
• In 8 to 3 line encoder, there is a total of eight inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6,
and Y7 and three outputs, i.e., A0, A1, and A2.
• In 8-input lines, one input-line is set to true at a time to get the respective
binary code in the output side.
• Below are the block diagram and the truth table of the 8 to 3 line encoder.
Block Diagram:
 Encoder & Decoder
Truth Table:
 Encoder & Decoder
The logical expression of the term A0, A1, and A2 are as follows:
A2=Y4+Y5+Y6+Y7
A1=Y2+Y3+Y6+Y7
A0=Y7+Y5+Y3+Y1
Logical circuit of the above expressions is given below:
 Encoder & Decoder
Decimal to BCD Encoder:
• The Octal to Binary Encoder is also known as 10 to 4 line Encoder.
• In 10 to 4 line encoder, there are total of ten inputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5, Y6,
Y7, Y8, and Y9 and four outputs, i.e., A0, A1, A2, and A3.
• In 10-input lines, one input-line is set to true at a time to get the
respective BCD code in the output side.
• The block diagram and the truth table of the decimal to BCD encoder are given
below.
Block Diagram:
 Encoder & Decoder
Truth Table:
 Encoder & Decoder
The logical expression of the term A0, A1, A2, and A3 is as follows:
A3 = Y9 + Y8 A2 = Y7 + Y6 + Y5 +Y4
A1 = Y7 + Y6 + Y3 +Y2 A0 = Y9 + Y7 +Y5 +Y3 + Y1
Logical circuit of the above expressions is given below:
 Encoder & Decoder
Priority Encoder:
4 to 2 line Priority Encoder:
• In this priority encoder, there are total of 4 inputs, i.e., Y0, Y1, Y2, and Y3, and
two outputs, i.e., A0 and A1.
• The Y3 has high and Y0 has low priority inputs. When more than one input is '1'
at the same time, the output will be the (binary) code corresponding to the
higher priority input.
• Below is the truth table of the 4 to 2 line priority encoder.
Truth Table:
 Encoder & Decoder
The logical expression of the term A0 and A1 can be found using K-map as:
A1=Y3+Y2
A0=Y3+Y2'.Y1
• Logical circuit of the above expressions is given below:
 Encoder & Decoder
Uses of Encoders:
• These systems are very easy to use in all digital systems.
• Encoders are used to convert a decimal number into the binary number. The
objective is to perform a binary operation such as addition, subtraction,
multiplication, etc.
• Other applications especially for Priority Encoders may include detecting
interrupts in microprocessor applications.
Drawbacks of Normal Encoders :
• There is an ambiguity, when all outputs of encoder are equal to zero.
• If more than one input is active High, then the encoder produces an output,
which may not be the correct code.
• So, to overcome these difficulties, we should assign priorities to each input of
encoder. Then, the output of encoder will be the ( code corresponding to the
active High inputs, which has higher priority.
 Encoder & Decoder
Decoder:
• The combinational circuit that change the binary information into 2N output
lines is known as Decoders.
• The binary information is passed in the form of N input lines. The output lines
define the 2N-bit code for the binary information.
• In simple words, the Decoder performs the reverse operation of the Encoder.
• At a time, only one input line is activated for simplicity.
• The produced 2N-bit output code is equivalent to the binary information.
 Encoder & Decoder
There are various types of decoders which are as follows:
2 to 4 line decoder:
• In the 2 to 4 line decoder, there is a total of three inputs, i.e., A0, and A1 and E
and four outputs, i.e., Y0, Y1, Y2, and Y3.
• For each combination of inputs, when the enable 'E' is set to 1, one of these
four outputs will be 1.
• The block diagram and the truth table of the 2 to 4 line decoder are given
below.
Block Diagram:
 Encoder & Decoder
Truth Table:

The logical expression of the term Y0, Y1, Y2, and Y3 is as follows:
Y3=E.A1.A0 Y2=E.A1.A0‘ Y1=E.A1'.A0 Y0=E.A1'.A0‘
Logical circuit of the above expressions is given below:
 Encoder & Decoder
3 to 8 line decoder:
• The 3 to 8 line decoder is also known as Binary to Octal Decoder.
• In a 3 to 8 line decoder, there is a total of eight outputs, i.e., Y0, Y1, Y2, Y3, Y4, Y5,
Y6, and Y7 and three outputs, i.e., A0, A1, and A2.
• This circuit has an enable input 'E'. Just like 2 to 4 line decoder, when enable 'E'
is set to 1, one of these four outputs will be 1.
• The block diagram and the truth table of the 3 to 8 line encoder are given
below.
Block Diagram:
 Encoder & Decoder
Truth Table:

The logical expression of the term Y0, Y1, Y2, Y3, Y4, Y5, Y6, and Y7 is as follows:
Y0=A0'.A1'.A2‘ Y1=A0.A1'.A2‘ Y2=A0'.A1.A2‘ Y3=A0.A1.A2'
Y4=A0'.A1'.A2 Y5=A0.A1'.A2 Y6=A0'.A1.A2 Y7=A0.A1.A2
 Encoder & Decoder
Logical circuit of the above expressions is given below:
 Encoder & Decoder
4 to 16 line Decoder:
• In the 4 to 16 line decoder, there is a total of 16 outputs, i.e., Y0, Y1, Y2,……,
Y16 and four inputs, i.e., A0, A1, A2, and A3.
• The 4 to 16 line decoder can be constructed using either 2 to 4 decoder or 3 to
8 decoder.
• There is the following formula used to find the required number of lower-order
decoders.
• Required number of lower order decoders=m2/m1 m1 = 8 m2 = 16
• Required number of 3 to 8 decoders=16/8=2
Block Diagram:
 Encoder & Decoder
Truth Table:
 Encoder & Decoder
The logical expression of the term Y0, Y1, Y2,…, Y15 are as follows:
Y0=A0'.A1'.A2'.A3'
Y1=A0'.A1'.A2'.A3
Y2=A0'.A1'.A2.A3'
Y3=A0'.A1'.A2.A3
Y4=A0'.A1.A2'.A3'
Y5=A0'.A1.A2'.A3
Y6=A0'.A1.A2.A3'
Y7=A0'.A1.A2.A3
Y8=A0.A1'.A2'.A3'
Y9=A0.A1'.A2'.A3
Y10=A0.A1'.A2.A3'
Y11=A0.A1'.A2.A3
Y12=A0.A1.A2'.A3'
Y13=A0.A1.A2'.A3
Y14=A0.A1.A2.A3'
Y15=A0.A1.A2'.A3

Logical circuit of the above expressions is given below:

Encoder & Decoder