2SK2796(L), 2SK2796(S)

Silicon N Channel MOS FET

High Speed Power Switching

ADE-208-534C (Z)
4th. Edition
Jun 1998

Features

• Low on-resistance
R DS(on) = 0.12Ω typ.
• 4V gate drive devices.
• High speed switching

Outline

DPAK |1

4 4

D
1 2
3
G
1. Gate
2. Drain
1 2
S 3 3. Source
4. Drain
2SK2796(L), 2SK2796(S)

Absolute Maximum Ratings (Ta = 25°C)

Item Symbol Ratings Unit
Drain to source voltage VDSS 60 V
Gate to source voltage VGSS ±20 V
Drain current ID 5 A
Note1
Drain peak current I D(pulse) 20 A
Body-drain diode reverse drain current I DR 5 A
Note3
Avalanche current I AP 5 A
Note3
Avalanche energy EAR 2.14 mJ
Note2
Channel dissipation Pch 20 W
Channel temperature Tch 150 °C
Storage temperature Tstg –55 to +150 °C
Note: 1. PW ≤ 10µs, duty cycle ≤ 1 %
2. Value at Tc = 25°C
3. Value at Tch = 25°C, Rg ≥ 50 Ω

2
 2SK2796(L), 2SK2796(S)

Electrical Characteristics (Ta = 25°C)

Item Symbol Min Typ Max Unit Test Conditions
Drain to source breakdown voltage V(BR)DSS 60 — — V I D = 10mA, VGS = 0
Gate to source breakdown voltage V(BR)GSS ±20 — — V I G = ±100µA, VDS = 0
Zero gate voltege drain current I DSS — — 10 µA VDS = 60 V, VGS = 0
Gate to source leak current I GSS — — ±10 µA VGS = ±16V, VDS = 0
Gate to source cutoff voltage VGS(off) 1.0 — 2.0 V I D = 1mA, VDS = 10V
Static drain to source on state RDS(on) — 0.12 0.16 Ω I D = 3 A, VGS = 10V Note4
resistance
Static drain to source on state RDS(on) — 0.16 0.25 Ω I D = 3A, VGS = 4V Note4
resistance
Forward transfer admittance |yfs| 2.5 4.0 — S I D = 3A, VDS = 10V Note4
Input capacitance Ciss — 180 — pF VDS = 10V
Output capacitance Coss — 90 — pF VGS = 0
Reverse transfer capacitance Crss — 30 — pF f = 1MHz
Turn-on delay time t d(on) — 9 — ns VGS = 10V, ID = 3A
Rise time tr — 25 — ns RL = 10Ω
Turn-off delay time t d(off) — 35 — ns
Fall time tf — 55 — ns
Body–drain diode forward voltage VDF — 1.0 — V I F = 5A, VGS = 0
Body–drain diode reverse t rr — 40 — ns I F = 5A, VGS = 0
recovery time diF/ dt =50A/µs
Note: 4. Pulse test

3
2SK2796(L), 2SK2796(S)

Main Characteristics

Power vs. Temperature Derating Maximum Safe Operation Area

40 100

10
30 µs
Pch (W)

I D (A)
30
10 10
PW 0
1 µ
m s
= s

Drain Current
Channel Dissipation

10

D
20 3

C
m

O
s(

pe
1s

ra
ho

tio
1 Operation in t)

n
(T
this area is

c
10

=
limited by R DS(on)

25
°C
0.3

)
0.1 Ta = 25°C
0 50 100 150 200 0.2 0.5 1 2 5 10 20 50 100
Ambient Temperature Ta (°C) Drain to Source Voltage V DS(V)

Typical Output Characteristics

10 V 6 V Typical Transfer Characteristics
5 5
5V 25°C
Pulse Test
4V –25°C
4 3.5 V 4 Tc = 75°C
I D (A)
I D (A)

3V
3 3
Drain Current

Drain Current

2 2
2.5 V

1 1
V DS = 10 V
VGS = 2 V Pulse Test
0 2 4 6 8 10 0 2 4 6 8 10
Drain to Source Voltage V DS(V) Gate to Source Voltage V (V)
GS

4
 2SK2796(L), 2SK2796(S)

Drain to Source Saturation Voltage vs. Static Drain to Source on State Resistance
Gate to Source Voltage vs. Drain Current
2.0 5

Drain to Source On State Resistance

R DS(on) ( W)
Pulse Test Pulse Test
Drain to Source Saturation Voltage
V DS(on) (V)

1.6 2

1
1.2
0.5
0.8 ID=5A
0.2 VGS = 4 V
0.4
2A 0.1 10 V
1A
0.05
0 2 4 6 8 10 0.1 0.3 1 3 10 30 100
Gate to Source Voltage V GS (V) Drain Current I D (A)

Static Drain to Source on State Resistance Forward Transfer Admittance vs.

vs. Temperature Drain Current
Static Drain to Source on State Resistance

0.5 10
Forward Transfer Admittance |y fs | (S)
R DS(on) ( W)

Pulse Test
Tc = –25 °C
5
0.4
1A
2A 25 °C
2
0.3 ID=5A
75 °C
V GS = 4 V 1
0.2
0.5
5A
1, 2 A
0.1
0.2 V DS = 10 V
10 V
Pulse Test
0 0.1
–40 0 40 80 120 160 0.1 0.2 0.5 1 2 5 10
Case Temperature Tc (°C) Drain Current I D (A)

5
2SK2796(L), 2SK2796(S)

Body–Drain Diode Reverse Typical Capacitance vs.

Recovery Time Drain to Source Voltage
500 1000
VGS = 0
Reverse Recovery Time trr (ns)

500 f = 1 MHz
200

Capacitance C (pF)
100 200
Ciss

50 100

50 Coss
20

10 di / dt = 50 A / µs 20
V GS = 0, Ta = 25 °C Crss
5 10
0.1 0.2 0.5 1 2 5 10 0 10 20 30 40 50
Reverse Drain Current I DR (A) Drain to Source Voltage V DS (V)

Dynamic Input Characteristics Switching Characteristics

100 20 100
ID=5A
V GS (V)
V DS (V)

t d(off)
50
80 V DD = 10 V 16
Switching Time t (ns)

25 V tf
50 V 20 tr
Gate to Source Voltage
Drain to Source Voltage

60 12
V DS t d(on)
10
V GS
40 8
5

20 V DD = 50 V 4
2 V GS = 10 V, V DD = 30 V
25 V
PW = 5 µs, duty < 1 %
10 V 0 1
0 2 4 6 8 10 0.1 0.2 0.5 1 2 5 10
Gate Charge Qg (nc) Drain Current I D (A)

6
 2SK2796(L), 2SK2796(S)

Reverse Drain Current vs. Maximun Avalanche Energy vs.

Source to Drain Voltage Channel Temperature Derating

Repetitive Avalanche Energy E AR (mJ)

10 2.5
I AP = 5 A
Reverse Drain Current I DR (A)

8 2.0 V DD = 25 V
5V duty < 0.1 %
Rg > 50 W
6 1.5
10 V
V GS = 0, –5 V
4 1.0

2 0.5

Pulse Test
0
0 0.4 0.8 1.2 1.6 2.0 25 50 75 100 125 150
Source to Drain Voltage V SD (V) Channel Temperature Tch (°C)

Avalanche Test Circuit Avalanche Waveform

VDSS
1 2
EAR = • L • I AP •
L 2 VDSS – V DD
V DS
Monitor
I AP V (BR)DSS
Monitor
I AP
Rg D. U. T VDD V DS
ID
Vin 50W
15 V
VDD
0

7
2SK2796(L), 2SK2796(S)

Normalized Transient Thermal Impedance vs. Pulse Width

3
Normalized Transient Thermal Impedance
g s (t)

Tc = 25°C
D=1
1

0.5

0.3
0.2

0.1
q ch – c(t) = g s (t) • q ch – c
0.1 0.05 q ch – c = 6.25 °C/W, Tc = 25 °C

0.02
e PW
0.0
1
Puls PDM D=
ot T
0.03 h
1s PW
T

0.01
10 µ 100 µ 1m 10 m 100 m 1 10
Pulse Width PW (S)

Switching Time Test Circuit Waveform

Vin Monitor Vout

Monitor
90%
D.U.T.
RL
Vin 10%

Vin V DD Vout 10%

50W 10%
10 V = 30 V

90% 90%

td(on) tr td(off) tf

8
 2SK2796(L), 2SK2796(S)

Package Dimensions

Unit: mm

1.7 ± 0.5

6.5 ± 0.5 2.3 ± 0.5

5.4 ± 0.5 0.55 ± 0.1
5.5 ± 0.5

7.2

1.7 ± 0.5
6.5 ± 0.5 2.3 ± 0.5
5.4 ± 0.5 0.55 ± 0.1
1.15 ± 0.1
3.1 ± 0.5

16.2 ± 0.5

5.5 ± 0.5
1.2 Max

9.5 ± 0.5
0.8 ± 0.1

1.15 ± 0.1 0 ~ 0.25

0.8 ± 0.1
2.29 ± 0.5 2.29 ± 0.5 0.55 ± 0.1
2.29 ± 0.5 2.29 ± 0.5 2.5 ± 0.5
0.55 ± 0.1 1.5 Max
Hitachi Code DPAK
EIAJ ( L type) SC–63
L type S type EIAJ ( S type) SC–64
JEDEC —

9
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