19-4320; Rev 3; 12/10

KIT
ATION
EVALU BL E
AVAILA
4A, 2MHz Step-Down Regulator
with Integrated Switches
General Description Features

MAX15038
The MAX15038 high-efficiency switching regulator ♦ Internal 31mΩ RDS(ON) High-Side and 24mΩ
delivers up to 4A load current at output voltages from RDS(ON) Low-Side MOSFETs
0.6V to 90% of VIN. The IC operates from 2.9V to 5.5V, ♦ Continuous 4A Output Current Over Temperature
making it ideal for on-board point-of-load and postregu- ♦ ±1% Output Accuracy Over Load, Line, and
lation applications. Total output error is less than ±1% Temperature
over load, line, and temperature ranges. ♦ Operates from 2.9V to 5.5V VIN Supply
The MAX15038 features fixed-frequency PWM mode ♦ Adjustable Output from 0.6V to (0.9 x VIN)
operation with a switching frequency range of 500kHz ♦ Soft-Start Reduces Inrush Supply Current
to 2MHz set by an external resistor. The MAX15038 ♦ 500kHz to 2MHz Adjustable Switching Frequency
provides the option of operating in a skip mode to ♦ Compatible with Ceramic, Polymer, and
improve light-load efficiency. High-frequency operation Electrolytic Output Capacitors
allows for an all-ceramic capacitor design. The high ♦ Nine Preset and Adjustable Output Voltages
operating frequency also allows for small-size external 0.6V, 0.7V, 0.8V, 1.0V, 1.2V, 1.5V, 1.8V, 2.0V,
components. 2.5V, and Adjustable
The low-resistance on-chip nMOS switches ensure high ♦ Monotonic Startup for Safe-Start into Prebiased
efficiency at heavy loads while minimizing critical induc- Outputs
tances, making the layout a much simpler task with ♦ Selectable Forced PWM or Skip Mode for Light
respect to discrete solutions. Following a simple layout Load Efficiency
and footprint ensures first-pass success in new designs. ♦ Overcurrent and Overtemperature Protection
♦ Output Current Sink/Source Capable with Cycle-
The MAX15038 comes with a high bandwidth (28MHz) by-Cycle Protection
voltage-error amplifier. The voltage-mode control archi-
♦ Open-Drain Power-Good Output
tecture and the voltage-error amplifier permit a type III
♦ Lead-Free, 4mm x 4mm, 24-Pin Thin QFN Package
compensation scheme to be utilized to achieve maxi-
mum loop bandwidth, up to 20% of the switching fre- Ordering Information
quency. High loop bandwidth provides fast transient
response, resulting in less required output capacitance PART TEMP RANGE PIN-PACKAGE
and allowing for all-ceramic-capacitor designs. MAX15038ETG+ -40°C to +85°C 24 Thin QFN-EP*
The MAX15038 provides two three-state logic inputs to +Denotes a lead(Pb)-free/RoHS-compliant package.
select one of nine preset output voltages. The preset *EP = Exposed pad.
output voltages allow customers to achieve ±1% out-
put-voltage accuracy without using expensive 0.1% Typical Operating Circuit
resistors. In addition, the output voltage can be set to
INPUT
any customer value by either using two external resis- 2.9V TO 5.5V
IN BST
tors at the feedback with a 0.6V internal reference or
applying an external reference voltage to the REFIN MAX15038 OUTPUT
EN 1.8V, 4A
input. The MAX15038 offers programmable soft-start LX
time using one capacitor to reduce input inrush current. VDD
OUT
Applications
PGND
Server Power Supplies CTL2
POLs
CTL1 FB
ASIC/CPU/DSP Core and I/O Voltages
FREQ
DDR Power Supplies REFIN
Base-Station Power Supplies SS COMP
VDD

Telecom and Networking Power Supplies

RAID Control Power Supplies
MODE
PWRGD
GND
Pin Configuration appears at end of data sheet.

________________________________________________________________ Maxim Integrated Products 1

For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
 4A, 2MHz Step-Down Regulator
with Integrated Switches
ABSOLUTE MAXIMUM RATINGS
MAX15038

IN, PWRGD to GND..................................................-0.3V to +6V VDD Output Short-Circuit Duration .............................Continuous

VDD to GND ..................-0.3V to the lower of +4V or (VIN + 0.3V) Converter Output Short-Circuit Duration ....................Continuous
COMP, FB, MODE, REFIN, CTL1, CTL2, SS, Continuous Power Dissipation (TA = +70°C)
FREQ to GND ..........................................-0.3V to (VDD + 0.3V) 24-Pin TQFN (derate 27.8mW/°C above +70°C) ........2222mW
OUT, EN to GND ......................................................-0.3V to +6V Thermal Resistance (Note 2)
BST to LX..................................................................-0.3V to +6V θJA.................................................................................36°C/W
BST to GND ............................................................-0.3V to +12V θJC ..................................................................................6°C/W
PGND to GND .......................................................-0.3V to +0.3V Operating Temperature Range ...........................-40°C to +85°C
LX to PGND ..................-0.3V to the lower of +6V or (VIN + 0.3V) Junction Temperature ......................................................+150°C
LX to PGND ..........-1V to the lower of +6V or (VIN + 1V) for 50ns Storage Temperature Range .............................-65°C to +150°C
ILX(RMS) (Note 1) ......................................................................4A Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) .......................................+260°C
Note 1: LX has internal clamp diodes to PGND and IN. Applications that forward bias these diodes should take care not to exceed
the IC’s package power dissipation limits.
Note 2: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-
layer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.

ELECTRICAL CHARACTERISTICS
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
IN
IN Voltage Range 2.9 5.5 V
VIN = 3.3V 4.7 8
IN Supply Current fS = 1MHz, no load mA
VIN = 5V 5 8.5
VIN = 5V, VEN = 0V 10 20
Total Shutdown Current from IN μA
VIN = VDD = 3.3V, VEN = 0V 45
3.3V LDO (VDD)
VDD rising 2.6 2.8
V
VDD Undervoltage Lockout VDD falling 2.35 2.55
LX starts/stops switching
Threshold Minimum glitch-width
10 μs
rejection
VDD Output Voltage VIN = 5V, IVDD = 0 to 10mA 3.1 3.3 3.5 V
VDD Dropout VIN = 2.9V, IVDD = 10mA 0.08 V
VDD Current Limit VIN = 5V, VDD = 0V 25 40 mA
BST
BST Supply Current VBST = VIN = 5V, VLX = 0 or 5V, VEN = 0V 0.025 μA
PWM COMPARATOR
PWM Comparator Propagation
10mV overdrive 20 ns
Delay
PWM Peak-to-Peak Ramp
1 V
Amplitude
PWM Valley Amplitude 0.8 V

2 _______________________________________________________________________________________
 4A, 2MHz Step-Down Regulator
with Integrated Switches
ELECTRICAL CHARACTERISTICS (continued)

MAX15038
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
ERROR AMPLIFIER
COMP Clamp Voltage, High VIN = 2.9V to 5V, VFB = 0.5V, VREFIN = 0.6V 2 V
COMP Clamp Voltage, Low VIN = 2.9V to 5V, VFB = 0.7V, VREFIN = 0.6V 0.7 V
COMP Slew Rate VFB step from 0.5V to 0.7V in 10ns 1.6 V/μs
From COMP to GND, VIN = 3.3V, VCOMP = 100mV,
COMP Shutdown Resistance 6 Ω
VEN = VSS = 0V
Internally Preset Output Voltage
VREFIN = VSS, MODE = GND -1 +1 %
Accuracy
FB Set Point Value CTL1 = CTL2 = GND, MODE = GND 0.594 0.6 0.606 V
FB to OUT Resistor All VID settings except CTL1 = CTL2 = GND 5.5 8 10.5 kΩ
Open-Loop Voltage Gain 115 dB
Error-Amplifier Unity-Gain
28 MHz
Bandwidth
Error-Amplifier and REFIN
VDD = 2.9V to 3.5V 0 VDD - 2 V
Common-Mode Input Range
Error-Amplifier Maximum Output VCOMP = 1V, VFB = 0.7V, sinking 1
mA
Current VREFIN = 0.6V VFB = 0.5V, sourcing -1
FB Input Bias Current CTL1 = CTL2 = GND -125 nA
CTL_
VCTL_ = 0V -7.2
CTL_ Input Bias Current μA
VCTL_ = VDD +7.2
Low, falling 0.8
Open VDD/2
CTL_ Input Threshold V
VDD -
High, rising
0.8
Hysteresis All VID transitions 50 mV
REFIN
REFIN Input Bias Current VREFIN = 0.6V -185 nA
REFIN Offset Voltage VREFIN = 0.9V, FB shorted to COMP -4.5 +4.5 mV
LX (All Pins Combined)
VIN = VBST - VLX = 3.3V 42
LX On-Resistance, High-Side ILX = -2A mΩ
VIN = VBST - VLX = 5V 31 54
VIN = 3.3V 30
LX On-Resistance, Low-Side ILX = 2A mΩ
VIN = 5V 24 42
High-side sourcing 5.7 7
LX Current-Limit Threshold Low-side sinking 7 A
Zero-crossing current threshold, MODE = VDD 0.2
VLX = 0V -0.01
LX Leakage Current VIN = 5V, VEN = 0V μA
VLX = 5V +0.01

_______________________________________________________________________________________ 3
 4A, 2MHz Step-Down Regulator
with Integrated Switches
ELECTRICAL CHARACTERISTICS (continued)
MAX15038

(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
RFREQ = 49.9kΩ 0.9 1 1.1
LX Switching Frequency VIN = 2.9V to 5V MHz
RFREQ = 23.6kΩ 1.8 2 2.2
Switching Frequency Range 500 2000 kHz
LX Minimum Off-Time 78 ns
LX Maximum Duty Cycle RFREQ = 49.9kΩ 92 95 %
LX Minimum Duty Cycle RFREQ = 49.9kΩ 5 15 %
Average Short-Circuit IN Supply
OUT connected to GND, VIN = 5V 0.15 A
Current
RMS LX Output Current 4 A
ENABLE
EN Input Logic-Low Threshold EN falling 0.9 V
EN Input Logic-High Threshold EN rising 1.5 V
EN Input Current VEN = 0 or 5V, VIN = 5V 0.01 μA
MODE
Logic-low, falling 26
MODE Input-Logic Threshold Logic VDD/2 or open, rising 50 %VDD
Logic-high, rising 74
MODE Input-Logic Hysteresis MODE falling 5 %VDD
MODE = GND -5
MODE Input Bias Current μA
MODE = VDD 5
SS
SS Current VSS = 0.45V, VREFIN = 0.6V, sourcing 6.7 8 9.3 μA
THERMAL SHUTDOWN
Thermal-Shutdown Threshold Rising 165 °C
Thermal-Shutdown Hysteresis 25 °C
POWER-GOOD (PWRGD)
VFB falling, VREFIN = 0.6V 88 90 92 %
Power-Good Threshold Voltage
VFB rising, VREFIN = 0.6V 92.5 VREFIN
Clock
Power-Good Edge Deglitch VFB rising or falling 48
cycles
PWRGD Output Voltage Low IPWRGD = 4mA 0.03 0.1 V
PWRGD Leakage Current VIN = VPWRGD = 5V, VFB = 0.7V, VREFIN = 0.6V 0.01 μA
HICCUP OVERCURRENT LIMIT
Clock
Current-Limit Startup Blanking 112
cycles
Clock
Autoretry Restart Time 896
cycles

4 _______________________________________________________________________________________
 4A, 2MHz Step-Down Regulator
with Integrated Switches
ELECTRICAL CHARACTERISTICS (continued)

MAX15038
(VIN = VEN = 5V, CVDD = 2.2μF, TA = TJ = -40°C to +85°C, typical values are at TA = +25°C, circuit of Figure 1, unless otherwise
noted.) (Note 3)
PARAMETER CONDITIONS MIN TYP MAX UNITS
%
FB Hiccup Threshold VFB falling 70
VREFIN
Hiccup Threshold Blanking Time VFB falling 28 μs
Note 3: Specifications are 100% production tested at TA = +25°C. Limits over the operating temperature range are guaranteed by design.

Typical Operating Characteristics

(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)

EFFICIENCY EFFICIENCY FREQUENCY

vs. OUTPUT CURRENT vs. OUTPUT CURRENT vs. INPUT VOLTAGE
100 100 2.20
MAX15038 toc01

MAX15038 toc02

MAX15038 toc03
2.15
90 90
2.10

FREQUENCY (MHz)
80 80
EFFICIENCY (%)

EFFICIENCY (%)

VOUT = 2.5V VOUT = 2.5V 2.05

70 VOUT = 1.8V 70 VOUT = 1.8V 2.00

VOUT = 1.2V 1.95 TA = +85°C

60 60
VOUT = 1.2V 1.90 TA = +25°C
50 50 TA = -40°C
PWM PWM 1.85
SKIP VIN = 3.3V SKIP RFREQ = 23.2kΩ
40 40 1.80
0.1 1.0 10.0 0.1 1.0 10.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
OUTPUT CURRENT (A) OUTPUT CURRENT (A) INPUT VOLTAGE (V)

FREQUENCY
vs. INPUT VOLTAGE LOAD REGULATION LINE REGULATION (LOAD = 4A)
1.20 0 0

MAX15038 toc05b
MAX15038 toc05a
MAX15038 toc04

VOUT = 2.5V
1.15 -0.05
-0.02
OUTPUT-VOLTAGE CHANGE (%)
OUTPUT-VOLTAGE CHANGE (%)

-0.10
1.10 VOUT = 1.8V
-0.15
FREQUENCY (MHz)

-0.04
1.05 -0.20
1.00 -0.25 VOUT = 1.2V -0.06

0.95 -0.30 VOUT = 1.8V

TA = +85°C
-0.08
TA = +25°C -0.35 VOUT = 2.5V
0.90
-0.40
TA = -40°C -0.10
0.85 VOUT = 1.2V
-0.45
RFREQ = 49.9kΩ
0.80 -0.50 -0.12
2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 1 2 3 4 2.5 3.0 3.5 4.0 4.5 5.0 5.5
INPUT VOLTAGE (V) LOAD CURRENT (A) INPUT VOLTAGE (V)

_______________________________________________________________________________________ 5
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Operating Characteristics (continued)
MAX15038

(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)

SWITCHING WAVEFORMS SWITCHING WAVEFORMS

LOAD TRANSIENT (FORCED PWM, 2A LOAD) (SKIP MODE, NO LOAD)
MAX15038 toc06 MAX15038 toc07 MAX15038 toc08

AC-COUPLED
VOUT
VOUT AC-COUPLED 100mV/div
VOUT
AC-COUPLED 50mV/div
100mV/div
1A/div

2A/div ILX 0A
ILX
2A 0A

IOUT 5V/div
VLX 5V/div
VLX
0A 0V

40μs/div 400ns/div 2μs/div

SOFT-START WAVEFORM SHUTDOWN WAVEFORM

(RLOAD = 0.5Ω) (RLOAD = 0.5Ω)
MAX15038 toc09 MAX15038 toc10

VEN
VEN
5V/div
5V/div

VOUT VOUT
1V/div 1V/div
0V 0V

400μs/div 10μs/div

INPUT SHUTDOWN CURRENT MAXIMUM OUTPUT CURRENT

vs. INPUT VOLTAGE vs. OUTPUT VOLTAGE
12 10
MAX15038 toc12
MAX15038 toc11

11 9
INPUT SHUTDOWN CURRENT (μA)

MAXIMUM OUTPUT CURRENT (A)

8
10
7
9
6
8
5
7
4

6 3
VEN = 0V
5 2
2.5 3.0 3.5 4.0 4.5 5.0 5.5 0.5 1.0 1.5 2.0 2.5
INPUT VOLTAGE (V) OUTPUT VOLTAGE (V)

6 _______________________________________________________________________________________
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Operating Characteristics (continued)

MAX15038
(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)

RMS INPUT CURRENT DURING EXPOSED PAD TEMPERATURE

HICCUP CURRENT LIMIT SHORT CIRCUIT vs. INPUT VOLTAGE vs. AMBIENT TEMPERATURE
MAX15038 toc13
0.5 100

MAX15038 toc14

MAX15038 toc15
VOUT 1V/div 90

EXPOSED PAD TEMPERATURE (°C)

RMS INPUT CURRENT (A) 0.4 80
0V
70
0.3 60

IOUT 5A/div 50

0A 0.2 40 4A LOAD
30
IIN 1A/div 0.1 20
0A 10
VOUT = 0V MEASURED ON A MAX15038EVKIT
0 0
400μs/div 2.5 3.0 3.5 4.0 4.5 5.0 5.5 0 20 40 60 80 100
INPUT VOLTAGE (V) AMBIENT TEMPERATURE (°C)

FEEDBACK VOLTAGE
vs. TEMPERATURE SOFT-START WITH REFIN
MAX15038 toc17
0.64
MAX15038 toc16

0.63 1A/div
IIN
0.62 0A
FEEDBACK VOLTAGE (V)

0.61 0.5V/div
VREFIN
0.60 0V

0.59 1V/div
VOUT
0.58 0V

0.57 VPWRGD 2V/div

0.56 0V
-40 -15 10 35 60 85 200μs/div
TEMPERATURE (°C)

STARTING INTO PREBIASED OUTPUT STARTING INTO PREBIASED OUTPUT

(MODE = VDD, VOUT = 2.5V, 2A LOAD) (MODE = VDD/2, VOUT = 2.5V, 2A LOAD)
MAX15038 toc18 MAX15038 toc19

5V/div 5V/div
VEN VEN
0V 0V

1V/div 1V/div
VOUT VOUT

0V 0V

2A 2A
IOUT IOUT
0A 0A

VPWRGD 5V/div VPWRGD 5V/div

0V 0V
200μs/div 200μs/div

_______________________________________________________________________________________ 7
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Operating Characteristics (continued)
MAX15038

(Typical values are VIN = VEN = 5V, VOUT = 1.8V, RFREQ = 49.9kΩ, IOUT = 4A, TA = +25°C, circuit of Figure 1, unless otherwise noted.)

STARTING INTO PREBIASED OUTPUT STARTING INTO PREBIASED OUTPUT

(MODE = VDD, VOUT = 2.5V, NO LOAD) (MODE = VDD/2, VOUT = 2.5V, NO LOAD)
MAX15038 toc20 MAX15038 toc21

VEN VEN
2V/div 2V/div
0V 0V

VOUT VOUT
1V/div 1V/div
0V 0V

VPWRGD VPWRGD
2V/div 2V/div
0V 0V

200μs/div 200μs/div

STARTING INTO PREBIASED OUTPUT STARTING INTO PREBIASED OUTPUT

ABOVE NOMINAL SETPOINT (VOUT = 1.5V) ABOVE NOMINAL SETPOINT (VOUT = 1.5V)
MAX15038 toc22 MAX15038 toc23

VEN VEN
2V/div 2V/div
0V 0V

VOUT
VOUT
1V/div
1V/div

0V 0V
VPWRGD VPWRGD
2V/div 2V/div
VMODE = VDD, 0V VMODE = VDD/2, 0V
NO LOAD NO LOAD

1ms/div 1ms/div

TRANSITION FROM SKIP MODE TRANSITION FROM FORCED

TO FORCED PWM MODE PWM MODE TO SKIP MODE
MAX15038 toc24 MAX15038 toc25

VMODE VMODE
5V/div 5V/div

VLX VLX
5V/div 5V/div

VOUT
VOUT
0.5V/div
0.5V/div

0V 0V
2ms/div 4ms/div

8 _______________________________________________________________________________________
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Pin Description

MAX15038
PIN NAME FUNCTION
1 MODE Functional MODE Selection Input. See the MODE Selection section for more information.
3.3V LDO Output. Supply input for the internal analog core. Connect a low-ESR, ceramic capacitor with a
2 VDD
minimum value of 2.2μF from VDD to GND.
3 CTL1 Preset Output-Voltage Selection Inputs. CTL1 and CTL2 set the output voltage to one of nine preset
4 CTL2 voltages. See Table 1 and the Programming the Output Voltage (CTL1, CTL2) section for preset voltages.

External Reference Input. Connect REFIN to SS to use the internal 0.6V reference. Connecting REFIN to an
5 REFIN external voltage forces FB to regulate to the voltage applied to REFIN. REFIN is internally pulled to GND
when the IC is in shutdown/hiccup mode.

Soft-Start Input. Connect a capacitor from SS to GND to set the startup time. Use a capacitor with a 1nF
6 SS
minimum value. See the Soft-Start and REFIN section for details on setting the soft-start time.
Analog Ground Connection. Connect GND and PGND together at one point near the input bypass capacitor
7 GND
return terminal.
Voltage Error-Amplifier Output. Connect the necessary compensation network from COMP to FB and OUT.
8 COMP
COMP is internally pulled to GND when the IC is in shutdown/hiccup mode.

Feedback Input. Connect FB to the center tap of an external resistive divider from the output to GND to set
9 FB the output voltage from 0.6V to 90% of VIN. Connect FB through an RC network to the output when using
CTL1 and CTL2 to select any of nine preset voltages.

Output-Voltage Sense. Connect to the converter output. Leave OUT unconnected when an external resistive
10 OUT
divider is used.
Oscillator Frequency Select. Connect a precision resistor from FREQ to GND to select the switching
11 FREQ
frequency. See the Frequency Select (FREQ) section.

Open-Drain, Power-Good Output. PWRGD is high impedance when VFB rises above 92.5% (typ) of VREFIN
and VREFIN is above 0.54V. PWRGD is internally pulled low when VFB falls below 90% (typ) of VREFIN or
12 PWRGD
VREFIN is below 0.54V. PWRGD is internally pulled low when the IC is in shutdown mode, VDD is below the
internal UVLO threshold, or the IC is in thermal shutdown.

High-Side MOSFET Driver Supply. Internally connected to IN through a pMOS switch. Bypass BST to LX with
13 BST
a 0.1μF capacitor.
14, 15, Inductor Connection. All LX pins are internally shorted together. Connect all LX pins to the switched side of
LX
16 the inductor. LX is high impedance when the IC is in shutdown mode.
Power Ground. Connect all PGND pins externally to the power ground plane. Connect all PGND pins
17–20 PGND
together near the IC.
21, 22, Input Power Supply. Input supply range is from 2.9V to 5.5V. Bypass IN to PGND with a 22μF ceramic
IN
23 capacitor.
24 EN Enable Input. Logic input to enable/disable the MAX15038.
Exposed Pad. Solder EP to a large contiguous copper plane connected to PGND to optimize thermal
— EP
performance. Do not use EP as a ground connection for the device.

_______________________________________________________________________________________ 9
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Block Diagram
MAX15038

VDD

3.3V LDO MAX15038

SHUTDOWN UVLO
EN CONTROL CIRCUITRY
BST

CURRENT-LIMIT BST SWITCH

COMPARATOR IN
BIAS
GENERATOR

VOLTAGE
REFERENCE THERMAL
CONTROL
SHUTDOWN LX
LOGIC
IN

SS SOFT-START
PGND

CURRENT-LIMIT
REFIN COMPARATOR

OUT
ERROR
8kΩ AMPLIFIER PWM
COMPARATOR

FB MODE

CTL1 VID
VOLTAGE-
CONTROL
CTL2 CIRCUITRY
1VP-P FREQ
OSCILLATOR

COMP
PWRGD
SHDN
FB
COMP CLAMPS
0.9 x VREFIN GND

10 ______________________________________________________________________________________
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Typical Application Circuit

MAX15038
INPUT 2.2Ω
2.9V TO 5.5V OPTIONAL
IN BST C15
C10
1000pF
C6 C7 0.1μF
22μF 0.1μF L1 OUTPUT
MAX15038 0.47μH 1.8V, 4A
LX
VDD
C5 OUT
2.2μF C3 C8 C9
560pF 22μF 0.01μF
CTL2 R3
158Ω
CTL1
PGND
EN
FB
C2
FREQ R2
1500pF
2.67kΩ
REFIN
R4
49.9kΩ SS
C1
C4
33pF
0.022μF
COMP VDD
R1
20kΩ
MODE
PWRGD
GND

Figure 1. 1MHz, All-Ceramic-Capacitor Design with VIN = 2.9V to 5.5V and VOUT = 1.8V

Detailed Description MOSFET and 31mΩ for the high-side n-channel

MOSFET) maintains high efficiency at both heavy-load
The MAX15038 high-efficiency, voltage-mode switching
and high-switching frequencies.
regulator delivers up to 4A of output current. The
MAX15038 provides output voltages from 0.6V to 0.9 x The MAX15038 employs voltage-mode control architec-
VIN from 2.9V to 5.5V input supplies, making it ideal for ture with a high bandwidth (28MHz) error amplifier. The
on-board point-of-load applications. The output voltage voltage-mode control architecture allows up to 2MHz
accuracy is better than ±1% over load, line, and tem- switching frequency, reducing board area. The op-amp
perature. voltage-error amplifier works with type III compensation
to fully utilize the bandwidth of the high-frequency
The MAX15038 features a wide switching frequency
switching to obtain fast transient response. Adjustable
range, allowing the user to achieve all-ceramic-capaci-
soft-start time provides flexibilities to minimize input
tor designs and fast transient responses (see Figure 1).
startup inrush current. An open-drain, power-good
The high operating frequency minimizes the size of
(PWRGD) output goes high when VFB reaches 92.5% of
external components. The MAX15038 is available in a
VREFIN and VREFIN is greater than 0.54V.
small (4mm x 4mm), lead-free, 24-pin thin QFN pack-
age. The REFIN function makes the MAX15038 an ideal The MAX15038 provides option for three modes of oper-
candidate for DDR and tracking power supplies. Using ation: regular PWM, PWM mode with monotonic startup
internal low-RDS(ON) (24mΩ for the low-side n-channel into prebiased output, or skip mode with monotonic
startup into prebiased output.

______________________________________________________________________________________ 11
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Controller Function external capacitor from SS to GND. The required
MAX15038

The controller logic block is the central processor that capacitance value is determined as:
determines the duty cycle of the high-side MOSFET 8μA × tSS
under different line, load, and temperature conditions. C=
0.6V
Under normal operation, where the current-limit and
temperature protection are not triggered, the controller where tSS is the required soft-start time in seconds. The
logic block takes the output from the PWM comparator MAX15038 also features an external reference input
and generates the driver signals for both high-side and (REFIN). The IC regulates FB to the voltage applied to
low-side MOSFETs. The break-before-make logic and REFIN. The internal soft-start is not available when
the timing for charging the bootstrap capacitors are using an external reference. A method of soft-start
calculated by the controller logic block. The error signal when using an external reference is shown in Figure 2.
from the voltage-error amplifier is compared with the Connect REFIN to SS to use the internal 0.6V reference.
ramp signal generated by the oscillator at the PWM Use a capacitor of 1nF minimum value at SS.
comparator and, thus, the required PWM signal is pro-
duced. The high-side switch is turned on at the begin-
ning of the oscillator cycle and turns off when the ramp Undervoltage Lockout (UVLO)
voltage exceeds the VCOMP signal or the current-limit The UVLO circuitry inhibits switching when VDD is below
threshold is exceeded. The low-side switch is then 2.55V (typ). Once VDD rises above 2.6V (typ), UVLO
turned on for the remainder of the oscillator cycle. clears and the soft-start function activates. A 50mV hys-
teresis is built in for glitch immunity.
Current Limit
The internal, high-side MOSFET has a typical 7A peak BST
current-limit threshold. When current flowing out of LX The gate-drive voltage for the high-side, n-channel
exceeds this limit, the high-side MOSFET turns off and switch is generated by a flying-capacitor boost circuit.
the synchronous rectifier turns on. The synchronous The capacitor between BST and LX is charged from the
rectifier remains on until the inductor current falls below VIN supply while the low-side MOSFET is on. When the
the low-side current limit. This lowers the duty cycle low-side MOSFET is switched off, the voltage of the
and causes the output voltage to drop until the current capacitor is stacked above LX to provide the necessary
limit is no longer exceeded. The MAX15038 uses a hic- turn-on voltage for the high-side internal MOSFET.
cup mode to prevent overheating during short-circuit
output conditions. Frequency Select (FREQ)
The switching frequency is resistor programmable from
During current limit, if VFB drops below 70% of VREFIN 500kHz to 2MHz. Set the switching frequency of the IC
and stays below this level for 12μs or more, the with a resistor (RFREQ) connected from FREQ to GND.
MAX15038 enters hiccup mode. The high-side RFREQ is calculated as:
MOSFET and the synchronous rectifier are turned off
and both COMP and REFIN are internally pulled low. If 50kΩ 1
RFREQ = × ( − 0.05μs)
REFIN and SS are connected together, both are pulled 0.95μs fS
low. The part remains in this state for 896 clock cycles
and then attempts to restart for 112 clock cycles. If the where fS is the desired switching frequency in Hertz.
fault causing current limit has cleared, the part resumes
normal operation. Otherwise, the part reenters hiccup
mode again.
R1
Soft-Start and REFIN REFIN
The MAX15038 utilizes an adjustable soft-start function
to limit inrush current during startup. An 8μA (typ) cur-
R2 C MAX15038
rent source charges an external capacitor connected to
SS. The soft-start time is adjusted by the value of the

Figure 2. Typical Soft-Start Implementation with External

Reference

12 ______________________________________________________________________________________
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Power-Good Output (PWRGD) Table 1. CTL1 and CTL2 Output Voltage

MAX15038
PWRGD is an open-drain output that goes high imped-
ance when VFB is above 0.925 x VREFIN and VREFIN is
Selection
above 0.54V for at least 48 clock cycles. PWRGD pulls VOUT WHEN
low when V FB is below 90% of V REFIN or V REFIN is USING
CTL1 CTL2 VOUT (V)
below 0.54V for at least 48 clock cycles. PWRGD is low EXTERNAL
when the IC is in shutdown mode, VDD is below the VREFIN (V)
internal UVLO threshold, or the IC is in thermal shut- 0.6* or VREFIN* or
down mode. GND GND 0.6 < V OUT VREFIN < VOUT

0.9 x VIN**
0.9 x VIN**
Programming the Output Voltage
(CTL1, CTL2) VDD VDD 0.7 VREFIN x (7/6)
As shown in Table 1, the output voltage is pin program- GND Unconnected 0.8 VREFIN x (4/3)
mable by the logic states of CTL1 and CTL2. CTL1 and GND VDD 1.0 VREFIN x (5/3)
CTL2 are trilevel inputs: VDD, unconnected, and GND. Unconnected GND 1.2 VREFIN x 2
An 8.06kΩ resistor must be connected between VOUT
Unconnected Unconnected 1.5 VREFIN x 2.5
and FB when CTL1 and CTL2 are connected to GND.
The logic states of CTL1 and CTL2 should be pro- Unconnected VDD 1.8 VREFIN x 3
grammed only before power-up. Once the part is VDD GND 2.0 VREFIN x (10/3)
enabled, CTL1 and CTL2 should not be changed. If the VDD Unconnected 2.5 VREFIN x (25/6)
output voltage needs to be reprogrammed, cycle
*Install an 8.06kΩ resistor at R3 and do not install a resistor at R4.
power or EN and reprogram before enabling. The out-
put voltage can be programmed continuously from **Install R3 and R4 following the equation in the Compensation
Design section (see Figure 3a).
0.6V to 90% of VIN by using a resistor-divider network
from VOUT to FB to GND as shown in Figure 3a. CTL1
and CTL2 must be connected to GND.
Inductor Selection
Shutdown Mode Choose an inductor with the following equation:
Drive EN to GND to shut down the IC and reduce quies-
cent current to a typical value of 10µA. During shutdown, VOUT × (VIN − VOUT )
the LX is high impedance. Drive EN high to enable the L=
fS × VIN × LIR × IOUT(MAX)
MAX15038.
where LIR is the ratio of the inductor ripple current to full
Thermal Protection load current at the minimum duty cycle. Choose LIR
Thermal-overload protection limits total power dissipation
between 20% to 40% for best performance and stability.
in the device. When the junction temperature exceeds
TJ = +165°C, a thermal sensor forces the device into Use an inductor with the lowest possible DC resistance
shutdown, allowing the die to cool. The thermal sensor that fits in the allotted dimensions. Powdered iron ferrite
turns the device on again after the junction temperature core types are often the best choice for performance.
cools by 20°C, causing a pulsed output during continu- With any core material, the core must be large enough
ous overload conditions. The soft-start sequence begins not to saturate at the current limit of the MAX15038.
after recovery from a thermal-shutdown condition.
Output-Capacitor Selection
Applications Information The key selection parameters for the output capacitor
are capacitance, ESR, ESL, and voltage-rating require-
IN and VDD Decoupling ments. These affect the overall stability, output ripple
To decrease the noise effects due to the high switching voltage, and transient response of the DC-DC convert-
frequency and maximize the output accuracy of er. The output ripple occurs due to variations in the
the MAX15038, decouple IN with a 22µF capacitor from charge stored in the output capacitor, the voltage drop
IN to PGND. Also, decouple V DD with a 2.2µF due to the capacitor’s ESR, and the voltage drop due to
low-ESR ceramic capacitor from VDD to GND. Place the capacitor’s ESL. Estimate the output-voltage ripple
these capacitors as close as possible to the IC. due to the output capacitance, ESR, and ESL:
VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL)

______________________________________________________________________________________ 13
 4A, 2MHz Step-Down Regulator
with Integrated Switches
where the output ripple due to output capacitance, where VIN-RIPPLE is the maximum allowed input ripple
MAX15038

ESR, and ESL is: voltage across the input capacitors and is recommended
IP −P to be less than 2% of the minimum input voltage. D is
VRIPPLE(C) = the duty cycle (VOUT/VIN) and TS is the switching peri-
8 x COUT x fS od (1/fS).
VRIPPLE(ESR) = IP −P x ESR The impedance of the input capacitor at the switching
frequency should be less than that of the input source so
I high-frequency switching currents do not pass through
VRIPPLE(ESL) = P −P x ESL the input source, but are instead shunted through the
tON
input capacitor. The input capacitor must meet the ripple
or: current requirement imposed by the switching currents.
I The RMS input ripple current is given by:
VRIPPLE(ESL) = P −P x ESL
tOFF
or whichever is larger. VOUT × (VIN − VOUT )
IRIPPLE = ILOAD ×
The peak-to-peak inductor current (IP-P) is: VIN

VIN − VOUT V where IRIPPLE is the input RMS ripple current.

IP −P = x OUT
fS × L VIN Compensation Design
The power transfer function consists of one double pole
Use these equations for initial output capacitor selec-
and one zero. The double pole is introduced by the
tion. Determine final values by testing a prototype or an
inductor L and the output capacitor CO. The ESR of the
evaluation circuit. A smaller ripple current results in less
output capacitor determines the zero. The double pole
output-voltage ripple. Since the inductor ripple current
and zero frequencies are given as follows:
is a factor of the inductor value, the output-voltage rip-
ple decreases with larger inductance. Use ceramic 1
capacitors for low ESR and low ESL at the switching fP1_ LC = fP2 _ LC =
⎛ R + ESR ⎞
frequency of the converter. The ripple voltage due to 2π x L x C O x ⎜ O ⎟
ESL is negligible when using ceramic capacitors. ⎝ R O + RL ⎠
Load-transient response depends on the selected out- 1
put capacitance. During a load transient, the output f Z _ ESR =
instantly changes by ESR x ΔILOAD. Before the con- 2π x ESR x C O
troller can respond, the output deviates further, where RL is equal to the sum of the output inductor’s DCR
depending on the inductor and output capacitor val- (DC resistance) and the internal switch resistance,
ues. After a short time, the controller responds by regu- RDS(ON). A typical value for RDS(ON) is 24mΩ (low-side
lating the output voltage back to its predetermined MOSFET) and 31mΩ (high-side MOSFET). RO is the out-
value. The controller response time depends on the put load resistance, which is equal to the rated output
closed-loop bandwidth. A higher bandwidth yields a voltage divided by the rated output current. ESR is the
faster response time, preventing the output from deviat- total equivalent series resistance of the output capacitor.
ing further from its regulating value. See the Compen- If there is more than one output capacitor of the same
sation Design section for more details. type in parallel, the value of the ESR in the above equa-
tion is equal to that of the ESR of a single output capacitor
Input-Capacitor Selection divided by the total number of output capacitors.
The input capacitor reduces the current peaks drawn
from the input power supply and reduces switching The high switching frequency range of the MAX15038
noise in the IC. The total input capacitance must be allows the use of ceramic output capacitors. Since the
equal or greater than the value given by the following ESR of ceramic capacitors is typically very low, the fre-
equation to keep the input-ripple voltage within quency of the associated transfer function zero is higher
specification and minimize the high-frequency ripple than the unity-gain crossover frequency, fC, and the zero
current being fed back to the input source: cannot be used to compensate for the double pole creat-
ed by the output filtering inductor and capacitor. The dou-
D x TS x IOUT ble pole produces a gain drop of 40dB/decade and a
CIN _ MIN = phase shift of 180°. The compensation network error
VIN − RIPPLE

14 ______________________________________________________________________________________
 4A, 2MHz Step-Down Regulator
with Integrated Switches
amplifier must compensate for this gain drop and phase The above equations are based on the assumptions

MAX15038
shift to achieve a stable high-bandwidth closed-loop sys- that C1 >> C2 and R3 >> R2 are true in most applica-
tem. Therefore, use type III compensation as shown in tions. Placements of these poles and zeros are deter-
Figures 3 and 4. Type III compensation possesses three mined by the frequencies of the double pole and ESR
poles and two zeros with the first pole, fP1_EA, located at zero of the power transfer function. It is also a function
zero frequency (DC). Locations of other poles and zeros of the desired close-loop bandwidth. The following sec-
of the type III compensation are given by: tion outlines the step-by-step design procedure to cal-
1 culate the required compensation components for the
f Z1_ EA = MAX15038. When the output voltage of the MAX15038
2π × R1 × C1 is programmed to a preset voltage, R3 is internal to the
1 IC and R4 does not exist (Figure 3b).
f Z2 _ EA = When externally programming the MAX15038
2π × R3 × C3
(Figure 3a), the output voltage is determined by:
1
fP3 _ EA = 0.6 × R3
2π × R1 × C2 R4 = (for VOUT > 0.6V)
( VOUT - 0.6)
1
fP2 _ EA =
2π × R2 × C3 or:
(VREFIN × R3)
R4 =
( VOUT - VREFIN )
L VOUT
LX if using an external VREFIN, and VOUT > VREFIN.
COUT For a 0.6V output or for VOUT = VREFIN, connect an
R2
MAX15038 R3 8.06kΩ resistor from FB to VOUT. The zero-cross fre-
OUT quency of the close-loop, fC, should be between 10%
C3
and 20% of the switching frequency, fS. A higher zero-
FB
CTL1 cross frequency results in faster transient response.
R1 C1
Once fC is chosen, C1 is calculated from the following
CTL2 COMP R4
equation:
C2
VIN
1.5625 ×
VP −P
a) EXTERNAL RESISTIVE DIVIDER C1 =
R
2 × π × fC × R3 × (1 + L )
RO
L VOUT
LX
where VP-P is the ramp peak-to-peak voltage (1V typ).
COUT
Due to the underdamped nature of the output LC double
MAX15038 R2
pole, set the two zero frequencies of the type III compen-
OUT sation less than the LC double-pole frequency to provide
adequate phase boost. Set the two zero frequencies to
R3 80% of the LC double-pole frequency. Hence:
8kΩ
C3
1 L x C O x (R O + ESR)
R1 = x
FB
R1 C1 0. 8 x C1 RL + R O
VOLTAGE CTL1
COMP
SELECT
CTL2
C2 1 L x C O x (R O + ESR)
C3 = x
0. 8 x R3 RL + R O
b) INTERNAL PRESET VOLTAGES
Setting the second compensation pole, f P2_EA , at
fZ_ESR yields:
Figure 3. Type III Compensation Network

______________________________________________________________________________________ 15
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Table 2. Mode Selection
MAX15038

C O x ESR
R2 =
C3 MODE CONNECTION OPERATION MODE
Set the third compensation pole at 1/2 of the switching GND Forced PWM
frequency. Calculate C2 as follows: Forced PWM. Soft-startup into a
1 Unconnected or VDD/2 prebiased output (monotonic
C2 =
π × R1 × fS startup).

The above equations provide application compensation Skip Mode. Soft-startup into a
when the zero-cross frequency is significantly higher VDD prebiased output (monotonic
than the double-pole frequency. When the zero-cross startup).
frequency is near the double-pole frequency, the actual
zero-cross frequency is higher than the calculated fre-
quency. In this case, lowering the value of R1 reduces
COMPENSATION OPEN-LOOP
the zero-cross frequency. Also, set the third pole of the TRANSFER GAIN
type III compensation close to the switching frequency FUNCTION
if the zero-cross frequency is above 200kHz to boost THIRD
the phase margin. The recommended range for R3 is DOUBLE POLE POLE
2kΩ to 10kΩ. Note that the loop compensation remains
unchanged if only R4’s resistance is altered to set dif- GAIN (dB)
ferent outputs. SECOND
POWER-STAGE
POLE
MODE Selection TRANSFER
FUNCTION
The MAX15038 features a mode selection input
(MODE) that users can select a functional mode for the FIRST AND SECOND ZEROS
device (see Table 2).
Forced-PWM Mode Figure 4. Type III Compensation Illustration
Connect MODE to GND to select forced-PWM mode. In
forced-PWM mode, the MAX15038 operates at a con-
stant switching frequency (set by the resistor at FREQ Soft-Starting into a Prebiased Output
terminal) with no pulse skipping. PWM operation starts Mode (Monotonic Startup)
after a brief settling time when EN goes high. The low- When MODE is left unconnected or biased to VDD/2, the
side switch turns on first, charging the bootstrap capaci- MAX15038 soft-starts into a prebiased output without dis-
tor to provide the gate-drive voltage for the high-side charging the output capacitor. This type of operation is
switch. The low-side switch turns off either at the end of also termed monotonic startup. See the Starting Into
the clock period or once the low-side switch sinks Prebiased Output waveforms in the Typical Operating
0.875A current (typ), whichever occurs first. If the low- Characteristics section for an example.
side switch is turned off before the end of the clock peri- In monotonic startup mode, both low-side and high-
od, the high-side switch is turned on for the remaining side switches remain off to avoid discharging the prebi-
part of the time interval until the inductor current reaches ased output. PWM operation starts when the FB voltage
0.58A, or the end of clock cycle is encountered. crosses the SS voltage. As in forced-PWM mode, the
Starting from the first PWM activity, the sink current PWM activity starts with the low-side switch turning on
threshold is increased through an internal 4-step DAC first to build the bootstrap capacitor charge.
to reach the current limit of 7A after 128 clock periods. The MAX15038 is also able to start into prebiased with
This is done to help a smooth recovery of the regulated the output above the nominal set point without abruptly
voltage even in case of accidental prebiased output in discharging the output, thanks to the sink current con-
spite of the initial forced-PWM mode selection. trol of the low-side switch through a 4-step DAC in 128
clock cycles. Monotonic startup mode automatically
switches to forced-PWM mode 4096 clock cycles delay

16 ______________________________________________________________________________________
 4A, 2MHz Step-Down Regulator
with Integrated Switches
after the voltage at FB increases above 92.5% of Changing from skip mode to forced-PWM mode and

MAX15038
VREFIN. The additional delay prevents an early transi- vice-versa can be done at any time. The output capaci-
tion from monotonic startup to forced-PWM mode dur- tor should be large enough to limit the output-voltage
ing soft-start when a prolonged time constant external overshoot/undershoot due to the settling times to reach
REFIN voltage is applied. different duty-cycle set points corresponding to forced-
The maximum allowed soft-start time is 2ms when an PWM mode and skip mode at light loads.
external reference is applied at REFIN in the case of PCB Layout Considerations and
starting up into prebiased output. Thermal Performance
Skip Mode Careful PCB layout is critical to achieve clean and sta-
Connect MODE to VDD to select skip mode. In skip ble operation. It is highly recommended to duplicate the
mode, the MAX15038 switches only as necessary to MAX15038 EV kit layout for optimum performance. If devi-
maintain the output at light loads (not capable of sinking ation is necessary, follow these guidelines for good PCB
current from the output), but still operates with fixed-fre- layout:
quency (set by the resistor at FREQ terminal) PWM at 1) Connect input and output capacitors to the power
medium and heavy loads. This maximizes light-load effi- ground plane; connect all other capacitors to the sig-
ciency and reduces the input quiescent current. nal ground plane.
In case of prolonged high-side idle activity (beyond 2) Place capacitors on VDD, IN, and SS as close as pos-
eight clock cycles), the low-side switch is turned on sible to the IC and its corresponding pin using direct
briefly to rebuild the charge lost in the bootstrap capac- traces. Keep power ground plane (connected to
itor before the next on-cycle of the high-side switch. PGND) and signal ground plane (connected to GND)
In skip mode, the low-side switch is turned off when the separate.
inductor current decreases to 0.2A (typ) to ensure no 3) Keep the high-current paths as short and wide as
reverse current flowing from the output capacitor and possible. Keep the path of switching current short
the best conversion efficiency/minimum supply current. and minimize the loop area formed by LX, the out-
The high-side switch minimum on-time is controlled to put capacitors, and the input capacitors.
guarantee that 0.58A current is reached to avoid high 4) Connect IN, LX, and PGND separately to a large
frequency bursts at no load conditions and that might copper area to help cool the IC to further improve
cause a rapid increase of the supply current caused by efficiency and long-term reliability.
additional switching losses. 5) Ensure all feedback connections are short and
Even if skip mode is selected at the device turn-on, the direct. Place the feedback resistors and compensa-
monotonic startup mode is internally selected during tion components as close as possible to the IC.
soft-start. The transition to skip mode is automatically 6) Route high-speed switching nodes, such as LX,
achieved 4096 clock cycles after the voltage at FB away from sensitive analog areas (FB, COMP).
increases above 92.5% of VREFIN.

______________________________________________________________________________________ 17
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Pin Configuration Chip Information
MAX15038

PROCESS: BiCMOS
TOP VIEW
PGND

PGND

BST
LX
LX

LX
18 17 16 15 14 13 Package Information
PGND 19 12 PWRGD For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
PGND 20 11 FREQ
“-” in the package code indicates RoHS status only. Package
IN 21 10 OUT drawings may show a different suffix character, but the drawing
IN 22 MAX15038 FB
pertains to the package regardless of RoHS status.
9
IN 23 8 COMP PACKAGE PACKAGE OUTLINE LAND
EP TYPE CODE NO. PATTERN NO.
EN 24 7 GND
+ 24 TQFN-EP T2444+4 21-0139 90-0022
1 2 3 4 5 6
MODE

VDD

CTL1
CTL2

REFIN

SS

THIN QFN

18 ______________________________________________________________________________________
 4A, 2MHz Step-Down Regulator
with Integrated Switches
Revision History

MAX15038
REVISION REVISION PAGES
DESCRIPTION
NUMBER DATE CHANGED
0 10/08 Initial release —
1 12/09 Updated the Typical Operating Characteristics 5
Updated the Electrical Characteristics table, Table 1, and updated the Compensation
2 5/10 3, 13, 15
Design section
3 12/10 Corrected the C1 equation in the Compensation Design section (changed 2.5 to 1.5625) 15

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implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

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