TM

The Verification IP Specialist

PCIe Gen4 Verification IP

Truechip's PCIe Gen4 Verification IP provides an Deliverables

effective & efficient way to verify the components Ø PCIe Gen4 Root-Complex/Device-Endpoint
interfacing with PCIe Gen4 interface of an IP or SoC Ø PCIe Gen4 BFM/Agents for :
l PHY Layer
Truechip's PCIe Gen4 VIP is fully compliant with l Data Link Layer
latest PCI Express Gen4 specifications. This VIP is a l Transaction Layer
light weight with an easy plug-and-play interface so l Register Space
that there is no hit on the design cycle time. Ø PCIe Gen4 Layered Monitor and Scoreboard
Key Benefits Ø Test Environment & Test Suite :
l Basic and Directed Protocol Tests
Ø Available in native SystemVerilog
l Random Tests
(UVM/OVM/VMM) and Verilog
l Error Scenario Tests
Ø Unique development methodology to
l Assertions & Cover Point Tests
ensure highest levels of quality
l Compliance Tests
Ø 24X5 customer support
Ø Unique and customizable licensing models Ø Integration Guide, User Manual and Release Notes
Ø Exhaustive set of assertions and cover Features
points with connectivity example for all the Ø Compliant with PCI Express Specifications 4.0 v1.0 (16GT/s), 3.0
components (8GT/s), 2.0 (5GT/s) and 1.1 (2.5GT/s).
Ø Consistency of interface, installation, Ø Verification IP configurable as PCI express Root Complex and
operation and documentation across all our Device Endpoint.
VIPs Ø Configurable LinkWidth: x1, x2, x4, x8, x12, x16, x32.
Ø Provide complete solution and easy Ø Configurable pipe width : 8,16,32,64
integration in IP and SoC environment.​ Ø Supports Low Power management LTSSM states - L0s, L1, L2, L1
sub states,PCI- PM, ASPM.
Ø Advanced Error Reporting (AER) with optional Malformed TLP checks,
PCIe Verification IP Testbench
ECRC and TLP Poisoning support.
PCIe - Scoreboard Ø Compliance testing in TL, DLL & PL including power management
test-suites.
PCIe Root Complex BFM/ DUT PCIe Device Endpoint BFM/ DUT
Ø On the fly protocol checking using protocol check functions, static
PCIe – Bus Monitor
Root Complex-
Sequences Sequences
Device Endpoint -
and dynamic assertion.
Agent
Assertions Agent
Ø Built in Coverage analysis.
Root Complex–
Sequencer BFM / DUT
Coverage Monitor
Device Endpoint-
BFM / DUT Sequencer Ø Provides a comprehensive user API (callbacks).
Register Map
TL Layer TL Layer Ø Graphical ​analyser for all three Layers to show PCIe transactions for
Register Map
TLChecker
easy debugging.
DL Layer
Config Driver
DLChecker
DL Layer
Config Driver Ø Complaint with Pipe specification 4.4.1.
PHY Layer PHY Layer
Ø Supports scale flow control.
Data Driver
Data Driver PHYChecker
Ø Supports simplified replay timer.
Ø Supports SR-IOV.
RX TX TX RX Ø Supports lane margining feature.
Ø Supports 10-bit Tag as requester as well as completer.
Ø Support for ATS with latest ATS Specification revision 1.1.
Ø Supports LTR.
Ø Supports FLR ( Function Level Reset).

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