PHYSICS 325 (Digital Electronics II)

TOPICS TO BE COVERED
1. Review of Digital Circuits and Systems
2. IC Logic families and their Properties
3. Flip Flops
4. Types of flip flops
5. Counters
6. Registers and Memory Circuits
7. Switches
8. Timers and Timing circuits

IMPORTANT NOTES:
*** The lecture material given (Electronic format) at the end of the class is an abridged version of what was
taught in Class and should only be used for reference purposes (it doesn’t contain solution practice questions).
***Questions related to the course taught that could not be addressed in class should be sent to the lecturer via
the course rep in written format. A solution in jpeg or pdf format will be sent back through the class rep within 2
to 3 days and will be solved for all at a fixed class before exam.

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REVIEW OF DIGITAL CIRCUITS AND SYSTEMS
Digital system are systems composed of digital circuits that symbolizes their associated quantities using
discretely packaged values that are well defined. Digital systems are not generally more accurate or efficient than
analog systems. Nevertheless, Digital systems are easier to work. On the flip side, digital systems do not support
real time symbolization because quantities have to be digitally processed before they are symbolized as opposed
to direct symbolization in analog systems. With recent technology advances, the gap in real time synchronization
has been extremely narrowed down.
Boolean Algebra and Logic gates
The Boolean algebra which is the switching algebra or operation based on logic was developed by George Boole.
This type of algebra makes use of the logic statements which are either true or false based on human reasoning.
Logic operations
Logic operations are carried out using logic operators the most basic of which are the AND, OR and NOT
Boolean operators. Other operators such as the NOR (which is basically a combination of the OR and NOT
operators), the NAND, etc. can be constructed using these basic operators. These operators are often referred to
as gates. The truth table gives the outcome of every possible input combination acted upon by the operator.
Figure 1.0 shows the basic symbols for the available Logic gates, their symbols, truth table, and the their
respective De Morgan’s representations.
Combinational and Sequential logic circuits
Combinational circuits are networks of logic gates having input variables that are completely independent of the
logic gate, and outputs values that are the Boolean functions of inputs. In these circuits the independent input
variables are obtained from other systems connected to the digital system. The output variables in these circuits
depend only on the present value of the inputs and thus do not the use of require memory elements. They include
Adders and subtractors, multiplexers, decoders and encoders, etc.
Sequential logic circuits on the other hand are classes of the switching circuits with memory elements in addition
to the input and output variables. They do not only rely on the current values of the input signals but consider
their respective previous states (old state) in determining the value of the output signal. They include counters,
flip flops, registers and memory elements.

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 LOGIC OPERATION SYMBOL TRUTH TABLE

Figure 1.0: Various Logic gates, their symbols and truth tables
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LOGIC FAMILIES
Logic circuits are based on logic gates such as the AND, NAND and OR gates. This circuits are the heart of
digital systems and perform several functions in them (mostly data manipulation). Logic circuits can be
implemented in several different ways using a combination of various electrical components such as resistors and
semiconductor switches such as diodes, transistors, metal oxide FETs, etc.
For example, the AND gate can be implemented using a combination of two diodes and two resistors as shown in
Fig 1.1 below;

Fig 1.1: AND gate using diodes and resistors

In this configuration, the two reversed biased diodes serves as gate inputs and the resistors serve as pull up and
pull down resistors. When the inputs of the system are both low, both diodes conducts through the pull up
resistor and the output is low (via the pull down resistor). If one of the input is high, the diode on the high input
doesn’t conduct but the other conducts and the output is low. When both inputs are high, both diodes do not
conduct and the output is high via the pull up resistor. This relationship corresponds to the truth table of the AND
gate.
The same can be done for the OR gate sing forward biased diodes and a pull down resistor. It can be seen that a
combination of just resistors and diodes can be used to implement a crude OR and AND gate logic circuit. If
more gates can be implemented using this approach, we have a logic family.
In recent times, the knowledge of semiconductor fabrication has increased and several gates can be integrated in
a small package to give us a digital integrated circuit (IC). A logic family refers to the fundamental component
combination approach employed in the production of a digital integrated circuit.
Integration of digital circuits has improved greatly over the past years giving rise to several types of integrated
circuits. These integrated circuits are classified based on their level of integration as follows;
1. Small Scale Integrated Circuits (SSI): Chips in this category have up to twelve (12) gates per IC and
the total number of components per chip is less than 100.
2. Medium Scale Integrated Circuits (MSI): ICs in this group contain 12 to 100 gates per IC and total
number of components per IC is from 100 to 1,000.
3. Large Scale Integrated Circuits (LSI): Chips in this category contain from 100 to 1,000 gates per IC
and number of components is 1,000 to 10,000 per IC.
4. Very Large Scale Integrated Circuits (LSI): These ICs contain more than 1,000 and less than 10,000
gates per IC and total number of components per chip is from 10,000 to 100,000.
5. Ultra Large Scale Integrated Circuits (LSI): For chips in this category, more than 10,000 gates are
fabricated contained in an IC and total components count is more than 100,000 per chip.
IC Logic families are classified into two major categories based on the semiconductor technology used in
fabricating them. They are
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 1. Bipolar Logic families (Families that uses active devices with bipolar conducting channels NPN, PNP)
2. Unipolar Logic families (Families that use active devices with unipolar conducting channel n-Channel)
The bipolar Logic families are mainly of two categories;
1. Saturated bipolar Logic families: This is made up of the logic families in which the transistors are driven
to saturation (very close to the supply voltages). Logic families in this categories are
1. Resistor – Transistor Logic (RTL)
2. Direct Coupled Transistor Logic (DCTL)
3. Diode – Transistor Logic (DTL)
4. Integrated Injection Logic (IIL or I2L)
5. High Threshold Logic (HTL)
6. Transistor – Transistor Logic (TTL)
2. Non saturated bipolar logic families: The bipolar logic families in this category avoid saturating the
transistor. Logic families in this category are;
1. Schottky Transistor – Transistor Logic (STTL)
2. Emitter Coupled Logic (ECL)
The Unipolar Logic families consists of the MOS (metal Oxide Semiconductor) based IC logic families which
are;
1. NMOS or PMOS Logic
2. CMOS (Complementary MOS) logic.

General Characteristics (Properties) of Logic families

The following parameters are the general parameters used in characterizing the various IC logic families. This
parameters are handy in comparing their performances.
1. Fan in: This is the number of digital inputs that can be applied to a logic gate. A 3 – Input NAND gate has a
fan in of 3.
2. Fan – Out: This is the number of digital inputs the output of a logic gate can drive without signal degradation.
A logic gate with a fan-out of 10 can drive up to 10 separate logic input.
3. HIGH-level input voltage, (VIH): This is the minimum voltage level that needs to be applied at the input to
be recognized as a legal HIGH level for the specified family. For the standard TTL family, a 2 V input voltage
is a legal HIGH logic state.
4. LOW-level input voltage, (VIL): This is the maximum voltage level applied at the input that is recognized as
a legal LOW level for the specified family. For the standard TTL family, an input voltage of 0.8 V is a legal
LOW logic state.
5. HIGH-level output voltage, (VOH): This is the minimum voltage on the output pin of a logic function when
the input conditions establish logic HIGH at the output for the specified family. In the case of the standard
TTL family of devices, the HIGH level output voltage can be as low as 2.4V and still be treated as a legal
HIGH logic state. It may be mentioned here that, for a given logic family, the (V OH) specification is always
greater than the (VIH) specification to ensure output-to-input compatibility when the output of one device feeds
the input of another.
6. LOW-level output voltage, (VOL): This is the maximum voltage on the output pin of a logic function when
the input conditions establish logic LOW at the output for the specified family. In the case of the standard
TTL family of devices, the LOW-level output voltage can be as high as 0.4V and still be treated as a legal

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 LOW logic state. It may be mentioned here that, for a given logic family, the (V OL) specification is always
smaller than the (VIL) specification to ensure output-to-input compatibility when the output of one device
feeds the input of another.
7. Rise time, (tr): This is the time that elapses between 10 and 90 % of the final signal level when the signal is
making a transition from logic LOW to logic HIGH.
8. Fall time, (tf): This is the time that elapses between 90 and 10 % of the signal level when it is making HIGH
to LOW transition.
9. Propagation Delay Time (tpd): The propagation delay time of a gate is defined as the time interval between
the application of the inputs to a gate and appearance of the signal at the output of the gate. In other words it is
defined as the time interval between a change in input state and the resulting change in output state of the gate.
This delay is a very small quantity; it is of the order of few nano second say 20 nsec (20x10 -9 sec) or 50 nsec
(50x10-9 sec). The propagation delay of the gate also specifies the speed of the logic gate. The delay time is
measured between 50% voltage levels of input and output waveforms. Figure 7.4 shows the input and output
waveforms of an inverter. If tPHL is the delay time when the output goes from low state (logic 0) to high state
(logic 1) and tPLH is the delay time when the output goes from high state (logic 1) to low state (logic 0), the
propagation delay time of the gate tpd expressed as the average of the two delays i.e. (t pHL +t pLH )/2

Fig 1.2: Graph of Propagation delay time showing tpHL and tpLH
10. Power Dissipation: It is defined as the amount of power that can be dissipated in an IC. It is calculated as the
product of the d.c voltage applied to an IC and the current drawn from the d.c. source. It is always desirable to
have low power dissipation per gate. The normal working power per gate is required from few micro-watts to
few milli-watts. The product of speed and power dissipation per gate is known as the figure of merit of the
logic family. A low value of this product is desirable.
11. Operating Temperature: The temperature range in which an IC functions properly is known as the operating
temperature of the gate. It is specified by the manufacturer. The acceptable temperature range of the ICs is
from 0 to +70 degrees for commercial applications and this range is from – 55 0C to 125 degrees for military
purposes.
12. Noise Margin: Spurious signals called noise are sometimes generated in the connecting leads of the logic
circuits due to the stray electric and magnetic fields in the surroundings. This results the unpredictable
operation of the logic circuit. The noise margin is sometimes called Noise- immunity. It is defined as the
difference between the maximum permitted low input and the maximum guaranteed low output, and that
between the minimum permitted high input and the minimum guaranteed high output.

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 As per definition of the noise margin, the noise margin for high state (VNH) and the noise margin for low state
(VNL) are given by:
VNH = VOH(min) – VIH(min)
VNL = VOL(max) – VIL(max)
The large noise margin is always desirable.
THE VARIOUS IC LOGIC FAMILIES
In this section, we discuss each of the logic family mentioned above earlier.
1. Resistor – Transistor Logic (RTL): this logic family contains digital logic circuits built with resistors and
transistors. It was the first logic family to be developed and fabricated as an IC and it dates back to the 1960s.
The circuit configuration required for logic implementation is simple regardless, the family is now obsolete.
RTL has the advantage of small power dissipation per gate also has the following disadvantages. 1. Low noise
margin (around 0.1 V) 2. Poor fan out, 3. Low speed of operation and high propagation delay.
2. Direct Coupled Transistor Logic (DCTL): This logic family is a direct integration of the RTL family. The
only difference is that in this family, the base resistors of the gate transistors are removed and the input is
directly coupled to the transistor. The circuit configuration for the DCTL is simpler than that of the RTL but it
wasn’t widely accepted because of its current hogging problem (This is a phenomenon whereby due to
manufacturer’s tolerance issues, one of the transistors on the output stage with the smallest base voltage
requirement reaches saturation before other transistors and hog all the current and prevent other transistors
from reaching saturation).
3. Diode – Transistor Logic (DTL): This logic family followed the RTL family. The circuitry was made using
diodes and Transistors. It was able to achieve high noise margin but has a relatively slow speed due to the
recovery time of the diodes used. The diagram below shows the positive logic of a two (2) input NAND gate.

Fig 1.3: DTL NAND gate configuration

It can be see that when both inputs are at logic 0, the two input diodes are forward biased and the voltage at
the test point is equal to the voltage drop of the diodes. At this point, the pull down resistor kicks in and the
transistor is cutoff and the output is high. The same thing happens for when either of the input is low. When
both inputs are high, the voltage at the test point is high is high and the transistor saturates bringing the output
low. The propagation delay of this logic circuit is around 50ns which is high.
4. High Threshold Logic (HTL): This logic is a variation of the DTL family. It was designed for industrial
applications and provides a very high noise margin. This is because a zener diode which is capable of
dropping a higher value of voltage is employed in the input isolation stage. It can only work with high power
supply voltages and its only advantage is in its high noise margin.

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5. Integrated Injection Logic (IIL or I2L): This logic family makes use of only transistors. Thus, it is very
cheap to manufacture and several gates can be integrated in one package. They have a low power
consumption and a very reasonable switching speed but have a low figure of merit. Below is the configuration
of a positive two input NAND gate.

Fig 1.4: IIL or I2L NAND gate configuration

When both or either of the inputs are low, the current from the source is sunk by the low input(s) and the
output transistor is cut off. When both inputs are high, the current from T1 switches on T2 and it saturates,
bringing the output close to zero (0).
6. Transistor – Transistor Logic (TTL): TTL is the one of the most common and widely use IC technology
today. It is based on transistors which are operated either in the cut-off or saturation region. It is a
modification of DTL in which multi-emitters transistors (a transistor with more than one emitter) are used as
inputs in place of diodes which greatly reduce the propagation delay time of this logic family. Standard TTL
were the earliest type of TTL available and they are available in various forms which are
1. TTL with Passive pull-up
2. TTL with TOTEM pole output
3. TTL with Open collector output
4. Tri-state TTL
1. TTL with passive pull-up: in this type of circuit configuration, the output of the gate circuit is pulled up
using via a passive component (a resistor) i.e. while the output transistor is in the cut-off region, the
output is obtained via the collector transistor. Below is the diagram of the configuration of a two (2) input
NAND gate with passive pull-up

Fig 1.5: TTL with passive pull-up NAND gate configuration

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 In this configuration, when any or both of the input is low, transistor T2 is turned off and the output is
high. When both of the inputs are high, transistor T1 s turned on and driven into saturation making the
output low.

2. TTL with TOTEM pole output: In this configuration, two output transistors are used. The diagram
below shows the configuration of a two (2) input NAND gate.

Fig 1.6: TTL with TOTEM pole output NAND gate configuration
One of the output transistor is configured as an emitter follower and the other as a common emitter. When
the inputs are low, the lower transistor T4 is cut off and the transistor T3 conducts raising the output.
When both inputs are high, T3 conducts and the output is low. Using active pull up increases the speed of
this logic type as compared to passive pull-up.
3. TTL with Open collector output: TTL with TOTEM pole output has a drawback and this is that the
output of two TOTEM output TTL cannot be connected together directly as this will cause a short circuit.
The open collector TTL solves this problem and makes the AND-ing of the output of several gates
possible using only wires. After the connection, a single pull up resistor can be used for raising the output.
The main disadvantage of open collector output is their slow speed.
4. Tri-state TTL: The tri-state TTL provides adds an extra ‘enable’ input which introduces a high
impedance mode to the output of the gate. When the enable input is high, it doesn’t interfere with the
operation of the gate but when it is low, it puts the gate output in high impedance mode. This allows
TOTEM pole output TTL to be AND-ed with wires and this overcome the slow speed problem of the
Open collector TTL
The standard TTL chips are denoted with the prefix 74/54 with 74 indicating an operating range of 0 – 70
degrees and 54 indicating -25 to 125 degrees.
Improvements in semiconductor technology also brought about the introduction of newer modifications to TTL
chips. The several varieties are;
1. 74L/54L series which is the low power and (s)low speed series (typical power around 1 mW and 33ns
propagation delay time)

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 2. 74H/54H series which are the high power and high speed series (typical power around 22 mW and 6ns
propagation delay time)
3. 74F/54F series which are the fast TTL series.
7. Schottky Transistor – Transistor Logic (STTL): in this family of TTL, schottky transistors are used instead
of normal transistors. Schottky transistors because of the schottky barrier diode connected across the base and
collector, prevents the transistor from saturating and it is always operating in the active and cut-off region.
This makes circuit switching much faster because less time is used in going to and from active and cut –off
region. The 74S series is an example of STTL. It has a typical switching speed which doubles that of the 74
standard series even at the same power level.
From the TTL, other series of STTL were made using different techniques. It is important to note that the as
the speed of TTL logic circuits increases, its power consumption.
1. 74LS/54LS series – Low power, slow speed schottky series (which are obtained by increasing the
resistance used in the 74s series)
2. 74HS/54HS series – High power, high speed schottky series
3. 74AS/54AS series – Advanced schottky series
4. 74ALS/54ALS series – Low power slow speed advanced schottky series
5. 74AHS/54AHS series – High power, high speed, advanced schottky series
8. Emitter coupled Logic (ECL): This logic family is an example of unsaturated logic family in which the
transistor never goes into saturation but operates in the active and cut-off region eliminating storage time. This
family is faster than the TTL family and the have one of the best propagation delay time which is
approximately 1ns per gate. A major example of the implementation of this circuitry is in the ECL OR/NOR
gate which is a two output gate with an OR output as well as the inverted OR output. The input to this gate
circuit is usually a differential amplifier stage. This way, the switching transistor is always operated in the
active region making its switching time smaller. The output of several ECL chips can be connected together to
produce a wired AND logic output.
9. MOS Logic: This logic family make uses of unipolar semiconductor devices which is the metal oxide
semiconductor Field Effect Transistors. The MOS logic is very easy to fabricate and uses up less space. In
their fabrication, only MOSFETs which are either N-channel or P-channel are used. It is characterized by high
packing density, low power dissipation and high fan out. The MOS logic family can be classified into three
categories. They are;
i. NMOS Logic, ii. PMOS Logic and iii. (Complementary MOS) CMOS Logic.
The PMOS logic is considerably slower than the NMOS logic making it less used practically.
1. NMOS Logic: This logic family is based on the N-channel enhancement mode MOSFETs. This logic
families have high input impedance giving them a high fan out but their output capacitance also reduces the
speed of the gate when overloaded. The presence of input capacitance also slows down the speed of
operation and in turn reduces the power dissipation. Below is the configuration of a 3 input NAND gate
using NMOS logic. In the configuration, four (4) n-channel MOSFETs are connected in series and their
gate terminal serves as inputs.

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 Fig 1.7: NMOS NAND gate configuration
When any or all of the input is low, the MOSFETs are turned off since they require a positive voltage to
work and the output is high. When all of the input is high, the MOSFETs are turned on and the output is
low and the transistors sink current. The above is for positive logic. For negative logic, PMOS are
employed.
2. CMOS Logic: This logic family make use of both n-channel and p-channel MOSFETs. Here, both FETs
are fabricated on the same chip and this increases the complexity of the system. Also, it reduces it package
density because of the integral difficulties of p-channel fabrications but has an advantage of reduced power
consumption. This makes them ideal for battery operated systems. The CMOS gate can be operated on
wide range of supply voltage between 3 V to 15 V. It has good noise margin better than TTL devices, a
much larger Fan-out, and a speed comparable with that of TTL circuits but larger than Schottky TTL
circuits. The diagram below shows the configuration of a two (2) input CMOS NAND gate. In this
configuration, two p-channel MOS are connected in parallel and two n-channel MOS are connected in
series.

Fig 1.8: CMOS NAND gate configuration

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 When any or both inputs are low, since the gates of T1 and T2 require low voltage to turn them on, the
output is high via T1 and T2. At this point, FET T3 and T4 are turned off. When both inputs are high, T1
and T2 are turned off while T3 and T4 are turned on and the output is low.
Comparism between the various logic families
Based on their various characteristics, the properties of the logic families are compared in the table below;
Logic parameter RTL DTL TTL ECL MOS CMOS
MAX Fan-In 5 10 8 5 8 8
Fan-out 5 8 10 25 20 >50
Power dissipation/ 12 10 10 50 1 Around 0.01
gate (in mW) at 1 MHz
Propagation delay 20 30 12 4 400 70
per gate (ns)
Noise immunity Nominal Good Very Good Good Nominal Very good
Number of High Fairly High Very High High Fair Good
functions
Max Clock rate (in 5 12 15 300 2 5
MHz)

Interfacing logic families

Since these various families have different input and output specifications, interfacing them requires bringing
them to the levels at which they can work with each other as direct connection is not possible. This requires
driving or interface circuits. This interface circuit converts the input from the driver and converts it to levels
required by the load. In the interfacing of TTL and ECL, a translator is reqired.an example is the MC10H124
which is a TTL to ECL translator.

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