Digital Logic Design

CSCS-2522

Program ADP-CS

Credit Hours 2

Duration 16 Weeks / 32 sessions

Prerequisites N/A
Course Introduction

Digital Electronics is the foundation of Computers and Microprocessor based systems found
in automobiles, Embedded systems, Industrial Control systems, and home entertainment
systems. The material presented in this course is appropriate for Digital Logic and
Design as applied both in Computer Science and Computer Engineering. This course
has been designed in such a way that computer science students who do not have in depth
knowledge of digital Electronics will also be able to. Hands on training is given on self-designed
prototypes /Digital logic Trainers and latest SPICE (Virtual Electronics Lab). Participants will
be able to make digital circuits on self-designed modules like Adder, ALU, MUX, DEMUX,
Decoder, Encoder, RAM, ROM, Parity Checker and also display decimal digits on Seven Segment
Indicators or State Monitors.
Course Objective
 To introduce the basics of digital system.
 To make students understand, design, Simulate and Implement digital systems.
 To equip students with techniques to solve complex logical problems, design digital systems and
State Machine
Learning Outcomes
 To introduce the basics of digital system.

 To make students understand, design, Simulate and Implement digital systems.

 To equip students with techniques to solve complex logical problems, design digital systems and
State Machine

Violation of Academic Honesty Policy:

All the groups involved will be awarded Zero in first instance.

Repeat of the same offense will result in (F) grade.
Marks will be uploaded on portal and can be contested within a week or would be considered final.

How to Keep Your Professor Happy?

Class attendance is mandatory. You may miss up to 6 class sessions. On the seventh absence,
you will be withdrawn from the course. As a courtesy to the instructor and other students, be
prepared to arrive at class and be in your seat on time. In addition, please note that each class
lasts for 90 minutes.

Also keep in mind some general rules as given below:

 Cell phones should be powered off.

 Eatables are not allowed in the class.
 The teacher will not tolerate any disruptive behavior in the class.
 The Dress Code has to be observed, no warnings will be given, and violators will be
asked politely to leave the class and consequently will be marked absent.
Participation:
Students are required to attend all classes and read all the assigned material in advance of
class (although not necessarily with perfect comprehension). Advanced preparation and class
participation are crucial for periods in which we discuss cases. During discussion sessions,
the instructor generally keeps track of the insightful and useful comments students make.
(Any unproductive contribution is not rewarded)

Text book:

 Digital Fundamentals by Floyd 11th edition,

 Digital Logic and Computer Design by Morris Mano 3rd Edition

Reference books:

Null
 Calendar of Activities

Weeks Contents Activities

 Digital and Analog quantities, Signals

 Sampling using ADC&DAC, Binary digits, Logic Levels,
Digital waveforms
1  Introduction to Logic Gates, Truth tables for 2,3, and 4
inputs, Logic symbols, Boolean expressions, Fundamental
Gates AND, OR and NOT gates. Importance of XOR, XNOR
gates

 Boolean Variables, Boolean Algebra, Basic Theorems,

Laws and rules of Boolean algebra, Boolean Functions,
2  Complement of a function, Demorgan’s Theorems (Two,
Three variables)
 Logic Simplification using Boolean Algebra

 Min terms and Max terms, Sum of Product terms(SOP),

Product of Sum terms(POS), Conversion Between
3 Canonical/ Standard Forms. Assignment 1
 Boolean Minimization using Karnaugh Map up to 4
Variable for SOP and POS. Don’t Care Conditions
 Verification by using Binary Testing Techniques for
standard and Minimized form.
 Introduction to Number systems, Binary, Octal, Decimal
and Hexadecimal.
 Number system conversions,
 Octal to Binary, Octal to Decimal, Octal to Hexadecimal,
Hexadecimal to Binary, Hexadecimal to Decimal,
4 Quiz 1
Hexadecimal to Octal
 1’S complement, 2’S complement ,Binary addition, Binary
subtraction, Binary multiplication, Binary Division ,Digital
codes (ASCII, Binary Coded Decimal), BCD addition, Gray
Code, 4 Bit Binary to Gray code convertor,
Gray to Binary code converters by using XOR gates.
NAND & NOR as Universal gates, Implementation of
Combinational logic circuits using NAND or NOR gates
only.
Half –Adder combinational logic design, Full-Adder
5 combinational logic design and Expressions of Sum and
Carry in XOR,
 Implementation by using K-maps for Sigma and Carry
output.
  Half subtractor, Full subtractor, 4 Bit Parallel Binary
Adder, Controlled Inverter
Combinational logic design for Decoders Active High / Active
6 low Assignment 2
 2 lines to 4 lines decoder
 3 lines to 8 lines decoder
 4 lines to 16 lines decoder
 BCD to Decimal Decoder
 BCD to 7 Segment decoder with Table implementation.
Combinational logic design for Encoders
 4 lines to 2 lines encoder
 8 lines to 3 lines encoder
 16 lines to 4 lines encoder
 Decimal to BCD encoder (Key Pad)
 Priority Encoder (Morris Mano)
Example (Full adder implementation with decoder and OR gate)
7 Example (Importance of Encoders and Decoders in Digital
Quiz 2
communication systems)
Combinational logic design for Multiplexers (PISO)
 4 line to 1-line MUX or (1-Of-4 MUX)
 8 line to 1-line MUX or (1-Of-8 MUX)
 16 line to 1-line MUX or (1-Of-16 MUX)
 10 line to 1-line MUX or (1-Of-10 MUX)
 Canonical function implementation with MUX

 Combinational logic design for DE Multiplexers (SIPO).

 1 line to 4 lines DEMUX
 1 line to 8 lines DEMUX
 1 line to 16 line DEMUX
8  1 line to 10 line DEMUX
 Combinational logic implementation using MUX Folding
Technique & DEMUX with active high and active low enable
inputs
 Review
9th
Week MID TERM

 BCD Adder design, 2 bit, 3 bit and 4-bit Magnitude Comparator

design
10
 Sequential circuits, Function of Latch, SR latch using NAND
and NOR gates, Active high and active low latch design,

 SR Flip-Flop, D Flip-Flop, JK Flip-Flop and T Flip Flop, Clocking

11  Flip- Flop Applications (Counters, Frequency divider, Registers
Assignment 3
and Memory)

 Excitation tables for SR, JK, T and D Flip-Flops using their

12 characteristics tables Quiz 3
 Flip Flop conversions SR to D, JK to D
  Sequential logic design process, State diagram and State
tables, steps to design sequential circuit.
13
 4 Bit Up/Down Synchronous Counters design with clock
diagram
 4 Bit Asynchronous Counters design with clock diagram,
Up/Down and Auto reset operations using NAND gate
14 Assignment 4
(Truncated sequence)
 Design 2 bit,3 bit up-down counter with gray code
sequence,
 Registers, Serial in serial out, Serial in parallel out, Parallel
15 in serial out and parallel in Parallel out Quiz 4
 Write and Read Operations in memory, Sizes of Address
bus and Data bus,
 Design of Binary Cell using SR Flip Flop, Design of 4X4
16
and 8 X 8 RAM
 Review

17
FINAL TERM