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Adv. Computer Architecture CS701 - Jan 011

This document is the question paper for the 7th semester Advanced Computer Architecture exam for Computer Science and Engineering students. It covers 10 questions divided across 5 units: 1. Types of computers and their features, ISA dimensions, and performance calculations for different instruction types. 2. Changes in parallel computer technology, Amdahl's law, pipeline implementation and hazards. 3. Cache coherence protocols, directory protocol, and spin locks. 4. Cache performance, compiler optimizations, and process resource sharing. 5. RAID levels, faults vs errors vs failures, I/O response time balancing, power issues in storage, benchmarks, and EPIC architecture.

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Sachin Kumar Goyel
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134 views

Adv. Computer Architecture CS701 - Jan 011

This document is the question paper for the 7th semester Advanced Computer Architecture exam for Computer Science and Engineering students. It covers 10 questions divided across 5 units: 1. Types of computers and their features, ISA dimensions, and performance calculations for different instruction types. 2. Changes in parallel computer technology, Amdahl's law, pipeline implementation and hazards. 3. Cache coherence protocols, directory protocol, and spin locks. 4. Cache performance, compiler optimizations, and process resource sharing. 5. RAID levels, faults vs errors vs failures, I/O response time balancing, power issues in storage, benchmarks, and EPIC architecture.

Uploaded by

Sachin Kumar Goyel
Copyright
© Attribution Non-Commercial (BY-NC)
Available Formats
Download as PDF, TXT or read online on Scribd
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CS 70 1

USN
M

M S RAMAIAH INSTITUTE OF TECHNOLOGY


(AUTONOMOUS INSTITUTE, AFFILIATED TO VTU) BANGALORE - 560 054

SEMESTER END EXAMINATIONS - JANUARY 2011


Course & Branch : Subject : Subject Code : B.E. - Computer Science & Engineering Semester: VII Advanced Computer Architecture Max. Marks: 100 CS701 Duration: 3 Hrs

Instructions to the Candidates: Answer one full question from each unit Draw neat figures wherever necessary UNIT - I What are the important classes of computers? List their important features and differentiate them on the basis of system design issues. What is ISA? Illustrate the seven dimensions of ISA. Consider the execution of a bench mark code with 200,000 instructions on a 40MHz processor. The program consists of four major instruction types. The instruction mix and CPI needed are given below on the result of a trace experi
Instruction Type Arithmetic Load store Branch F.P. CPI 1 2 4 8 Instruction mix 60% 18% 12% 10%

1 a) b) C)

(06) (08) (06)

Calculate the average CPI and the CPU time for the above results. If the CPI of FP operations are reduced to 6, what will be the effect? Calculate the speed up. 2. a) What are the different changes in technology that have brought rapid (06) changes in parallel computers? Discuss bandwidth versus latency issue. b) State Amdahl's law. Suppose that we want to enhance the processor used (06) for web applications. The new processor is 10 times faster on computation in the web application than the original processor. Original processor is busy with computation 40% of time, waiting for I/O 60% of time, what is the overall speed up gained by the enhancement? c) Illustrate how every instruction in RISC subset can be implemented using a (08) pipeline. Briefly discuss the three classes of hazards.
UNIT - II

3. a) What are the different types of dependencies? Explain with examples. (06) b) How to overcome data hazards using dynamic scheduling? (08) Illustrate the information tables using Tomasulo algorithm for the given code sequence when the first two load instructions are completed i) L.D F6, 16(R2) ii) L.D F2, 32(R3) iii) MUL D FO, F2, F4 iv) SUB D F8, F2, F6 c) With a neat diagram, explain the Pentium 4 micro architecture. (06) 4. a) What is a data hazard? How are they classified? (05) b) Suppose we have a VLIW that could issue two memory references two FP (10) operations and one integer operation or branch in every clock cycle. Show an unrolled version of the loop x[i]=x[i]+S for the given MIPS code. Unroll as many times to eliminate all stalls, ignore delayed branch. Draw relevant figures.
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CS70i
c) List any five important characteristics of the recent Pentium implementation (05) in 90nm technology. UNIT - III 5. a) What is cache coherence? When is the memory system is said to be (04) coherent? b) Discuss the protocols used for cache coherence. Show the different states (12) with a' state diagram for a write invalidate cache coherence protocol for a write-back cache. c) What sources influence the coherence misses? Discuss. (04) 6. a) With a neat state transition diagram, explain the Directory Protocol. (08) b) What is a Spin Lock? Consider the following code. (06) DADDUI R2, R0, #1 lock-it: EXCH R2, 0(R1) BNEZ R2, lock-it Explain how this above code is used as spin lock. c) Show the organization of T1 processor. List its important features. (06) UNIT - IV 7. a) How a small and simple cache help the cache performance? The hit time of (06) a two way set associative cache is 1.1 times faster than four way set associative cache of the same size. The miss rate falls from 0.049 to 0.044 to 8KB cache. Hit is 1 clock cycle and miss penalty is 10 clock cycles to the L2 cache for two way cache and L2 cache does not miss. Which has the faster average memory access time? b) How compiler optimization can reduce miss rate? Consider the given loop (08) interchange in such a way that it reduces miss rate.
for (j=0; j<100; j=j++)

for (i=0; i<5000; i=i++) x[i][j]=2*x[i][j]; c) How the computer architecture facilitates sharing of hardware resources by (06) all processes? What is TLB? 8, a) How a critical word first and early restart reduces the miss penalty in a (03) cache? b) Write a brief note on the following (09) i) Protection and ISA ii) Speculative execution and memory system iii) I/O and consistency of cached data c) What are the requirements of a virtual machine monitor? (04) d) List the important components of memory of a AMD opteron processor. (04) UNIT - V 9. a) What is RAID? Summarize the fire standard RAID levels. (07) b) "A mistake by a human operator is a fault. The resulting altered data is an (06) error. It is latest until activated and leads to failure". Clarify the relation between faults, errors and failures. c) Show the typical response time of a I/O system. How does the architect (07) balance the demands? 10. a) Why power is an important issue in a disc storage system? (06) b) What are bench marks? What are the typical characteristics of a TPC bench (06) mark? c) Discuss the EPIC architecture in brief. (08)

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