Scribd
Upload
1 views

CSF201 Computer Organization & Architecture

Csf paper of my university

Uploaded by

purplehathacks
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
1 views

CSF201 Computer Organization & Architecture

Csf paper of my university

Uploaded by

purplehathacks
Copyright
© © All Rights Reserved
Available Formats
Download as PDF, TXT or read online on Scribd
You are on page 1/ 2

Paper Code: CSF201 Printed Page 1 of 2

DIT UNIVERSITY DEHRADUN


B.TECH (CSE) MIDTERM EXAMINATION,ODD SEM 2021-22 (SEMIII)
Roll No.
Subject Name: Computer Organization & Architecture
Time: 2 Hours Total Marks: 50
Note: All questions are compulsory. No student is allowed to leave the examination hall before the completion of the exam.
______________________________________________________________________________________________________
Q.1) Attempt all Parts:
A digital computer has a common bus system implemented with multiplexers for 16 registers of 16 bits each.
(i) What size of multiplexers is needed?
(a)
(ii) How many selections input is there in each multiplexer?
(iii) How many multiplexers are there in a bus?
Starting from an initial value of R= 11011101, determine the sequence of binary values in R; after a logical
(b)
shift-left, followed by a circular shift-right, followed by a logical shift-right and a circular shift-left.
(c) What is the difference between half-adder and full-adder?
The following two binary numbers are multiplied using the Booth’s algorithm.
Multiplicand:0101101011101110
(d)
Multiplier: 0111011110111101
Find the number of additions and Subtractions carried out in the multiplication process.
[4 x 2.5= 10]

Q.2) Attempt all Parts:


(a) Demonstrate a 4-bit combinational circuit decrementer using four full adder circuits.
A program is running on a specific machine (CPU) with following parameters:
 Total executed instruction counts: 10,000,00 instructions.
(b)  Average CPI for the program: 2.5 cycles/ instruction.
 CPU clock rate: 250 MHz
Evaluate the execution time for this program?
Draw a neat diagram using Multiplexers and Adders for 4-bit arithmetic operations and provide its function
(c)
table.
(d) Demonstrate a 4 Bit Shifting Circuit with 2 shifting operations i.e. cil & cir. Explain with a proper example.
[4 x 2.5= 10]

Q.3) Attempt any Two Parts:


Explain the basic functional Units of a computer system. What are the parameters used to defined the
(a)
performance of a computer?
(b) Demonstrate the number (0.625)10 in IEEE single precision (32 bits).
Demonstrate the algorithm in flowchart form for addition and subtraction of fixed-point binary numbers in
(c)
signed magnitude representation.
[2 x 5= 10]

Q.4) Attempt any Two Parts:


Explain the following terms in relevance of computer organizations:
i) Registers
(a) ii) Register transfer language
iii) Micro-operations
iv) Memory transfer
Demonstrate the Carry Look ahead Adder (i.e. Fast Adder) for the addition of two 4-bit Numbers (A: 0111
(b)
and B: 0110).
(c) Evaluate the results after dividing the number (1010)2 by (0011)2 with restoring division method.
[2 x 5= 10]
Paper Code: CSF201 Printed Page 2 of 2

Q.5) Attempt any Two Parts:


(a) Demonstrate the hardware implementation for 4-Bit Binary Adder- Subtractor.
The 8-bit registers A, B, C and D initially have the following values: A: 11110010, B: 11111111, C: 10111001,
D: 11101010. Determine the 8-bit values in each register after the execution of all the four sequence of
micro-operations (as mentioned below)
A←A+B
(b)
C←C˄D
B←B+1
A←A-C
*(˄: AND)
Explain the Booth’s Algorithm for multiplication operations with flowchart. Show the step-by-step
(c)
multiplication process using Booth's Algorithm when the numbers (+15) and (-6) are multiplied.
[2 x 5= 10]
-----END OF PAPER ----

You might also like