Chapter 5: Link layer

Chapter 5
our goals:
Link Layer  understand principles behind link layer
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services:
We’re making these slides freely available to all (faculty, students, readers).
They’re in PowerPoint form so you see the animations; and can add, modify,
 error detection, correction
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They obviously represent a lot of work on our part. In return for use, we only
 sharing a broadcast channel: multiple access
ask the following:
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Computer  link layer addressing

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Networking: A Top  local area networks: Ethernet, VLANs
from (or perhaps identical to) our slides, and note our copyright of this
material.
Down Approach  instantiation, implementation of various link
6th edition
Thanks and enjoy! JFK/KWR Jim Kurose, Keith Ross layer technologies
All material copyright 1996-2012 Addison-Wesley
J.F Kurose and K.W. Ross, All Rights Reserved
March 2012
The course notes are adapted for Bucknell’s CSCI 363
Xiannong Meng
Spring 2016
Link Layer 5-1 Link Layer 5-2

Link layer, LANs: outline Link layer: introduction

terminology:
5.1 introduction, services 5.5 link virtualization:  hosts and routers: nodes
5.2 error detection, MPLS  communication channels that global ISP

correction 5.6 data center connect adjacent nodes along

5.3 multiple access networking communication path: links
protocols 5.7 a day in the life of a  wired links
web request  wireless links
5.4 LANs
 LANs and WANs
 addressing, ARP
 layer-2 packet: frame,
 Ethernet encapsulates datagram
 switches
 VLANS data-link layer has responsibility of
transferring datagram from one node
to physically adjacent node over a link
Link Layer 5-3 Link Layer 5-4

Internet protocol stack Link layer: context

 application: supporting network transportation analogy:
applications  datagram transferred by
application different link protocols over  trip from Princeton to
 FTP, SMTP, HTTP different links: Lausanne
 transport: process-process data  e.g., Ethernet (802.3) on  limo: Princeton to JFK
transfer transport first link, frame relay on  plane: JFK to Geneva
 TCP, UDP intermediate links, 802.11  train: Geneva to Lausanne
network on last link tourist = datagram
 network: routing of datagrams 
from source to destination  each link protocol provides  transport vehicle =
link different services communication link
 IP, routing protocols
 e.g., may or may not transportation procedure =
 link: data transfer between physical provide rdt over link


neighboring network elements link layer protocol

 Ethernet, 802.11 (WiFi), PPP  travel agent = routing
algorithm
 physical: bits “on the wire”
Introduction 1-5 Link Layer 5-6

1
Link layer services Link layer services (more)
 framing, link access:  flow control:
 encapsulate datagram into frame, adding header, trailer  pacing between adjacent sending and receiving nodes
 channel access if shared medium
 “MAC” addresses used in frame headers to identify  error detection:
source, dest  errors caused by signal attenuation, noise.
 receiver detects presence of errors:
• different from IP address!
• signals sender for retransmission or drops frame
 reliable delivery between adjacent nodes
 we learned how to do this already (chapter 3)!  error correction:
 receiver identifies and corrects bit error(s) without resorting to
 seldom used on low bit-error link (fiber, some twisted retransmission
pair)
 wireless links: high error rates  half-duplex and full-duplex
• Q: why both link-level and end-to-end reliability?  with half duplex, nodes at both ends of link can transmit, but not
at same time

Link Layer 5-7 Link Layer 5-8

Where is the link layer implemented? Adaptors communicating

 in each and every host
 link layer implemented in
“adaptor” (a.k.a. network datagram datagram

interface card NIC) or on a controller controller

chip application
 Ethernet card, 802.11 transport
network cpu memory sending host receiving host
card; Ethernet chipset link
datagram

 implements link, physical host frame

layer controller
bus
(e.g., PCI)
 attaches into host’s system
link
physical
 sending side:  receiving side
buses
physical
transmission  encapsulates datagram in  looks for errors, rdt,
 combination of hardware, frame flow control, etc
software, firmware network adapter
card
 adds error checking bits,  extracts datagram, passes
rdt, flow control, etc. to upper layer at
receiving side
Link Layer 5-9 Link Layer 5-10

Link layer, LANs: outline Error detection

EDC= Error Detection and Correction bits (redundancy)
5.1 introduction, services 5.5 link virtualization: D = Data protected by error checking, may include header fields
5.2 error detection, MPLS
• Error detection not 100% reliable!
correction 5.6 data center • protocol may miss some errors, but rarely
5.3 multiple access networking • larger EDC field yields better detection and correction
protocols 5.7 a day in the life of a
5.4 LANs web request
otherwise
 addressing, ARP
 Ethernet
 switches
 VLANS

Link Layer 5-11 Link Layer 5-12

2
Parity checking What can 2-D parity check do? (1)
single bit parity: two-dimensional bit parity:
 detect single bit  detect and correct single bit errors  Correct all 1-bit errors (we already saw it);
errors  Detect all 2-bit errors;
 An even parity example with two bit errors

0110100 1 row parities

data
1011010 0
The above is an odd-parity 0000111 0
Odd number of 1’s in 3rd
1110101 1 and 7th columns indicate
1001011 0 errors! We know the
errors are in these two
The example to the right columns, not sure which row.
is an even-parity check column parities
1000110 1
0 http://www.ccs.neu.edu/home/amislove/teaching/cs4700/spring11/lectures/lecture13.pdf
Link Layer 5-13 Data Link Layer 5-14

What can 2-D parity check do? (2) What can 2-D parity check do? (3)
 Detect all 3-bit errors;  Detect most 4-bit errors;
 An even parity example with three bit errors  An even parity example with four bit errors that won’t
be detected

0110100 1 row parities

0110100 1 row parities
data data
1011010 0 1011010 0
0000111 0 0000111 0
Odd number of 1’s in 7th All row and column parity
1100101 1 column indicates 1100100 1 checks remain valid.
1001011 0 errors! We can’t tell where 1001011 0
the errors are.

column parities column parities

1000110 1 1000110 1

Data Link Layer 5-15 Data Link Layer 5-16

Internet checksum (review) Cyclic redundancy check

 more powerful error-detection coding
goal: detect “errors” (e.g., flipped bits) in transmitted packet
(note: used at transport layer only)  view data bits, D, as a binary number
 choose r+1 bit pattern (generator), G
sender: receiver:  goal: choose r CRC bits, R, such that
 treat segment contents  compute checksum of  <D,R> exactly divisible by G (modulo 2)
as sequence of 16-bit received segment  receiver knows G, divides <D,R> by G. If non-zero remainder:
integers  check if computed
error detected!
 checksum: addition (1’s checksum equals checksum  can detect all burst errors less than r+1 bits
complement sum) of field value:  widely used in practice (Ethernet, 802.11 WiFi, ATM)
segment contents  NO - error detected
 sender puts checksum  YES - no error detected.
value into UDP But maybe errors
checksum field nonetheless?

Link Layer 5-17 Link Layer 5-18

3
CRC basics CRC example
data CRC G D*2r
want: equivalently: want: G D r=3
D.2r XOR R = nG D.2r = nG XOR R D.2r XOR R = nG 101011
equivalently: 1001 101110000
1001
Are we convinced that the above are equivalent? D.2r = nG XOR R 101
equivalently: 000
if we divide D.2r by 1010
G, want remainder R 1001
Because A XOR A = 0, A XOR 0 = A, to satisfy: (remember 110
and (A XOR B) XOR B = A XOR (B XOR B), 1 XOR A = A) 000
we have (D.2r XOR R) XOR R = nG XOR R 1100
R = remainder of [
D.2r
] R 1001
1010
G
1001
0011

Link Layer 5-19 Link Layer 5-20

Good generating polynomials How many bit errors can be

(IEEE Standards) detected with CRC? (1)
 Consider message received as T(x)+E(x), where
GCRC-32 = x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x1+1
T(x) is the original, correct message, E(x) is the
or
error. Take [T(x)+E(x)]/G(x), because T(x)/G(x)
GCRC-32 = 1 0000 0100 1100 0001 0001 1101 1011 0111 is zero, we only need to focus on E(x)/G(x)
 If a single bit error, E(x) = xi, if G(x) has two or more
terms, G(x) will never divide E(x), all single bit errors
GCRC-16 = x16+x12+x5+1 can be detected;
or  If two isolated single bit errors, E(x) = xi + xj, i > j, we
can rewrite E(x) = xj(xi-j + 1). Assume G(x) is not
GCRC-16 = 1 0001 0000 0010 0001
divisible by x, we can choose G(x) to contain a term
not divisible by (xi-j + 1), then all double errors can be
detected (e.g., choose k to be the length of the frame);

Data Link Layer 5-21 Data Link Layer 5-22

How many bit errors can be Why various different types of

detected with CRC? (2) error checking and correction?
 If there are odd number of bits in error, E(x) contains
an odd number of terms, (e.g., x5 + x2 + 1, but not  CRC is effective in detecting and correcting
x3+1). No polynomial with an odd number of terms errors and can be easily implemented in hardware
has x+1 as a factor in the modulo 2 system. By making (shift registers).
x+1 a factor of G(x), we can detect all errors with odd
number of error bits!  Internet checksum implementation is in software,
 Polynomial code with r check bits will detect all burst mostly at the network and transport layer.
errors of length <= r! A burst error of length k can be
written as xi(xk-i + … + 1). If G(x) contains an x0 term,
it will not have xi as a factor, thus will not divide E(x)
evenly. For example a 16-bit polynomial can detect all
burst errors of 16 bits or less.

Computer Networks by A.S. Tanenbaum, 4th edition, Prentice Hall 2003

Data Link Layer 5-23 Data Link Layer 5-24