Chapter 9: Main Memory

Operating System Concepts – 10th Edition Silberschatz, Galvin and Gagne ©2018
 Chapter 9: Memory Management

 Background
 Contiguous Memory Allocation
 Paging
 Structure of the Page Table
 Swapping
 Example: The Intel 32 and 64-bit Architectures
 Example: ARMv8 Architecture

Operating System Concepts – 10th Edition 9.2 Silberschatz, Galvin and Gagne ©2018
 Objectives

 To provide a detailed description of various ways of organizing memory

hardware
 To discuss various memory-management techniques,
 To provide a detailed description of the Intel Pentium, which supports
both pure segmentation and segmentation with paging

Operating System Concepts – 10th Edition 9.3 Silberschatz, Galvin and Gagne ©2018
 Memory Management

 Memory Management consists of many tasks, including

• Being aware of what parts of the memory are in use and which
parts are not
• Allocating memory to processes when they request it and de-
allocating memory when a process releases it
• Moving data from memory to disc, when the physical capacity
becomes full, and vice versa.

Operating System Concepts – 10th Edition 9.4 Silberschatz, Galvin and Gagne ©2018
 Background
 Program must be brought (from disk) into memory and placed within a
process for it to be run
 Main memory and registers are only storage CPU can access directly
 Memory unit only sees a stream of:
• addresses + read requests, or
• address + data and write requests
 Register access is done in one CPU clock (or less)
 Main memory can take many cycles, causing a stall
 Cache sits between main memory and CPU registers
 Protection of memory required to ensure correct operation

Operating System Concepts – 10th Edition 9.5 Silberschatz, Galvin and Gagne ©2018
 Monoprogramming
 Only allow a single process in memory and only allow one process to
run at any one time
• Very Simple
• No swapping of processes to disc when we run out of memory
• No problems in having separate processes in memory
 Even this simple scheme has its problems.
• Operating system can be seen as a process
 Additional Problems
• Monoprograming is unacceptable as multi-programming is expected
• Multiprogramming makes more effective use of the CPU

 Could allow only a single process in memory at any one time but
allow multi-programming
• i.e. swap out to disc
• Context switch would take time
Operating System Concepts – 10th Edition 9.6 Silberschatz, Galvin and Gagne ©2018
 Modelling Multiprogramming

 Probabilistic model
• A process spends p percent of its time waiting for I/O
• There are n processes in memory
• The probability that all n processes are waiting for I/O (CPU is idle) is pn
• The CPU utilization is then given by
 CPU Utilization = 1 - pn

Operating System Concepts – 10th Edition 9.7 Silberschatz, Galvin and Gagne ©2018
 Mulitprogramming with Fixed Partitions

 Accept that mulitiprogramming is a good idea

• How do we to organise the available memory?
 One method is to divide the memory into fixed sized partitions
 Partitions can be of different sizes but their size remain fixed

Partition 4
Partition 3 700K

Partition 2 400K

Partition 1 200K

OS 100K
0

Operating System Concepts – 10th Edition 9.8 Silberschatz, Galvin and Gagne ©2018
 Mulitprogramming with Fixed Partitions

 Memory divided into four

partitions
 When job arrives it is placed in
the input queue for the smallest
partition that will accommodate it

 Just have a single input queue

where all jobs are held
 When a partition becomes free
we search the queue looking for
the first job that fits into the
partition

Operating System Concepts – 10th Edition 9.9 Silberschatz, Galvin and Gagne ©2018
 Mulitprogramming with Fixed Partitions

 Drawbacks
• As the partition sizes are
fixed, any space not used
by a particular job is lost.
• It may not be easy to state
how big a partition a
particular job needs.
• If a job is placed in (say)
queue there it may be
prevented from running by
other jobs waiting (and using)
that partition.

Operating System Concepts – 10th Edition 9.10 Silberschatz, Galvin and Gagne ©2018
 Mulitprogramming with Fixed Partitions

 Alternative search strategy

• Search the entire input queue looking for the largest job that fits
into the partition

 Do not waste a large partition on a small job but smaller jobs

are discriminated against

 Have at least one small partition or ensure that small jobs only
get skipped a certain number of times.

Operating System Concepts – 10th Edition 9.11 Silberschatz, Galvin and Gagne ©2018
 Protection
 Need to ensure that a process can access only those addresses in its
address space.
 We can provide this protection by using a pair of base and limit
registers define the logical address space of a process

Operating System Concepts – 10th Edition 9.12 Silberschatz, Galvin and Gagne ©2018
 Hardware Address Protection
 CPU must check every memory access generated in user mode to
be sure it is between base and limit for that user

 the instructions to loading the base and limit registers are privileged

Operating System Concepts – 10th Edition 9.13 Silberschatz, Galvin and Gagne ©2018
 Address Binding
 Programs on disk, ready to be brought into memory to execute form
an input queue
• Without support, must be loaded into address 0000
 Inconvenient to have first user process physical address always at
0000
• How can it not be?
 Addresses represented in different ways at different stages of a
program’s life
• Source code addresses usually symbolic
• Compiled code addresses bind to relocatable addresses
 i.e., “14 bytes from beginning of this module”
• Linker or loader will bind relocatable addresses to absolute
addresses
 i.e., 74014
• Each binding maps one address space to another

Operating System Concepts – 10th Edition 9.14 Silberschatz, Galvin and Gagne ©2018
 Binding of Instructions and Data to Memory

 Address binding of instructions and data to memory addresses can

happen at three different stages
• Compile time: If memory location known a priori, absolute code
can be generated; must recompile code if starting location
changes
• Load time: Must generate relocatable code if memory location
is not known at compile time
• Execution time: Binding delayed until run time if the process can
be moved during its execution from one memory segment to
another
 Need hardware support for address maps (e.g., base and limit
registers)

Operating System Concepts – 10th Edition 9.15 Silberschatz, Galvin and Gagne ©2018
 Multistep Processing of a User Program

Operating System Concepts – 10th Edition 9.16 Silberschatz, Galvin and Gagne ©2018
 Logical vs. Physical Address Space

 The concept of a logical address space that is bound to a separate

physical address space is central to proper memory management
• Logical address – generated by the CPU; also referred to as
virtual address
• Physical address – address seen by the memory unit
 Logical and physical addresses are the same in compile-time and
load-time address-binding schemes; logical (virtual) and physical
addresses differ in execution-time address-binding scheme
 Logical address space is the set of all logical addresses generated
by a program
 Physical address space is the set of all physical addresses
generated by a program

Operating System Concepts – 10th Edition 9.17 Silberschatz, Galvin and Gagne ©2018
 Memory-Management Unit (MMU)
 Hardware device that at run time maps virtual to physical address

 Many methods possible, covered in the rest of this chapter

Operating System Concepts – 10th Edition 9.18 Silberschatz, Galvin and Gagne ©2018
 Memory-Management Unit (Cont.)
 Consider simple scheme. which is a generalization of the base-
register scheme.
 The base register now called relocation register
 The value in the relocation register is added to every address
generated by a user process at the time it is sent to memory
 The user program deals with logical addresses; it never sees the real
physical addresses
• Execution-time binding occurs when reference is made to location
in memory
• Logical address bound to physical addresses

Operating System Concepts – 10th Edition 9.19 Silberschatz, Galvin and Gagne ©2018
 Memory-Management Unit (Cont.)
 Consider simple scheme. which is a generalization of the base-
register scheme.
 The base register now called relocation register
 The value in the relocation register is added to every address
generated by a user process at the time it is sent to memory

Operating System Concepts – 10th Edition 9.20 Silberschatz, Galvin and Gagne ©2018
 Dynamic Loading
 The entire program does need to be in memory to execute
 Routine is not loaded until it is called
 Better memory-space utilization; unused routine is never loaded
 All routines kept on disk in relocatable load format
 Useful when large amounts of code are needed to handle
infrequently occurring cases
 No special support from the operating system is required
• Implemented through program design
• OS can help by providing libraries to implement dynamic
loading

Operating System Concepts – 10th Edition 9.21 Silberschatz, Galvin and Gagne ©2018
 Dynamic Linking
 Static linking – system libraries and program code combined by the
loader into the binary program image
 Dynamic linking –linking postponed until execution time
 Small piece of code, stub, used to locate the appropriate memory-
resident library routine
 Stub replaces itself with the address of the routine, and executes the
routine
 Operating system checks if routine is in processes’ memory address
• If not in address space, add to address space
 Dynamic linking is particularly useful for libraries
 System also known as shared libraries
 Consider applicability to patching system libraries
• Versioning may be needed

Operating System Concepts – 10th Edition 9.22 Silberschatz, Galvin and Gagne ©2018
 Swapping

 A process can be swapped temporarily out of memory to a backing

store, and then brought back into memory for continued execution.

 Assume a multiprogramming environment with a round robin CPU

scheduling algorithm.
• When a quantum expires the memory manager will start to swap out the
process that just finished and to swap another process into the memory
space that has been freed. In the meantime, the CPU scheduler will
allocate a time slice to some other process in memory. When each
process finishes its quantum it will be swapped with another process.

Operating System Concepts – 10th Edition 9.23 Silberschatz, Galvin and Gagne ©2018
 Swapping
 A variant of this swapping policy is used for priority based
scheduling algorithm.
 If a higher priority process arrives and wants service, the
memory manager can swap out the lower priority process and
then load and execute the higher priority process.
 When the higher priority process finishes, the lower priority process
can be swapped back in and continued.
 This variant of swapping is sometimes called roll out, roll in.

Operating System Concepts – 10th Edition 9.24 Silberschatz, Galvin and Gagne ©2018
 Swapping

 Backing store –
• Commonly a fast disk.
• It must be large enough to accommodate copies of all memory images
for all users, and it must provide direct access to these memory images.
• The system maintains a ready queue consisting of all processes whose
memory images are on the backing store or in memory and are ready to
run.
 Major part of swap time is transfer time; total transfer time is
directly proportional to the amount of memory swapped.
 Context Switching

 Example: Book Silberschatz

Operating System Concepts – 10th Edition 9.25 Silberschatz, Galvin and Gagne ©2018
 Contiguous Allocation
 Main memory must support both OS and user processes
 Limited resource, must allocate efficiently
 Contiguous allocation is one early method
 Main memory usually into two partitions:
• Resident operating system, usually held in low memory with
interrupt vector
• User processes then held in high memory
• Each process contained in single contiguous section of memory

Operating System Concepts – 10th Edition 9.26 Silberschatz, Galvin and Gagne ©2018
 Contiguous Allocation (Cont.)
 Relocation registers used to protect user processes from each other,
and from changing operating-system code and data
• Base register contains value of smallest physical address
• Limit register contains range of logical addresses – each logical
address must be less than the limit register
• MMU maps logical address dynamically
• Can then allow actions such as kernel code being transient and
kernel changing size

Operating System Concepts – 10th Edition 9.27 Silberschatz, Galvin and Gagne ©2018
 Hardware Support for Relocation and Limit Registers

Operating System Concepts – 10th Edition 9.28 Silberschatz, Galvin and Gagne ©2018
 Contiguous Allocation

Operating System Concepts – 10th Edition 9.29 Silberschatz, Galvin and Gagne ©2018
 Contiguous Allocation

Operating System Concepts – 10th Edition 9.30 Silberschatz, Galvin and Gagne ©2018
 Variable Partition
 Multiple-partition allocation
• Degree of multiprogramming limited by number of partitions
• Variable-partition sizes for efficiency (sized to a given process’ needs)
• Hole – block of available memory; holes of various size are scattered
throughout memory
• When a process arrives, it is allocated memory from a hole large enough to
accommodate it
• Process exiting frees its partition, adjacent free partitions combined
• Operating system maintains information about:
a) allocated partitions b) free partitions (hole)

Operating System Concepts – 10th Edition 9.31 Silberschatz, Galvin and Gagne ©2018
 Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?

 First-fit: Allocate the first hole that is big enough

 Best-fit: Allocate the smallest hole that is big enough; must
search entire list, unless ordered by size
• Produces the smallest leftover hole
 Worst-fit: Allocate the largest hole; must also search entire list
• Produces the largest leftover hole

First-fit and best-fit better than worst-fit in terms of speed and storage
utilization

Operating System Concepts – 10th Edition 9.32 Silberschatz, Galvin and Gagne ©2018
 Fragmentation
 External Fragmentation – total memory space exists to satisfy a
request, but it is not contiguous
 Internal Fragmentation – allocated memory may be slightly larger
than requested memory; this size difference is memory internal to a
partition, but not being used
 First fit analysis reveals that given N blocks allocated, 0.5 N blocks
lost to fragmentation
• 1/3 may be unusable -> 50-percent rule

Operating System Concepts – 10th Edition 9.33 Silberschatz, Galvin and Gagne ©2018
 Fragmentation (Cont.)
 Reduce external fragmentation by compaction
• Shuffle memory contents to place all free memory together in one
large block
• Compaction is possible only if relocation is dynamic, and is done
at execution time
• I/O problem
 Latch job in memory while it is involved in I/O
 Do I/O only into OS buffers
 Now consider that backing store has same fragmentation problems

Operating System Concepts – 10th Edition 9.34 Silberschatz, Galvin and Gagne ©2018
 Buddy System

 A reasonable compromize to overcome disadvantages of both

fixed and variable partitionning schemes
 A modified form is used in Unix SVR4 for kernal memory
allocation
 Memory blocks are available in size of 2^{K} where L <= K <= U
and where
• 2^{L} = smallest size of block allocatable
• 2^{U} = largest size of block allocatable (generally, the entire
memory available)

Operating System Concepts – 10th Edition 9.35 Silberschatz, Galvin and Gagne ©2018
 Buddy System
 We start with the entire block of size 2^{U}
 When a request of size S is made:
• If 2^{U-1} < S <= 2^{U} then allocate the entire block of size 2^{U}
• Else, split this block into two buddies, each of size 2^{U-1}
• If 2^{U-2} < S <= 2^{U-1} then allocate one of the 2 buddies
• Otherwise one of the 2 buddies is split again
 This process is repeated until the smallest block greater or equal to S is
generated
 Two buddies are coalesced whenever both of them become unallocated

Operating System Concepts – 10th Edition 9.36 Silberschatz, Galvin and Gagne ©2018
 Buddy System

 The OS maintains several lists of holes

• the i-list is the list of holes of size 2^{i}
• whenever a pair of buddies in the i-list occur, they are removed from
that list and coalesced into a single hole in the (i+1)-list
 Presented with a request for an allocation of size k such that 2^{i-
1} < k <= 2^{i}:
• the i-list is first examined
• if the i-list is empty, the (i+1)-list is then examined...

Operating System Concepts – 10th Edition 9.37 Silberschatz, Galvin and Gagne ©2018
 Example of Buddy System

Operating System Concepts – 10th Edition 9.38 Silberschatz, Galvin and Gagne ©2018
 Paging
 Physical address space of a process can be noncontiguous;
process is allocated physical memory whenever the latter is
available
• Avoids external fragmentation
• Avoids problem of varying sized memory chunks
 Divide physical memory into fixed-sized blocks called frames
• Size is power of 2, between 512 bytes and 16 Mbytes
 Divide logical memory into blocks of same size called pages
 Keep track of all free frames
 To run a program of size N pages, need to find N free frames and
load program
 Set up a page table to translate logical to physical addresses
 Backing store likewise split into pages
 Still have Internal fragmentation

Operating System Concepts – 10th Edition 9.39 Silberschatz, Galvin and Gagne ©2018
 Assignment of Process Pages to Free Frames

Operating System Concepts – 10th Edition 9.40 Silberschatz, Galvin and Gagne ©2018
 Assignment of Process Pages to Free Frames

Operating System Concepts – 10th Edition 9.41 Silberschatz, Galvin and Gagne ©2018
 Paging

 Each process has its own page table

 Each page table entry contains the frame number of the
corresponding page in main memory
 A bit is needed to indicate whether the page is in main
memory or not

Operating System Concepts – 10th Edition 9.42 Silberschatz, Galvin and Gagne ©2018
 Address Translation Scheme
 Address generated by CPU is divided into:
• Page number (p) – used as an index into a page table which
contains base address of each page in physical memory
• Page offset (d) – combined with base address to define the
physical memory address that is sent to the memory unit

page number page offset

p d
m -n n

• For given logical address space 2m and page size 2n

Operating System Concepts – 10th Edition 9.43 Silberschatz, Galvin and Gagne ©2018
 Paging Hardware

Operating System Concepts – 10th Edition 9.44 Silberschatz, Galvin and Gagne ©2018
 Paging Model of Logical and Physical Memory

Operating System Concepts – 10th Edition 9.45 Silberschatz, Galvin and Gagne ©2018
 Paging Example
 Logical address: n = 2 and m = 4. Using a page size of 4 bytes and
a physical memory of 32 bytes (8 pages)

Operating System Concepts – 10th Edition 9.46 Silberschatz, Galvin and Gagne ©2018
 Paging -- Calculating internal fragmentation

 Page size = 2,048 bytes

 Process size = 72,766 bytes
 35 pages + 1,086 bytes
 Internal fragmentation of 2,048 - 1,086 = 962 bytes
 Worst case fragmentation = 1 frame – 1 byte
 On average, fragmentation = 1 / 2 frame size
 So small frame sizes desirable?
 But each page table entry takes memory to track
 Page sizes growing over time
• Solaris supports two page sizes – 8 KB and 4 MB

Operating System Concepts – 10th Edition 9.47 Silberschatz, Galvin and Gagne ©2018
 Free Frames

Before allocation After allocation

Operating System Concepts – 10th Edition 9.48 Silberschatz, Galvin and Gagne ©2018
 Implementation of Page Table
 Page table is kept in main memory
• Page-table base register (PTBR) points to the page table
• Page-table length register (PTLR) indicates size of the page
table
 In this scheme every data/instruction access requires two memory
accesses
• One for the page table and one for the data / instruction
 The two-memory access problem can be solved by the use of a special
fast-lookup hardware cache called translation look-aside buffers
(TLBs) (also called associative memory).

Operating System Concepts – 10th Edition 9.49 Silberschatz, Galvin and Gagne ©2018
 Translation Look-Aside Buffer
 Some TLBs store address-space identifiers (ASIDs) in each
TLB entry – uniquely identifies each process to provide address-
space protection for that process
• Otherwise need to flush at every context switch
 TLBs typically small (64 to 1,024 entries)
 On a TLB miss, value is loaded into the TLB for faster access
next time
• Replacement policies must be considered
• Some entries can be wired down for permanent fast access

Operating System Concepts – 10th Edition 9.50 Silberschatz, Galvin and Gagne ©2018
 Hardware
 Associative memory – parallel search
Page # Frame #

 Address translation (p, d)

• If p is in associative register, get frame # out
• Otherwise get frame # from page table in memory

Operating System Concepts – 10th Edition 9.51 Silberschatz, Galvin and Gagne ©2018
 Paging Hardware With TLB

Operating System Concepts – 10th Edition 9.52 Silberschatz, Galvin and Gagne ©2018
 Effective Access Time
 Hit ratio – percentage of times that a page number is found in the TLB
 An 80% hit ratio means that we find the desired page number in the
TLB 80% of the time.
 Suppose that 10 nanoseconds to access memory.
• If we find the desired page in TLB then a mapped-memory access
take 10 ns
• Otherwise we need two memory access so it is 20 ns
 Effective Access Time (EAT)
EAT = 0.80 x 10 + 0.20 x 20 = 12 nanoseconds
implying 20% slowdown in access time
 Consider amore realistic hit ratio of 99%,
EAT = 0.99 x 10 + 0.01 x 20 = 10.1ns
implying only 1% slowdown in access time.

Operating System Concepts – 10th Edition 9.53 Silberschatz, Galvin and Gagne ©2018
 Memory Protection
 Memory protection implemented by associating protection bit with
each frame to indicate if read-only or read-write access is allowed
• Can also add more bits to indicate page execute-only, and so on
 Valid-invalid bit attached to each entry in the page table:
• “valid” indicates that the associated page is in the process’
logical address space, and is thus a legal page
• “invalid” indicates that the page is not in the process’ logical
address space
• Or use page-table length register (PTLR)
 Any violations result in a trap to the kernel

Operating System Concepts – 10th Edition 9.54 Silberschatz, Galvin and Gagne ©2018
 Valid (v) or Invalid (i) Bit In A Page Table

Operating System Concepts – 10th Edition 9.55 Silberschatz, Galvin and Gagne ©2018
 Shared Pages
 Shared code
• One copy of read-only (reentrant) code shared among processes
(i.e., text editors, compilers, window systems)
• Similar to multiple threads sharing the same process space
• Also useful for interprocess communication if sharing of read-write
pages is allowed
 Private code and data
• Each process keeps a separate copy of the code and data
• The pages for the private code and data can appear anywhere in
the logical address space

Operating System Concepts – 10th Edition 9.56 Silberschatz, Galvin and Gagne ©2018
 Shared Pages Example

Operating System Concepts – 10th Edition 9.57 Silberschatz, Galvin and Gagne ©2018
 Structure of the Page Table
 Memory structures for paging can get huge using straight-forward
methods
• Consider a 32-bit logical address space as on modern computers
• Page size of 4 KB (212)
• Page table would have 1 million entries (232 / 212)
• If each entry is 4 bytes  each process 4 MB of physical address
space for the page table alone
 Don’t want to allocate that contiguously in main memory
• One simple solution is to divide the page table into smaller units
 Hierarchical Paging
 Hashed Page Tables
 Inverted Page Tables

Operating System Concepts – 10th Edition 9.58 Silberschatz, Galvin and Gagne ©2018
 Hierarchical Page Tables
 Break up the logical address space into multiple page tables
 A simple technique is a two-level page table
 We then page the page table

Operating System Concepts – 10th Edition 9.59 Silberschatz, Galvin and Gagne ©2018
 Two-Level Paging Example
 A logical address (on 32-bit machine with 4K page size) is divided into:
• a page number consisting of 20 bits
• a page offset consisting of 12 bits
 Since the page table is paged, the page number is further divided into:
• a 10-bit page number
• a 10-bit page offset
 Thus, a logical address is as follows:

 where p1 is an index into the outer page table, and p2 is the

displacement within the page of the inner page table
 Known as forward-mapped page table

Operating System Concepts – 10th Edition 9.60 Silberschatz, Galvin and Gagne ©2018
 Address-Translation Scheme

Operating System Concepts – 10th Edition 9.61 Silberschatz, Galvin and Gagne ©2018
 64-bit Logical Address Space
 Even two-level paging scheme not sufficient
 If page size is 4 KB (212)
• Then page table has 252 entries
• If two level scheme, inner page tables could be 210 4-byte entries
• Address would look like

• Outer page table has 242 entries or 244 bytes

• One solution is to add a 2nd outer page table
• But in the following example the 2nd outer page table is still 234
bytes in size
 And possibly 4 memory access to get to one physical memory
location

Operating System Concepts – 10th Edition 9.62 Silberschatz, Galvin and Gagne ©2018
 Three-level Paging Scheme

Operating System Concepts – 10th Edition 9.63 Silberschatz, Galvin and Gagne ©2018
 Logical to Physical Address Translation in IA-32

Operating System Concepts – 10th Edition 9.64 Silberschatz, Galvin and Gagne ©2018
 Example Page Sizes
Computer Page Size
 Atlas 512 48-bit words
 Honeywell-Multics 1024 36-bit word
 IBM 370/XA and 370/ESA 4 Kbytes
 VAX family 512 bytes
 IBM AS/400 512 bytes
 DEC Alpha 8 Kbytes
 MIPS 4 kbyes to 16 Mbytes
 UltraSPARC 8 Kbytes to 4 Mbytes
 Pentium 4 Kbytes or 4 Mbytes
 PowerPc 4 Kbytes

Operating System Concepts – 10th Edition 9.65 Silberschatz, Galvin and Gagne ©2018
 Virtual Memory

Operating System Concepts – 10th Edition 9.66 Silberschatz, Galvin and Gagne ©2018
 Background

 Virtual memory – separation of users logical memory from

physical memory.
• Only part of the program needs to be in memory for execution.
• Logical address space can therefore be much larger than physical
address space.
• Need to allow pages to be swapped in and out.
 Virtual memory can be implemented via:
• Demand paging
• Demand segmentation

Operating System Concepts – 10th Edition 9.67 Silberschatz, Galvin and Gagne ©2018
 Demand Paging

 Bring a page into memory only when it is needed.

• Less I/O needed
• Less memory needed
• Faster response
• More users
 Page is needed implies a reference to it
• invalid reference  abort
• not-in-memory  bring to memory

Operating System Concepts – 10th Edition 9.68 Silberschatz, Galvin and Gagne ©2018
 Valid-Invalid Bit

 With each page table entry a valid–invalid

bit is associated Frame # valid-invalid bit
(1  in-memory, 0  not-in-memory) 1
 Initially valid–invalid bit is set to 0 on all 1
entries. 1
 Example of a page table snapshot. 1
0

 During address translation, if valid–invalid 0
bit in page table entry is 0  page fault. 0
page table

Operating System Concepts – 10th Edition 9.69 Silberschatz, Galvin and Gagne ©2018
Operating System Concepts – 10th Edition 9.70 Silberschatz, Galvin and Gagne ©2018
 Page Fault

 Occurs when a process tries to access a page which is

not currently in memory.
 Trap to the OS.
 Save process’ registers and process state.
 OS checks to determine if the interrupt was a page fault.
 While executing steps to deal with the page fault, allocate
CPU to another process.
 Wait for CPU to be allocated to the interrupted process
again.

Operating System Concepts – 10th Edition 9.71 Silberschatz, Galvin and Gagne ©2018
 Page Fault, cont.
Steps in handling a Page Fault :
1. Check an internal table (usually kept with PCB for the process, to
determine whether the reference was a valid or invalid memory access.
2. If the reference was invalid => terminate process
3. If valid, but page not in memory,
• find a free frame (from free-frame list)
• schedule disk operation to read desired page into frame
4. Update page table an internal table to indicate that the new page is now
in memory.
5. Restart instruction that was interrupted by trap.

Operating System Concepts – 10th Edition 9.72 Silberschatz, Galvin and Gagne ©2018
Operating System Concepts – 10th Edition 9.73 Silberschatz, Galvin and Gagne ©2018
 What happens if there is no free
frame?
Two major problems in implementing demand
paging :
(i) must develop a page replacement
algorithm: - find some frame
in memory that’s currently in use and
swap it out.
- want an algorithm which will result in a
minimum number of page faults.
(ii) must develop a frame allocation algorithm

Operating System Concepts – 10th Edition 9.74 Silberschatz, Galvin and Gagne ©2018
 Page Replacement

frame valid-invalid
bit 1. Swap out
victim
f victim
4. reset 2. change 3. Swap desired
0 i
page table f v to invalid page in
for new
page backing store
page table
physical memory

Operating System Concepts – 10th Edition 9.75 Silberschatz, Galvin and Gagne ©2018
 Page-Replacement Algorithms
 First-in-First-Out
 Optimal
 Least Recently Used
 Least Frequently Used
 Second Chance
are but a few of such algorithms. We will look at the first three.

Operating System Concepts – 10th Edition 9.76 Silberschatz, Galvin and Gagne ©2018
 Page-Replacement Algorithms,
 Want the one that gives the cont.
lowest page-fault rate.
 Evaluate algorithm by running it on a particular string of memory
references (reference string) and computing the number of page faults
on that string.
 In all our examples, the reference string is
1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5.

Operating System Concepts – 10th Edition 9.77 Silberschatz, Galvin and Gagne ©2018
 First-In-First-Out (FIFO) Algorithm

 Associates with each page the time it was brought into memory.
 When a page must be replaced, the oldest page is chosen.
 3 frames (3 pages per process can be in memory at a time)

Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 1 1 4 4 4 5 5 5 5 5
2 2 2 1 1 1 1 1 3 3
3 3 3 2 2 2 2 2 4
1f 1f 1f 1f 1f 1f 1f 1f 1f

Operating System Concepts – 10th Edition 9.78 Silberschatz, Galvin and Gagne ©2018
 FIFO Algorithm, cont.
 9 page faults in this example.
 In general, the more frames there are, the less page faults.
 Notice, however, that the no. of faults for 4 frames is 10 (i.e. greater
than that for 3 frames). The student is asked to verify this.
 For some algorithms, the page fault rate may increase as the number
of frames increase. This is known as Belady’s Anomaly.

Operating System Concepts – 10th Edition 9.79 Silberschatz, Galvin and Gagne ©2018
 First-In-First-Out (FIFO) Algorithm

Operating System Concepts – 10th Edition 9.80 Silberschatz, Galvin and Gagne ©2018
 Least Recently Used (LRU) Algorithm

 LRU is an approximation to the optimal algorithm. Simply,

Replace the page that has not been used for the longest
period of time.
 LRU algorithm associates with each page the time of that page’s
last use.
 2 methods of implementation:
• Counter implementation
• Stack

Operating System Concepts – 10th Edition 9.81 Silberschatz, Galvin and Gagne ©2018
 Use LRU Algorithm
Page
Reference
Order
0 1 2 3 0 1 4 0 1 2 3 4
Youngest
page
0 1 2 3 0 1 4 0 1 2 3 4
0 1 2 3 0 1 4 0 1 2 3
0 1 2 3 0 1 4 0 1 2
Oldest
page
P P P P P P P P P P
 10 PF’s compared to 9 with FIFO
 FIFO keeps “4” in memory because it comes in last
 Even a bad algorithm shines under the right circumstances

Operating System Concepts – 10th Edition 9.82 Silberschatz, Galvin and Gagne ©2018
 LRU Algorithm (Cont.)

 Counter Implementation:
• Every page entry has a counter; every time page is referenced
through this entry, copy the clock into the counter.
• When a page needs to be changed, look at the counters to
determine which are to change.
E.g. Reference string: 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5

1 1 1 1 1 1 1 5
2 2 2 2 2 2 2
3 3 5 5 4 4
4 4 3 3 3

No. of page faults = 8

Operating System Concepts – 10th Edition 9.83 Silberschatz, Galvin and Gagne ©2018
 Optimal Algorithm
As a result of Belady’s anomaly, a search was
launched for an optimal page-replacement algorithm.
That is, one that has the lowest page-fault rate.
The optimal algorithm is simply:
Replace the page that will not be used for the
longest period of time.
Example using 4 frames
Reference string : 1, 2, 3, 4, 1, 2, 5, 1, 2, 3, 4, 5
1 1 1 1 1 5
2 2 2 2 2
3 3 3 3
4 5 4

Operating System Concepts – 10th Edition 9.84 Silberschatz, Galvin and Gagne ©2018
 Optimal Algorithm, cont.

 No. of page faults = 6

 Compare with 10 for FIFO
 Difficult to implement - requires future knowledge

Operating System Concepts – 10th Edition 9.85 Silberschatz, Galvin and Gagne ©2018
 Thrashing

 If a process does not have “enough” frames,

the page-fault rate is very high. This leads to
thrashing.
 A process is thrashing if it is spending more
time paging than executing.
 Thrashing results in severe performance
problems.

Operating System Concepts – 10th Edition 9.86 Silberschatz, Galvin and Gagne ©2018
 Cause of Thrashing
Consider the following scenario:
• The OS monitors CPU utilization. If the utilization is too
low, we increase the degree of multiprogramming by
admitting a new process to the system. A global page
replacement algorithm is used. Now, suppose that a
process needs more frames. It starts faulting and taking
away frames from other processes. These processes
need those pages, so they also fault, taking frames
from other processes.
• These faulting processes must use the paging device
to swap pages in and out, so they enter the wait queue.
As processes queue, CPU utilization decreases.

Operating System Concepts – 10th Edition 9.87 Silberschatz, Galvin and Gagne ©2018
 Thrashing, cont.

The CPU scheduler sees the decreasing

utilization and increases the degree of
multiprogramming by scheduling a new
process. The new process tries to get started
by taking frames from running processes,
causing more page faults and a longer
waiting queue. As a result, the CPU utilization
drops even further and the scheduler tries to
increase multiprogramming even more.
Thrashing has occurred and throughput
plunges. No work is being done,because the
processes are spending all their time paging.
Operating System Concepts – 10th Edition 9.88 Silberschatz, Galvin and Gagne ©2018
 Thrashing, cont.

 How do we deal with Thrashing?

The effects of thrashing can be limited by
using a local (or priority) replacement
algorithm. With local replacement, if one
process starts thrashing, it cannot steal
frames from another process and cause the
latter to thrash also.
 To prevent thrashing, we must provide a
process as many frames as it needs. How do
we know how many frames it needs? There
are several techniques. One common
technique is the Working Set Model.
Operating System Concepts – 10th Edition 9.89 Silberschatz, Galvin and Gagne ©2018
 The Working Set Model
 Working Set: the set of pages that a process is currently using.
 If the entire working set is in memory, the process will run without
causing many faults.
 See page 366-367 of text for further details on the working set model.

Operating System Concepts – 10th Edition 9.90 Silberschatz, Galvin and Gagne ©2018
 Intel IA-32 Segmentation

Operating System Concepts – 10th Edition 9.91 Silberschatz, Galvin and Gagne ©2018
 Intel IA-32 Paging Architecture

Operating System Concepts – 10th Edition 9.92 Silberschatz, Galvin and Gagne ©2018
 Intel IA-32 Page Address Extensions
 32-bit address limits led Intel to create page address extension (PAE),
allowing 32-bit apps access to more than 4GB of memory space
• Paging went to a 3-level scheme
• Top two bits refer to a page directory pointer table
• Page-directory and page-table entries moved to 64-bits in size
• Net effect is increasing address space to 36 bits – 64GB of
physical memory

Operating System Concepts – 10th Edition 9.93 Silberschatz, Galvin and Gagne ©2018
 Intel x86-64
 Current generation Intel x86 architecture
 64 bits is ginormous (> 16 exabytes)
 In practice only implement 48 bit addressing
• Page sizes of 4 KB, 2 MB, 1 GB
• Four levels of paging hierarchy
 Can also use PAE so virtual addresses are 48 bits and physical
addresses are 52 bits

Operating System Concepts – 10th Edition 9.94 Silberschatz, Galvin and Gagne ©2018
 Example: ARM Architecture
 Dominant mobile platform chip
(Apple iOS and Google Android 32 bits
devices for example)
outer page inner page offset
 Modern, energy efficient, 32-bit
CPU
 4 KB and 16 KB pages 4-KB
or
16-KB
 1 MB and 16 MB pages (termed page

sections)
 One-level paging for sections,
1-MB
two-level for smaller pages or
16-MB
 Two levels of TLBs section

• Outer level has two micro

TLBs (one data, one
instruction)
• Inner is single main TLB
• First inner is checked, on
miss outers are checked,
and on miss page table
walk performed by CPU
Operating System Concepts – 10th Edition 9.95 Silberschatz, Galvin and Gagne ©2018
 End of Chapter 9

Operating System Concepts – 10th Edition Silberschatz, Galvin and Gagne ©2018