LOGIC DIAGRAM OF HALF ADDER:

A 1
3
Sum
B 2

2
3
Carry

TRUTH TABLE:
INPUT OUTPUT
A B Sum Carry
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1
PROGRAM:
DATA FLOW MODEL:
module ha(a, b, s, c);
input a;
input b;
output s;
output c;
assign s=a^b;
assign c=a&b;
endmodule
STRUCTURAL MODEL:
module ha(a, b, s, c);
input a;
input b;
output c;
output s;
xor(s,a,b);
and(c,a,b);
endmodule

2
BEHAVIOURAL MODEL:
module ha(a, b, s, c);
input a;
input b;
output s;
output c;
reg s,c;
always@(a or b)
begin
s=a^b;
c=a&b;
end
endmodule

HALF ADDER
RTL SCHEMATIC:

SIMULATED OUTPUT:

3
LOGIC DIAGRAM OF FULL ADDER:

TRUTH TABLE:
A B C Sum Carry
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

4
PROGRAM:
DataFlow model:
module fabe(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
wire w1,w2,w3;
assign sum=(a^b)^c;
assign w1=a^b;
assign w2=a&b;
assign w3=w1&c;
assign carry=w2|w3;
endmodule
Structural model:
module fabe(a, b,c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
wire w1,w2,w3;
xor(w1,a,b);
and(w2,a,b);
xor(sum,w1,c);
and (w3,w1,c);
or(carry,w3,w2);
endmodule

Behavioral model:
module fabe(a, b, c, sum, carry);
input a;
input b;
input c;
output sum;
output carry;
reg sum, carry, w1,w2,w3; always @(a or b or c)
begin
sum=(a^b)^c;
w1=a^b;
w2=a&b;
w3=w1&c;
carry=w2|w3;
end
endmodule

5
 FULL ADDER

RTL SCHEMATIC:

SIMULATED OUTPUT:

6
  Verify the truth table of the required digital circuit in simulation window that appears.

LOGIC DIAGRAM OF T-FLIP FLOP:

T
Q

C
P

TRUTH TABLE:
Q(t) T Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0

PROGRAM:
module TFF(q, clk, t);
output q;
input clk;
input t;
reg q;
initial q=0;
always@(posedge clk) begin
q=q^t;
end
endmodule

9
 T-FLIP FLOP

RTL SCHEMATIC:

SIMULATED OUTPUT:

10
LOGIC DIAGRAM OF D-FLIP FLOP:

C
P

TRUTH TABLE:
Q(t) D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1

PROGRAM:
module dff (d, clk, q, qbar);
input d;
input clk;
output q;
output qbar;
reg q,qbar;
initial q=0;
always @(posedge clk)
begin
q=d;
qbar=~d;
end
endmodule

11
 D-FLIP FLOP

RTL SCHEMATIC:

SIMULATED OUTPUT:

12
 i. Verify the truth table of the required digital circuit in simulation window that appears.

Main program:

module sw(a, b, c, sum, carry);

input [7:0]a;
input [7:0]b;
input c;
output [7:0]sum;
output carry;
wire [6:0]c;
gk fa0(a[0],b[0],c,sum[0],c1);
gk fa1(a[1],b[1],c1,sum[1],c2);
gk fa2(a[2],b[2],c2,sum[2],c3);
gk fa3(a[3],b[3],c3,sum[3],c4);
gk fa4(a[4],b[4],c4,sum[4],c5);
gk fa5(a[5],b[5],c5,sum[5],c6);
gk fa6(a[6],b[6],c6,sum[6],c7);
gkfa7(a[7],b[7],c7,sum[7],carry);
endmodule

Sub-Program
module fulladd (sum, carry, a, b, c);
input a, b, c;
output sum, carry;
wire w1, w2, w3;
xor (sum,a,b,c);
and (w1,a,b);
and(w2,b,c,);
and(w3,c,a);
or(carry,w1,w2,w3);
endmodule

15
RIPPLE CARRY ADDER:

16
RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:

17
OUTPUT WAVEFORM:

18
OUTPUT WAVEFORM:

19
PROGRAM:

module HA (sout,cout,a,b);
input a,b;
output sout,cout;
assign sout=(a^b);
assign cout=(a&b);
endmodule

module FA (sout,cout,a,b,cin);
input a,b,cin;
output sout,cout;
assign sout=(a^b^cin);
assign cout=((a&b)|(b&cin)|(cin&a));
endmodule

module bitmul
(m,x,y);output
[7:0]m;
input [3:0]x;
input [3:0]y;
assign m[0]=(x[0]&y[0]);
wire
x1,x2,x3,x4,x5,x6,x7,x8,x9,x10,x11,x12,x13,x14,x15,x16,x17;
HA HA1 (m[1],x1,(x[1]&y[0]),(x[0]&y[1]));
FA FA1 (x2,x3,(x[1]&y[1]),(x[0]&y[2]),x1);
FA FA2
(x4,x5,(x[1]&y[2]),(x[0]&y[3]),x3);HA
HA2 (x6,x7,(x[1]&y[3]),x5);
HA HA3 (m[2],x15,x2,(x[2]&y[0]));
FA FA5 (x14,x16,x4,(x[2]&y[1]),x15);
FA FA4 (x13,x17,x6,(x[2]&y[2]),x16);
FA FA3 (x9,x8,x7,(x[2]&y[3]),x17);
HA HA4 (m[3],x12,x14,(x[3]&y[0]));
FA FA8 (m[4],x11,x13,(x[3]&y[1]),x12);
FA FA7 (m[5],x10,x9,(x[3]&y[2]),x11);
FA FA6 (m[6],m[7],x8,(x[3]&y[3]),x10);
endmodule

22
TECHNOLOGICAL SCHEMATIC:

23
OUTPUT WAVEFORM:

24
CIRCUIT DIAGRAM

27
PROGRAM:
SIPO
module SIPO ( din ,clk ,reset ,dout );
output [3:0] dout ;wire [3:0] dout ;
inputdin,clk,reset;
wiredin,clk,reset;
reg [3:0]s;
always @ (posedge (clk)) begin
if (reset)
s <= 0;
else begin
s[3] <= din;
s[2] <= s[3];
s[1] <= s[2];
s[0] <= s[1];
end
end
assigndout = s;
endmodule
TESTBENCH
moduletestSIPO;
// Inputs
reg din;regclk;reg reset;
// Outputs
wire [3:0] dout;
// Instantiate the Unit Under Test (UUT)
SIPO uut (.din(din), .clk(clk), .reset(reset), .dout(dout));
initial begin
// Initialize Inputs
din = 0;clk = 0;reset = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset = 1;
#100 reset =0 ;din=1;
#10 din = 0;
#10 din = 1;
#20 din = 1;
end
always #1 clk = ~clk;
endmodule

28
PISO
moduleparallel_in_serial_out ( din ,clk ,reset ,load ,dout );
outputdout ;regdout ;
input [3:0] din ;input clk,reset,load ;
wire [3:0] din ;wire clk,reset,load ;
reg [3:0]temp;
always @ (posedge (clk)) begin
if (reset)
temp<= 1;
else if (load)
temp<= din;
else begin
dout<= temp[3];
temp<= {temp[2:0],1'b0};
end
end
endmodule

TESTBENCH
moduletestPISO;
// Inputs
reg [3:0] din;
regclk, reset, load;
// Outputs
wiredout;
// Instantiate the Unit Under Test (UUT)
parallel_in_serial_outuut (.din(din), .clk(clk), .reset(reset), .load(load), .dout(dout));
initial begin
// Initialize Inputs
din = 0;clk = 0;reset = 0;load = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
reset=1;
#10 reset = 0;
#10 load = 1; din=4'b1000;
#10 load = 0;
end
always #1 clk = ~clk;
endmodule

29
THEOTY:
There are two main types of RAM: Dynamic RAM (DRAM) and Static RAM (SRAM). DRAM (pronounced
DEE-RAM), is widely used as a computer's main memory. Each DRAM memory cell is made up of a transistor
and a capacitor within an integrated circuit, and a data bit is stored in the capacitor

SINGLE-PORT RAM WITH ASYNCHRONOUS READ:

Verilog CODE:

Following is the Verilog code for a single-port RAM with asynchronous read.
module raminfr (clk, we, a, di, do);

input
clk;
input
we;
input
[4:0]
a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];

always @(posedge
clk) beginif
(we)
ram[a] <= di;
end
assign do
= ram[a];
endmodule

32
 SINGLE-PORT RAM WITH "FALSE" SYNCHRONOUS READ:

VERILOG CODE:

Following is the Verilog code for a single-port RAM with "false" synchronous read.
module raminfr (clk, we, a, di, do);
input clk;
input we;input [4:0] a;
input [3:0] di;
output [3:0] do;
reg [3:0] ram [31:0];
reg [3:0] do;

always @(posedge clk)begin

if (we)
ram[a] <= di;
do <= ram[a];
end

33
MOORE MACHINE:

36
ROGRAM:
module moore( clk, rst, inp, outp);
input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst )
begin
if( rst )
state <= 2'b00;
else
begin
case( state )
2'b00:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
2'b01:
begin
if( inp ) state <= 2'b11;
else state <= 2'b10;
end
2'b10:
begin
if( inp ) state <= 2'b01;
else state <= 2'b11;
end
2'b11:
begin
if( inp ) state <= 2'b01;
else state <= 2'b10;
end
endcase
end
end
always @(posedge clk, posedge rst)
begin
if( rst )
outp <= 0;
else if( state == 2'b11 )
outp <= 1;
else outp <= 0;
end
endmodule

37
RTL SCHEMATIC:

TECHNOLOGICAL SCHEMATIC:

38
OUTPUT WAVEFORM:

39
MEALY MACHINE: State diagram

PROGRAM:

module mealy( clk, rst, inp, outp);

input clk, rst, inp;
output outp;
reg [1:0] state;
reg outp;
always @( posedge clk, posedge rst ) begin
if( rst ) begin
state <= 2'b00;
outp <= 0;
end
else begin
case( state )
2'b00: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b10;
outp <= 0;
end
end
2'b01: begin
if( inp ) begin
state <= 2'b00;
outp <= 1;

40
end
else begin
state <= 2'b10;
outp <= 0;
end
end
2'b10: begin
if( inp ) begin
state <= 2'b01;
outp <= 0;
end
else begin
state <= 2'b00;
outp <= 1;
end
end
default: begin
state <= 2'b00;
outp <= 0;
end
endcase
end
end
endmodule

41
OUTPUT WAVEFORM:

42
SIMULATION OUTPUT: (Synchronous up counter)

46
 PROGRAM:

SYNCHRONOUS COUNTER:
module upcounter(clear, clk, q);
input clear;
nput clk;
output [3:0] q;
reg [3:0] q;
reg [3:0]z=4'b0000;
always@(clk)
begin
if(clk==1'b1)
if(clear==1'b1)
z=4'b0000;
else
z=z+4'b0001;
q=z;
end
endmodule

SYNTHESIS REPORT:

Device utilization summary:

Selected Device : 3s400tq144-5
Number of Slices: 5 out of 3584 0%
Number of Slice Flip Flops: 8 out of 7168 0%
Number of 4 input LUTs: 3 out of 7168 0%
Number of bonded IOBs: 5 out of 97 5%
Number of GCLKs: 1 out of 8 12%
Clock Information:
+ + +
Clock Signal | Clock buffer(FF name) | Load |
-----------------------------------+------------------------+-------+
clk | BUFGP |8 |
-----------------------------------+------------------------+-------+
Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.670ns (frequency: 374.574MHz)
Total number of paths / destination ports: 14 / 8
Delay: 2.670ns (Levels of Logic = 1)
Source: d_0 (LATCH)
Destination: d_0 (LATCH)
Source Clock: clk falling
Destination Clock: clk falling

47
MOD-10 SYNCHRONOUS COUNTER

48
MOD-10 COUNTER: 4 BIT UPDOWN COUNTER:
module mod(clk,d,q); module updown(m,clk,i,a, b, c,d);
input clk,d; input clk;
output [3:0]q; input i,m;
wire p; output a,b,c,d;
not a(p,q[3]); wire p;
jkff a1(d,d,q[0],clk); not(p,m);
jkff a2(d&p&q[0],d&q[0],q[1],clk); jkff aa(clk,i,i,d);
jkff a3(d&q[1]&q[0],d&q[1]&q[0],q[2],clk); jkff bb((m&d)|(p&(~d)),i,i,c);
jkff a4(d&q[2]&q[1]&q[0],d&q[0],q[3],clk); jkff cc((m&c&d)|(p&(~c)&(~d)),i,i,b);
endmodule jkff dd((m&d&c&b)|(p&(~d)&(~c)&(~b)),i,i,a);
endmodule
module jkff(j,k,q,clk);
input j,k,clk; module jkff(clk,j,k,q);
output q; input clk,j,k;
reg q=0; output q;
always @(posedge clk) reg q=0;
begin always @(negedge clk )
if(j==0 && k==0) q=q; begin
else if(j==0 && k==1) q=0; if(j==0 & k==0)
else if(j==1 && k==0) q=1; q=q;
else else if (j==0 & k==1)
q=~q; q=0;
end else if(j==1 & k==0)
endmodule q=1;
else q=~q;
end
endmodule

RESULT:
Thus, the 3-bit SYNCHRONOUS COUNTER are simulated and synthesized with VERILOG
program.

49
SIMULATION OUTPUT: (Asynchronous down counter )

52
 PROGRAM:

ASYNCHRONOUS COUNTER:
module downcounter(clear,clk,q); input
clear;
input clk; output
[3:0] q;
reg [3:0] q;
reg [3:0] z;
always@(clk)
begin
if(clear==1'b1)
begin
z=4'b0000;
end
else if(clk==1'b1)
begin
z=z-"0001";
end
q=z;
end
endmodule
SYNTHESIS REPORT:

Device utilization summary:

Selected Device : 3s400tq144-5
Number of Slices: 5 out of 3584 0%
Number of Slice Flip Flops: 8 out of 7168 0%
Number of 4 input LUTs: 3 out of 7168 0%
Number of bonded IOBs: 5 out of 97 5%
Number of GCLKs: 1 out of 8 12%

Timing Detail:
All values displayed in nanoseconds (ns)
Timing constraint: Default period analysis for Clock 'clk'
Clock period: 2.670ns (frequency: 374.574MHz)
Total number of paths / destination ports: 14 / 8
Delay: 2.670ns (Levels of Logic = 1)
Source: d_0 (LATCH)
Destination: d_0 (LATCH)
Source Clock: clk falling
Destination Clock: clk falling

53
4 BIT ASYNCHRONOUS UP/DOWN COUNTER:

54
4 BIT UPDOWN COUNTER:
module up down(m,clk,i,a, b, c,d);
input clk;
input i,m; output
a,b,c,d;wire p;
not(p,m);
jkff aa(clk,i,i,d);
jkff bb((m&d)|(p&(~d)),i,i,c);
jkff cc((m&c&d)|(p&(~c)&(~d)),i,i,b);
jkff dd((m&d&c&b)|(p&(~d)&(~c)&(~b)),i,i,a); endmodule

module jkff(clk,j,k,q);input
clk,j,k;
output q;reg
q=0;
always @(negedge clk ) begin
if(j==0 & k==0) q=q;
else if (j==0 & k==1) q=0;
else if(j==1 & k==0) q=1;
else q=~q; end
endmodule

RESULT:
Thus, the 4-BIT ASYNCHRONOUS COUNTER are simulated and synthesized with
VERILOG program.

55
CIRCUIT DIAGRAM:

NAND gate:

Verilog code:
module cmosNand2( A,B,Nand2);
input A,B;
output Nand2;
nmos #(121) nmos(Nand2,w1,A); // 2.0u 0.25u
pmos #(121) pmos(Nand2,vdd,A); // 2.0u 0.25u
pmos #(121) pmos(Nand2,vdd,B); // 2.0u 0.25u
nmos #(107) nmos(w1,vss,B); // 2.0u 0.25u
endmodule

57
Layout:

Waveform:

58
NOR gate:

Verilog code:

module nor2Cmos( B,A,Nor2);

input B,A;
output Nor2;
nmos #(121) nmos(Nor2,vss,A); // 1.0u 0.12u
pmos #(121) pmos(Nor2,w4,B); // 2.0u 0.12u
pmos #(107) pmos(w4,vdd,A); // 2.0u 0.12u
nmos #(121) nmos(Nor2,vss,B); // 1.0u 0.12u
endmodule

59
Layout:

Waveform:

60
64
OUTPUT WAVEFORM:

65
CMOS Inverter

68
OUTPUT:

Transient Analysis

Dc analysis

TSPICE - Tanner SPICE

Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "C:\Tanner\S-Edit\Module011.sp"
Including "C:\Tanner\TSpice70\models\ml2_125.md"

69
Device and node counts:
MOSFETs - 2 BJTs - 0 MESFETs - 0 Capacitors - Inductors - 0
MOSFET geometries - 2
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors - 0
Voltage sources - 2
VCVS - 0
CCVS - 0

V-control switch - 0

Macro devices - 0
Subcircuits - 0
Independent nodes - 1
Total nodes - 4
Current sources - 0
VCCS - 0
CCCS - 0

I- control switch - 0
Functional model instances - 0
Subcircuit instances - 0
Boundary nodes - 3
Parsing 0.01 seconds
Setup 0.00 seconds
DC operating point 0.00 seconds
Transient Analysis 0.04 seconds

Total 0.05 seconds

70
 SCHEMATIC ENTRY: (Common Source Amplifier)

OUTPUT WAVEFORM:

74
SCHEMATIC ENTRY: (Common Drain Amplifier)

OUTPUT WAVEFORM:

78
79
SCHEMATIC ENTRY: (Common Gate Amplifier)

OUTPUT WAVEFORM:

82
  Obtain the spice code using T-edit.

DIFFERENTIAL AMPLIFIER CIRCUIT:

85
WAVEFORM:

OUTPUT

TSPICE - Tanner SPICE

Version 7.10
Copyright (c) 1993-2001 Tanner Research, Inc.
Parsing "C:\Tanner\S-Edit\Module0.sp"
Including "C:\Tanner\TSpice70\models\ml2_125.md"
Device and node counts:
MOSFETs - 5 BJTs - 0 MESFETs - 0 Capacitors - 0 Inductors - 0
MOSFET geometries - 2
JFETs - 0
Diodes - 0
Resistors - 0
Mutual inductors - 0
Transmission lines - 0 Coupled transmission lines - 0
Voltage sources - 4
VCVS - 0
CCVS - 0
V-control switch - 0
Macro devices - 0
Subcircuits - 0

86
Independent nodes - 4
Total nodes - 9
Current sources - 0
VCCS - 0
CCCS - 0
I-control switch - 0
Functional model instances - 0
Subcircuit instances - 0
Boundary nodes - 5

Parsing 0.00 seconds

Setup 0.01 seconds
DC operating point 0.01 seconds
Transient Analysis 0.07 seconds

Total 0.09 seconds

87
PROGRAM:

DATA FLOW MODELLING:

Module logicgates(a,b,c,d,e,f,g,h,I);
Input a,b;
Output c,d,e,f,g,h,I;
assign c= a&b;
assign d= ~(a&b);
assign e= a|b;
assign f= ~(a|b);
assign g= a^b;
assign h= ~(a^b);
assign i= ~a;
end module

90
BEHAVIORAL MODELLING:

Module logicgates(a,b,c,d,e,f,g,h,I);
Input a,b;
Output c,d,e,f,g,h,I;
Reg c,d,e,f,g,h,I;
always@(a or b)
begin
c= a&b;
d= ~(a&b);
e= a|b;
f= ~(a|b);
g= a^b;
h= ~(a^b);
i= ~a;
end
endmodule

GATE LEVEL MODELLING:

Module logicgates(a,b,c,d,e,f,g,h,I);
Input a,b;
Output c,d,e,f,g,h,I;
and(c,a,b);
nand(d,a,b);
or(e,a,b);
nor(f,a,b);
xor(g,a,b);
xnor(h,a,b);
not(i,a,b);
end module

91
/ Test bench program

Module test_logic_gates;
Reg A,B;
Wire C,D,E,F,G,H,I;
Logicgates lg(A,B,C,D,E,F,G,H,I;);
Initial
Begin

A=0;B=0;
#5 A=0;B=1;
#5 A=1;B=0;
#5 A=1;B=1;
End
End module

92
93
TECHNOLOGICAL SCHEMATIC:

OUTPUT:

94